ANALOG DEVICES AD7787

Low Power, 2-Channel 24-Bit Sigma-Delta ADC AD7787 FEATURES APPLICATIONS Power Smart transmitters Supply: 2.5 V to 5.25 V operation Battery applications Normal mode: 75 µA max Portable instrumentation Power-down mode: 1 µA max Sensor measurement RMS noise: 1.1 µV at 9.5 Hz update rate Temperature measurement 19.5-bit p-p resolution (22 bits effective resolution) Pressure measurement Integral nonlinearity: 3.5 ppm typical Weigh scales Simultaneous 50 Hz and 60 Hz rejection 4 to 20 mA loops Internal clock oscillator GENERAL DESCRIPTION Rail-to-rail input buffer VDD monitor channel The AD7787 is a low power, complete analog front end for low Temperature range: −40°C to +105°C frequency measurement applications. It contains a low noise 10-lead MSOP 24-bit Σ-Δ ADC with one differential input and one single- ended input that can be buffered or unbuffered. INTERFACE The device operates from an internal clock. Therefore, the user 3-wire serial does not have to supply a clock source to the device. The output SPI®, QSPI™, MICROWIRE™, and DSP compatible data rate from the part is software programmable and can be Schmitt trigger on SCLK varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time scales with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP. FUNCTIONAL BLOCK DIAGRAM GND V REFIN DD AD7787 V DD DOUT/RDY SERIAL DIN INTERFACE AIN1(+) AND SCLK Σ-∆ LOGIC BUF MUX ADC CONTROL CS AIN1(–) AIN2 CLOCK GND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 04477-0-001 AD7787 TABLE OF CONTENTS Specifications..................................................................................... 3 Overview ..................................................................................... 14 Timing Characteristics..................................................................... 5 Noise Performance..................................................................... 14 Absolute Maximum Ratings............................................................ 7 Reduced Current Modes ........................................................... 14 ESD Caution.................................................................................. 7 Digital Interface.......................................................................... 15 Pin Configuration and Function Descriptions............................. 8 Circuit Description......................................................................... 18 Typical Performance Characteristics ............................................. 9 Analog Input Channel ............................................................... 18 On-Chip Registers.......................................................................... 10 Bipolar/Unipolar Configuration .............................................. 18 Communications Register (RS1, RS0 = 0, 0)........................... 10 Data Output Coding .................................................................. 18 Status Register (RS1, RS0 = 0, 0; Power-On/Reset Reference Input........................................................................... 18 = 0×8C)........................................................................................ 11 VDD Monitor ................................................................................ 19 Mode Register (RS1, RS0 = 0, 1; Power-On/Reset Grounding and Layout .............................................................. 19 = 0×02)......................................................................................... 12 Applications ................................................................................ 19 Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04)......................................................................................... 13 Outline Dimensions ....................................................................... 20 Data Register (RS1, RS0 = 1, 1; Power-On/Reset Ordering Guide .......................................................................... 20 = 0×000000) ................................................................................ 13 ADC Circuit Information.............................................................. 14 REVISION HISTORY 4/04—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD7787 SPECIFICATIONS Temperature range is −40°C to +105°C. VDD = 2.5 V to 5.25 V; REFIN = 2.5 V; GND = 0 V; CDIV1 = CDIV0 = 0; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter AD7787B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATION Output Update Rate 9.5 Hz min nom 120 Hz max nom ADC CHANNEL 1 No Missing Codes 24 Bits min Update rate ≤ 20 Hz. Resolution 19.5 Bits p-p 9.5 Hz update rate. Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ. Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typ 2 Full-Scale Error ±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V. ANALOG INPUTS Bipolar Input Voltage Range ±REFIN V nom Because AIN2 is single-ended, it can have a negative voltage of 100 mV minimum (see Page 18). Unipolar Voltage Range 0 to REFIN V nom 1 Absolute AIN Voltage Limits GND + 100 mV V min Buffered mode. VDD – 100 mV V max Analog Input Current Buffered mode. 1 Average Input Current ±1 nA max Average Input Current Drift ±5 pA/°C typ 1, 3 Absolute AIN Voltage Limits GND – 100 mV V min Unbuffered mode. VDD + 30 mV V max Analog Input Current Unbuffered mode. Current varies with input voltage. Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ 1 Normal Mode Rejection 4 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 . 4 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101 . 4 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011 . Common-Mode Rejection (AIN1) AIN = 1 V. @ DC 90 dB min 100 dB typ. 1 4 4 @ 50 Hz, 60 Hz 100 dB min 50 ± 1 Hz (FS[2:0] = 101 ), 60 ± 1 Hz (FS[2:0] = 011 ). REFERENCE INPUT REFIN Voltage 2.5 V nom 1 Reference Voltage Range 0.1 V min VDD V max Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ 1 Normal Mode Rejection 4 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 100 . 4 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 101 . 4 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 011 . Rev. 0 | Page 3 of 20 AD7787 Parameter AD7787B Unit Test Conditions/Comments LOGIC INPUTS 1 All Inputs Except SCLK VINL, Input Low Voltage 0.8 V max VDD = 5 V. 0.4 V max V = 3 V. DD V , Input High Voltage 2.0 V min V = 3 V or 5 V. INH DD 1 SCLK Only (Schmitt-Triggered Input) VT(+) 1.4/2 V min/V max VDD = 5 V. VT(−) 0.8/1.4 V min/V max VDD = 5 V. V (+) − V (−) 0.3/0.85 V min/V max V = 5 V. T T DD V (+) 0.9/2 V min/V max V = 3 V. T DD V (−) 0.4/1.1 V min/V max V = 3 V. T DD VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 3 V. Input Currents ±1 µA max VIN = VDD or GND. Input Capacitance 10 pF typ All Digital Inputs. LOGIC OUTPUTS 1 VOH, Output High Voltage VDD − 0.6 V min VDD = 3 V, ISOURCE = 100 µA. 1 VOL, Output Low Voltage 0.4 V max VDD = 3 V, ISINK = 100 µA. 1 V , Output High Voltage 4 V min V = 5 V, I = 200 µA. OH DD SOURCE 1 V , Output Low Voltage 0.4 V max V = 5 V, I = 1.6 mA. OL DD SINK Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary 5 POWER REQUIREMENTS Power Supply Voltage VDD − GND 2.5/5.25 V min/max Power Supply Currents 6 I Current 75 µA max 65 µA typ, V = 3.6 V, unbuffered mode. DD DD 145 µA max 130 µA typ, V = 3.6 V, buffered mode. DD 80 µA max 73 µA typ, VDD = 5.25 V, unbuffered mode. 160 µA max 145 µA typ, VDD = 5.25 V, buffered mode. IDD (Power-Down Mode) 1 µA max 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V). 3 The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4 FS[2:0] are the three bits used in the filter register to select the output word rate. 5 Digital inputs equal to V or GND. DD 6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14). Rev. 0 | Page 4 of 20 AD7787 TIMING CHARACTERISTICS Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 3 and Figure 4). VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments t 100 ns min SCLK High Pulse Width 3 t4 100 ns min SCLK Low Pulse Width Read Operation t 0 ns min CS Falling Edge to DOUT/RDY Active Time 1 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD 1 2 t2 0 ns min SCLK Active Edge to Data Valid Delay 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V 3, 4 t 10 ns min Bus Relinquish Time after CS Inactive Edge 5 80 ns max t 100 ns max 6 SCLK Inactive Edge to CS Inactive Edge t7 10 ns min SCLK Inactive Edge to DOUT/RDY High Write Operation 2 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 8 t 30 ns min Data Valid to SCLK Edge Setup Time 9 t 25 ns min Data Valid to SCLK Edge Hold Time 10 t11 0 ns min CS Rising Edge to SCLK Edge Hold Time 1 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 2 The SCLK active edge is the falling edge of SCLK. 3 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 4 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. Rev. 0 | Page 5 of 20 AD7787 I (1.6mA WITH V = 5V, SINK DD 100µA WITH V = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH V = 5V, SOURCE DD 100µA WITH V = 3V) DD Figure 2. Load Circuit for Timing Characterization CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 8 11 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. 0 | Page 6 of 20 04477-0-002 04477-0-004 04477-0-003 AD7787 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating V to GND −0.3 V to +7 V DD Stresses above those listed under Absolute Maximum Ratings Analog Input Voltage to GND −0.3 V to V + 0.3 V DD may cause permanent damage to the device. This is a stress Reference Input Voltage to GND −0.3 V to VDD + 0.3 V rating only; functional operation of the device at these or any Total AIN/REFIN Current (Indefinite) 30 mA other conditions above those listed in the operational sections Digital Input Voltage to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Digital Output Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Operating Temperature Range −40°C to +105°C device reliability. Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C MSOP θJA Thermal Impedance 206°C/W θ Thermal Impedance 44°C/W JC Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 20 AD7787 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN CS 2 9 DOUT/RDY AD7787 AIN1(+) 3 8 V DD TOP VIEW (Not to Scale) AIN1(–) 4 7 GND REFIN 5 6 AIN2 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 3 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 4 AIN1(–) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 5 REFIN Reference Input. REFIN can be anywhere between VDD and GND + 0.1 V. The nominal reference voltage is 2.5 V, but the part functions with a reference from 0.1 V to VDD. 6 AIN2 Analog Input. AIN2 is a single-ended analog input. 7 GND Ground Reference Point. 8 V Supply Voltage, 2.5 V to 5.25 V. DD 9 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated, but the RDY bit remains active. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers 10 DIN within the ADC; the register selection bits of the communications register identifying the appropriate register. Rev. 0 | Page 8 of 20 04477-0-005 AD7787 TYPICAL PERFORMANCE CHARACTERISTICS 0 9 V = 3V DD –10 = 2.048V V REF 8 1.1875Hz UPDATE RATE –20 T = 25°C A 7 RMS NOISE = 1.25µF –30 –40 6 –50 5 –60 4 –70 –80 3 –90 2 –100 1 –110 –120 0 04 200 6080 100 120 140 160 8388592 8388616 FREQUENCY (Hz) CODE Figure 6. Frequency Response with 16.6 Hz Update Rate Figure 9. Noise Histogram for Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1) 8388616 V = 3V DD 100 V = 2.048V REF 9.5Hz UPDATE RATE T = 25°C A RMS NOISE = 1µV 80 60 40 20 V = 3V, V = 2.048V DD REF 1.1875Hz UPDATE RATE T = 25°C, RMS NOISE = 1.25µF A 0 8388592 8388591 8388619 0 20406080 100 CODE READ NO. Figure 10. Noise Plot in Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1) Figure 7. Noise Distribution Histogram (CDIV1 = CDIV0 = 0) 8388619 3.0 V = 5V DD UPDATE RATE = 16.6Hz T = 25°C A 2.5 2.0 1.5 1.0 0.5 V = 3V, V = 2.048V, 9.5Hz UPDATE RATE DD REF T = 25°C, RMS NOISE = 1µV A 0 8388591 0 200 400 600 800 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) READ NO. REF Figure 11. RMS Noise vs. Reference Voltage Figure 8. Typical Noise Plot with 16.6 Hz Update Rate (CDIV1 = CD1V0 = 0) Rev. 0 | Page 9 of 20 OCCURRENCE dB CODE 04477-0-010 04477-0-012 04477-0-011 OCCURRENCE RMS NOISE (µV) CODE 04477-0-014 04477-0-015 04477-0-013 AD7787 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN (0) 0 (0) RS1 (0) RS0 (0) R/W (0) CREAD (0) CH1 (0) CH0 (0) Table 5. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. CR6 0 This bit must be programmed to Logic 0 for correct operation. CR5 to RS1 to Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected during CR4 RS0 this serial interface communication (see Table 6). CR3 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 00111100 (Channel AIN1) or 00111101 (Channel AIN2) must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. CR1 to CH1 to These bits are used to select the analog input channel. Channel AIN1 or AIN2 can be selected or an internal short CR0 CH0 (AIN1(−)/AIN1(−)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring power supply variation. To perform this measurement, the power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source when this channel is selected. Any change in channel resets the filter and a new conversion is started. Table 6. Register Selection RS1 RS0 Register Register Size 0 0 Communications Register during a Write Operation 8-Bit 0 0 Status Register during a Read Operation 8-Bit 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register 24-Bit Rev. 0 | Page 10 of 20 AD7787 Table 7. Channel Selection CH1 CH0 Channel 0 0 AIN1(+) − AIN1(−) 0 1 AIN2 1 0 AIN1(−) − AIN1(−) 1 1 V Monitor DD STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY (1) ERR (0) 0 (0) 0 (0) 1 (1) 1 (1) CH1 (0) CH0 (0) Table 8. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write operation to start a conversion. SR5 to 0 These bits are automatically cleared. SR4 SR3 to 1 These bits are automatically set. SR2 SR1 to CH1 to These bits indicate which channel is being converted by the ADC. SR0 CH0 Rev. 0 | Page 11 of 20 AD7787 MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0×02) The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 9 outlines the bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the bit. RDY MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD1 (0) MD0 (0) 0 (0) 0 (0) BO (0) U/B (0) BUF (1) 0 (0) Table 9. Mode Register Bit Designations Bit Bit Location Name Description MR7 to MD1 to Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby MR6 MD0 mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/fADC while subsequent conversions are available at a frequency of fADC. In single conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/f . The conversion result is placed in the data register, ADC RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed (see Table 10). MR5 to 0 These bits must be programmed with a Logic 0 for correct operation. MR4 MR3 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active. MR2 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input results in 0x000000 output and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF. MR1 BUF Configures the AD7787 for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the device operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR0 0 This bit must be programmed with a Logic 0 for correct operation. Table 10. Operating Modes MD1 MD0 Mode 0 0 Continuous Conversion Mode (Default) 0 1 Reserved 1 0 Single Conversion Mode 1 1 Power-Down Mode Rev. 0 | Page 12 of 20 AD7787 FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04) The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 0 (0) 0 (0) CDIV1 (0) CDIV0 (0) 0 (0) FS2 (1) FS1 (0) FS0 (0) Table 11. Filter Register Bit Designations Bit Location Bit Name Description FR7 to 0 These bits must be programmed with a Logic 0 for correct operation. FR6 FR5 to CLKDIV1 These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the FR4 to CDIV0 power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also. 00 Normal Mode 01 Clock Divided by 2 10 Clock Divided by 4 11 Clock Divided by 8 FR3 0 This bit must be programmed with a Logic 0 for correct operation. FR2 to FS2 to FS0 These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the FR0 noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes, the update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2, the corresponding update rates are divided by 2 also. Table 12. Update Rates FS2 FS1 FS0 fADC (Hz) f3dB (Hz) RMS Noise (µV) Rejection 0 0 0 120 28 40 25 dB @ 60 Hz 0 0 1 100 24 25 25 dB @ 50 Hz 0 1 0 33.3 8 3.36 0 1 1 20 4.7 1.6 80 dB @ 60 Hz 1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting) 1 0 1 16.7 4 1.5 80 dB @ 50 Hz 1 1 0 13.3 3.2 1.2 1 1 1 9.5 2.3 1.1 67 dB @ 50 Hz/60 Hz DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. Rev. 0 | Page 13 of 20 AD7787 ADC CIRCUIT INFORMATION of 2.5 V. These numbers are typical and generated with a OVERVIEW differential input voltage of 0 V. The peak-to-peak resolution The AD7787 is a low power ADC that incorporates an Σ-Δ figures represent the resolution for which there is no code modulator, a buffer, and an on-chip digital filter intended for flicker within a six-sigma limit. The output noise comes from the measurement of wide dynamic range, low frequency signals, two sources. The first is the electrical noise in the semiconductor such as those in pressure transducers, weigh scales, and devices (device noise) used in the implementation of the temperature measurement applications. modulator. The second is quantization noise, which is added when the analog input is converted into the digital domain. The device The part has one differential input and one single-ended input. The noise is at a low level and is independent of frequency. The inputs can be operated in buffered or unbuffered mode. Buffering quantization noise starts at an even lower level but rises rapidly the input channel means that the part can accommodate significant with increasing frequency to become the dominant noise source. source impedances on the analog input .The device requires an external reference of 2.5 nominal. Figure 12 shows the basic connections required to operate the part. Table 13. Typical Peak-to-Peak Resolution (Effective Resolution) vs. Update Rate POWER SUPPLY Peak-to-Peak Effective Update Rate Resolution Resolution 0.1µF 10µF 9.5 19.5 22 13.3 19 21.5 V DD 16.7 19 21.5 REFIN IN+ 16.6 19 21.5 AD7787 20 18.5 21 OUT– OUT+ CS AIN+ 33.3 17.5 20 DOUT/RDY MICROCONTROLLER AIN– SCLK 100 14.5 17 IN– DIN 10kΩ 120 14 16.5 AIN2 GND THERMISTOR REDUCED CURRENT MODES The AD7787 has a current consumption of 160 µA maximum Figure 12. Basic Connection Diagram when operated with a 5 V power supply, the buffer enabled, and The output rate of the AD7787 (fADC) is user programmable the clock operating at its maximum speed. The clock frequency with the settling time equal to 2 × tADC. Normal mode rejection can be divided by a factor of 2, 4, or 8 before being applied to is the major function of the digital filter. Table 12 lists the the modulator and filter, resulting in a reduction in the current available update rates from the AD7787. Simultaneous 50 Hz consumption of the AD7787. Bits CDIV1 and CDIV0 in the and 60 Hz rejection is optimized when the update rate equals filter register are used to enter these low power modes (see 16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this Table 14). update rate (see Figure 6). When the internal clock is reduced, the update rate is also NOISE PERFORMANCE reduced. For example, if the filter bits are set to give an update rate of 16.6 Hz when the AD7787 is operated in full power Table 13 shows the output rms noise, rms resolution, and peak- mode, the update rate equals 8.3 Hz in divide-by-2 mode. In the to-peak resolution (rounded to the nearest 0.5 LSB) for the low power modes, there may be some degradation in the ADC different update rates and input ranges for the AD7787. The performance. numbers given are for the bipolar input range with a reference Table 14. Low Power Mode Selection CDIV[1:0] Clock Typ Current, Buffered (µA) Typ Current, Unbuffered (µA) 50 Hz/60 Hz Rejection (dB) 00 1 146 75 65 10 1/2 87 45 64 10 1/4 56 30 75 11 1/8 41 25 86 Rev. 0 | Page 14 of 20 04477-0-006 AD7787 DIGITAL INTERFACE operation to the input shift register. In all modes, except As previously outlined, the AD7787’s programmable functions continuous read mode, it is possible to read the same word from are controlled using a set of on-chip registers. Data is written to the data register several times even though the DOUT/RDY line these registers via the part’s serial interface and read access to returns high after the first read operation. However, care must be the on-chip registers is also provided by this interface. All taken to ensure that the read operations have been completed communications with the part must start with a write to the before the next output update occurs. In continuous read mode, the communications register. After power-on or reset, the device data register can only be read once. expects a write to its communications register. The data written to this register determines whether the next operation is a read The serial interface can operate in 3-wire mode by tying CS low. operation or a write operation and also determines to which In this case, the SCLK, DIN, and DOUT/ lines are used to RDY register this read or write operation occurs. Therefore, write communicate with the AD7787. The end of the conversion can access to any of the other registers on the part begins with a be monitored using the bit in the status register. This RDY write operation to the communications register followed by a scheme is suitable for interfacing to microcontrollers. If CS is write to the selected register. A read operation from any other required as a decoding signal, it can be generated from a port register (except when continuous read mode is selected) starts pin. For microcontroller interfaces, it is recommended that with a write to the communications register followed by a read SCLK idle high between data transfers. operation from the selected register. The AD7787 can be operated with being used as a frame CS The AD7787’s serial interface consists of four signals: CS, DIN, synchronization signal. This scheme is useful for DSP interfaces. SCLK, and DOUT/ . The DIN line is used to transfer data RDY In this case, the first bit (MSB) is effectively clocked out by , CS into the on-chip registers while DOUT/RDY is used for because CS would normally occur after the falling edge of SCLK accessing data from the on-chip registers. SCLK is the serial in DSPs. The SCLK can continue to run between data transfers, clock input for the device and all data transfers (either on DIN provided the timing numbers are obeyed. or DOUT/RDY) occur with respect to the SCLK signal. The serial interface can be reset by writing a series of 1s to the The DOUT/ RDY pin operates as a data-ready signal as well as DIN input. If a Logic 1 is written to the AD7787 line for at least a DOUT pin. Each time a conversion is available in the output 32 serial clock cycles, the serial interface is reset. In 3-wire register, DOUT/RDY goes low. DOUT/RDY resets high when a systems, this ensures that the interface can be reset to a known read operation from the data register is completed. It also goes state if the interface gets lost due to a software error or some high prior to the updating of the data register to indicate when glitch in the system. Reset returns the interface to the state in not to read from the device to ensure that a data read is not which it is expecting a write to the communications register. is used to attempted while the register is being updated. CS This operation resets the contents of all registers to their power- select a device. It can be used to decode the AD7787 in systems on values. where several components are connected to the serial bus. The AD7787 can be configured to continuously convert or to Figure 3 and Figure 4 show timing diagrams for interfacing to perform a single conversion (see Figure 13 through Figure 15). the AD7787 with being used to decode the part. Figure 3 CS shows the timing for a read operation from the AD7787’s output shift register, while Figure 4 shows the timing for a write CS 0x10 0x82 0x10 0x82 DIN DATA DATA DOUT/RDY SCLK Figure 13. Single Conversion Rev. 0 | Page 15 of 20 04477-0-007 AD7787 Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7787 is placed in shutdown This is the default power-up mode. The AD7787 will mode between conversions. When a single conversion is continuously converts with the RDY pin in the status register initiated by setting MD1 to 1 and MD0 to 0 in the mode going low each time a conversion is complete. If is low, the CS register, the AD7787 powers up, performs a single conversion, DOUT/RDY line also goes low when a conversion is complete. and then returns to shutdown mode. When a single conversion To read a conversion, the user can write to the communications is initiated, the AD7787’s oscillator requires 1 ms to power up register, indicating that the next operation is a read of the data and settle. The AD7787 then performs a conversion which register. The digital conversion is placed on the DOUT/ RDY requires 2 × t . DOUT/ is high while the conversion is ADC RDY pin as soon as SCLK pulses are applied to the ADC. being performed and goes low to indicate the completion of the DOUT/RDY returns high when the conversion is read. The user conversion. When the data word has been read from the data can read this register additional times, if required. However, the register, DOUT/ goes high. If is low, DOUT/ RDY CS RDY user must ensure that the data register is not being accessed at remains high until another conversion is initiated and the completion of the next conversion or the new conversion completed. The data register can be read several times, if word is lost. required, even when DOUT/RDY has gone high. CS 0x38 0x38 DIN DATA DATA DOUT/RDY SCLK Figure 14. Continuous Conversion Rev. 0 | Page 16 of 20 04477-0-009 AD7787 Continuous Read Mode read before the next conversion is complete. If the user has not read the conversion before the completion of the next Rather than write to the communications register each time a conversion, or if insufficient serial clocks are applied to the conversion is complete to access the data, the AD7787 can be AD7787 to read the word, the serial output register is reset placed in continuous read mode. By writing 00111100 when the next conversion is complete, and the new conversion (Channel AIN1) or 00111101 (Channel AIN2) to the is placed in the output serial register. communications register, the user only needs to apply the appropriate number of SCLK cycles to the ADC, and the 24-bit To exit the continuous read mode, the instruction 001110XX word is automatically placed on the DOUT/ line when a RDY must be written to the communications register while the RDY conversion is complete. pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the When DOUT/RDY goes low to indicate the end of a instruction to exit the continuous read mode. Additionally, a conversion, sufficient SCLK cycles must be applied to the ADC, reset occurs if 32 consecutive 1s are seen on DIN. Therefore, and the data conversion is placed on the DOUT/RDY line. DIN should be held low in continuous read mode until an When the conversion is read, DOUT/RDY returns high until instruction is written to the device. the next conversion is available. In this mode, the data can only be read once. Also, the user must ensure that the data-word is CS 0x3C DIN DATA DATA DATA DOUT/RDY SCLK Figure 15. Continuous Read Rev. 0 | Page 17 of 20 04477-0-008 AD7787 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7787 has two analog input channels that are connected The voltage on AIN2 is referenced to GND. Therefore, when to the on-chip buffer amplifier when the device is operated in bipolar mode is selected and the part is operated in unbuffered buffered mode and directly to the modulator when the device is mode, the voltage on AIN2 can vary from GND − 100 mV to operated in unbuffered mode. In buffered mode (the BUF bit in +2.5 V. In unipolar mode, the voltage on AIN2 can vary from the mode register is set to 1), the input channel feeds into a high 0 V to 2.5 V. The bipolar/unipolar option is chosen by impedance input stage of the buffer amplifier. Therefore, the programming the U/B bit in the mode register. input can tolerate significant source impedances and is tailored DATA OUTPUT CODING for direct connection to external resistive-type sensors, such as strain gauges or resistance temperature detectors (RTDs). When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input When BUF = 0, the part is operated in unbuffered mode. voltage resulting in a code of 00...00, a midscale voltage This results in a higher analog input current. Note that this resulting in a code of 100...000, and a full-scale input voltage unbuffered input path provides a dynamic load to the driving resulting in a code of 111...111. The output code for any analog source. Therefore, resistor/capacitor combinations on the input input voltage can be represented as pins can cause dc gain errors, depending on the output N impedance of the source that is driving the ADC input. Table 15 Code= 2 ×(AIN /V ) REF shows the allowable external resistance/capacitance values for the unbuffered mode such that no gain error at the 20-bit level When the ADC is configured for bipolar operation, the output is introduced. code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting Table 15. External R-C Combination for No 20-Bit Gain Error in a code of 100...000, and a positive full-scale input voltage C (pF) R (Ω) resulting in a code of 111...111. The output code for any analog 50 16.7 k input voltage can be represented as 100 9.6 k 500 2.2 k N−1 Code= 2 ×[(AIN /V )+1] REF 1000 1.1 k 5000 160 where AIN is the analog input voltage and N = 24. REFERENCE INPUT The absolute input voltage range in buffered mode is restricted The AD7787 has a single-ended reference that is 2.5 V nominal, to a range between GND + 100 mV and VDD − 100 mV. Care but the AD7787 is functional with reference voltages from 0.1 V must be taken in setting up the common-mode voltage so that to VDD. In applications where the excitation (voltage or current) these limits are not exceeded. Otherwise, there is degradation in for the transducer on the analog input also drives the reference linearity and noise performance. voltage for the part, the effect of the low frequency noise in the The absolute input voltage in unbuffered mode includes the excitation source is removed because the application is range between GND − 100 mV and V + 30 mV resulting from DD ratiometric. If the AD7787 is used in a nonratiometric being unbuffered. The negative absolute input voltage limit does application, a low noise reference should be used. allow the possibility of monitoring small true bipolar signals Recommended 2.5 V reference voltage sources for the AD7787 with respect to GND. include the ADR381 and ADR391, which are low noise, low BIPOLAR/UNIPOLAR CONFIGURATION power references. In a system that operates from a 2.5 V power supply, the reference voltage source requires some headroom. In The analog input to the AD7787 can accept either unipolar or this case, a 2.048 V reference, such as the ADR380 or ADR390, bipolar input voltage ranges. Unipolar and bipolar signals on the can be used, requiring only 300 mV of headroom. Also note that AIN1(+) input are referenced to the voltage on the AIN(−) the reference input provides a high impedance, dynamic load. input. For example, if AIN1(−) is 2.5 V and the ADC is Because the input impedance of the reference input is dynamic, configured for unipolar mode, the input voltage range on the resistor/capacitor combinations on this input can cause dc gain AIN1(+) pin is 2.5 V to 5 V when REFIN = 2.5 V. If the ADC is errors, depending on the output impedance of the source configured for bipolar mode, the analog input range on the driving the reference inputs. AIN1(+) input is 0 V to 5 V. Rev. 0 | Page 18 of 20 AD7787 Reference voltage sources like those previously recommended, possible to the paths the currents took to reach their e.g., ADR391, will typically have low output impedances and are, destinations. Avoid forcing digital currents to flow through the therefore, tolerant to having decoupling capacitors on REFIN AGND sections of the layout. without introducing gain errors in the system. Deriving the The AD7787’s ground plane should be allowed to run under the reference input voltage across an external resistor means that AD7787 to prevent noise coupling. The power supply lines to the reference input sees a significant external source impedance. the AD7787 should use as wide a trace as possible to provide External decoupling on the REFIN pin is not recommended in low impedance paths and reduce the effects of glitches on the this type of circuit configuration. power supply line. Fast switching signals, such as clocks, should V MONITOR be shielded with digital ground to avoid radiating noise to other DD sections of the board, and clock signals should never be run Along with converting external voltages, the AD7787 can near the analog inputs. Avoid crossover of digital and analog monitor the voltage on the VDD pin. When the CH1 and CH0 signals. Traces on opposite sides of the board should run at bits in the communications register are set to 1, the voltage on right angles to each other. This reduces the effects of the V pin is internally attenuated by 5 and the resultant DD feedthrough through the board. A microstrip technique is by far voltage is applied to the Σ-Δ modulator using an internal the best, but it is not always possible with a double-sided board. 1.17 V reference for the analog-to-digital conversion. This is In this technique, the component side of the board is dedicated useful because variations in the power supply voltage can be to ground planes, while signals are placed on the solder side. monitored. Good decoupling is important when using high resolution GROUNDING AND LAYOUT ADCs. VDD should be decoupled with 10 µF tantalum in parallel The digital filter provides rejection of broadband noise on the with 0.1 µF capacitors to GND. To achieve the best from these power supply, except at integer multiples of the modulator decoupling components, they should be placed as close as sampling frequency. The digital filter also removes noise from possible to the device, ideally right up against the device. All the analog and reference inputs, provided that these noise logic chips should be decoupled with 0.1 µF ceramic capacitors sources do not saturate the analog modulator. As a result, the to DGND. AD7787 is more immune to noise interference than a conventional high resolution converter. However, because the APPLICATIONS resolution of the AD7787 is so high, and the noise levels from Battery Monitoring the AD7787 are so low, care must be taken with regard to In battery monitoring, the battery current and voltage are grounding and layout. measured. The current is passed through a 100 µΩ resistor. Because the current is from −200 A to +2000 A, the result is a The printed circuit board that houses the AD7787 should be voltage from −20 mV to +200 mV. Channel AIN1 of the designed such that the analog and digital sections are separated AD7787 can be connected directly to the shunt resistor to and confined to certain areas of the board. A minimum etch measure this current. The battery voltage can vary from 12 V to technique is generally best for ground planes because it gives 42 V with peaks up to 60 V. This voltage is attenuated using an the best shielding. external resistor network before being applied to the AD7787. It is recommended that the AD7787’s GND pin be tied to the The buffers onboard the AD7787 mean that channel AIN2 can be connected directly to the high impedance attenuator circuit AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, without introducing gain errors. ensuring that the return paths for all currents are as close as GND V REFIN DD AD7787 DOUT/RDY SERIAL AIN1(+) DIN INTERFACE AND SCLK Σ-∆ LOGIC AIN1(–) R MUX SHUNT ADC CONTROL CS 100µΩ + – –200A TO 12V OR 42V AIN2 +2000A (60V PEAK) ATTENUATION CIRCUIT Figure 16. Battery Monitoring Rev. 0 | Page 19 of 20 04477-0-016 AD7787 OUTLINE DIMENSIONS 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.27 0.60 SEATING 0.23 0° 0.00 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA Figure 17. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Models Temperature Range Package Description Package Option Branding AD7787BRM −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C1T AD7787BRM-REEL −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C1T EVAL-AD7787EB Evaluation Board © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04477–0–4/04(0) Rev. 0 | Page 20 of 20