ANALOG DEVICES AD7783

Read-Only, Pin Configured 24-Bit �-� ADC with Excitation Current Sources AD7783 FEATURES FUNCTIONAL BLOCK DIAGRAM Single-Channel, 24-Bit �-� ADC V REFIN(–) XTAL1 XTAL2 DD GND REFIN(+) Pin Configurable (No Programmable Registers) ISOURCE Select™ V DD IEXC1 IEXC2 Pin Programmable Input Ranges (±2.56 V or ±160 mV) 200�A 200�A IOUT1 Fixed 19.79 Hz Update Rate OSCILLATOR AND Simultaneous 50 Hz and 60 Hz Rejection PLL IOUT2 24-Bit No Missing Codes IPIN 18.5-Bit p-p Resolution (±2.56 V Range) DOUT/RDY SERIAL 16.5-Bit p-p Resolution (±160 mV Range) INTERFACE AIN(+) 24-BIT �-� AND MUX BUF PGA SCLK ADC AIN(–) CONTROL INTERFACE LOGIC MODE Master or Slave Mode of Operation Slave Mode CS AD7783 3-Wire Serial ® SPI , QSPI™, MICROWIRE™, and DSP-Compatible Schmitt Trigger on SCLK RANGE POWER Specified for Single 3 V and 5 V Operation BASIC CONNECTION DIAGRAM Normal: 1.3 mA @ 3 V Power-Down: 9 �A POWER SUPPLY ON-CHIP FUNCTIONS V DD Rail-to-Rail Input Buffer and PGA AD7783 APPLICATIONS ANALOG AIN(+) CS INPUT AIN(–) Sensor Measurement DIGITAL DOUT/RDY INTERFACE Industrial Process Control IOUT1 CURRENT SCLK IOUT2 Temperature Measurement SOURCES XTAL1 Pressure Measurement 32.768kHz REFIN(+) REFERENCE CRYSTAL Weigh Scales XTAL2 INPUT REFIN(–) Portable Instrumentation GND GENERAL DESCRIPTION The device operates from a 32.768 kHz crystal with an on-chip The AD7783 is a complete analog front end for low frequency PLL generating the required internal operating frequency. The measurement applications. The 24-bit sigma-delta ADC con- output data rate from the part is fixed via the master clock at tains one fully differential input channel that can be configured 19.79 Hz and provides simultaneous 50 Hz and 60 Hz rejection with a gain of 1 or 16 allowing full-scale input signal ranges of at this update rate. At this update rate, 18-bit p-p resolution can ±2.56 V or ±160 mV from a +2.5 V differential reference input. be obtained. It also contains two 200 mA integrated current sources. The part operates from a single 3 V or 5 V supply. When oper- The AD7783 has an extremely simple, read-only digital inter- ating from 3 V supplies, the power dissipation for the part is face that can be operated in master mode or slave mode. 3.9 mW. The AD7783 is available in a 16-lead TSSOP. There are no on-chip registers to be programmed. The input Another part in the AD778x family is the AD7782. It is similar signal range and current source selection are configured using to the AD7783 except it has no integrated current sources and two external pins. two differential input channels. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: © Analog Devices, Inc. All rights reserved. 1 AD7783–SPECIFICATIONS (V = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; DD GND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T to T , unless otherwise noted.) MIN MAX Parameter AD7783B Unit Test Conditions ADC CHANNEL SPECIFICATION Output Update Rate 19.79 Hz nom ADC CHANNEL 2 No Missing Codes 24 Bits min Resolution 16 Bits p-p ±160 mV Range, RANGE = 0 18 Bits p-p ±2.56 V Range, RANGE = 1 Output Noise See Table I 21 ¥ .024 REFIN FSR = Integral Nonlinearity ±10 ppm of FSR max Typically 2 ppm, Gain Offset Error ±3 mV typ AIN(+) = AIN(–) = 2.5 V Offset Error Drift versus Temperature ±10 nV/∞C typ Full-Scale Error ±10 mV typ V = 3 V DD Gain Drift versus Temperature ±0.5 ppm/∞C typ Power Supply Rejection (PSR) 100 dB typ Input Range = ±160 mV, V = 1/16 V IN 85 dB typ Input Range = ±2.56 V, V = 1 V IN ANALOG INPUTS Differential Input Voltage Ranges ±160 mV nom Range = 0 ±2.56 V nom Range = 1 ADC Range Matching ±2 mV typ Input Voltage = 159 mV on Both Ranges Absolute AIN Voltage Limits GND + 100 mV V min V – 100 mV V max DD 2 Analog Input Current DC Input Current ±1nA max DC Input Current Drift ±5pA/∞C typ 2, 3 Normal-Mode Rejection @ 50 Hz 60 dB min 50 Hz ± 1 Hz @ 60 Hz 94 dB min 60 Hz ± 1 Hz Common-Mode Rejection Input Range = ±160 mV, V = 1/16 V IN @ DC 105 dB min 125 dB typ, 110 dB typ when Input Range = ±2.56 V 2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz 2 @ 60 Hz 100 dB min 60 Hz ± 1 Hz REFERENCE INPUT REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) 2 REFIN Voltage Range 1V min V V max DD 2 Absolute REFIN Voltage Limits GND – 30 mV V min V + 30 mV V max DD Average Reference Input Current 0.5 mA/V typ Average Reference Input Current Drift ±0.01 nA/V/∞C typ 2, 3 Normal-Mode Rejection @ 50 Hz 60 dB min 50 Hz ± 1 Hz @ 60 Hz 94 dB min 60 Hz ± 1 Hz Common-Mode Rejection Input Range = ±160 mV, V = 1/16 V IN @ DC 100 dB typ @ 50 Hz 110 dB typ 50 Hz ± 1 Hz @ 60 Hz 110 dB typ 60 Hz ± 1 Hz EXCITATION CURRENT SOURCES (IEXC1, IEXC2) Output Current 200 mA Initial Tolerance at 25∞C ±10 % typ Drift 200 ppm/∞C typ Initial Current Matching at 25∞C ±2.5 % max No Load Drift Matching 20 ppm/∞C typ Line Regulation 2.5 mA/V max V = 5 V ± 5%. Typically 1.25 mA/V. DD Load Regulation 300 nA/V typ Output Compliance V – 0.6 V max DD GND – 30 mV V min –2– REV. C AD7783 Parameter AD7783B Unit Test Conditions LOGIC INPUTS 2 All Inputs Except SCLK and XTAL1 V , Input Low Voltage 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD V , Input High Voltage 2.0 V min V = 3 V or 5 V INH DD 2 SCLK Only (Schmitt-Triggered Input) V 1.4/2 V min/V max V = 5 V T(+) DD V 0.8/1.4 V min/V max V = 5 V T(–) DD V – V 0.3/0.85 V min/V max V = 5 V T(+) T(–) DD V 0.95/2 V min/V max V = 3 V T(+) DD V 0.4/1.1 V min/V max V = 3 V T(–) DD V – V 0.3/0.85 V min/V max V = 3 V T(+) T(–) DD 2 XTAL1 Only V , Input Low Voltage 0.8 V max V = 5 V INL DD V , Input High Voltage 3.5 V min V = 5 V INH DD V , Input Low Voltage 0.4 V max V = 3 V INL DD V , Input High Voltage 2.5 V min V = 3 V INH DD Input Currents ±1 mA max V = V IN DD –70 mA max V = GND, Typically –40 mA at 5 V and IN –20 mA at 3 V Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2) 2 V , Output High Voltage V – 0.6 V min V = 3 V, I = 100 mA OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 3 V, I = 100 mA OL DD SINK 2 V , Output High Voltage 4V min V = 5 V, I = 200 mA OH DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 5 V, I = 1.6 mA OL DD SINK Floating-State Leakage Current ±10 mA max Floating-State Output Capacitance ±10 pF typ Data Output Coding Offset Binary START-UP TIME From Power-On 300 ms typ POWER REQUIREMENTS Power Supply Voltage V – GND 2.7/3.6 V min/V max V = 3 V nom DD DD 4.75/5.25 V min/V max V = 5 V nom DD Power Supply Currents 4 I Current (Normal Mode) 1.5 mA max V = 3 V, 1.3 mA typ DD DD 1.7 mA max V = 5 V, 1.5 mA typ DD I (Power-Down Mode, CS = 1) 9 mA max V = 3 V, 6 mA typ DD DD 24 mA max V = 5 V, 20 mA typ DD NOTES 1 Temperature range –40∞C to +85∞C. 2 Guaranteed by design and/or characterization data on production release. 3 When a 28.8 kHz crystal is used, normal-mode rejection is improved so that the rejection equals 75 dB at 50 Hz ±1 Hz and equals 66 dB at 60 Hz ±1 Hz. 4 Normal mode refers to the case where the ADC is running. Specifications subject to change without notice. REV. C –3– AD7783 1, 2 TIMING CHARACTERISTICS (V = 2.7 V to 3.6 V or V = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; DD DD Input Logic 0 = 0 V, Logic 1 = V , unless otherwise noted.) DD Limit at T , T MIN MAX Parameter (B Version) Unit Conditions/Comments t 30.5176 ms typ Crystal Oscillator Period 1 t 50.54 ms typ 19.79 Hz Update Rate ADC t 0 ns min CS Falling Edge to DOUT Active 2 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.7 V to 3.6 V DD t 2 ¥ t ns typ Channel Settling Time 3 ADC 3 4 t 0 ns min SCLK Active Edge to Data Valid Delay 4 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.7 V to 3.6 V DD 5 t 10 ns min Bus Relinquish Time after CS Inactive Edge 7 80 ns max t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 8 t 10 ns min SCLK Inactive to DOUT High 9 80 ns max Slave Mode Timing t 100 ns min SCLK High Pulse Width 5 t 100 ns min SCLK Low Pulse Width 6 Master Mode Timing t t /2 ms typ SCLK High Pulse Width 5 1 t t /2 ms typ SCLK Low Pulse Width 6 1 4 t t /2 ms min DOUT Low to First SCLK Active Edge 10 1 3t /2 ms max 1 NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DD 2 See Figure 2. 3 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin- quish times of the part and as such are independent of external bus loading capacitances. I ( 1.6mA WITH V = 5V SINK DD 100�A WITH V = 3V) DD TO OUTPUT 1.6V PIN 50pF I ( 200�A WITH V = 5V SOURCE DD 100�A WITH V = 3V) DD Figure 1. Load Circuit for Timing Characterization –4– REV. C AD7783 CS (I) t 2 t 8 t 7 t 3 DOUT/RDY (O) MSB MSB LSB LSB t t 4 9 t 6 SLAVE MODE SCLK (I) t 5 t 4 t 10 t MASTER MODE 6 SCLK (O) t 5 I = INPUT TO AD7783, AND O = OUTPUT FROM AD7783. SLAVE MODE IS SELECTED BY TYING THE MODE PIN +,*+, WHILE MASTER MODE IS SELECTED BY TYING THE MODE PIN /2:. Figure 2. Slave/Master Mode Timing Diagram ABSOLUTE MAXIMUM RATINGS* TSSOP Package (T = 25∞C, unless otherwise noted.) A � Thermal Impedance . . . . . . . . . . . . . . . . . . . . 97.9∞C/W JA V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14∞C/W DD JC Analog Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V Lead Temperature, Soldering DD Reference Input Voltage to GND . . . . –0.3 V to V + 0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C DD Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . 30 mA Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V DD *Stresses above those listed under Absolute Maximum Ratings may cause per- Digital Output Voltage to GND . . . . . –0.3 V to V + 0.3 V manent damage to the device. This is a stress rating only; functional operation of DD the device at these or any other conditions above those listed in the operational Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C sections of this specification is not implied. Exposure to absolute maximum rating Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C conditions for extended periods may affect device reliability. Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7783 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –5– AD7783 PIN CONFIGURATION XTAL1 1 16 XTAL2 V REFIN(+) 2 15 DD 3 14 REFIN(–) GND 4 AIN(+) AD7783 13 MODE TOP VIEW 5 12 DOUT/RDY AIN(–) (Not to Scale) 6 IOUT1 11 CS 7 10 SCLK IOUT2 IPIN 8 9 RANGE PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 XTAL1 Input to the 32.768 kHz Crystal Oscillator Inverter. 2 REFIN(+) Positive Reference Input. REFIN(+) can lie anywhere between V and GND + 1 V. The nominal refer- DD ence voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 1 V to V . DD 3REFIN(–)Negative Reference Input. This reference input can lie anywhere between GND and V – 1 V. DD 4 AIN(+) Analog Input. AIN(+) is the positive terminal of the fully differential analog input pair AIN(+)/AIN(–). 5 AIN(–)Analog Input. AIN(–) is the negative terminal of the fully differential analog input pair AIN(+)/AIN(–). 6 IOUT1 Output from Internal 200 mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be switched to this output using hardware control pin IPIN. 7 IOUT2 Output from Internal 200 mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be switched to this output using hardware control pin IPIN. 8 IPIN Logic Input that Selects the Routing of the On-Chip Current Sources. When IPIN is tied to GND, IEXC1 is routed to IOUT1 and IEXC2 is routed to IOUT2. When IPIN is tied to V , IEXC1 is routed to DD IOUT2 and IEXC2 is routed to IOUT1. 9 RANGE Logic Input that Configures the Input Range on the Internal PGA. With RANGE = 0, the full-scale input range is ±160 mV; the full-scale input range equals ±2.56 V when RANGE = 1 for a 2.5 V reference. 10 SCLK Serial Clock Input/Output for Data Transfers from the ADC. When the device is operated in master mode, SCLK is an output with one SCLK period equal to one XTAL period. In slave mode, SCLK is generated by an external source. In slave mode, all the data can be transmitted on a continuous train of pulses. Alter- natively, it can be a noncontinuous clock with the information being transmitted from the AD7783 in smaller batches of data. SCLK is Schmitt triggered (slave mode), making the interface suitable for opto- isolated applications. 11 CS Chip Select Input. CS is an active low logic input used to select the AD7783. When CS is low, the PLL establishes lock and allows the AD7783 to initiate a conversion. When CS is high, the conversion is aborted, DOUT and SCLK are three-stated, the AD7783 enters standby mode, and any conversion result in the output shift register is lost. 12 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose in this interface. When a conver- sion is initiated, DOUT/RDY goes high and remains high until the conversion is complete. DOUT/RDY will then return low to indicate that valid data is available to be read from the device. In slave mode, this acts as an interrupt to the processor, indicating that valid data is available. If data is not read after a conversion, DOUT/RDY will go high before the next update occurs. In master mode, DOUT/RDY goes low for at least half an SCLK cycle before the device produces SCLKs. When SCLK becomes active, data is output on the DOUT/RDY pin. Data is output on the falling SCLK edge and is valid on the rising edge. 13 MODE The MODE pin selects master or slave mode of operation. When MODE = 0, the AD7783 operates in master mode; the AD7783 is configured for slave mode when MODE = 1. 14 GND Ground Reference Point for the AD7783. 15 V Supply Voltage, 3 V or 5 V Nominal. DD 16 XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter. –6– REV. C Typical Performance Characteristics–AD7783 3.0 9 8 �2.56V RANGE 2.5 7 2.0 6 V = 5V DD 5 V = 2.5V REF 1.5 T = 25�C A 4 �160mV RANGE 1.0 3 2 0.5 1 0 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) REF TPC 1. Noise Distribution Histogram TPC 2. RMS Noise vs. Reference Input ADC CIRCUIT INFORMATION Overview The output rate of the AD7783 (f ) equals ADC The AD7783 incorporates a S-D ADC channel, on-chip pro- 3 grammable gain amplifier, and on-chip digital filtering intended f =¥ 32./ 768 10 69¥ 8¥ 3 () ADC for the measurement of wide dynamic range, low frequency while the settling time equals signals such as those in weigh-scale, strain gage, pressure trans- ducer, or temperature measurement applications. Ê 2 ˆ t = =¥ 2 t SETTLE ADC Á ˜ This ADC input is buffered and can be programmed to have an f Ë ADC ¯ input voltage range of ±160 mV or ±2.56 V. The input channel Normal-mode rejection is the major function of the digital filter is configured as a fully differential input. Buffering the input on the AD7783. Simultaneous 50 Hz and 60 Hz rejection of channel means that the part can accommodate significant source better than 60 dB is achieved as notches are placed at both 50 Hz impedances on the analog input and that R, C filtering (for and 60 Hz. Figure 4 shows the filter rejection. noise rejection or RFI reduction) can be placed on the analog input if required. The device requires an external reference of 0 2.5 V nominal. Figure 3 shows the basic connections required to operate the part. –20 POWER –40 SUPPLY 10�F 0.1�F –60 –80 IN+ –100 V DD AD7783 OUT+ –120 OUT– AIN(+) AIN(–) CS –140 IN– �CONTROLLER DOUT/RDY IOUT1 SCLK –160 10k� IOUT2 010 20 30 40 50 608 700 90 100 XTAL1 FREQUENCY (Hz) 32.768kHz REFIN(+) CRYSTAL OUTPUT DATA RATE = 19.8Hz REFIN(–) XTAL2 6k� INPUT BANDWIDTH = 4.74Hz GND 50Hz REJECTION = –66dB, 50Hz �1Hz REJECTION = –60dB 60Hz REJECTION = –117dB, 60Hz �1Hz REJECTION = –94dB Figure 4. Filter Profile (Filter Notches at Both Figure 3. Basic Connection Diagram 50 Hz and 60 Hz) REV. C –7– 8388039 8388382 8388449 8388499 8388547 8388579 8388615 8388657 8388687 8388721 8388754 8388779 8388805 8388841 8388874 8388906 8388941 8388985 8389033 8389110 ATTENUATION (dB) RMS NOISE (�V) AD7783 NOISE PERFORMANCE MASTER MODE (MODE = 0) Table I shows the output rms noise and output peak-to-peak In this mode, SCLK is provided by the AD7783. With CS low, resolution in bits (rounded to the nearest 0.5 LSB) for the two SCLK becomes active when a conversion is complete and gener- input voltage ranges. The numbers are typical and are generated ates 24 falling and rising edges. The DOUT/RDY pin, which is at a differential input voltage of 0 V. The peak-to-peak reso- normally high, goes low to indicate that a conversion is complete. lution figures represent the resolution for which there will be Data is output on the DOUT/RDY pin following the SCLK no code flicker within a six-sigma limit. The output noise comes falling edge and is valid on the SCLK rising edge. When the from two sources. The first is the electrical noise in the semi- 24-bit word has been output, SCLK idles high until the next conductor devices (device noise) used in the implementation of conversion is complete. DOUT/RDY returns high and will remain the modulator. Secondly, when the analog input is converted high until another conversion is available. It then operates as a into the digital domain, quantization noise is added. The device RDY signal again. The part will continue to convert until CS is noise is at a low level and is independent of frequency. The taken high. SCLK and DOUT/RDY are three-stated when CS is quantization noise starts at an even lower level but rises rapidly taken high. with increasing frequency to become the dominant noise source. SLAVE MODE (MODE = 1) Table I. Typical Output RMS Noise and In slave mode, the SCLK is generated externally. SCLK must Peak-to-Peak Resolution vs. Input Range idle high between data transfers. With CS low, DOUT/RDY goes low when a conversion is complete. Twenty-four SCLK Input Range pulses are needed to transfer the digital word from the AD7783. Twenty-four consecutive pulses can be generated or, alterna- ±160 mV ±2.56 V tively, the data transfer can be split into batches. This is useful Noise (mV) 0.65 2.30 when interfacing to a microcontroller that uses 8-bit transfers. Peak-to-Peak Resolution (Bits) 16.5 18.5 Data is output following the SCLK falling edge and is valid on the SCLK rising edge. DIGITAL INTERFACE CIRCUIT DESCRIPTION The AD7783’s serial interface consists of four signals: CS, Analog Input Channel SCLK, DOUT/RDY, and MODE. The MODE pin is used to The ADC has one fully differential input channel. It feeds into a select the master/slave mode of operation. When the part is high impedance input stage of the buffer amplifier. As a result, configured as a master, SCLK is an output; SCLK is an input the ADC input can handle significant source impedances and is when slave mode is selected. Data transfers take place with tailored for direct connection to external resistive-type sensors, respect to this SCLK signal. The DOUT/RDY line is used such as strain gages or resistance temperature detectors (RTDs). for accessing data from the data register. This pin also functions as a RDY line. When a conversion is complete, DOUT/RDY The absolute input voltage range on the ADC input is restricted goes low to indicate that data is ready to be read from the to a range between GND + 100 mV and V – 100 mV. Care DD AD7783’s data register. It is reset high when a read operation must be taken in setting up the common-mode voltage and input from the data register is complete. It also goes high prior to voltage range so that these limits are not exceeded; otherwise, the updating of the output register to indicate when not to there will be a degradation in linearity and noise performance. read from the device to ensure that a data read is not attempted Programmable Gain Amplifier while the register is being updated. The digital conversion is The output from the buffer on the ADC is applied to the input of also output on this pin. the on-chip programmable gain amplifier (PGA). The PGA gain CS is used to select the device and to place the device in standby range is programmed via the RANGE pin. With an external 2.5 V mode. When CS is taken low, the AD7783 is powered up, the reference applied, the PGA can be programmed to have a bipolar PLL locks, and the device initiates a conversion. The device will range of ±160 mV (RANGE = 0) or ±2.56 V (RANGE = 1). continue to convert until CS is taken high. When CS is taken These are the ranges that should appear at the input to the high, the AD7783 is placed in standby mode, minimizing the on-chip PGA. current consumption. The conversion is aborted, DOUT and Bipolar Configuration/Output Coding SCLK are three-stated, and the result in the data register is lost. The analog input on the AD7783 accepts bipolar input voltage Figure 2 shows the timing diagram for interfacing to the AD7783 ranges. Signals on the AIN(+) input of the ADC are referenced with CS used to decode the part. –8– REV. C AD7783 to the voltage on the AIN(–) input. For example, if AIN(–) is Deriving the reference input voltage across an external resistor 2.5 V and the AD7783 is configured for an analog input range will mean that the reference input sees a significant external of ±160 mV, the analog input range on the AIN(+) input is source impedance. External decoupling on the REFIN pins 2.34 V to 2.66 V (i.e., 2.5 V ± 0.16 V). would not be recommended in this type of circuit configuration. The coding is offset binary with a negative full-scale voltage Grounding and Layout resulting in a code of 000 . . . 000, a zero differential voltage Since the analog inputs and reference inputs on the ADC are resulting in a code of 100 . . . 000, and a positive full-scale differential, most of the voltages in the analog modulator are voltage resulting in a code of 111 . . . 111. The output code for common-mode voltages. The excellent common-mode rejection any analog input voltage can be represented as follows: of the part will remove common-mode noise on these inputs. The digital filter will provide rejection of broadband noise on N -1 Code=¥21 AIN¥ GAIN/.024¥V + 1 () () [] REF the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from where AIN is the analog input voltage, GAIN is the PGA gain, the analog and reference inputs, provided these noise sources do i.e., 1 on the ±2.56 V range and 16 on the ±160 mV range, not saturate the analog modulator. As a result, the AD7783 is and N = 24. more immune to noise interference than a conventional high Excitation Currents resolution converter. However, because the resolution of the The AD7783 also contains two matched 200 mA constant cur- AD7783 is so high, and the noise levels from the AD7783 are so rent sources. Both source current from V that is directed to DD low, care must be taken with regard to grounding and layout. either the IOUT1 or IOUT2 pins of the device depending on The printed circuit board that houses the AD7783 should be the polarity of the IPIN pin. These current sources can be used designed such that the analog and digital sections are separated to excite external resistive bridge or RTD sensors. and confined to certain areas of the board. A minimum etch technique is generally best for ground planes as it gives the best Crystal Oscillator shielding. The AD7783 is intended for use with a 32.768 kHz watch crys- tal. A PLL internally locks onto a multiple of this frequency to It is recommended that the AD7783’s GND pin be tied to the provide a stable 4.194304 MHz clock for the ADC. The modu- AGND plane of the system. In any layout, it is important that lator sample rate is the same as the crystal oscillator frequency. the user keep in mind the flow of currents in the system, ensur- The start-up time associated with 32.768 kHz crystals is typically ing that the return paths for all currents are as close as possible 300 ms. In some cases, it will be necessary to connect capacitors to the paths the currents took to reach their destinations. Avoid on the crystal to ensure that it does not oscillate at overtones of forcing digital currents to flow through the AGND sections of its fundamental operating frequency. The values of capacitors will the layout. vary depending on the manufacturer’s specifications. The AD7783’s ground plane should be allowed to run under Reference Input the AD7783 to prevent noise coupling. The power supply lines The AD7783 has a fully differential reference input capability to the AD7783 should use as wide a trace as possible to provide for the channel. The common-mode range for differential inputs low impedance paths and reduce the effects of glitches on the is from GND to V . The reference input is unbuffered, and DD power supply line. Fast switching signals like clocks should be therefore excessive R-C source impedances will introduce gain shielded with digital ground to avoid radiating noise to other errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) sections of the board, and clock signals should never be run is 2.5 V nominal for specified operation, but the AD7783 is near the analog inputs. Avoid crossover of digital and analog functional with reference voltages from 1 V to V . In applica- DD signals. Traces on opposite sides of the board should run at tions where the excitation (voltage or current) for the transducer right angles to each other. This will reduce the effects of on the analog input also drives the reference voltage for the part, feedthrough through the board. A microstrip technique is by far the effect of the low frequency noise in the excitation source will the best but is not always possible with a double-sided board. In be removed as the application is ratiometric. If the AD7783 is this technique, the component side of the board is dedicated to used in a nonratiometric application, a low noise reference should ground planes while signals are placed on the solder side. be used. Recommended reference voltage sources for the AD7783 Good decoupling is important when using high resolution ADCs. include the AD780, REF43, and REF192. It should also be noted V should be decoupled with 10 mF tantalum in parallel with DD that the reference inputs provide a high impedance, dynamic load. 0.1 mF capacitors to GND. To achieve the best from these Because the input impedance of each reference input is dynamic, decoupling components, they have to be placed as close as pos- resistor/capacitor combinations on these inputs can cause dc gain sible to the device, ideally right up against the device. All errors, depending on the output impedance of the source that is logic chips should be decoupled with 0.1 mF ceramic capaci- driving the reference inputs. Recommended reference voltage tors to DGND. sources (e.g., AD780) will typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on the REFIN(+) without introducing gain errors in the system. REV. C –9– AD7783 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0° 0.65 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 1. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7783BRU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7783BRU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7783BRU-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7783BRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7783BRUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 EVAL-AD7783EBZ −40°C to +85°C Evaluation Board 1 Z = RoHS Compliant Part. REVISION HISTORY 10/11—Rev. B to Rev. C Changes to Figure 2 ........................................................................... 5 Changes to Ordering Guide ........................................................... 10 8/04—Data Sheet Changed from Rev. A to Rev. B. Change to Features ............................................................................ 1 Changes to Ordering Guide ............................................................. 5 4/03—Data Sheet Changed from Rev. 0 to Rev. A. Change to Specifications ..................................................................2 Updated Outline Dimensions ........................................................ 10 Rev. C | Page 10 of 12 AD7783 NOTES Rev. C | Page 11 of 12 AD7783 NOTES ©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02702-0-10/11(C) Rev. C | Page 12 of 12