ANALOG DEVICES AD7780

24-Bit, Pin-Programmable, Ultralow Power Sigma-Delta ADC AD7780 FEATURES FUNCTIONAL BLOCK DIAGRAM GND AV GAIN REFIN(+) REFIN(–) DD Pin-programmable filter response Update rate: 10 Hz or 16.7 Hz AIN(+) DOUT/RDY Pin-programmable in-amp gain G = 1 24-BIT Σ-Δ OR 128 ADC Pin-programmable power-down and reset AIN(–) SCLK Status function DV DD BPDSW INTERNAL Internal clock oscillator CLOCK FILTER Internal bridge power-down switch AD7780 PDRST Current Figure 1. 115 μA typical (gain = 1) 330 μA typical (gain = 128) Table 1. Simultaneous 50 Hz/60 Hz rejection Parameter Gain = 128 Gain = 1 Power supply: 2.7 V to 5.25 V Output Data Rate 10 Hz 16.7 Hz 10 Hz 16.7 Hz −40°C to +105°C temperature range RMS Noise 44 nV 65 nV 2.4 μV 2.7 μV Independent interface power supply P-P Resolution 17.6 17.1 18.8 18.7 Packages Settling Time 300 ms 120 ms 300 ms 120 ms 14-lead, narrow body SOIC 16-lead TSSOP 2-wire serial interface (read-only device) SPI compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Pressure measurement Industrial process control Portable instrumentation GENERAL DESCRIPTION The on-chip PGA has a gain of 1 or 128, supporting a full-scale The AD7780 is a complete low power front-end solution for differential input of ±5 V or ±39 mV. The device has two filter bridge sensor products, including weigh scales, strain gages, and response options. The filter response at the 16.7 Hz update rate pressure sensors. It contains a precision, low power, 24-bit sigma- provides superior dynamic performance. The settling time is delta (Σ-Δ) ADC; an on-chip, low noise programmable gain 120 ms at this update rate. At the 10 Hz update rate, the filter amplifier (PGA); and an on-chip oscillator. response provides greater than −45 dB of stop-band attenuation. Consuming only 330 μA, the AD7780 is particularly suitable for In load cell applications, this stop-band rejection is useful to reject portable or battery-operated products where very low power is low frequency mechanical vibrations of the load cell. The settling required. The AD7780 also has a power-down mode that allows time is 300 ms at this update rate. Simultaneous 50 Hz/60 Hz the user to switch off the power to the bridge sensor and power rejection occurs at both the 10 Hz and 16.7 Hz update rates. down the AD7780 when not converting, thus increasing the The AD7780 operates with a power supply from 2.7 V to 5.25 V. battery life of the product. It is available in a narrow body, 14-lead SOIC package and a 16-lead For ease of use, all the features of the AD7780 are controlled by TSSOP package. dedicated pins. Each time a data read occurs, eight status bits are appended to the 24-bit conversion. These status bits contain a pattern sequence that can be used to confirm the validity of the serial transfer. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07945-001 AD7780 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Down/Reset (PDRST) ................................................... 12 Applications ....................................................................................... 1 Analog Input Channel ............................................................... 12 Functional Block Diagram .............................................................. 1 Bipolar Configuration ................................................................ 12 General Description ......................................................................... 1 Data Output Coding .................................................................. 12 Revision History ............................................................................... 2 Reference ..................................................................................... 12 Specif ica t ions ..................................................................................... 3 Bridge Power-Down Switch ...................................................... 13 Timing Characteristics ................................................................ 5 Digital Interface .......................................................................... 13 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 14 Thermal Resistance ...................................................................... 6 Weigh Scales ................................................................................ 14 ESD Caution .................................................................................. 6 Performance in a Weigh Scale System ..................................... 14 Pin Configurations and Function Descriptions ........................... 7 EMI Recommendations ............................................................. 14 Typical Performance Characteristics ............................................. 8 Grounding and Layout .............................................................. 15 Output Noise and Resolution........................................................ 10 Outline Dimensions ....................................................................... 16 Theory of Operation ...................................................................... 11 Ordering Guide .......................................................................... 16 Filter, Data Rate, and Settling Time ......................................... 11 Gain .............................................................................................. 12 REVISION HISTORY 9/09—Rev. 0 to Rev. A Changes to Specifications Table ...................................................... 3 4/09—Revision 0: Initial Version Rev. A | Page 2 of 16 AD7780 SPECIFICATIONS 1 AV = 2.7 V to 5.25 V, V = AV , DV = 2.7 V to 5.25 V, GND = 0 V, all specifications T to T , unless otherwise noted. DD REF DD DD MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL Output Update Rate (f ) 10 Hz FILTER = 1, settling time = 3/f ADC ADC 16.7 Hz FILTER = 0, settling time = 2/f ADC 2 No Missing Codes 24 Bits Resolution Peak-to-Peak See Table 7 and Table 8 RMS Noise See Table 7 and Table 8 Integral Nonlinearity ±6 ppm of FSR Offset Error ±6 μV Gain = 128 with FILTER = 1 ±200 μV Gain = 1 with FILTER = 1 ±1 μV Gain = 128 with FILTER = 0 ±2 μV Gain = 1 with FILTER = 0 Offset Error Drift vs. Temperature ±10 nV/°C Gain = 128 ±150 nV/°C Gain = 1 with FILTER = 1 ±10 nV/°C Gain = 1 with FILTER = 0 Full-Scale Error ±0.25 % of FS Gain Drift vs. Temperature ±2 ppm/°C Power Supply Rejection 100 dB Gain = 128, FILTER = 1, AIN = 7.81 mV 120 dB Gain = 128, FILTER = 0, AIN = 7.81 mV 2 Normal-Mode Rejection 50 Hz, 60 Hz 63 75 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f = ADC 16.7 Hz 50 Hz, 60 Hz 72 90 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f = 10 Hz ADC Common-Mode Rejection DC 90 dB Gain = 1, AIN = 1 V 90 dB Gain = 128, AIN = 7.81 mV 50 Hz, 60 Hz 110 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz ANALOG INPUTS Differential Input Voltage Range ±VREF/gain V VREF = REFIN(+) − REFIN(−), gain = 1 or 128 2 Absolute AIN Voltage Limits GND + 100 mV AVDD − 100 mV V Gain = 1 GND + 450 mV AV − 1.1 V Gain = 128, FILTER = 0 DD GND + 1.1 AVDD − 1.1 V Gain = 128, FILTER = 1, AVDD ≤ 3.6 V GND + 1.5 AV − 1.5 V Gain = 128, FILTER = 1, AV > 3.6 V DD DD Average Input Current ±1 nA Gain = 1 ±250 pA typ Gain = 128 Average Input Current Drift ±3 pA/°C REFERENCE External REFIN Voltage AVDD V REFIN = REFIN(+) − REFIN(−) 2 0.5 AV V Reference Voltage Range DD 2 Absolute REFIN Voltage Limits GND − 30 mV AVDD + 30 mV V Average Reference Input Current 400 nA/V Average Reference Input Current Drift ±0.15 nA/V/°C Normal-Mode Rejection Same as for analog inputs Common-Mode Rejection 110 dB BRIDGE POWER-DOWN SWITCH (BPDSW) Controlled via the PDRST pin R 9 Ω ON 2 Allowable Current 30 mA Continuous current INTERNAL CLOCK Frequency 64 − 3% 64 + 3% kHz Duty Cycle 50:50 % Rev. A | Page 3 of 16 AD7780 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS 2 SCLK, FILTER, GAIN, PDRST Input Low Voltage, VINL 0.4 V DVDD = 3 V 0.8 V DV = 5 V DD Input High Voltage, VINH 1.8 V DVDD = 3 V 2.4 V DV = 5 V DD SCLK (Schmitt-Triggered Input) 100 mV DV = 3 V DD Hysteresis 140 mV DV = 5 V DD Input Currents ±2 μA VIN = DVDD or GND Input Capacitance 10 pF All digital inputs LOGIC OUTPUT (DOUT/RDY) 2 DV − 0.6 V DV = 3 V, I = 100 μA Output High Voltage, VOH DD DD SOURCE 4 V DV = 5 V, I = 200 μA DD SOURCE 2 Output Low Voltage, V 0.4 V DV = 3 V, I = 100 μA OL DD SINK 0.4 V DV = 5 V, I = 1.6 mA DD SINK Floating-State Leakage Current ±2 μA Floating-State Output Capacitance 10 pF Data Output Coding Offset binary 3 POWER REQUIREMENTS Power Supply Voltage AV to GND 2.7 5.25 V DD DV to GND 2.7 5.25 V DD Power Supply Currents I Current 115 μA Gain = 1, AV = 3 V DD DD 130 160 μA Gain = 1, AVDD = 5 V 330 μA Gain = 128, AV = 3 V DD 420 500 μA Gain = 128, AV = 5 V DD IDD (Power-Down/Reset Mode) 10 μA 1 Temperature range is −40°C to +105°C. 2 This specification is not production tested but is supported by characterization data at initial product release. 3 Digital inputs are equal to DV or GND. DD Rev. A | Page 4 of 16 AD7780 TIMING CHARACTERISTICS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 3. 1 Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments 2 Read t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width 3 4 t3 0 ns min SCLK active edge to data valid delay 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t4 10 ns min SCLK inactive edge to DOUT/RDY high 130 ns max Reset t5 100 ns min PDRST low pulse width 5 t6 FILTER/GAIN change to data valid delay 120 ms typ Update rate = 16.7 Hz 300 ms typ Update rate = 10 Hz 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. R F DD 2 See Figure 3. 3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 PDRST The high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle. Circuit and Timing Diagrams I (1.6mA WITH DV = 5V, SINK DD PDRST 100µA WITH DV = 3V) (INPUT) DD t 5 TO OUTPUT 1.6V PIN DOUT/RDY 50pF (OUTPUT) (200µA WITH DV = 5V, I SOURCE DD 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Figure 4. Resetting the AD7780 GAIN OR FILTER DOUT/RDY (INPUT) MSB LSB (OUTPUT) t 6 t t 3 4 t DOUT/RDY 1 (OUTPUT) SCLK (INPUT) t 2 Figure 3. Read Cycle Timing Diagram Figure 5. Changing Gain or Filter Option Rev. A | Page 5 of 16 07945-002 07945-003 07945-004 07945-005 AD7780 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Table 4. soldered in a circuit board for surface-mount packages. Parameter Rating AV to GND −0.3 V to +7 V DD Table 5. DV to GND −0.3 V to +7 V DD Package Type θ θ Unit JA JC Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V 14-Lead SOIC 104.5 42.9 °C/W Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V 16-Lead TSSOP 150.4 27.6 °C/W Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V Digital Output Voltage to GND −0.3 V to DV + 0.3 V DD ESD CAUTION AIN/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 16 AD7780 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 16 NC 2 15 FILTER SCLK DOUT/RDY 3 14 PDRST SCLK 1 14 FILTER AD7780 NC 4 13 DV DOUT/RDY 2 13 PDRST DD TOP VIEW NC 3 12 DV (Not to Scale) GAIN 5 12 AV AD7780 DD DD GAIN 4 TOP VIEW 11 AV DD AIN(+) 6 11 GND (Not to Scale) AIN(+) 5 10 GND AIN(–) 7 10 BPDSW AIN(–) 6 9 BPDSW 8 REFIN(+) 9 REFIN(–) REFIN(+) 7 8 REFIN(–) NC = NO CONNECT NC = NO CONNECT Figure 6. SOIC Pin Configuration Figure 7. TSSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. SOIC TSSOP Mnemonic Description 1 2 SCLK Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt- triggered input. The serial clock can be active only when transferring data from the AD7780. The data from the AD7780 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous during the data transfer, with the information being transmitted from the ADC in smaller data batches. 2 3 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose: as a data ready pin, going low to indicate the completion of a conversion, and as a serial data output pin to access the data register of the ADC. Eight status bits accompany each data read (see Figure 22). The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If the data is not read after the conver- sion, the pin goes high before the next update occurs. The serial interface is reset each time that a conversion is available. Therefore, the user must ensure that any conversions being transmitted are completed before the next conversion is available. 3 1, 4, 16 NC No Connect. This pin can be left floating. 4 5 GAIN Gain Select Pin. When GAIN is low, the gain is set to 128. When GAIN is high, the gain is set to 1. 5 6 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair, AIN(+)/AIN(−). 6 7 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair, AIN(+)/AIN(−). 7 8 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). The nomi- nal reference voltage (REFIN(+) − REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to AV . DD 8 9 REFIN(−) Negative Reference Input. 9 10 BPDSW Bridge Power-Down Switch to GND. When PDRST is high, the bridge power-down switch is closed. When PDRST is low, the switch is opened. 10 11 GND Ground Reference Point. 11 12 AVDD Supply Voltage, 2.7 V to 5.25 V. 12 13 DV Digital Interface Supply Voltage. The logic levels for the serial interface pins and the digital control pins DD are related to this supply, which is between 2.7 V and 5.25 V. The DV voltage is independent of the DD ; therefore, AV can equal 5 V with DV at 3 V or vice versa. voltage on AVDD DD DD 13 14 PDRST Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode, and the low-side power switch is opened. All the logic on the chip is reset, and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC continuously converts. In addition, the low-side power switch is closed. The internal clock requires approximately 1 ms to power up. 14 15 FILTER Filter Select. When FILTER is low, the fast settling filter is selected. The update rate is set to 16.7 Hz, which gives a filter settling time of 120 ms. When FILTER is high, the high rejection filter is selected. The update rate is set to 10 Hz, which gives a filter settling time of 300 ms. With this filter, the stop-band (higher than f ) attenuation is better than −45 dB. ADC Rev. A | Page 7 of 16 07945-006 07945-007 AD7780 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,670 60 8,388,660 8,388,650 8,388,640 40 8,388,630 8,388,620 8,388,610 20 8,388,600 8,388,590 8,388,580 8,388,570 0 0 200 400 600 800 1000 8,388,390 8,388,408 8,388,426 8,388,444 SAMPLE CODE Figure 8. Noise (V = AV , Update Rate = 16.7 Hz, Gain = 128) Figure 11. Noise Distribution Histogram REF DD (V = AV , Update Rate = 10 Hz, Gain = 128) REF DD 60 8,388,630 8,388,625 8,388,620 40 8,388,615 8,388,610 8,388,605 8,388,600 20 8,388,595 8,388,590 0 8,388,585 8,388,570 8,388,594 8,388,618 8,388,642 8,388,666 0 200 400 600 800 1000 CODE SAMPLE Figure 9. Noise Distribution Histogram Figure 12. Noise (VREF = AVDD, Update Rate = 16.7 Hz, Gain = 1) (V = AV , Update Rate = 16.7 Hz, Gain = 128) REF DD 8,388,460 200 8,388,450 150 8,388,440 8,388,430 100 8,388,420 8,388,410 50 8,388,400 8,388,390 0 0 200 400 600 800 1000 8,388,585 8,388,593 8,388,601 8,388,609 8,388,617 8,388,625 SAMPLE CODE Figure 10. Noise (VREF = AVDD, Update Rate = 10 Hz, Gain = 128 ) Figure 13. Noise Distribution Histogram (VREF = AVDD, Update Rate = 16.7 Hz, Gain = 1) Rev. A | Page 8 of 16 CODE CODE OCCURRENCE 07945-009 07945-010 07945-008 CODE OCCURRENCE OCCURRENCE 07945-011 07945-013 07945-012 AD7780 8,388,415 2.0 1.5 8,388,410 1.0 8,388,405 0.5 8,388,400 0 8,388,395 –0.5 8,388,390 –1.0 8,388,385 –1.5 8,388,380 –2.0 0 200 400 600 800 1000 –6 –4 –2 0246 SAMPLE V (V) IN Figure 14. Noise (VREF = AVDD, Update Rate = 10 Hz, Gain = 1) Figure 17. Integral Nonlinearity V = AV , Gain = 1) ( REF DD 100 10 8 6 75 4 2 50 0 –2 –4 25 –6 –8 0 –10 8,388,385 8,388,391 8,388,397 8,388,403 8,388,409 8,388,415 –60 –40 –20 0 20 40 60 80 100 120 CODE TEMPERATURE (°C) Figure 15. Noise Distribution Histogram Figure 18. Offset vs. Temperature (Gain = 128) (V = AV , Update Rate = 10 Hz, Gain = 1) REF DD 150 3.0 2.5 100 2.0 50 1.5 1.0 0 0.5 –50 0 –0.5 –100 –1.0 –150 –1.5 –2.0 –200 –60 –40 –20 0 20 40 60 80 100 120 –2.5 –0.04 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 0.04 TEMPERATURE (°C) V (V) IN Figure 19. Gain Error vs. Temperature (Gain = 128) Figure 16. Integral Nonlinearity (VREF = AVDD, Gain = 128) Rev. A | Page 9 of 16 CODE INL (ppm FS) OCCURRENCE 07945-015 07945-016 07945-014 GAIN ERROR (ppm) OFFSET (µV) INL (ppm FS) 07945-019 07945-018 07945-017 AD7780 OUTPUT NOISE AND RESOLUTION Table 7 and Table 8 show the rms noise of the AD7780 for the two output data rates and gain settings when 3 V and 5 V references are used. These numbers are typical and are generated using a differential input voltage of 0 V. The corresponding peak-to-peak (p-p) resolution is also listed. The p-p resolution represents the resolution for which there is no code flicker. Table 7. RMS Noise and Peak-to-Peak Resolution when AVDD = 3 V and VREF = 3 V Parameter Gain = 128 Gain = 1 Update Rate 10 Hz 16.7 Hz 10 Hz 16.7 Hz RMS Noise 44 nV 65 nV 2.4 μV 2.7 μV P-P Resolution 17.6 17.1 18.8 18.7 Table 8. RMS Noise and Peak-to-Peak Resolution when AV = 5 V and V = 5 V DD REF Parameter Gain = 128 Gain = 1 Update Rate 10 Hz 16.7 Hz 10 Hz 16.7 Hz RMS Noise 49 nV 69 nV 3 μV 2.7 μV P-P Resolution 18.2 17.7 19.3 19.4 Rev. A | Page 10 of 16 AD7780 THEORY OF OPERATION 0 The AD7780 is a low power ADC that incorporates a precision 24-bit, Σ-Δ modulator; a PGA; and an on-chip digital filter –20 intended for measuring wide dynamic range, low frequency signals. The part provides a complete front-end solution for –40 bridge sensor applications such as weigh scales and pressure sensors. –60 The device has an internal clock and one buffered differential input. It offers a choice of two update rates (10 Hz or 16.7 Hz) –80 and two gain settings (1 or 128). These functions are controlled –100 using dedicated pins, which makes the interface easy to configure. A 2-wire interface simplifies data retrieval from the AD7780. –1000 FILTER, DATA RATE, AND SETTLING TIME 01 20 40 60 80 10020 INPUT SIGNAL FREQUENCY (Hz) The AD7780 has two filter options. When the FILTER pin is low, Figure 20. Filter Profile with Update Rate = 16.7 Hz (FILTER = 0) the 16.7 Hz filter is selected; when the FILTER pin is high, the 10 Hz filter is selected. When the polarity of FILTER is changed, 0 the AD7780 modulator and filter are reset immediately. DOUT/ RDY is set high, and the ADC then begins conversions using –20 the selected filter response. The first conversion requires the complete settling time of the filter. Subsequent conversions occur –40 at the selected update rate. The settling time of the 10 Hz filter is 300 ms (three conversion cycles), and the settling time of the –60 16.7 Hz filter is 120 ms (two conversion cycles). When a step change occurs on the analog input, the AD7780 –80 requires several conversion cycles to generate a valid conversion. If the step change occurs synchronous to the conversion period, the –100 settling time of the AD7780 must be allowed to generate a valid conversion. If the step change occurs asynchronous to the end –1000 01 20 40 60 80 10020 of a conversion, an extra conversion must be allowed to generate INPUT SIGNAL FREQUENCY (Hz) a valid conversion. The data register is updated with all the con- Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1) versions, but, for an accurate result, the user must allow for the required time. Figure 20 and Figure 21 show the filter response for each filter. The 10 Hz filter provides greater than −45 dB of rejection in the stop band. The only external filtering required on the analog inputs is a simple R-C filter to provide rejection at multiples of the master clock. A 1 kΩ resistor in series with each analog input, a 0.01 μF capacitor from each input to GND, and a 0.1 μF capacitor from AIN(+) to AIN(−) are recommended. RDY When the filter is changed, DOUT/ goes high and remains high until the appropriate settling time for that filter elapses (see Figure 5). Therefore, the user should complete any read operations before changing the filter. Otherwise, 1s are read back from the AD7780 because the DOUT/RDY pin is set high following the filter change. Rev. A | Page 11 of 16 FILTER GAIN (dB) FILTER GAIN (dB) 07945-021 07945-020 AD7780 GAIN BIPOLAR CONFIGURATION The AD7780 has two gain options: gain = 1 and gain = 128. The AD7780 accepts a bipolar input range. A bipolar input range When the GAIN pin is low, the gain is set to 128; when the does not imply that the part can tolerate negative voltages with GAIN pin is high, the gain is set to 1. The acceptable analog respect to system GND. Signals on the AIN(+) input are refer- input range is ±V /gain. Thus, with V = 5 V, the input range enced to the voltage on the AIN(−) input. For example, if AIN(−) REF REF is ±5 V when the GAIN pin is high and ±39 mV when the GAIN is 2.5 V, the analog input range on the AIN(+) input is 2.46 V to pin is low. 2.54 V for a gain of 128. When the polarity of the GAIN pin is changed, the AD7780 modu- DATA OUTPUT CODING lator and filter are reset immediately. DOUT/RDY is set high, and The AD7780 uses offset binary coding. Thus, a negative full- the ADC then begins conversions. DOUT/RDY remains high until scale voltage results in a code of 000...000, a zero differential the appropriate settling time for the filter elapses (see Figure 5). input voltage results in a code of 100...000, and a positive full- Therefore, the user should complete any read operations before scale input voltage results in a code of 111...111. changing the gain. Otherwise, 1s are read back from the AD7780 The output code for any analog input voltage can be represented as RDY because the DOUT/ pin is set high following the gain change. N − 1 Code = 2 × [(AIN × Gain /VREF) + 1] The total settling time of the selected filter is required to generate the first conversion after the gain change; subsequent conversions where: occur at the selected update rate. AIN is the analog input voltage. Gain is 1 or 128. POWER-DOWN/RESET (PDRST) N = 24. PDRST The pin functions as a power-down pin and a reset pin. REFERENCE When PDRST is taken low, the AD7780 is powered down. The The AD7780 has a fully differential input capability for the channel. entire ADC is powered down (including the on-chip clock), the The common-mode range for these differential inputs is GND to low-side power switch is opened, and the DOUT/RDY pin is AV . The reference input is unbuffered; therefore, excessive R-C DD tristated. The circuitry and serial interface are also reset, which source impedances introduce gain errors. The reference voltage of resets the logic, the digital filter, and the analog modulator. REFIN (REFIN(+) − REFIN(−)) is AVDD nominal, but the AD7780 PDRST must be held low for 100 ns minimum to initiate the is functional with reference voltages of 0.5 V to AVDD. In applica- reset function (see Figure 4) . tions where the excitation (voltage or current) for the transducer When PDRST is taken high, the AD7780 is taken out of power- on the analog input also drives the reference voltage for the part, down mode. When the on-chip clock has powered up (1 ms, the effect of the low frequency noise in the excitation source is typically), the modulator begins sampling the analog input. The removed because the application is ratiometric. If the AD7780 low-side power switch is closed, and the DOUT/RDY pin is used in a nonratiometric application, a low noise reference becomes active. should be used. A reset is automatically performed on power-up. Recommended 2.5 V reference voltage sources for the AD7780 include the ADR381 and ADR391, which are low noise, low ANALOG INPUT CHANNEL power references. These references have low output impedances The AD7780 has one differential analog input channel. The and are, therefore, tolerant to decoupling capacitors on REFIN(+) input channel feeds into a high impedance input stage of the without introducing gain errors in the system. Deriving the amplifier. Therefore, the input can tolerate significant source reference input voltage across an external resistor means that impedances and is tailored for direct connection to external the reference input sees a significant external source impedance. resistive-type sensors such as strain gages. External decoupling on the REFIN pins is not recommended in The absolute input voltage range is restricted to a range between this type of circuit configuration. GND + 300 mV and AVDD − 1.1 V. Care must be taken in setting up the common-mode voltage to avoid exceeding these limits. Otherwise, there is degradation in linearity and noise performance. The low noise in-amp means that signals of small amplitude can be amplified within the AD7780, while maintaining excellent noise performance. The amplifier can be configured to have a gain of 128 or 1, using the GAIN pin. The analog input range is equal to ±VREF/gain. The common-mode voltage (AIN(+) + AIN(−))/2 must be ≥0.5 V. Rev. A | Page 12 of 16 AD7780 RDY BRIDGE POWER-DOWN SWITCH DOUT/ is reset high when the conversion has been read. RDY If the conversion is not read, DOUT/ goes high prior to the The bridge power-down switch (BPDSW) is useful in battery- data register update to indicate when not to read from the device. powered applications where the optimization of system power This ensures that a read operation is not attempted while the reg- consumption is essential. A 350 Ω load cell typically consumes ister is being updated. Each conversion can be read only once. The 15 mA when excited with a 5 V power supply. To minimize the data register is updated for every conversion. When a conversion current consumption, the load cell is disconnected when it is is complete, the serial interface is reset, and the new conversion is not being used. The bridge power-down switch can be included placed in the data register. Therefore, the user must ensure that in series with the load cell. When is high, the bridge power- PDRST the complete word is read before the next conversion is complete. down switch is closed, and the load cell measures the strain. When is low, the bridge power-down switch is opened so no PDRST RDY PDRST When is low, the DOUT/ pin is tristated. When PDRST current flows through the load cell. Therefore, the current is taken high, the internal clock requires approximately consumption of the system is minimized. The bridge power- 1 ms to power up. Following power-up, the ADC continuously down switch has an on resistance of 9 Ω maximum. The switch converts. The first conversion requires the total settling time (see is capable of withstanding 30 mA of continuous current. Figure 4). DOUT/RDY goes high when PDRST is taken high and returns low only when a conversion is available. The ADC then DIGITAL INTERFACE converts continuously, and subsequent conversions are avail-able The serial interface of the AD7780 consists of two signals: SCLK at the selected update rate. Figure 3 shows the timing for a read and DOUT/RDY. SCLK is the serial clock input for the device, operation from the AD7780. and data transfers occur with respect to the SCLK signal. The When the filter response is changed (using FILTER) or the gain RDY DOUT/ pin is dual purpose: it functions as a data ready pin is changed (using GAIN), the modulator and filter are reset RDY and as a data output pin. DOUT/ goes low when a new immediately (see Figure 5). DOUT/RDY is set high. The ADC data-word is available in the output register. A 32-bit word is then begins conversions using the selected filter response/gain placed on the DOUT/RDY pin when sufficient SCLK pulses are RDY setting. DOUT/ remains high until the appropriate settling applied. This word consists of a 24-bit conversion result and eight time for that filter has elapsed. Therefore, the user should complete status bits. Figure 22 shows the status bits, and Table 9 describes any read operations before changing the gain or update rate. the status bits and their functions. Otherwise, 1s are read back from the AD7780 because the DOUT/RDY pin is set high following the gain/filter change. RDY FILTER ERR ID1 ID0 GAIN PAT1 PAT0 Figure 22. Status Bits Table 9. Status Bit Functions Bit Name Description RDY Ready bit. 0: a conversion is available. FILTER Filter bit. 1: 10 Hz filter is selected 0: 16.7 Hz filter is selected. ERR Error bit. 1: an error occurred during conversion. (An error occurs when the analog input is outside the range.) ID1, ID0 ID bits. ID1 ID0 Function 0 1 Indicates the ID number for the AD7780 GAIN Gain bit. 1: gain = 1. 0: gain = 128. PAT1, PAT0 Status pattern bits. When the user reads data from the AD7780, a pattern check can be performed. PAT1 PAT0 Function 0 1 Indicates that the serial transfer from the ADC was performed correctly (default). 0 0 Indicates that the serial transfer from the ADC was not performed correctly. 1 0 Indicates that the serial transfer from the ADC was not performed correctly. 1 1 Indicates that the serial transfer from the ADC was not performed correctly. Rev. A | Page 13 of 16 07945-121 AD7780 APPLICATIONS INFORMATION no load is applied to the load cell) and the full-scale error (the The AD7780 provides a low cost, high resolution analog-to-digital function. Because the analog-to-digital function is provided by a conversion result from the ADC when the maximum load is Σ-Δ architecture, the parts are more immune to noisy environ- applied to the load cell) must be determined. Subsequent conver- ments, making them ideal for use in sensor measurement and sions from the AD7780 are then corrected, using the offset and industrial and process control applications. gain coefficients that were calculated from these calibrations. WEIGH SCALES PERFORMANCE IN A WEIGH SCALE SYSTEM Figure 23 shows the AD7780 being used in a weigh scale If the load cell has a sensitivity of 2 mV/V and a 5 V excitation application. The load cell is arranged in a bridge network and voltage is used, the full-scale signal from the load cell is 10 mV. gives a differential output voltage between its OUT+ and OUT− When the AD7780 operates with a 10 Hz output data rate and terminals. Assuming a 5 V excitation voltage, the full-scale the gain is set to 128, the device has a p-p resolution of 18.2 bits output range from the transducer is 10 mV when the sensitivity when the reference is equal to 5 V. Postprocessing the data from is 2 mV/V. The excitation voltage for the bridge can be used to the AD7780 using a microprocessor increases the p-p resolution. directly provide the reference for the ADC because the refer- For example, an average by 4 in the microprocessor increases ence input range includes the supply voltage. the accuracy by 2 bits. The noise-free counts is equal to the following: A second advantage of using the AD7780 in transducer-based Effective Bits applications is that the bridge power-down switch (BPDSW) Noise-Free Counts = (2 )(FSLC/FSADC) can be fully utilized in low power applications. The bridge power- where: down switch is connected in series with the low side of the bridge. Effective Bits = 18.2 bits + 2 bits (due to post-processing in the In normal operation, the switch is closed and measurements microprocessor). can be taken. In applications where power is of concern, the FSLC is the full-scale signal from the load cell (10 mV). AD7780 can be placed in power-down mode, significantly FSADC is the full-scale input range when gain = 128 and VREF = 5 V reducing the power consumed in the application. In addition, (78 mV). the bridge power-down switch is opened while in power-down The noise-free counts are equal to the following: mode, thus avoiding unnecessary power consumption by the 18.2 + 2 front-end transducer. When the part is taken out of power-down (2 )(10 mV/78 mV) = 154,422 mode and the bridge power-down switch is closed, the user should This example shows that with a 5 V supply, 154,422 noise-free ensure that the front-end circuitry is fully settled before attempting counts can be achieved with the AD7780. a read from the AD7780. EMI RECOMMENDATIONS The load cell has an offset or tare associated with it. This tare is For simplicity, the EMI filters are not included in Figure 23. the main component of the system offset (load cell + ADC) and is However, an R-C antialiasing filter should be included on each similar in magnitude to the full-scale signal from the load cell. analog input. This filter is needed because the on-chip digital For this reason, calibrating the offset and gain of the AD7780 alone filter does not provide any rejection around the master clock or is not sufficient for optimum accuracy; a system calibration that multiples of the master clock. Suitable values are a 1 kΩ resistor calibrates the offset and gain of the ADC, plus the load cell, is in series with each analog input, a 0.1 μF capacitor from AIN(+) required. A microprocessor can be used to perform the calibra- to AIN(−), and 0.01 μF capacitors from AIN(+)/AIN(−) to GND. tions. The offset (the conversion result from the AD7780 when VDD IN+ GND AV DD REFIN(+) AIN(+) OUT– OUT+ DOUT/RDY G = 1 24-BIT Σ-Δ OR 128 ADC IN– AIN(–) SCLK DV DD REFIN(–) INTERNAL CLOCK FILTER BPDSW PDRST AD7780 GAIN Figure 23. Weigh Scales Using the AD7780 Rev. A | Page 14 of 16 07945-022 AD7780 The ground plane of the AD7780 should be allowed to run under GROUNDING AND LAYOUT the AD7780 to prevent noise coupling. The power supply lines Because the analog input and reference input of the ADC are to the AD7780 should use as wide a trace as possible to provide differential, most of the voltages in the analog modulator are low impedance paths and reduce the effects of glitches on the common-mode voltages. The excellent common-mode reject- power supply line. Fast switching signals such as clocks should tion of the part removes common-mode noise on these inputs. be shielded with digital ground to avoid radiating noise to other The digital filter provides rejection of broadband noise on the sections of the board, and clock signals should never be run near power supply, except at integer multiples of the modulator sam- the analog inputs. Avoid crossover of digital and analog signals. pling frequency. The digital filter also removes noise from the Traces on opposite sides of the board should run at right angles analog and reference inputs, provided that these noise sources to each other. This reduces the effects of feedthrough through do not saturate the analog modulator. As a result, the AD7780 the board. A microstrip technique is by far the best, but it is not is more immune to noise interference than conventional high always possible with a double-sided board. In this technique, resolution converters. However, because the resolution of the the component side of the board is dedicated to ground planes, AD7780 is so high, and the noise levels from the AD7780 are so and the signals are placed on the solder side. low, care must be taken with regard to grounding and layout. Good decoupling is important when using high resolution The printed circuit board that houses the AD7780 should be ADCs. AV should be decoupled with 10 μF tantalum capa- DD designed such that the analog and digital sections are separated citors in parallel with 0.1 μF capacitors to GND. DV should DD and confined to certain areas of the board. A minimum etch be decoupled with 10 μF tantalum capacitors in parallel with technique is generally best for ground planes because it gives 0.1 μF capacitors to GND, with the system’s AGND to DGND the best shielding. connection kept close to the AD7780. To achieve the best results It is recommended that the GND pin of the AD7780 be tied from these decoupling components, place them as close as possible to the AGND plane of the system. In any layout, pay attention to the device, ideally right up against the device. All logic chips to the flow of currents in the system and ensure that the return should be decoupled with 0.1 μF ceramic capacitors to DGND. paths for all currents are as close as possible to the paths that the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. Rev. A | Page 15 of 16 AD7780 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 14 8 4.00 (0.1575) 6.20 (0.2441) 1 3.80 (0.1496) 5.80 (0.2283) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7780BRZ –40°C to +105°C 14-Lead SOIC_N R-14 1 AD7780BRZ-REEL –40°C to +105°C 14-Lead SOIC_N R-14 1 AD7780BRUZ –40°C to +105°C 16-Lead TSSOP RU-16 1 AD7780BRUZ-REEL –40°C to +105°C 16-Lead TSSOP RU-16 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07945-0-9/09(A) Rev. A | Page 16 of 16 060606-A