ANALOG DEVICES AD7767

24-Bit, 8.5 mW, 109 dB, 128 kSPS/64 kSPS/32 kSPS ADCs AD7767 FEATURES GENERAL DESCRIPTION Oversampled successive approximation (SAR) architecture The AD7767/AD7767-1/AD7767-2 are high performance, High performance ac and dc accuracy, low power 24-bit, oversampled SAR analog-to-digital converters (ADCs). 115.5 dB dynamic range, 32 kSPS (AD7767-2) The AD7767/AD7767-1/AD7767-2 combine the benefits of a 112.5 dB dynamic range, 64 kSPS (AD7767-1) large dynamic range and input bandwidth, consuming 15 mW, 109.5 dB dynamic range, 128 kSPS (AD7767) 10.5 mW, and 8.5 mW power, respectively, and are contained in −118 dB THD a 16-lead TSSOP package. Exceptionally low power Ideal for ultralow power data acquisition (such as PCI- and 8.5 mW, 32 kSPS (AD7767-2) USB-based systems), the AD7767/AD7767-1/AD7767-2 10.5 mW, 64 kSPS (AD7767-1) provide 24-bit resolution. The combination of exceptional SNR, 15 mW, 128 kSPS (AD7767) wide dynamic range, and outstanding dc accuracy make the High dc accuracy AD7767/AD7767-1/AD7767-2 ideally suited for measuring 24 bits, no missing codes (NMC) small signal changes over a wide dynamic range. This is INL: ±3 ppm (typical), ±7.6 ppm (maximum) particularly suitable for applications where small changes on the Low temperature drift input are measured on larger ac or dc signals. In such an Zero error drift: 15 nV/°C application, the AD7767/AD7767-1/AD7767-2 accurately Gain error drift: 0.4 ppm/°C gather both ac and dc information. On-chip low-pass FIR filter The AD7767/AD7767-1/AD7767-2 include an on-board digital Linear phase response filter (complete with linear phase response) that acts to elimi- Pass-band ripple: ±0.005 dB nate out-of-band noise by filtering the oversampled input Stop-band attenuation: 100 dB voltage. The oversampled architecture also reduces front-end 2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options antialias requirements. Other features of the AD7767 include a Flexible interfacing options SYNC PD Synchronization of multiple devices / (synchronization/power-down) pin, allowing the Daisy-chain capability synchronization of multiple AD7767 devices. The addition of Power-down function an SDI pin provides the option of daisy chaining multiple Temperature range: −40°C to +105°C AD7767 devices. The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply APPLICATIONS using a 5 V reference. The devices operate from −40°C to +105°C. Low power PCI/USB data acquisition systems Low power wireless acquisition systems RELATED DEVICES Vibration analysis Table 1. 24-Bit ADCs Instrumentation Part No. Description High precision medical acquisition 1 AD7760 2.5 MSPS, 100 dB dynamic range, on-board differential FUNCTIONAL BLOCK DIAGRAM amp and reference buffer, parallel, variable decimation 1 AV AGND MCLK DV V DGND AD7762/ 625 kSPS, 109 dB dynamic range, on-board differential DD DD DRIVE AD7763 amp and reference buffer, parallel/serial, variable V decimation REF+ 1 V AD7764 312 kSPS, 109 dB dynamic range, on-board differential IN+ DIGITAL SUCCESSIVE amp and reference buffer, variable decimation (pin) FIR FILTER APPROXIMATION 1 ADC AD7765 156 kSPS, 112 dB dynamic range, on-board differential SYNC/PD V IN– amp and reference buffer, variable decimation (pin) SERIAL INTERFACE 1 REFGND AND CS AD7766 128 kSPS, 109.5 dB, 15 mW, 16-bit INL, serial interface CONTROL LOGIC AD7767/ 1 AD7766-1 64 kSPS 112.5 dB, 10.5 mW, 16-bit INL, serial interface AD7767-1/ 1 AD7766-2 32 kSPS, 115.5 dB, 8.5 mW, 16-bit INL, serial interface AD7767-2 SCLK DRDY SDO SDI 1 Dynamic range at maximum output data rate. Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06859-001 AD7767 TABLE OF CONTENTS Features .............................................................................................. 1  Supply and Reference Voltages ................................................. 16  Applications ....................................................................................... 1  AD7767 Interface ........................................................................... 17  Functional Block Diagram .............................................................. 1  Initial Power-Up ......................................................................... 17  General Description ......................................................................... 1  Reading Data ............................................................................... 17  Related Devices ................................................................................. 1  Power-Down, Reset, and Synchronization ............................. 17  Revision History ............................................................................... 2  Daisy Chaining ............................................................................... 18  Specif ica t ions ..................................................................................... 3  Reading Data in Daisy-Chain Mode ....................................... 18  Timing Specifications .................................................................. 5  Choosing the SCLK Frequency ................................................ 18  Timing Diagrams .......................................................................... 6  Daisy-Chain Mode Configuration and Timing Diagrams ... 19  Absolute Maximum Ratings ............................................................ 8  Driving the AD7767 ....................................................................... 20  ESD Caution .................................................................................. 8  Differential Signal Source ......................................................... 20  Pin Configuration and Function Descriptions ............................. 9  Single-Ended Signal Source ...................................................... 20  Typical Performance Characteristics ........................................... 10  Antialiasing ................................................................................. 21  Terminology .................................................................................... 14  Power Dissipation....................................................................... 21  Theory of Operation ...................................................................... 15  V Input Signal ....................................................................... 22  REF+ AD7767/AD7767-1/AD7767-2 Transfer Function ................ 15  Multiplexing Analog Input Channels ...................................... 22  Converter Operation .................................................................. 15  Outline Dimensions ....................................................................... 23  Analog Input Structure .............................................................. 16  Ordering Guide .......................................................................... 23  REVISION HISTORY 5/10—Rev. B to Rev. C Changes to Pin 8 Description ......................................................... 9 Changes to Table 8 .......................................................................... 20 3/09—Rev. A to Rev. B Changes to t Parameter, Table 3 .......................................... 5 SETTLING Changes to Table 7 .......................................................................... 17 1/09—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Change to Intermodulation Distortion (IMD) Parameter and Integral Nonlinearity Parameter, Table 2 ................................. 3 Changes to Supply and Reference Voltages Section ................... 16 Changes to Choosing the SCLK Frequency Section .................. 18 Changes to Figure 24 ...................................................................... 12 Changes to Driving the AD7767 Section .................................... 20 Changes to Single-Ended Signal Source Section ........................ 20 Added Figure 41; Renumbered Sequentially .............................. 20 Change to Figure 42 ....................................................................... 21 Added Table 8; Renumbered Sequentially .................................. 20 Replaced V Input Signal Section ............................................ 22 REF+ Replaced Figure 46 ......................................................................... 22 8/07—Revision 0: Initial Version Rev. C | Page 2 of 24 AD7767 SPECIFICATIONS AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.8 V to 3.6 V, VREF = 5 V, MCLK = 1 MHz, common-mode input = VREF/2, TA = −40°C to +105°C, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT DATA RATE (ODR) AD7767 Decimate by 8 128 kHz AD7767-1 Decimate by 16 64 kHz AD7767-2 Decimate by 32 32 kHz 1 ANALOG INPUT Differential Input Voltage VIN+ − VIN− ±VREF V p-p Absolute Input Voltage VIN+ −0.1 +VREF + 0.1 V VIN− −0.1 +VREF + 0.1 V Common-Mode Input Voltage VREF/2 − 5% VREF/2 VREF/2 + 5% V Input Capacitance 22 pF DYNAMIC PERFORMANCE AD7767 Decimate by 8, ODR = 128 kHz 2 Dynamic Range Shorted inputs 108 109.5 dB 2 Signal-to-Noise Ratio (SNR) Full-scale input amplitude, 1 kHz tone 107 108.5 dB 2 Spurious-Free Dynamic Range (SFDR) Full-scale input amplitude, 1 kHz tone −128 −116 dB 2 Total Harmonic Distortion (THD) Full-scale input amplitude, 1 kHz tone −118 −105 dB 2 Intermodulation Distortion (IMD) Tone A = 49.7 kHz, Tone B = 50.3 kHz Second-Order Terms −133 dB Third-Order Terms −109 dB AD7767-1 Decimate by 16, ODR = 64 kHz 2 Dynamic Range Shorted inputs 111 112.5 dB 2 Signal-to-Noise Ratio (SNR) Full-scale input amplitude, 1 kHz tone 110 111.5 dB 2 Spurious-Free Dynamic Range (SFDR) Full-scale input amplitude, 1 kHz tone −128 −116 dB 2 Total Harmonic Distortion (THD) Full-scale input amplitude, 1 kHz tone −118 −105 dB 2 Intermodulation Distortion (IMD) Tone A = 24.7 kHz, Tone B = 25.3 kHz dB Second-Order Terms −133 dB Third-Order Terms −108 dB AD7767-2 Decimate by 32, ODR = 32 kHz 2 Dynamic Range Shorted inputs 114 115.5 dB 2 Signal-to-Noise Ratio (SNR) Full-scale input amplitude, 1 kHz tone 112 113.5 dB 2 Spurious-Free Dynamic Range (SFDR) Full-scale input amplitude, 1 kHz tone −128 −116 dB 2 Total Harmonic Distortion (THD) Full-scale input amplitude, 1 kHz tone −118 −105 dB 2 Intermodulation Distortion (IMD) Tone A = 11.7 kHz, Tone B = 12.3 kHz dB Second-Order Terms −137 dB Third-Order Terms −108 dB 1 DC ACCURACY For all devices Resolution No missing codes 24 Bits 2 Differential Nonlinearity Guaranteed monotonic to 24 bits 2 Integral Nonlinearity 18-bit linearity ±3 ±7.6 ppm 2 Zero Error 20 μV 2 Gain Error 0.0075 0.075 % FS 2 Zero Error Drift 15 nV/°C 2 Gain Error Drift 0.4 ppm/°C 2 Common-Mode Rejection Ratio 50 Hz tone −110 dB Rev. C | Page 3 of 24 AD7767 Parameter Test Conditions/Comments Min Typ Max Unit 1 DIGITAL FILTER RESPONSE Group Delay 37/ODR μs Settling Time (Latency) Complete settling 74/ODR μs Pass-Band Ripple ±0.005 dB Pass Band 0.453 × ODR Hz −3 dB Bandwidth 0.49 × ODR Hz Stop-Band Frequency 0.547 × ODR Hz Stop-Band Attenuation 100 dB 1 REFERENCE INPUT VREF+ Input Voltage 2.4 2 × AVDD V 1 DIGITAL INPUTS (Logic Levels) VIL −0.3 +0.3 × VDRIVE V VIH 0.7 × VDRIVE VDRIVE + 0.3 V Input Leakage Current ±1 μA/pin Input Capacitance 5 pF Master Clock Rate 1.024 MHz Serial Clock Rate 1/t Hz 8 1 DIGITAL OUTPUTS Data Format Serial 24 bits, twos complement (MSB first) VOL ISINK = +500 μA 0.4 V VOH ISOURCE = −500 μA VDRIVE – 0.3 V 1 POWER REQUIREMENTS AVDD ± 5% 2.5 V DVDD ± 5% 2.5 V V 1.7 2.5 3.6 V DRIVE CURRENT SPECIFICATIONS MCLK = 1.024 MHz AD7767 Operational Current 128 kHz output data rate AI 1.3 1.5 mA DD DI 3.9 4.8 mA DD IREF 0.35 0.425 mA AD7767-1 Operational Current 64 kHz output data rate AIDD 1.3 1.5 mA DI 2.2 2.85 mA DD I 0.35 0.425 mA REF AD7767-2 Operational Current 32 kHz output data rate AIDD 1.3 1.5 mA DIDD 1.37 1.86 mA IREF 0.35 0.425 mA Static Current with MCLK Stopped For all devices AI 0.9 1 mA DD DIDD 1 93 μA Power-Down Mode Current For all devices AIDD 0.1 6 μA DI 1 93 μA DD POWER DISSIPATION MCLK = 1.024 MHz AD7767 Operational Power 128 kHz output data rate 15 18 mW AD7767-1 Operational Power 64 kHz output data rate 10.5 13 mW AD7767-2 Operational Power 32 kHz output data rate 8.5 10.5 mW 1 Specifications are for all devices, AD7767, AD7767-1, and AD7767-2. 2 See the Terminology section. Rev. C | Page 4 of 24 AD7767 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = −40°C (TMIN) to +105°C (TMAX), 1 unless otherwise noted. Table 3. Parameter Limit at tMIN, tMAX Unit Description DRDY OPERATION t1 510 ns typ MCLK rising edge to DRDY falling edge 2 t2 100 ns min MCLK high pulse width 2 t 900 ns max MCLK low pulse width 3 t 265 ns typ MCLK rising edge to DRDY rising edge (AD7767) 4 128 ns typ MCLK rising edge to DRDY rising edge (AD7767-1) 71 ns typ MCLK rising edge to DRDY rising edge (AD7767-2) t5 294 ns typ DRDY pulse width (AD7767) 435 ns typ DRDY pulse width (AD7767-1) 492 ns typ DRDY pulse width (AD7767-2) 3 t t − t ns typ DRDY low period, read data during this period READ DRDY 5 3 t n × 8 × t ns typ DRDY period DRDY MCLK Read OPERATION t 0 ns min DRDY falling edge to CS setup time 6 t7 6 ns max CS falling edge to SDO tristate disabled t8 60 ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V) 50 ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V) 25 ns max Data access time after SCLK falling edge (V = 2.7 V) DRIVE 24 ns max Data access time after SCLK falling edge (V = 3.0 V) DRIVE t9 10 ns min SCLK falling edge to data valid hold time (VDRIVE = 3.6 V) t10 10 ns min SCLK high pulse width t11 10 ns min SCLK low pulse width t 1/t sec min Minimum SCLK period SCLK 8 t 6 ns max Bus relinquish time after CS rising edge 12 t 0 ns min CS rising edge to DRDY rising edge 13 Read OPERATION WITH CS LOW t 0 ns min DRDY falling edge to data valid setup time 14 t 0 ns max DRDY rising edge to data valid hold time 15 DAISY-CHAIN OPERATION t 1 ns min SDI valid to SCLK falling edge setup time 16 t 2 ns max SCLK falling edge to SDI valid hold time 17 SYNC/PD OPERATION t 1 ns typ SYNC/PD falling edge to MCLK rising edge 18 t19 20 ns typ MCLK rising edge to DRDY rising edge going into SYNC/PD mode t20 1 ns min SYNC/PD rising edge to MCLK rising edge t21 510 ns typ MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode 3 t (592 × n) + 2 t Filter settling time after a reset or power-down SETTLING MCLK 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V. 2 t and t allow a ~90% to 10% duty cycle to be used for the MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum 2 3 MCLK frequency is 1.024 MHz. 3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2. Rev. C | Page 5 of 24 AD7767 TIMING DIAGRAMS t 2 1 8 × n 1 8 × n MCLK t 3 t 4 t t t 1 5 5 t READ DRDY t DRDY DRDY Figure 2. vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32) t DRDY DRDY t READ t 13 t 6 CS t 10 1 23 SCLK t 11 t t 8 9 t 7 t 12 SDO MSB D22 D21 D20 D1 LSB Figure 3. Serial Timing Diagram, Reading Data Using CS CS = 0 t DRDY DRDY t READ t 14 t 10 1 23 24 SCLK t 11 t t t 8 9 15 DATA DATA SDO MSB D22 D21 D20 D1 LSB INVALID INVALID Figure 4. Serial Timing Diagram, Reading Data Setting CS Logic Low Rev. C | Page 6 of 24 06859-004 06859-003 06859-002 AD7767 PART OUT OF POWER-DOWN FILTER RESET PART IN POWER-DOWN BEGINS SAMPLING MCLK (I) ABCD t 20 t 18 SYNC/PD (I) t t 21 19 DRDY (O) t SETTLING VALID DATA INVALID DATA VALID DATA DOUT (O) Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section) Rev. C | Page 7 of 24 06859-005 AD7767 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AV to AGND −0.3 V to +3 V DD rating only; functional operation of the device at these or any DV to DGND −0.3 V to +3 V DD other conditions above those indicated in the operational AVDD to DVDD −0.3 V to +0.3 V section of this specification is not implied. Exposure to absolute VREF+ to REFGND −0.3 V to +7 V maximum rating conditions for extended periods may affect REFGND to AGND −0.3 V to +0.3 V device reliability. V to DGND −0.3 V to +6 V DRIVE V , V to AGND −0.3 V to V + 0.3 V ESD CAUTION IN+ IN– REF+ Digital Inputs to DGND −0.3 V to V + 0.3 V DRIVE Digital Outputs to DGND −0.3 V to VDRIVE + 0.3 V AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 150.4°C/W JA θ Thermal Impedance 27.6°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. C | Page 8 of 24 AD7767 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 AV 1 CS DD 2 V 15 SDI REF+ AD7767/ 3 14 REFGND MCLK AD767-1/ 4 V 13 SCLK IN+ AD7767-2 TOP VIEW 5 12 V DRDY IN– (Not to Scale) 6 11 AGND DGND 7 10 SYNC/PD SDO 8 9 DV V DD DRIVE Figure 6. 16-Lead TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 AVDD +2.5 V Analog Power Supply. 2 V Reference Input for the AD7767. An external reference must be applied to this input pin. The V input can range REF+ REF+ from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude applied to the AV pin. DD 3 REFGND Reference Ground. Ground connection for the reference voltage. The input reference voltage (V ) should be REF+ decoupled to this pin. 4 VIN+ Positive Input of the Differential Analog Input. 5 VIN− Negative Input of the Differential Analog Input. 6 AGND Power Supply Ground for Analog Circuitry. 7 SYNC/PD Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple AD7767 devices and/or to put the AD7767 device into power-down mode. See the Power-Down, Reset, and Synchronization section for further details. 8 DVDD 2.5 V Digital Power Supply Input. In cases where an logic voltage of 2.5 V is used for interfacing (2.5 V applied to V pin), the DVDD and V pin may be connected to the same voltage supply rail. DRIVE DRIVE 9 V Logic Power Supply Input, 1.8 V to 3.6 V. The voltage supplied at this pin determines the operating voltage of the DRIVE digital logic interface. 10 SDO Serial Data Output. The conversion result from the AD7767 is output on the SDO pin as a 24-bit, twos complement, MSB first, serial data stream. 11 DGND Digital Logic Power Supply Ground. 12 DRDY Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the output register of the AD7767. See the AD7767 Interface section for further details. 13 SCLK Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7767 device. See the AD7767 Interface section for further details. 14 MCLK Master Clock Input. The AD7767 sampling frequency is equal to the MCLK frequency. 15 SDI Serial Data Input. This is the daisy-chain input of the AD7767. See the Daisy Chaining section for further details. 16 CS Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on the CS falling edge. The CS input allows multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by supplying it with a logic low CS signal, which enables the SDO pin of the device concerned. See the AD7767 Interface section for further details. Rev. C | Page 9 of 24 06859-006 AD7767 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.8 V to 3.6 V, VREF = 5 V, MCLK = 1 MHz, common-mode input = VREF/2. TA = 25°C, unless otherwise noted. All FFTs were generated using 8192 samples using a four-term Blackman-Harris window. 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 8k 16k 24k 32k 40k 48k 56k 64k 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz) FREQUENCY (Hz) Figure 10. AD7767 FFT, 1 kHz, −6 dB Input Tone Figure 7. AD7767 FFT, 1 kHz, −0.5 dB Input Tone 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 4k 8k 12k 16k 20k 24k 28k 32k 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. AD7767-1 FFT, 1 kHz, −6 dB Input Tone Figure 8. AD7767-1 FFT, 1 kHz, −0.5 dB Input Tone 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 01 4k 8k 12k6k 01 4k 8k 12k6k FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. AD7767-2 FFT, 1 kHz, −0.5 dB Input Tone Figure 12. AD7767-2 FFT, 1 kHz, −6 dB Input Tone Rev. C | Page 10 of 24 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06859-103 06859-102 06859-101 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06859-106 06859-105 06859-104 AD7767 0 0 TONE A = 49.7kHz TONE B = 50.3kHz –20 –20 SECOND-ORDER IMD = –133.71dB THIRD-ORDER IMD = –109.05dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 8k 16k 24k 32k 40k 48k 56k 64k 0 8k 16k 24k 32k 40k 48k 56k 64k FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. AD7767 FFT, 1 kHz, −60 dB Input Tone Figure 16. AD7767 IMD FFT, 50 kHz Center Frequency 0 0 TONE A = 24.7kHz TONE B = 25.3kHz –20 –20 SECOND-ORDER IMD = –133.33dB THIRD-ORDER IMD = –108.15dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 4k 8k 12k 16k 20k 24k 28k 32k 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. AD7767-1 FFT, 1 kHz, −60 dB Input Tone Figure 17. AD7767-1 IMD FFT, 25 kHz Center Frequency 0 0 TONE A = 11.7kHz TONE B = 12.3kHz –20 –20 SECOND-ORDER IMD = –137.96dB THIRD-ORDER IMD = –108.1dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 01 4k 8k 12k6k 01 4k 8k 12k6k FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. AD7767-2 FFT, 1 kHz, −60 dB Input Tone Figure 18. AD7767-2 IMD FFT, 12 kHz Center Frequency Rev. C | Page 11 of 24 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06859-109 06859-108 06859-107 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06859-112 06859-111 06859-110 AD7767 –110 120 –112 115 –114 DYNAMIC RANGE –116 110 AD7767-2 –118 –120 105 –122 OPEN INPUTS AD7767-1 AD7767 100 –124 –126 95 FULL-SCALE 921Hz –128 –130 90 01 100k 200k 300k 400k 500k 600k 700k 800k 900kM 06 10k 20k 30k 40k 50k0k MCLK FREQUENCY (Hz) f (Hz) NOISE Figure 19. AD7767/AD7767-1/AD7767-2 THD vs. MCLK Frequency Figure 22. AD7767 CMRR vs. Common-Mode Ripple Frequency (fNOISE) 115 200 MAX = 8388637 MIN = 8388493 180 114 SPREAD = 145 AD7767-2 160 113 140 112 120 111 100 AD7767-1 80 110 60 109 AD7767 40 108 20 107 0 01 100k 200k 300k 400k 500k 600k 700k 800k 900kM MCLK FREQUENCY (Hz) CODES Figure 20. AD7767/AD7767-1/AD7767-2 SNR vs. MCLK Frequency Figure 23. AD7767 24-Bit Histogram 150 250 AV DD DV MAX = 8388608 DD MIN = 8388507 SPREAD = 102 CODES 140 200 130 150 V DRIVE 120 100 110 50 100 0 06 10k 20k 30k 40k 50k0k f (Hz) NOISE CODES Figure 21. AD7767 Power Supply Sensitivity vs. Supply Ripple Frequency Figure 24. AD7767-1 24-Bit Histogram (fNOISE) with Decoupling Capacitors Rev. C | Page 12 of 24 SNR (dB) THD (dB) PSRR (dB) 06859-117 06859-114 06859-113 CMRR (dB) OCCURRENCE OCCURRENCE 8388493 8388508 8388497 8388512 8388501 8388516 8388505 8388509 8388520 8388513 8388524 8388517 8388521 8388528 8388525 8388532 8388529 8388533 8388536 8388537 8388540 8388541 8388544 8388545 8388549 8388548 8388553 8388552 8388557 8388561 8388556 8388565 8388560 8388569 8388564 8388573 8388577 8388568 8388581 8388572 8388585 8388589 8388576 8388593 8388580 8388597 8388601 8388584 8388605 8388588 8388609 8388592 8388613 8388617 8388596 8388621 8388600 8388625 8388629 8388604 8388633 8388608 8388637 06859-119 06859-118 06859-116 AD7767 3.80 MAX = 8388593 LOW TEMPERATURE 350 MIN = 8388526 NOMINAL TEMPERATURE 3.04 SPREAD = 69 CODES HIGH TEMPERATURE 300 2.28 1.52 250 0.76 200 0 150 –0.76 –1.52 100 –2.28 50 –3.04 0 –3.80 0 4194304 8388608 12582912 16777216 2097152 6291456 10485760 14680064 24-BIT CODES CODES Figure 25. AD7767-2 24-Bit Histogram Figure 27. AD7767/AD7767-1/AD7767-2 24-Bit INL 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4194304 8388608 12582912 16777216 2097152 6291456 10485760 14680064 24-BIT CODES Figure 26. AD7767/AD7767-1/AD7767-2 24-Bit DNL Rev. C | Page 13 of 24 DNL (LSBs) OCCURRENCE 8388526 8388529 8388532 8388535 8388538 8388541 8388544 8388547 8388550 8388553 8388556 8388559 8388562 8388565 8388568 8388571 8388574 8388577 8388580 8388583 8388586 8388589 8388592 06859-120 06859-121 INL (ppm) 06859-122 AD7767 TERMINOLOGY Signal-to-Noise Ratio (SNR) as per the THD specification, where it is the ratio of the rms SNR is the ratio of the actual input signal’s rms value to the rms sum of the individual distortion products to the rms amplitude sum of all other spectral components below the Nyquist frequency, of the sum of the fundamentals expressed in decibels. excluding harmonics and dc. The value for SNR is expressed in Integral Nonlinearity (INL) decibels. INL is the maximum deviation from a straight line passing Total Harmonic Distortion (THD) through the endpoints of the ADC transfer function. THD is the ratio of the rms sum of harmonics to the fundamen- Differential Nonlinearity (DNL) tal. For the AD7767, it is defined as DNL is the difference between the measured and the ideal 2 2 2 2 2 1 LSB change between any two adjacent codes in the ADC. V + V + V + V + V 2 3 4 5 6 THD() dB = 20 log Zero Error V 1 Zero error is the difference between the ideal midscale input where: voltage (when both inputs are shorted together) and the actual V1 is the rms amplitude of the fundamental. voltage producing the midscale output code. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to Zero Error Drift the sixth harmonics. Zero error drift is the change in the actual zero error value due Nonharmonic Spurious-Free Dynamic Range (SFDR) to a temperature change of 1°C. It is expressed as a percentage SFDR is the ratio of the rms signal amplitude to the rms value of full scale at room temperature. of the peak spurious spectral component, excluding harmonics. Gain Error Dynamic Range The first transition (from 100 … 000 to 100 … 001) should occur Dynamic range is the ratio of the rms value of the full scale to ½ LSB above the nominal negative full scale for an analog voltage. the rms noise measured with the inputs shorted together. The The last transition (from 011 … 110 to 011 … 111) should occur value for the dynamic range is expressed in decibels. 1½ LSB below the nominal full scale for an analog voltage. The gain error is the deviation of the difference between the actual Intermodulation Distortion (IMD) level of the last transition and the actual level of the first transition, With inputs consisting of sine waves at two frequencies, fa from the difference between the ideal levels. and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where Gain Error Drift m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms Gain error drift is the change in the actual gain error value due are those for which neither m nor n are equal to 0. For example, to a temperature change of 1°C. It is expressed as a percentage the second-order terms include (fa + fb) and (fa − fb), and the of full scale at room temperature. third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and Common-Mode Rejection Ratio (CMRR) (fa − 2fb). CMRR is defined as the ratio of the power in the ADC output The AD7767 is tested using the CCIF standard, where two input at full-scale frequency f to the power of a 100 mV sine wave frequencies near the top end of the input bandwidth are used. applied to the common-mode voltage of the VIN+ and VIN− inputs at frequency fS. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order CMRR (dB) = 10 log(Pf/Pf ) S terms are usually at a frequency close to the input frequencies. where Pf is the power at the frequency f in the ADC output, and As a result, the second- and third-order terms are specified Pf is the power at the frequency f in the ADC output. S S separately. The calculation of the intermodulation distortion is Rev. C | Page 14 of 24 AD7767 THEORY OF OPERATION The AD7767/AD7767-1/AD7767-2 operate using a fully The digital filtering that follows the converter output acts to differential analog input applied to a successive approximation remove the out-of-band quantization noise (see Figure 30). This (SAR) core. The output of the oversampled SAR is filtered using also has the effect of reducing the data rate from fMCLK at the a linear-phase digital FIR filter. The fully filtered data is output input of the filter to fMCLK/8, fMCLK/16, or fMCLK/32 at the digital in a serial format, with the MSB being clocked out first. output, depending on which model of the device is being used. The digital filter consists of three separate filter blocks. Figure 31 AD7767/AD7767-1/AD7767-2 TRANSFER shows the three constituent blocks of the filter. The order of FUNCTION decimation of the first filter block is set as 2, 4, or 8. The The conversion results of the AD7767/AD7767-1/AD7767-2 remaining sections each operate with a decimation of 2. are output in a twos complement, 24-bit serial format. The fully differential inputs VIN+ and VIN− are scaled by the AD7767/ DIGITAL FILTER AD7767-1/AD7767-2 relative to the reference voltage input STAGE 1 STAGE 2 STAGE 3 (VREF+) as shown in Figure 28. DATA SINC FILTER FIR FILTER FIR FILTER SDO 24 BITS STREAM TWOS COMPLEMENT DEC × (2 × n) DEC × 2 DEC × 2 011 ... 111 011 ... 110 Figure 31. FIR Filter Stages (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) 000 ... 010 Table 6 shows the three available models of the AD7767, listing 000 ... 001 the change in output data rate relative to the order of decimation 000 ... 000 rate implemented. This brings into focus the trade-off that exists between extra filtering and reduction in bandwidth, whereby 111 ... 111 using a filter option with a larger decimation rate increases the 111 ... 110 noise performance while decreasing the usable input bandwidth. 100 ... 001 Table 6. AD7767 Models 100 ... 000 Model Decimation Rate Output Data Rate (ODR) V = 0V V V = V – 1LSB IN+ REF IN+ REF V = AD7767 8 128 kHz IN+ 2 V = V – 1LSB V V = 0V IN– REF REF IN– AD7767-1 16 64 kHz V = IN– 2 AD7767-2 32 32 kHz Figure 28. AD7767/AD7767-1/AD7767-2 Transfer Function CONVERTER OPERATION Note that the output data rates shown in Table 6 are realized Internally, the input waveform applied to the SAR core is when using the maximum MCLK input frequency of 1.024 MHz. converted and an equivalent digital word is output to the digital The output data rate scales linearly with the MCLK frequency, filter at a rate equal to MCLK. By employing oversampling, the as does the digital power dissipated in the device. quantization noise of the converter is spread across a wide The settling time of the filter implemented on the AD7767, bandwidth from 0 to f . This means that the noise energy MCLK AD7767-1, and AD7767-2 is related to the length of the filter contained in the signal band of interest is reduced (see employed. The response of the filter in the time domain sets the Figure 29). filter settling time. Table 7 shows the filter settling times of the AD7767/AD7767-1/AD7767-2. The frequency responses of the digital filters on the AD7767, QUANTIZATION NOISE AD7767-1, and AD7767-2 are shown in Figure 32, Figure 33, f MCLK/2 BAND OF INTEREST and Figure 34, respectively. At the Nyquist frequency (output data rate/2), the digital filter provides 6 dB of attenuation. In each Figure 29. Quantization Noise case, the filter provides stop-band attenuation of 100 dB and pass-band ripple of ±0.005 dB. DIGITAL FILTER CUTOFF FREQUENCY f MCLK/2 BAND OF INTEREST Figure 30. Digital Filter Cutoff Frequency Rev. C | Page 15 of 24 24-BIT OUTPUT 06859-214 06859-213 06859-012 06859-019 AD7767 0 ANALOG INPUT STRUCTURE –20 The AD7767/AD7767-1/AD7767-2 are configured as a differential input structure. A true differential signal is sampled between the –40 analog inputs VIN+ and VIN−, Pin 4 and Pin 5, respectively. Using –60 differential inputs provides rejection of signals that are common to both the V and V pins. IN+ IN− –80 Figure 35 shows the equivalent analog input circuit of the –100 AD7767/AD7767-1/AD7767-2. The two diodes on each of the –120 differential inputs provide ESD protection for the analog inputs. V –140 REF+ D –160 C2 R IN 0 16k 32k 48k 64k 80k 96k 112k 128k V IN+ FREQUENCY (Hz) C1 D Figure 32. AD7767 Digital Filter Frequency Response GND AGND V REF+ 0 D C2 R IN V –20 IN– C1 D –40 GND AGND –60 Figure 35. Equivalent Analog Input Structure –80 Take care to ensure that the analog input signal does not exceed the reference supply voltage (V ) by more than 0.3 V, as specified –100 REF+ in the Absolute Maximum Ratings section. If the input voltage –120 exceeds this limit, the diodes become forward biased and start –140 to conduct current. The diodes can handle 130 mA maximum. –160 The impedance of the analog inputs can be modeled as a parallel 0 8k 16k 24k 32k 40k 48k 56k 64k combination of C1 and the network formed by the series con- FREQUENCY (Hz) nection of R , C1, and C2. The value of C1 is dominated by the IN Figure 33. AD7767-1 Digital Filter Frequency Response pin capacitance. R is typically 1.4 kΩ, the lumped component IN of the switches. C2 is typically of serial resistors and the RON 0 22 pF, and its value is dominated by the sampling capacitor. –20 SUPPLY AND REFERENCE VOLTAGES The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply –40 applied to the DV and AV pins. The interface is specified to DD DD –60 operate between 1.7 V and 3.6 V. The AD7767/AD7767-1/ –80 AD7767-2 operate from a reference input in the range of 2.2 V to 2 × AVDD applied to the VREF+ pin. The nominal reference –100 supply voltage is 5 V, but a 2.5 V supply can also be used. When –120 using a 5 V reference, the recommended reference devices are the ADR445, ADR435, or ADR425; when using 2.5 V, the ADR441, –140 ADR431, or ADR421 are recommended. The voltage applied to –160 the reference input (VREF+) operates both as a reference supply 0 4k 8k 12k 16k 20k 24k 28k 32k FREQUENCY (Hz) and as a power supply to the AD7767/AD7767-1/AD7767-2 Figure 34. AD7767-2 Digital Filter Frequency Response device. Therefore, when using a 5 V reference input, the full-scale differential input range of the AD7767/AD7767-1/AD7767-2 is 10 V. See the Driving the AD7767 section for details on the maximum input voltage. Rev. C | Page 16 of 24 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06859-218 06859-217 06859-216 06859-219 AD7767 AD7767 INTERFACE The AD7767 provides the user with a flexible serial interface, The AD7767 offers the option of using a chip select input signal enabling the user to implement the most desirable interfacing (CS) in its data read cycle. The CS signal is a gate for the SDO pin scheme for their application. The AD7767 interface comprises and allows many AD7767 devices to share the same serial bus. It seven different signals. Five of these signals are inputs: MCLK, acts as an instruction signal to each of these devices indicating CS SYNC PD , / , SCLK, and SDI. The other two signals are CS permission to use the bus. When is logic high, the SDO line DRDY outputs: and SDO. of the AD7767 is tristated. There are two distinct patterns that can be initiated to read data INITIAL POWER-UP CS from the AD7767 device: a pattern for when the falling edge On initial power-up, apply a continuous MCLK signal. It is occurs after the DRDY falling edge and a pattern for when the recommended that the user reset the AD7767 to clear the filters CS CS falling edge occurs before the DRDY falling edge (when and ensure correct operation. The reset is completed as shown in Figure 5, with all events occurring relative to the rising edge is set to logic low). of MCLK. A negative pulse on the / input initiates the SYNC PD CS When the falling edge occurs after the DRDY falling edge, reset, and the DRDY output switches to logic high and remains the MSB of the conversion result is available on the SDO line on high until valid data is available. Following the power-up of the the CS falling edge. The remaining bits of the conversion result AD7767 by transitioning the SYNC/PD pin to logic high, a settling (MSB − 1, MSB − 2, and so on) are clocked onto the SDO line time is required before valid data is output by the device. This by the falling edges of SCLK that follow the CS falling edge. settling time, tSETTLING, is a function of the MCLK frequency and Figure 3 details this interfacing scheme. the decimation rate. Table 7 lists the settling time of each AD7767 CS When is tied low, the AD7767 serial interface can operate in model and should be referenced when reviewing Figure 5. 3-wire mode as shown in Figure 4. In this case, the MSB of the SYNC PD Table 7. Filter Settling Time After / conversion result is available on the SDO line on the falling 1 Model Decimation Rate t edge of DRDY. The remaining bits of the data conversion result SETTLING AD7767 8 (594 × tMCLK) + t21 (MSB − 1, MSB − 2, and so on) are clocked onto the SDO line AD7767-1 16 (1186 × tMCLK) + t21 by the subsequent SCLK falling edges. AD7767-2 32 (2370 × t ) + t MCLK 21 POWER-DOWN, RESET, AND SYNCHRONIZATION 1 t is measured from the first MCLK rising edge after the rising edge of SYNC/PD SETTLING The AD7767 SYNC/PD pin allows the user to synchronize to the falling edge of DRDY. multiple AD7767 devices. This pin also allows the user to reset and power down the AD7767 device. These features are READING DATA implemented relative to the rising edges of MCLK and are The AD7767 outputs its data conversion results in an MSB-first, shown in Figure 5, marked as A, B, C, and D. twos complement, 24-bit format on the serial data output pin To power down, reset, or synchronize a device, the AD7767 (SDO). MCLK is the master clock, which controls all the AD7767 / pin should be taken low. On the first rising edge of SYNC PD conversions. The SCLK is the serial clock input for the device. MCLK, the AD7767 is powered down. The DRDY pin transi- All data transfers take place with respect to the SCLK signal. tions to logic high, indicating that the data in the output register The line is used as a status signal to indicate when the DRDY is no longer valid. The status of the / pin is checked on SYNC PD data is available to be read from the AD7767. The falling edge of each subsequent rising edge of MCLK. On the first rising edge indicates that a new data-word is available in the output DRDY of MCLK after the SYNC/PD pin is taken high, the AD7767 is register of the device. DRDY stays low during the period that taken out of power-down. On the next rising edge, the filter of output data is permitted to be read from the SDO pin. The the AD7767 is reset. On the following rising edge, the first new signal returns to logic high to indicate when not to read DRDY sample is taken. from the device. Ensure that a data read is not attempted during A settling time, tSETTLING, from the filter reset must elapse before this period while the output register is being updated. DRDY valid data is output by the device (see Table 7). The output goes logic low after t to indicate when valid data is SETTLING available on SDO for readback. Rev. C | Page 17 of 24 AD7767 DAISY CHAINING Daisy chaining devices allows numerous devices to use the same This is illustrated in the examples shown (Figure 37 and Figure 38), digital interface lines by cascading the outputs of multiple ADCs where the conversion results from the devices labeled A, B, C, on a single data line. This feature is especially useful for reduc- and D are clocked onto SDO (A) during the time between the ing component count and wiring connections, for example, in falling edge of DRDY (A) and the rising edge of DRDY (A). isolated multiconverter applications or for systems with a limited CHOOSING THE SCLK FREQUENCY interfacing capacity. Data readback is analogous to clocking a As shown in Figure 37, the number of SCLK falling edges that shift register where data is clocked on the falling edge of SCLK. occur during the period when DRDY (A) is active low must The block diagram in Figure 36 shows how devices must be match the number of devices in the chain multiplied by 24 (the connected to achieve daisy-chain functionality. The scheme number of bits that must be clocked through onto SDO (A) for shown operates by passing the output data of the SDO pin of an each device). AD7767 device to the SDI input of the next AD7767 device in The period of SCLK (t ) required for a known daisy-chain SCLK the chain. The data then continues through the chain until it is length using a known common MCLK frequency must, clocked onto the SDO pin of the first device in the chain. therefore, be established in advance. Note that the maximum READING DATA IN DAISY-CHAIN MODE SCLK frequency is governed by t8 and is specified in the Timing An example of a daisy chain of four AD7767 devices is shown in Specifications table for different VDRIVE voltages. Figure 36 and Figure 37. In the case illustrated in Figure 36, the CS In the case where is tied logic low, output of the AD7767 labeled A is the output of the full daisy chain. The last device in the chain (the AD7767 labeled D) has t ⎡ ⎤ READ t ≤ (1) SCLK ⎢ ⎥ its serial data input (SDI) pin connected to ground. All the 24× K ⎣ ⎦ CS devices in the chain must use common MCLK, SCLK, , and where: SYNC/PD signals. K is the number of AD7767 devices in the chain. t is the period of the SCLK. To enable the daisy-chain conversion process, apply a common SCLK t equals t − t . SYNC/PD pulse to all devices, synchronizing all the devices in READ 5 DRDY the chain (see the Power-Down, Reset, and Synchronization In the case where CS is used in the daisy-chain interface, section). (t )−(t + t + t ) ⎡ ⎤ 6 7 13 READ SYNC PD After applying a / pulse to all the devices, there is a t ≤ (2) SCLK ⎢ ⎥ 24× K ⎣ ⎦ delay (as listed in Table 7) before valid conversion data appears where: at the output of the chain of devices. As shown in Figure 37, the K is the number of AD7767 devices in the chain. first conversion result is output from the AD7767 device labeled t is the period of the SCLK. A. This 24-bit conversion result is followed by the conversion SCLK t equals t − t . results from the devices labeled B, C, and D, respectively, with READ 5 DRDY all conversion results output in an MSB-first sequence. The Note that the maximum value of SCLK is governed by t8 and is stream of conversion results is clocked through each device in specified in the Timing Specifications table for different VDRIVE the chain and is eventually clocked onto the SDO pin of the voltages. AD7767 device labeled A. The conversion results of all the devices in the chain must be clocked onto the SDO pin of the final device in the chain while its DRDY signal is active low. Rev. C | Page 18 of 24 AD7767 DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS SYNC/PD CS SYNC/PD SYNC/PD SYNC/PD SYNC/PD CS CS CS CS DRDY AD7767 AD7767 AD7767 AD7767 (D) (C) (B) (A) SDI SDI SDO SDI SDO SDI SDO SDI SDO SCLK SCLK SCLK SCLK MCLK MCLK MCLK MCLK SCLK MCLK Figure 36. Daisy-Chain Configuration with Four AD7767 Devices 1 8 × n MCLK DRDY (A) CS 24 × t 24 × t 24 × t 24 × t SCLK SCLK SCLK SCLK SCLK AD7767 (A) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (A) SDO (A) SDI (A) = SDO (B) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (B) AD7767 (C) AD7767 (D) AD7767 (C) SDI (B) = SDO (C) SDI (C) = SDO (D) AD7767 (D) AD7767 (D) Figure 37. Daisy-Chain Timing Diagram (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) When Driving the AD7767 1 MCLK DRDY (A) CS SDO (A) MSB (A) LSB (A) MSB (B) LSB (B) MSB (C) LSB (C) SCLK t 16 t 17 SDI (A) = SDO (B) MSB (B) LSB (B) MSB (C) LSB (C) MSB (D) LSB (D) Figure 38. Daisy-Chain SDI Setup and Hold Timing Rev. C | Page 19 of 24 06859-013 06859-015 06859-014 AD7767 DRIVING THE AD7767 The AD7767 must be driven with fully differential inputs. The R1 and R2 set the attenuation ratio between the input range and common-mode voltage of the differential inputs to the AD7767 the ADC range (VREF). R1, R2, and CF are chosen depending on device and therefore the limits on the differential inputs are set the desired input resistance, signal bandwidth, antialiasing, and by the reference voltage (VREF) applied to the device. The common- noise contribution. The ratio of R2 to R1 should be equal to the mode voltage of the AD7767 is V /2. When the AD7767 V pin ratio of REF to the peak-to-peak input voltage. For example, for REF REF+ has a 5 V supply (using ADR445, ADR435, or ADR425), the the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. common mode is at 2.5 V, meaning that the maximum inputs that R3 and R4 set the common mode on the IN− input, and R5 and R6 can be applied on the AD7767 differential inputs are a 5 V p-p set the common mode on the IN+ input of the ADC. The common input around 2.5 V. mode, which is equal to the voltage present at VOFFSET1, should be V REF close to VREF/2. The voltage present should roughly be set to the ratio of VOFFSET1 to 1 + R2/R1. V V 1kΩ REF IN+ 2 3.3nF ADP3330-2.5 1kΩ 0V AIN+ 2.5V 15Ω V ADA4841-1 REF 2.2nF 1 V IN– 1kΩ 4 AV V DD V REF IN+ 2 AD7767 3.3nF 5 V V REF+ IN– 1kΩ 2 AIN– 0V 2.2nF 15Ω * Figure 39. Maximum Differential Inputs to the AD7767 ADA4841-1 2.5V TO 5V 1kΩ REFERENCE An analog voltage of 2.5 V supplies the AD7767 AVDD pin. VOLTAGE ADR4xx 1kΩ However, the AD7767 allows the user to apply a reference voltage of up to 5 V. This provides the user with an increased full-scale range, offering the user the option of using the *SEE V INPUT SIGNAL SECTION FOR DETAILS. REF+ AD7767 with a greater LSB voltage. Figure 39 shows the Figure 40. Driving the AD7767 from a Fully Differential Source maximum inputs to the AD7767. V IN VOUT = 5V REF ADR445 0.1µF 0.1µF DIFFERENTIAL SIGNAL SOURCE ADP3330-2.5 ADR425 R6 R5 Voffset1 2.5V An example of recommended driving circuitry that can be used LDO R3 R4 Voffset2 in conjunction with the AD7767/AD7767-1/AD7767-2 is shown in 100µF 5.2V Figure 40. Figure 40 shows how the ADA4841-1 device can be 100nF REF OUTN 15Ω used to drive an input to the AD7767/AD7767-1/AD7767-2 V REF+ AVDD V IN+ 2.2nF from a differential source. Each of the differential paths is AD7767 OUTP 2.2nF driven by an ADA4841-1 device. V IN– 100nF 15Ω IN AGND DGND SINGLE-ENDED SIGNAL SOURCE FB ADA4941 For applications using a single-ended analog signal, either –0.2V R1 bipolar or unipolar, the ADA4941-1 single-ended-to-differential Vin R2 driver creates a fully differential input to the AD7767/AD7767-1/ C AD7767-2. The schematic is shown in Figure 41. F Figure 41. Driving the AD7767 from a Single-Ended Source Table 8. Resistor Values Required When Using the Differential to Single-Ended Circuit with ADA4941 (See Figure 41) VIN (V) VOFFSET1 (V) VOFFSET2 (V) OUT+ (V) OUT− (V) R1 (kΩ) R2 (kΩ) R4 (kΩ) R3 = R5 = R6 (kΩ) +20, −20 2.5 2.203 −0.01, +4.96 5.01, 0.04 8.06 1 12.7 10 +10, −10 2.5 2.000 0.01, 4.99 4.99, 0.01 4.02 1 15 10 +5, −5 2.5 1.667 0.00, 5.00 5.00, 0.00 2 1 20 10 Rev. C | Page 20 of 24 06859-016 06859-018 06859-020 AD7767 applied divided by the decimation rate employed by the device ANTIALIASING in use. For instance, operating the AD7767 device with an MCLK The AD7767/AD7767-1/AD7767-2 sample the analog input of 800 kHz results in an output data rate of 100 kHz due to the at a maximum rate of 1.024 MHz. The on-board digital filter decimate-by-8 filtering. provides up to 100 dB attenuation for any possible aliasing 4.5 frequency in the range from the beginning of the filter stop band (0.547 × ODR) to where the image of the digital filter pass 4.0 band occurs. This occurs at MCLK minus the filter stop band 3.5 (MCLK − 0.547 × ODR), as shown in Figure 42. DI DD 3.0 f MCLK 2.5 2.0 DIGITAL FILTER 1.5 DIGITAL FILTER 100dB IMAGE AT f MCLK AI DD ANTIALIAS PROTECTION 1.0 f – (0.547 × ODR) MCLK 0.5 I REF BAND OF INTEREST FIRST IMAGE POINT 0 Figure 42. AD7767/AD7767-1/AD7767 Spectrum 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k FREQUENCY (Hz) Table 9 shows the attenuation achieved by various orders of Figure 43. AD7767 Current vs. MCLK Frequency front-end antialias filters prior to the signal entering the AD7767/ 2.5 AD7767-1/AD7767-2 at the image of the digital filter stop band, which is 1.024 MHz − 0.547 × ODR. 2.0 Table 9. Antialias Filter Order, DI DD Attenuation at at First Image Point Attenuation at 1.5 Model Filter Order 1.024 MHz – 0.547 × ODR AD7767 First 27 dB 1.0 Second 50 dB AI DD Third 70 dB 0.5 AD7767-1 First 33 dB I REF Second 62 dB Third 89 dB 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k AD7767-2 First 38 dB FREQUENCY (Hz) Second 74 dB Figure 44. AD7767-1 Current vs. MCLK Frequency Third 110 dB 1.4 DI DD The AD7764 and AD7765 ∑-Δ devices are available to 1.2 customers that require extra antialias protection. These devices 1.0 sample the signal internally at a rate of 20 MHz to achieve up to AI DD a maximum of 156 kHz or 312 kHz output data rate. This 0.8 means that the first alias point of these devices when run at the maximum speeds is 19.921 MHz and 19.843 MHz, respectively. 0.6 POWER DISSIPATION 0.4 I REF The AD7767/AD7767-1/AD7767-2 offer exceptional perform- 0.2 ance at ultralow power. Figure 43, Figure 44, and Figure 45 show how the current consumption of the AD7767/AD7767-1/ 0 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k AD7767-2 scales with the MCLK frequency applied to the device. FREQUENCY (Hz) Both the digital and analog currents scale as the MCLK frequency Figure 45. AD7767-2 Current vs. MCLK Frequency is reduced. The actual throughput equals the MCLK frequency Rev. C | Page 21 of 24 06859-231 CURRENT (mA) CURRENT (mA) CURRENT (mA) 06859-228 06859-227 06859-226 AD7767 V INPUT SIGNAL MULTIPLEXING ANALOG INPUT CHANNELS REF+ The AD7767/AD7767-1/AD7767-2 VREF + pin is supplied with a The AD7767/AD7767-1/AD7767-2 can be used with a multi- voltage in the range of 2.4 V to 2 × AVDD (nominally 5 V). It is plexer configuration. As per any converter that uses a digital recommended that the VREF+ input be generated by a low noise filtering block, the maximum switching rate or the output data voltage reference. Examples of such references are the ADR445, rate per channel is a function of the digital filter settling time. ADR435, ADR425 (5 V output), and ADR421 (2.5 V output). A user multiplexing the analog inputs to a converter that Typical reference supply circuits are shown in Figure 46. employs a digital filter must wait the full digital filter settling The reference voltage input pin (VREF+) also acts as a power time before a valid conversion result can be achieved; after this supply to the AD7767/AD7767-1/AD7767-2 device. For a 5 V settling time, the channel can be switched. Then, the full VREF+ input, a full-scale input of 5 V on both VIN+ and VIN− can settling time must again be observed before a valid conversion be applied while voltage supplies to pins AVDD remain at 2.5 V. result is available and the input is switched once more. This configuration reduces the number of different supplies The AD7767 filter settling time equals 74 divided by the output required. data rate in use. The maximum switching frequency in a The output of the low noise voltage reference does not require a multiplexed application is, therefore, 1/(74/ODR), where the buffer; however, decoupling the output of the low noise reference is output data rate (ODR) is a function of the applied MCLK important. Place a 0.1 μF capacitor at the output of the voltage frequency and the decimation rate employed by the device in reference devices (ADR445, ADR435, ADR425, and ADR421) question. For example, applying a 1.024 MHz MCLK frequency and follow the decoupling advice provided for the reference to the AD7767 results in a maximum output data rate of 128 kHz, device chosen. which in turn allows a 1.729 kHz multiplexer switching rate. As mentioned, the nominal supply to the V pin is 5 V to The AD7767-1 and the AD7767-2 employ digital filters with REF+ achieve the full dynamic range available. When a 2.5 V V longer settling time to achieve greater precision; thus, the REF+ input is used (that is, in low power applications), the signal-to- maximum switching frequency for these devices is 864 Hz and 432 Hz, respectively. noise ratio and dynamic range figures (generated using a 5 V VREF+ input) quoted in the Specifications section decrease by 6 dB, a direct result of halving the available input range. The AD7767/AD7767-1/AD7767-2 device requires a 100 μF capacitor to ground, which acts as a decoupling capacitor and as a reservoir of charge for the V pin. Place this capacitor as REF+ close to the AD7767/AD7767-1/AD7767-2 device as possible. Reducing the value of this capacitor (C40 in Figure 46) to 10 μF typically degrades noise performance by 1 dB. C40 can be an electrolytic or tantalum capacitor. REFERENCE SUPPLY V+ V V V IN OUT REF+ C39 C40 C34 C35 AD7767/ 0.1µF 100µF 10µF 0.1µF ADR4xx AD7767-1/ AD7767-2 Figure 46. AD7767/AD7767-1/AD7767-2 Reference Input Configuration Rev. C | Page 22 of 24 06859-021 AD7767 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7767BRUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7767BRUZ-RL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7767BRUZ-1 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7767BRUZ-1-RL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7767BRUZ-2 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD7767BRUZ-2-RL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 EVAL-AD7767EDZ Evaluation Board EVAL-AD7767-1EDZ Evaluation Board EVAL-AD7767-2EDZ Evaluation Board EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. Rev. C | Page 23 of 24 AD7767 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06859-0-5/10(C) Rev. C | Page 24 of 24