ANALOG DEVICES AD7765

24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface AD7765 FEATURES FUNCTIONAL BLOCK DIAGRAM V A– V A+ V + V – MCLK GND OUT OUT IN IN High performance, 24-bit Σ-Δ ADC 115 dB dynamic range at 78 kHz output data rate AV 1 V A+ DD IN DIFF AV 2 DD 112 dB dynamic range at 156 kHz output data rate MULTIBIT V A– IN AV 3 Σ-Δ DD 156 kHz maximum fully filtered output word rate MODULATOR AV 4 DD DV Pin-selectable oversampling rate (128× and 256×) DD V + REF BUF Low power mode RECONSTRUCTION OVERRANGE Flexible SPI REFGND DECIMATION DEC_RATE Fully differential modulator input SYNC INTERFACE LOGIC AND OFFSET AND GAIN On-chip differential amplifier for signal buffering FIR FILTER ENGINE R CORRECTION REGISTERS BIAS RESET/PWRDWN On-chip reference buffer AD7765 Full band low-pass finite impulse response (FIR) filter FSO SCO SDI SDO FSI Overrange alert pin Figure 1. Digital gain correction registers The differential input is sampled at up to 40 MSPS by an analog Power-down mode modulator. The modulator output is processed by a series of Synchronization of multiple devices via SYNC pin low-pass filters. The external clock frequency applied to the Daisy chaining AD7765 determines the sample rate, filter corner frequencies, APPLICATIONS and output word rate. Data acquisition systems The AD7765 device boasts a full band on-board FIR filter. The Vibration analysis full stop-band attenuation of the filter is achieved at the Nyquist Instrumentation frequency. This feature offers increased protection from signals that lie above the Nyquist frequency being aliased back into the GENERAL DESCRIPTION input signal bandwidth. The AD7765 is a high performance, 24-bit sigma-delta (Σ-Δ) The reference voltage supplied to the AD7765 determines the analog-to-digital converter (ADC). It combines wide input input range. With a 4 V reference, the analog input range is bandwidth, high speed, and performance of 112 dB dynamic ±3.2768 V differential, biased around a common mode of range at a 156 kHz output data rate. With excellent dc specifications, the converter is ideal for high speed data 2.048 V. This common-mode biasing can be achieved using acquisition of ac signals where dc data is also required. the on-chip differential amplifier, further reducing the external signal conditioning requirements. Using the AD7765 eases the front-end antialias filtering The AD7765 is available in a 28-lead TSSOP package and is requirements, simplifying the design process significantly. The specified over the industrial temperature range of −40°C AD7765 offers pin-selectable decimation rates of 128× and to +85°C. 256×. Other features include an integrated buffer to drive the reference, as well as a fully differential amplifier to buffer and Table 1. Related Devices level shift the input to the modulator. Part No. Description An overrange alert pin indicates when an input signal has AD7760 2.5 MSPS, 100 dB, parallel output, on-chip buffers exceeded the acceptable range. The addition of internal gain AD7762 625 kSPS, 109 dB, parallel output, on-chip buffers and internal overrange registers makes the AD7765 a compact, AD7763 625 kSPS, 109 dB, serial output, on-chip buffers highly integrated data acquisition device requiring minimal AD7764 312 kSPS, 109 dB, serial output, on-chip buffers peripheral components. AD7766 128/64/32 kSPS, 8.5 mW, 109 dB SNR The AD7765 also offers a low power mode, significantly AD7767 128/64/32 kSPS, 8.5 mW, 109 dB SNR reducing power dissipation without reducing the output data rate or available input bandwidth. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06519-001 AD7765 TABLE OF CONTENTS AD7765 Functionality ................................................................... 21 Features .............................................................................................. 1 Synchronization .......................................................................... 21 Applications ....................................................................................... 1 Overrange Alerts ........................................................................ 21 General Description ......................................................................... 1 Power Modes ............................................................................... 22 Functional Block Diagram .............................................................. 1 Decimation Rate Pin .................................................................. 22 Revision History ............................................................................... 2 Daisy Chaining ............................................................................... 23 Specifications ..................................................................................... 3 Reading Data in Daisy-Chain Mode ....................................... 23 Timing Specifications .................................................................. 6 Writing Data in Daisy-Chain Mode ........................................ 24 Timing Diagrams .......................................................................... 7 Clocking the AD7765 .................................................................... 25 Absolute Maximum Ratings ............................................................ 8 MCLK Jitter Requirements ....................................................... 25 ESD Caution .................................................................................. 8 Decoupling and Layout Information ........................................... 26 Pin Configuration and Function Descriptions ............................. 9 Supply Decoupling ..................................................................... 26 Typical Performance Characteristics ........................................... 11 Reference Voltage Filtering ....................................................... 26 Terminology .................................................................................... 14 Differential Amplifier Components ........................................ 26 Theory of Operation ...................................................................... 15 Layout Considerations ............................................................... 26 Σ-Δ Modulation and Digital Filtering ...................................... 15 Using the AD7765 ...................................................................... 27 AD7765 Antialias Protection .................................................... 16 Bias Resistor Selection ............................................................... 27 AD7765 Input Structure ................................................................ 17 AD7765 Registers ........................................................................... 28 On-Chip Differential Amplifier ............................................... 18 Control Register ......................................................................... 28 Modulator Input Structure ........................................................ 19 Status Register ............................................................................. 28 Driving the Modulator Inputs Directly ................................... 19 Gain Register—Address 0x0004 ............................................... 29 AD7765 Interface ............................................................................ 20 Overrange Register—Address 0x0005 ..................................... 29 Reading Data ............................................................................... 20 Outline Dimensions ....................................................................... 30 Reading Status and Other Registers ......................................... 20 Ordering Guide .......................................................................... 30 Writing to the AD7765 .............................................................. 20 REVISION HISTORY 8/09—Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 8 Changes to Σ-Δ Modulation and Digital Filtering Section ....... 15 Added AD7765 Antialias Protection Section ............................. 16 Added Driving the Modulator Inputs Directly Section ............ 19 Changes to Synchronization Section, Added Figure 35 ............ 21 Changes to Power Modes Section, Added RESET/PWRDWN Mode Section, Added Figure 38 ................................................... 22 Changes to Daisy Chaining Section ............................................. 23 Changes to Using the AD7765 Section ........................................ 27 6/07—Revision 0: Initial Version Rev. A | Page 2 of 32 AD7765 SPECIFICATIONS AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, MCLK amplitude = 5 V, TA = +25°C, normal power mode, using 1 the on-chip amplifier with components as shown in the Optimal row in Table 7, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Specification Unit DYNAMIC PERFORMANCE Decimate 256× Normal Power Mode MCLK = 40 MHz, ODR = 78.125 kHz, fIN = 1 kHz sine wave Dynamic Range Modulator inputs shorted 115 dB typ 110 dB min Differential amplifier inputs shorted 113.4 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 109 dB typ 106 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 130 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −103 dB typ Input amplitude = −60 dB −71 dB typ Low Power Mode MCLK = 40 MHz, ODR = 78.125 kHz, fIN = 1 kHz sine wave Dynamic Range Modulator inputs shorted 113 dB typ 110 dB min Differential amplifier inputs shorted 112 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 109 dB typ 106 dB min Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −111 dB typ Input amplitude = −6 dB −100 dB max Input amplitude = −60 dB −76 dB typ Decimate 128× Normal Power Mode MCLK = 40 MHz, ODR = 156.25 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 112 dB typ 108 dB min Differential amplifier inputs shorted 110.4 dB typ 2 Signal-to-Noise Ratio (SNR) 107 dB typ 105 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 130 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −103 dB typ Intermodulation Distortion (IMD) Input amplitude = −6 dB, f A = 50.3 kHz, f B = 47.3 kHz IN IN Second-order terms −117 dB typ Third-order terms −108 dB typ Low Power Mode MCLK = 40 MHz, ODR = 156.25 kHz, fIN = 1 kHz sine wave Dynamic Range Modulator inputs shorted 110 dB typ 109 dB min Differential amplifier inputs shorted 109 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 107 dB typ 105 dB min Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −111 dB typ Input amplitude = −6 dB −100 dB max Intermodulation Distortion (IMD) Input amplitude = −6 dB, f A= 50.3 kHz, f B = 47.3 kHz IN IN Second-order terms −134 dB typ Third-order terms −110 dB typ Rev. A | Page 3 of 32 AD7765 Parameter Test Conditions/Comments Specification Unit DC ACCURACY Resolution Guaranteed monotonic to 24 bits 24 Bits Normal power mode 0.0036 % typ Integral Nonlinearity Low power mode 0.0014 % typ Normal power mode 0.006 % typ Zero Error 0.03 % max Including on-chip amplifier 0.04 % typ Low power mode 0.002 % typ 0.024 % max 0.018 % typ Gain Error Including on-chip amplifier 0.04 % typ Zero Error Drift 0.00006 %FS/°C typ Gain Error Drift 0.00005 %FS/°C typ DIGITAL FILTER CHARACTERISTICS Pass-Band Ripple 0.1 dB typ 3 Pass Band −1 dB frequency ODR × 0.4016 kHz 3 −3 dB Bandwidth ODR × 0.4096 kHz 3 Stop Band Beginning of stop band ODR × 0.5 kHz Stop-Band Attenuation Decimate 128× 120 dB typ Decimate 256× 115 Group Delay Decimate 128× MCLK = 40 MHz 177 µs typ Decimate 256× MCLK = 40 MHz 358 µs typ ANALOG INPUT Differential Input Voltage Modulator input pins: VIN+ − VIN−, VREF+ = 4.096 V ±3.2768 V p-p Input Capacitance At on-chip differential amplifier inputs 5 pF typ At modulator inputs 29 pF typ REFERENCE INPUT/OUTPUT VREF+ Input Voltage AVDD3 = 5 V ± 5% 4.096 V VREF+ Input DC Leakage Current ±1 µA max V Input Capacitance 5 pF typ REF+ DIGITAL INPUT/OUTPUT MCLK Input Amplitude 2.25 to 5.25 V Input Capacitance 7.3 pF typ Input Leakage Current ±1 μA/pin max VINH 0.8 × DVDD V min VINL 0.2 × DVDD V max 4 VOH 2.2 V min V 0.1 V max OL ON-CHIP DIFFERENTIAL AMPLIFIER Input Impedance >1 MΩ Bandwidth for 0.1 dB Flatness 125 kHz Common-Mode Input Voltage Voltage range at input pins: V A− and V A+ −0.5 to +2.2 V IN IN Common-Mode Output Voltage On-chip differential amplifier pins: V A+ and V A− 2.048 V OUT OUT POWER REQUIREMENTS AV 1 (Modulator Supply) ±5% 2.5 V DD AV 2 (General Supply) ±5% 5 V DD AVDD3 (Differential Amplifier Supply) ±5% 5 V min/max AVDD4 (Reference Buffer Supply) ±5% 5 V min/max DVDD ±5% 2.5 V Rev. A | Page 4 of 32 AD7765 Parameter Test Conditions/Comments Specification Unit Normal Power Mode AIDD1 (Modulator) 19 mA typ 5 AIDD2 (General) MCLK = 40 MHz 13 mA typ AI 3 (Differential Amplifier) AV 3 = 5 V 10 mA typ DD DD AI 4 (Reference Buffer) AV 4 = 5 V 9 mA typ DD DD 5 DI MCLK = 40 MHz 37 mA typ DD Low Power Mode AIDD1 (Modulator) 10 mA typ 5 AI 2 (General) MCLK = 40 MHz 7 mA typ DD AI 3 (Differential Amplifier) AV 3 = 5 V 5.5 mA typ DD DD AI 4 (Reference Buffer) AV 4 = 5 V 5 mA typ DD DD 5 DIDD MCLK = 40 MHz 20 mA typ POWER DISSIPATION Normal Power Mode MCLK = 40 MHz, decimate 128× 300 mW typ 371 mW max Low Power Mode MCLK = 40 MHz, decimate 128× 160 mW typ 215 mW max 6 Power-Down Mode PWRDWN held logic low 1 mW typ 1 See Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7765 = [(40 MHz/2)/128] = 156.25 kHz. 4 Tested with a 400 µA load current. 5 Tested at MCLK = 40 MHz. This current scales linearly with the MCLK frequency applied. 6 Tested at 125°C. Rev. A | Page 5 of 32 AD7765 TIMING SPECIFICATIONS AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, TA = 25°C, CLOAD = 25 pF. Table 3. Parameter Limit at TMIN, TMAX Unit Description f 500 kHz min Applied master clock frequency MCLK 40 MHz max fICLK 250 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1 × t typ SCO high period 1 ICLK t 1 × t typ SCO low period 2 ICLK t3 1 ns typ SCO rising edge to FSO falling edge t4 2 ns typ Data access time, FSO falling edge to data active t5 8 ns max MSB data access time, SDO active to SDO valid t 40 ns min Data hold time (SDO valid to SCO rising edge) 6 t 9.5 ns max Data access time (SCO rising edge to SDO valid) 7 t 2 ns typ 8 SCO rising edge to FSO rising edge t9 32 × tSCO max FSO low period t10 12 ns min Setup time from FSI falling edge to SCO falling edge t11 1 × tSCO min FSI low period 1 t 32 × t max FSI low period 12 SCO t 12 ns min SDI setup time for the first data bit 13 t14 12 ns min SDI setup time t15 0 ns max SDI hold time tR MIN 1 × tMCLK min Minimum time for a valid RESET pulse tR HOLD 5 ns min Minimum time between the MCLK rising edge and RESET rising edge t 5 ns min Minimum time between the RESET rising edge and MCLK rising edge R SETUP t 4 × t min Minimum time for a valid SYNC pulse S MIN MCLK tS HOLD 5 ns min Minimum time between the MCLK falling edge and SYNC rising edge tS SETUP 5 ns min Minimum time between the SYNC rising edge and MCLK falling edge 1 FSI This is the maximum time can be held low when writing to an individual device (a device that is not daisy-chained). Rev. A | Page 6 of 32 AD7765 TIMING DIAGRAMS 32 × t SCO t 1 SCO (O) t 8 t 2 t 9 t 3 FSO (O) t 4 t 6 t 5 t 7 SDO (O) D23 D22 D21 D20 D19 D1 D0 ST4 ST3 ST2 ST1 ST0 0 0 0 Figure 2. Serial Read Timing Diagram t 1 SCO (O) t 2 t 12 t 10 t FSI (I) 11 t 14 t 13 t 15 SDI (I) RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA1 RA0 D15 D14 D1 D0 Figure 3. AD7765 Register Write SCO (O) ≥8 × t SCO FSO (O) STATUS REGISTER DON’T CARE SDO (O) CONTENTS [31:16] BITS [15:0] NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER FSI (I) CONTROL REGISTER CONTROL REGISTER SDI (I) ADDR (0x0001) INSTRUCTION Figure 4. AD7765 Status Register Read Cycle Rev. A | Page 7 of 32 06519-004 06519-003 06519-002 AD7765 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any other conditions above those listed in the operational sections Parameters Rating of this specification is not implied. Exposure to absolute AV 1 to GND −0.3 V to +2.8 V DD maximum rating conditions for extended periods may affect AV 2, AV 3, AV 4 to GND −0.3 V to +6 V DD DD DD device reliability. DVDD to GND −0.3 V to +2.8 V 1 VINA+, VINA− to GND −0.3 V to +6 V 1 VIN+, VIN− to GND −0.3 V to +6 V ESD CAUTION 2 Digital Input Voltage to GND −0.3 V to +2.8 V 3 V + to GND −0.3 V to +6 V REF 4 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV 1 Absolute maximum voltage for V −, V +, V A−, and V A+ is 6.0 V or IN IN IN IN AVDD3 + 0.3 V, whichever is lower. 2 Absolute maximum voltage on digital inputs is 3.0 V or DV + 0.3 V, DD whichever is lower. 3 Absolute maximum voltage on V input is 6.0 V or AV 4 + 0.3 V, REF+ DD whichever is lower. 4 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 8 of 32 AD7765 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 28 V A– AV 3 IN DD V A+ 2 27 V + OUT REF V A+ 3 26 REFGND IN V A– 4 25 AV 4 OUT DD V – 5 24 AV 1 IN DD V + 6 AD7765 23 AGND1 IN TOP VIEW AV 2 7 22 R DD BIAS (Not to Scale) 8 21 AGND3 AV 2 DD 9 20 OVERRANGE AGND2 10 19 SCO MCLK 11 18 FSO DEC_RATE 12 17 SDO DV DD SDI 13 16 RESET/PWRDWN 14 15 FSI SYNC Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 24 AVDD1 2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 7 and 21 AV 2 5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be DD decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 28 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a 100 nF capacitor. 25 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 17 DV 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with DD a 100 nF capacitor. 22 RBIAS Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the Bias Resistor Selection section. 23 AGND1 Power Supply Ground for Analog Circuitry. 20 AGND2 Power Supply Ground for Analog Circuitry. 8 AGND3 Power Supply Ground for Analog Circuitry. 26 REFGND Reference Ground. Ground connection for the reference voltage. 27 VREF+ Reference Input. 1 VINA− Negative Input to Differential Amplifier. 2 VOUTA+ Positive Output from Differential Amplifier. 3 V A+ Positive Input to Differential Amplifier. IN 4 V A− Negative Output from Differential Amplifier. OUT 5 VIN− Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7765 section for further details. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address and the second word contains the data. See the AD7765 Interface section for further details. Rev. A | Page 9 of 32 06519-005 AD7765 Pin No. Mnemonic Description 14 FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7765 Interface section for further details. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. See the Synchronization section for further details. 16 RESET Reset/Power-Down Pin. When a logic low is sensed on this pin, the part is powered down and all internal / circuitry is reset. PWRDWN 19 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the AD7765 section for more details. 18 DEC_RATE Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a decimation rate of 128× is selected. A decimation rate of 256× is selected by setting the pin to ground. Rev. A | Page 10 of 32 AD7765 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, MCLK amplitude = 5 V, TA = 25°C. Linearity plots measured to 16-bit accuracy; input signal reduced to avoid modulator overload and digital clipping; fast Fourier transforms (FFTs) generated from 8,192 samples. 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 25k 50k 75k 0 10k 20k 30k 40k 50k 60k 70k FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Normal Power Mode; FFT, 1 kHz, −0.5 dB Input Tone, Figure 9. Low Power Mode; FFT, 1 kHz, −0.5 dB Input Tone, 128× Decimation Rate 128× Decimation Rate 0 –15 –25 –35 –50 –55 –75 –75 –95 –100 –115 –125 –135 –150 –155 –175 –175 0 5k 10k 15k 20k 25k 30k 35k 0 10k 20k 30k FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Normal Power Mode; FFT, 1 kHz, −0.5 dB Input Tone, Figure 10. Low Power Mode; FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation Rate 256× Decimation Rate 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 25k 50k 75k 0 25k 50k 75k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Normal Power Mode; FFT, 1 kHz, −6 dB Input Tone, Figure 11. Low Power Mode; FFT, 1 kHz, −6 dB Input Tone, 128× Decimation Rate 128× Decimation Rate Rev. A | Page 11 of 32 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06519-201 06519-008 06519-007 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06519-204 06519-210 06519-211 AD7765 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 10k 20k 30k 0 5k 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Normal Power Mode; FFT, 1 kHz, −6 dB Input Tone, Figure 15. Low Power Mode; FFT, 1 kHz, −6 dB Input Tone, 256× Decimation Rate 256× Decimation Rate 40 25 DV DD 35 DV DD 20 30 25 15 AV 1 DD 20 AV 1 DD AV 2 DD 10 15 AV 2 DD 10 5 AV 3 DD 5 AV 3 DD AV 4 AV 4 DD DD 0 0 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 13. Normal Power Mode; Current Consumption vs. MCLK Frequency, Figure 16. Low Power Mode; Current Consumption vs. MCLK Frequency, 128× Decimation Rate 128× Decimation Rate 40 20 18 35 DV DD DV DD 16 30 14 25 AV 1 12 DD AV 1 DD 20 10 AV 2 8 DD AV 2 15 DD 6 10 4 AV 3 AV 3 DD DD 5 2 AV 4 AV 4 DD DD 0 0 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 14. Normal Power Mode; Current Consumption vs. MCLK Frequency, Figure 17. Low Power Mode; Current Consumption vs. MCLK Frequency, 256× Decimation Rate 256× Decimation Rate Rev. A | Page 12 of 32 CURRENT (mA) CURRENT (mA) AMPLITUDE (dB) 06519-400 06519-112 06519-114 CURRENT (mA) CURRENT (mA) AMPLITUDE (dB) 06519-205 06519-113 06519-115 AD7765 0.003225 0.00300 –40°C 0.003000 +85°C 0.00225 0.00150 0.002250 +25°C 0.00075 +25°C 0 0.001500 –0.00075 +85°C –40°C 0.000075 –0.00150 –0.00225 0 –0.00300 –0.000120 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 16-BIT CODE SCALING 16-BIT CODE SCALING Figure 18. Normal Power Mode INL Figure 21. Low Power Mode INL 0 110 –20 109 LOW SNR –40 108 NORMAL SNR –60 107 –80 106 –100 105 –120 104 –140 103 –160 –180 102 0 20k 40k 60k 78,124 0 64 128 192 256 FREQUENCY (Hz) DECIMATION RATE Figure 19. Normal Power Mode; IMD, fIN A = 49.7 kHz, fIN B = 50.3 kHz, Figure 22. Normal and Low Power Mode; SNR vs. Decimation Rate, 50 kHz Center Frequency, 128× Decimation Rate 1 kHz, −0.5 dB Input Tone 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 CODE Figure 20. DNL Plot Rev. A | Page 13 of 32 INL (%) DNL (LSB) AMPLITUDE (dB) 06519-209 06519-208 06519-206 INL (%) SNR (dB) 06519-009 06519-207 AD7765 TERMINOLOGY Signal-to-Noise Ratio (SNR) In this case, the second-order terms are usually distanced in The ratio of the rms value of the actual input signal to the rms frequency from the original sine waves and the third-order sum of all other spectral components below the Nyquist fre- terms are usually at a frequency close to the input frequencies. quency, excluding harmonics and dc. The value for SNR is As a result, the second- and third-order terms are specified expressed in decibels (dB). separately. The calculation of the intermodulation distortion is as per the THD specification, that is, the ratio of the rms sum of Total Harmonic Distortion (THD) the individual distortion products to the rms amplitude of the The ratio of the rms sum of harmonics to the fundamental. sum of the fundamentals expressed in dB. For the AD7765, it is defined as Integral Nonlinearity (INL) 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 The maximum deviation from a straight line passing through THD(dB)= 20 log V the endpoints of the ADC transfer function. 1 Differential Nonlinearity (DNL) where: The difference between the measured and the ideal 1 LSB V1 is the rms amplitude of the fundamental. change between any two adjacent codes in the ADC. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Zero Error The difference between the ideal midscale input voltage (when Nonharmonic Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the both inputs are shorted together) and the actual voltage peak spurious spectral component, excluding harmonics. producing the midscale output code. Zero Error Drift Dynamic Range The change in the actual zero error value due to a temperature The ratio of the rms value of the full scale to the rms noise change of 1°C. It is expressed as a percentage of full scale at measured with the inputs shorted together. The value for room temperature. dynamic range is expressed in dB. Gain Error Intermodulation Distortion The first transition (from 100…000 to 100…001) should occur With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products for an analog voltage 1/2 LSB above the nominal negative full at sum and difference frequencies of mfa ± nfb, where m, n = 0, scale. The last transition (from 011…110 to 011…111) should occur for an analog voltage 1 1/2 LSB below the nominal full 1, 2, 3, and so on. Intermodulation distortion terms are those scale. The gain error is the deviation of the difference between for which neither m nor n is equal to 0. For example, the second- the actual level of the last transition and the actual level of the order terms include (fa + fb) and (fa − fb), while the third-order first transition, from the difference between the ideal levels. terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Gain Error Drift The AD7765 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. The change in the actual gain error value due to a temperature change of 1°C. It is expressed as a percentage of full scale at room temperature. Rev. A | Page 14 of 32 AD7765 THEORY OF OPERATION The AD7765 features an on-chip fully differential amplifier to The digital filtering that follows the modulator removes the feed the Σ-Δ modulator pins, an on-chip reference buffer, and a large out-of-band quantization noise (see Figure 25) while also FIR filter block to perform the required digital filtering of the reducing the data rate from f at the input of the filter to ICLK Σ-Δ modulator output. Using this Σ-Δ conversion technique f /128 or less at the output of the filter, depending on the ICLK with the added digital filtering, the analog input is converted decimation rate used. into an equivalent digital word. The AD7765 employs three FIR filters in series. By using Σ-Δ MODULATION AND DIGITAL FILTERING different combinations of decimation ratios, data can be obtained from the AD7765 at three data rates. The input waveform applied to the modulator is sampled, and an equivalent digital word is output to the digital filter at a rate The first filter receives data from the modulator at ICLK MHz equal to ICLK. By employing oversampling, the quantization where it is decimated 4× to output data at (ICLK/4) MHz. The noise is spread across a wide bandwidth from 0 to f . This ICLK second filter allows a choice of decimation rates: 16× or 32×. means that the noise energy contained in the signal band of The third filter has a fixed decimation rate of 2×. Table 6 shows interest is reduced (see Figure 23). To further reduce the some characteristics of the digital filtering where ICLK = quantization noise, a high order modulator is employed to MCLK/2. The group delay of the filter is defined to be the shape the noise spectrum so that most of the noise energy is delay to the center of the impulse response and is equal to the shifted out of the signal band (see Figure 24). computation plus the filter delays. The delay until valid data is available (the FILTER-SETTLE status bit is set) is approximately twice the filter delay plus the computation delay. This is listed in QUANTIZATION NOISE terms of MCLK periods in Table 6. f /2 ICLK 0 PASS-BAND RIPPLE = 0.1dB BAND OF INTEREST –0.1dB FREQUENCY = 125.1kHz –3dB FREQUENCY = 128kHz Figure 23. Σ-Δ ADC, Quantization Noise –20 STOP BAND = 156.25kHz –40 –60 NOISE SHAPING –80 f /2 ICLK BAND OF INTEREST –100 Figure 24. Σ-Δ ADC, Noise Shaping –120 –140 –160 DIGITAL FILTER CUTOFF FREQUENCY 0 50 100 150 200 250 300 FREQUENCY (kHz) f /2 ICLK BAND OF INTEREST Figure 26. Filter Frequency Response (156.25 kHz ODR) Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency Table 6. Configuration with Default Filter SYNC to ICLK Decimation Computation Pass-Band Output Data Rate Frequency Rate Data State Delay Filter Delay FILTER-SETTLE Bandwidth (ODR) 20 MHz 128× Fully filtered 3.1 µs 174 µs 14217 × tMCLK 62.5 kHz 156.25 kHz 20 MHz 256× Fully filtered 4.65 µs 346.8 µs 27895 × tMCLK 31.25 kHz 78.125 kHz 12.288 MHz 128× Fully filtered 5.05 µs 283.2 µs 14217 × t 38.4 kHz 96 kHz MCLK 12.288 MHz 256× Fully filtered 7.57 µs 564.5 µs 27895 × t 19.2 kHz 48 kHz MCLK Rev. A | Page 15 of 32 06519-014 06519-013 06519-012 AMPLITUDE (dB) 06519-015 AD7765 AD7765 ANTIALIAS PROTECTION The decimation of the AD7765, along with its counterparts in Figure 26 shows the frequency response of the decimation filter the AD776x family, namely the AD7760, AD7762, AD7763, and when the AD7765 is operated with a 40 MHz MCLK in AD7764, provides top of the range antialias protection. decimate 128× mode. Note that the first stop-band frequency occurs at Nyquist. The frequency response of the filter scales The decimation filter of the AD7765 features more than 115 dB with both the decimation rate chosen and the MCLK frequency of attenuation across the full stop band, which ranges from the applied. When using low power mode, the modulator sample Nyquist frequency, namely ODR/2, up to ICLK − ODR/2 rate is MCLK/4. (where ODR is the output data rate). Starting the stop band at the Nyquist frequency prevents any signal component above Taking as an example the AD7765 in normal power and in Nyquist (and up to ICLK − ODR/2) from aliasing into the decimate 128× mode, the first possible alias frequency is at the desired signal bandwidth. ICLK frequency minus the pass band of the digital filter (see Figure 27). NO ALIASING OF SIGNALS INTO PASSBAND AROUND NYQUIST FREQUENCY SIMPLFIES ANTIALIAS DIGITAL FILTER FILTER ROLL-OFF REQUIRED RESPONSE IMAGE DIGITAL FILTER RESPONSE NOISE SHAPING FREQUENCY (Hz) NYQUIST = 78kHz ODR = 156kHz FIRST ALIAS POINT MODULATOR 20MHz TO 78kHz SAMPLING RATE = MCLK/2 = 20MHz Figure 27. Antialias Example Using the AD7765 in Normal Mode, Decimate 128× Using MCLK/2 = ICLK = 20 MHz Rev. A | Page 16 of 32 AMPLITUDE (dB) 06519-300 AD7765 AD7765 INPUT STRUCTURE The AD7765 requires a 4.096 V input to the reference pin VREF+, This means that a maximum of ±3.2768 V p-p can be applied to supplied by a high precision reference, such as the ADR444. each of the AD7765 modulator inputs (Pin 5 and Pin 6), with Because the input to the device’s Σ-Δ modulator is fully differ- the AD7765 being specified with an input −0.5 dB down from ential, the effective differential reference range is 8.192 V. full scale (−0.5 dBFS). The AD7765 modulator inputs must have a common-mode input of 2.048 V. V = 2× 4.096= 8.192V REF+(Diff ) Figure 28 shows the relative scaling between the differential As is inherent in Σ-Δ modulators, only a certain portion of this voltages applied to the modulator pins and the respective 24-bit full reference may be used. In the case of the AD7765, 80% of twos complement digital outputs. the full differential reference can be applied to the modulator’s differential inputs. Modulator _ Input = 8.192V× 0.8= 6.5536V FULLSCALE TWOS COMPLEMENT INPUT VOLTAGE (V) DIGITAL OUTPUT OVERRANGE REGION +4.096V +3.2768V = MODULATOR FULL-SCALE = 80% OF 4.096V V + = 3.6855V IN 0111 1111 1111 1111 1111 1111 V – = 0.4105V IN 0111 1000 1101 0110 1111 1101 –0.5dBFS INPUT INPUT TO MODULATOR 0000 0000 0000 0000 0000 0001 DIGITAL OUTPUT PIN 5 AND PIN 6 V + = 2.048V ON SDO PIN IN V – AND V + 0000 0000 0000 0000 0000 0000 IN IN V – = 2.048V IN 1111 1111 1111 1111 1111 1111 –0.5dBFS INPUT 1000 0111 0010 1001 0000 0010 V + = 0.4105V IN 1000 0000 0000 0000 0000 0000 V – = 3.6855V IN 80% OF 4.096V = MODULATOR FULL-SCALE = –3.2768V –4.096V OVERRANGE REGION Figure 28. AD7765 Scaling; Modulator Input Voltage vs. Digital Output Code Rev. A | Page 17 of 32 06519-120 AD7765 The common-mode input at each of the differential amplifier ON-CHIP DIFFERENTIAL AMPLIFIER inputs (Pin V A+ and Pin V A−) can range from−0.5 V dc to IN IN The AD7765 contains an on-board differential amplifier that 2.2 V dc. The amplifier has a constant output common-mode is recommended to drive the modulator input pins. Pin 1, Pin 2, voltage of 2.048 V, that is, VREF/2, the requisite common-mode Pin 3, and Pin 4 on the AD7765 are the differential input and voltage for the modulator input pins (VIN+ and VIN−). output pins of the amplifier. The external components, R , R , IN FB C , C , and R , are placed around Pin 1 through Pin 6 to create Figure 30 shows the signal conditioning that occurs using the FB S M the recommended configuration. To achieve the specified differential amplifier configuration detailed in Table 7 with a ±2.5 V input signal to the differential amplifier. The amplifier performance, the differential amplifier should be configured as in this example is biased around ground and is scaled to give a first-order antialias filter, as shown in Figure 29, using the ±3.168 V p-p (−0.5 dBFS) on each modulator input with a component values listed in Table 7. The inputs to the differential 2.048 V common mode. amplifier are then routed through this external component network before being applied to the modulator inputs V − and IN +2.5V +3.632V V +(Pin 5 and Pin 6). Using the optimal values in the table as IN an example yields a 25 dB attenuation at the first alias point of V + IN 0V +2.048V 19.84 MHz. C FB A +0.464V –2.5V R FB V A– V A+ IN OUT R R IN M A 1 2 5 V – IN +2.5V +3.632V DIFF C S C M AMP B 3 4 6 B V + IN R R M V – IN IN R 0V FB +2.048V V A+ V A– IN OUT C FB +0.464V –2.5V Figure 29. Differential Amplifier Configuration Figure 30. Differential Amplifier Signal Conditioning Table 7. On-Chip Differential Filter Component Values To obtain maximum performance from the AD7765, it is advisable RIN RFB RM CS CFB CM to drive the ADC with differential signals. Figure 31 shows how a (kΩ) (kΩ) (Ω) (pF) (pF) (pF) bipolar, single-ended signal biased around ground can drive the Optimal 4.75 3.01 43 8.2 47 33 AD7765 with the use of an external op amp, such as the AD8021. Tolerance 2.37 2.4 to 36 to 0 to 20 to 39 to 1 C FB Range to 4.87 47 10 100 56 5.76 1 R 2R FB Values shown were the acceptable tolerances for each component when altered relative to the optimal values used to achieve the stated 2R V specifications of the device. IN R R IN M AD8021 V – IN The range of values that can be used for each of the listed DIFF C S C M AMP R M components in the differential amplifier configuration is also R V + IN listed in Table 7. When using the differential amplifier to gain R R IN FB the input voltages to the required modulator input range, it is advisable to implement the gain function by changing R , IN C FB leaving the R as the listed optimal value. FB Figure 31. Single-Ended-to-Differential Conversion Rev. A | Page 18 of 32 06519-024 06519-122 06519-026 AD7765 MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY The AD7765 employs a double-sampling front end, as shown in The AD7765 can be configured so that the on-board differential Figure 32. For simplicity, only the equivalent input circuitry for amplifier can be disabled and the modulator can be driven VIN+ is shown. The equivalent circuitry for VIN− is the same. directly using discrete amplifiers. This allows the user to lower the power dissipation. V + IN CS1 SS1 To power down the on board differential amplifier, the user SH3 CPA issues a write to set the AMP OFF bit in the control register to SS3 SH1 CPB1 logic high (see Figure 33). ANALOG MODULATOR SCO (O) 32 × t SCO CS2 SS2 FSI (I) SH4 SDI (I) SS4 SH2 CPB2 CONTROL REGISTER AMP OFF MODE ADDRESS 0x0001 DATA 0x0001 Figure 33. Writing to the AD7765 Control Register Turning Off the On-Board Figure 32. Equivalent Input Circuit Differential Amplifier The SS1 and SS3 sampling switches are driven by ICLK, The AD7765 modulator inputs must have a common-mode whereas the SS2 and SS4 sampling switches are driven by ICLK. voltage of 2.048 V and adhere to the amplitudes as described in When ICLK is high, the analog input voltage is connected to the AD7765 Input Structure section. CS1. On the falling edge of ICLK, the SS1 and SS3 switches An example of a typical circuit to drive the AD7765 for open and the analog input is sampled on CS1. Similarly, when applications requiring excellent ac and dc performance is shown ICLK is low, the analog input voltage is connected to CS2. On in Figure 34. Either the AD8606 or AD8656 can be used to the rising edge of ICLK, the SS2 and SS4 switches open, and the drive the AD7765 modulator inputs directly. analog input is sampled on CS2. Best practice is to short the differential amplifier inputs to The CPA, CPB1, and CPB2 capacitors represent parasitic capa- ground through the typical input resistors and leave the typical citances that include the junction capacitances associated with feedback resistors in place. the MOS switches. 2 C2 Table 8. Equivalent Component Values 10kΩ CS1 CS2 CPA CPB1/CPB2 10kΩ 51Ω 2 0Ω C1 U1 13 pF 13 pF 13 pF 5 pF 4.99kΩ ANALOG 1 INPUT AD8606 10kΩ 2.048V AD8655 10kΩ 5 V – U2 6 IN 4.99kΩ V + IN 51Ω 0Ω AD8606 1.024V AD7764/ AD8655 AD7765 V A– V A+ V A+ V A– IN OUT IN OUT 1 2 3 4 R R FB FB R R IN IN 1 –0.5dBFS INPUT SIGNAL AS DESCRIBED IN INPUT STRUCTURE SECTION. 2 SET C1 AND C2 AS REQUIRED FOR APPLICATION INPUT BW AND ANTI-ALIAS REQUIREMENT. Figure 34. Driving the AD7765 Modulator Inputs Directly from a Single- Ended Source (On-Board Differential Amplifier Powered Down) Rev. A | Page 19 of 32 06519-027 06519-302 06519-301 AD7765 AD7765 INTERFACE READING DATA READING STATUS AND OTHER REGISTERS The AD7765 uses an SPI-compatible serial interface. The The AD7765 features a gain correction register, an overrange timing diagram in Figure 2 shows how the AD7765 transmits register, and a read-only status register. To read back the its conversion results. contents of these registers, the user must first write to the control register of the device and set the bit that corresponds The data read from the AD7765 is clocked out using the serial to the register to be read. The next read operation outputs the clock output (SCO). The SCO frequency is half that of the contents of the selected register (on the SDO pin) instead of a MCLK input to the AD7765. conversion result. The conversion result output on the serial data output (SDO) To ensure that the next read cycle contains the contents of the line is framed by the frame synchronization output, FSO, which register written to, the write operation to that register must be is sent logic low for 32 SCO cycles. Each bit of the new FSO completed a minimum of 8 × tSCO before the falling edge of , conversion result is clocked onto the SDO line on the rising which indicates the start of the next read cycle. See Figure 4 for SCO edge and is valid on the falling SCO edge. The 32-bit result further details. consists of the 24 data bits followed by five status bits followed further by three zeros. The five status bits are listed in Table 9 The AD7765 Registers section provides more information on and described below the table. the relevant bits in the control register. Table 9. Status Bits During Data Read WRITING TO THE AD7765 D7 D6 D5 D4 D3 A write operation to the AD7765 is shown in Figure 3. The FILTER-SETTLE OVR LPWR DEC_RATE 1 Don’t care serial writing operation is synchronous to the SCO signal. The status of the frame synchronization input, FSI, is checked on the • The FILTER-SETTLE bit indicates whether the data output FSI from the AD7765 is valid. After resetting the device (using falling edge of the SCO signal. If the line is low, then the the RESET pin) or clearing the digital filter (using the first data bit on the serial data in (SDI) line is latched in on the next SCO falling edge. pin), the FILTER-SETTLE bit goes logic low to SYNC indicate that the full settling time of the filter has not yet FSI Set the active edge of the signal to occur at a position when passed and that the data is not yet valid. The FILTER- the SCO signal is high or low to allow setup and hold times SETTLE bit also goes to zero when the input to the part from the SCO falling edge to be met. The width of the FSI has asserted the overrange alerts. signal can be set to between 1 and 32 SCO periods wide. A • The OVR (overrange) bit is described in the Overrange second, or subsequent, falling edge that occurs before Alerts section. 32 SCO periods have elapsed is ignored. • The LPWR bit is set to logic high when the AD7765 is Figure 3 details the format for the serial data being written to operating in low power mode. See the Power Modes the AD7765 through the SDI pin. Thirty-two bits are required section for further details. for a write operation. The first 16 bits are used to select the • The DEC_RATE 1 and DEC_RATE 0 bits indicate the register address for which the data being read is intended. The decimation ratio used. Table 10 is a truth table for the second 16 bits contain the data for the selected register. decimation rate bits. Writing to the AD7765 is allowed at any time, even while Table 10. Truth Table reading a conversion result. Note that, after writing to the Decimate DEC_RATE 1 devices, valid data is not output until after the settling time for the filter has elapsed. The FILTER-SETTLE status bit is asserted 128× 1 at this point to indicate that the filter has settled and that valid 256× 0 data is available at the output. Rev. A | Page 20 of 32 AD7765 AD7765 FUNCTIONALITY Note that the FILTER-SETTLE bit is designed as a reactionary SYNCHRONIZATION flag to alert the user when the conversion data output is valid. SYNC The input to the AD7765 provides a synchronization OVERRANGE ALERTS function that allows the user to begin gathering samples of the analog front-end input from a known point in time. The AD7765 offers an overrange function in both a pin and status bit output. The overrange alerts indicate when the voltage The SYNC function allows multiple AD7765 devices, operated applied to the AD7765 modulator input pins exceeds the limit from the same master clock that use common SYNC and RESET set in the overrange register, indicating that the voltage applied signals, to be synchronized so that each ADC simultaneously is approaching an overrange level for the modulator. To set this updates its output register. Note that all devices being synchro- limit, the user must program the register. The default overrange nized must operate in the same power mode and at the same limit is set to 80% of the V + voltage (see the AD7765 REF decimation rate. Registers section). In the case of a system with multiple AD7765s, connect The OVERRANGE pin outputs logic high to alert the user that SYNC RESET common MCLK, , and signals to each AD7765. the modulator has sampled an input voltage greater in magni- The AD7765 SYNC pin is polled by the falling edge of MCLK. tude than the overrange limit as set in the overrange register. The AD7765 device goes into SYNC when an MCLK falling The OVERRANGE pin is set to logic high when the modulator samples an input above the overrange limit. After the input edge senses that the SYNC input signal is logic low. At this returns below the limit, the OVERRANGE pin returns to zero. point, the digital filter sequencer is reset to 0. The filter is held The OVERRANGE pin is updated after the first FIR filter stage. SYNC in a reset state (in mode) until the first MCLK falling Its output changes at the ICLK/4 frequency. SYNC edge senses to be logic high. The OVR status bit is output as Bit D6 on SDO during a data SYNC Where possible, ensure that all transitions of occur conversion and can be checked in the AD7765 status register. synchronously with the rising edge of MCLK (that is, as far This bit is less dynamic than the OVERRANGE pin output. It is away as possible from MCLK falling edge, or decision edge). updated on each conversion result output; that is, the bit Otherwise, abide by the timing specified in Figure 35, which changes at the output data rate. If the modulator has sampled a excludes the SYNC rising edge from occurring in a 10 ns voltage input that exceeded the overrange limit during the window centered around the MCLK falling edge. process of gathering samples for a particular conversion result SYNC Keep logic low for a minimum of four MCLK periods. output, then the OVR bit is set to logic high. SYNC When the MCLK falling edge senses that has returned to LOGIC LEVEL logic high, the AD7765 filters begin to gather input samples HIGH simultaneously. The FSO falling edges are also synchronized, LOW allowing for simultaneous output of conversion data. t MCLK OVERRANGE LIMIT OUTPUT FREQUENCY OF FIR FILTER 1 = ICLK/4 ABSOLUTE INPUT t TO AD7765 S SETUP [(V +) – (V –)] IN IN SYNC OUTPUT DATA RATE (ODR) (ICLK/DECIMATION RATE t S MIN OVERRANGE 4 × t t MCLK LIMIT S HOLD LOGIC LEVEL Figure 35. SYNC Timing Relative to MCLK HIGH Following a SYNC, the digital filter needs time to settle before LOW valid data can be read from the AD7765. The user knows there t is valid data on the SDO line by checking the FILTER-SETTLE Figure 36. OVERRANGE Pin and OVR Bit vs. Absolute Voltage status bit (see D7 in Table 9) that is output with each conversion Applied to Modulator SYNC result. The time from the rising edge of until the The output points from FIR Filter 1 in Figure 36 are not drawn FILTER-SETTLE bit asserts depends on the filter configuration to scale relative to the output data rate points. The FIR Filter 1 used. See the Theory of Operation section and the values listed output is updated either 16× or 32× faster than the output data in Table 6 for details on calculating the time until FILTER- rate, depending on the decimation rate in operation. SETTLE asserts. Rev. A | Page 21 of 32 06519-303 OVERRANGE PIN OVR BIT OUTPUT 06519-016 AD7765 RESET POWER MODES The best practice is to ensure that all transitions of occur synchronously with the falling edge of MCLK; otherwise, Low Power Mode adhere to the timing requirements shown in Figure 38. During power-up, the AD7765 defaults to operate in normal RESET should be kept logic low for a minimum of 1 MCLK power mode. There is no register write required. period for a valid reset to occur. The AD7765 also offers low power mode. To operate the device In cases where multiple AD7765 devices are being synchronized in low power mode, the user sets the LPWR bit in the control SYNC pulse and in the case of daisy chaining multiple register to logic high (see Figure 37). Operating the AD7765 in using the low power mode has no impact on the output data rate or RESET AD7765 devices, a common pulse must be provided in available bandwidth. SYNC addition to the common and MCLK signals. SCO (O) 32 × t SCO MCLK FSI (I) t R SETUP SDI (I) CONTROL REGISTER LOW POWER MODE ADDRESS 0x0001 DATA 0x0004 RESET Figure 37. Write Scheme for Low Power Mode t R MIN 1 × t MCLK t R HOLD RESET/PWRDWN Mode Figure 38. RESET Timing Synchronous to MCLK The AD7765 features a RESET/PWRDWN pin. Holding the input to this pin logic low places the AD7765 in power-down DECIMATION RATE PIN RESET mode. All internal circuitry is reset. Apply a pulse to the The decimation rate of the AD7765 is selected using the AD7765 after initial power-up of the device. DEC_RATE pin. Table 11 shows the voltage input settings The AD7765 RESET pin is polled by the rising edge of MCLK. required for each of the three decimation rates. The AD7765 device goes into reset when an MCLK rising Table 11. DEC_RATE Pin Settings senses the RESET input signal to be logic low. AD7765 comes Decimate DEC_RATE Pin Maximum Output Data Rate out of RESET on the first MCLK rising edge that senses RESET 128× DVDD 156.25 kHz to be logic high. 256× GND 78.125 kHz Rev. A | Page 22 of 32 06519-017 06519-304 AD7765 DAISY CHAINING Daisy chaining allows numerous devices to use the same digital output from the device labeled AD7765 (A). This 32-bit interface lines. This feature is especially useful for reducing conversion result is then followed by the conversion results component count and wiring connections, such as in isolated from the devices AD7765 (B), AD7765 (C), and AD7765 (D), multiconverter applications or for systems with a limited with all conversion results output in an MSB-first sequence. The interfacing capacity. Data readback is analogous to clocking a signals output from the daisy chain are the stream of conversion shift register. When daisy chaining is used, all devices in the FSO results from the SDO pin of AD7765 (A) and the signal chain must operate in a common power mode and at a common output by the first device in the chain, AD7765 (A). decimation rate. FSO The falling edge of signals the MSB of the first conversion The block diagram in Figure 39 shows how to connect devices output in the chain. FSO stays logic low throughout the 32 SCO to achieve daisy-chain functionality. Figure 39 shows four clock periods needed to output the AD7765 (A) result and then AD7765 devices daisy-chained together with a common MCLK goes logic high during the output of the conversion results from signal applied. the AD7765 (B), AD7765 (C), and AD7765 (D) devices. READING DATA IN DAISY-CHAIN MODE The maximum number of devices that can be daisy-chained is dependent on the decimation rate selected. Calculate the Referring to Figure 39, note that the SDO line of AD7765 (A) maximum number of devices that can be daisy-chained by provides the output data from the chain of AD7765 converters. simply dividing the chosen decimation rate by 32 (the number Also, note that for the last device in the chain, AD7765 (D), the of bits that must be clocked out for each conversion). Table 12 SDI pin is connected to ground. All of the devices in the chain provides the maximum number of chained devices for each SYNC must use common MCLK and signals. decimation rate. To enable the daisy-chain conversion process, apply a common SYNC pulse to all devices (see the Synchronization section). Table 12. Maximum Chain Length for All Decimation Rates Decimation Rate Maximum Chain Length After a SYNC pulse is applied to all devices, the filter settling 256× 8 time must pass before the FILTER-SETTLE bit is asserted 128× 4 indicating valid conversion data at the output of the chain of devices. As shown in Figure 40, the first conversion result is FSI AD7765 AD7765 AD7765 AD7765 (D) (C) (B) (A) FSI FSI FSI FSI FSO SDI SDO SDI SDO SDI SDO SDI SDO SYNC SYNC SYNC SYNC MCLK MCLK MCLK MCLK SYNC MCLK Figure 39. Daisy Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal 32 × t 32 × t 32 × t 32 × t SCO SCO SCO SCO SCO AD7765 (A) AD7765 (B) AD7765 (C) AD7765 (D) AD7765 (A) AD7765 (B) SDO (A) 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT FSO (A) AD7765 (B) AD7765 (C) AD7765 (D) AD7765 (B) AD7765 (C) SDI (A) = SDO (B) SDI (B) = SDO (C) AD7765 (C) AD7765 (D) AD7765 (C) AD7765 (D) SDI (C) = SDO (D) AD7765 (D) AD7765 (D) Figure 40. Daisy-Chain Mode, Data Read Timing Diagram (for the Daisy-Chain Configuration Shown in Figure 39) Rev. A | Page 23 of 32 06519-018 06519-019 AD7765 FSI WRITING DATA IN DAISY-CHAIN MODE and the rising edge of must be between 32 × (n − 1) to 32 × n SCO periods. For example, if three AD7765 devices are being Writing to AD7765 devices in daisy-chain mode is similar to FSI written to in daisy-chain mode, is logic low for between writing to a single device. The serial writing operation is 32 × (3 − 1) to 32 × 3 SCO pulses. This means that the rising synchronous to the SCO signal. The status of the frame synchro- th th edge of FSI must occur between the 64 and 96 SCO period. FSI nization input, , is checked on the falling edge of the SCO FSI signal. If the line is low, then the first data bit on the serial The AD7765 devices can be written to at any time. The falling data in the SDI line is latched in on the next SCO falling edge. edge of FSI overrides all attempts to read data from the SDO FSI pin. In the case of a daisy chain, the signal remaining logic Writing data to the AD7765 in daisy-chain mode operates with low for more than 32 SCO periods indicates to the AD7765 the same timing structure as writing to a single device (see device that there are more devices further on in the chain. This Figure 3). The difference between writing to a single device means that the AD7765 directs data that is input on the SDI pin and writing to a number of daisy-chained devices is in the to its SDO pin. This ensures that data is passed to the next FSI implementation of the signal. The number of devices that device in the chain. FSI are in the daisy chain determines the period for which the signal must remain logic low. To write to n number of devices FSI in the daisy chain, the period between the falling edge of FSI AD7765 AD7765 AD7765 AD7765 (D) (C) (B) (A) FSI FSI FSI FSI FSO SDI SDO SDI SDO SDI SDO SDI SDO SDI SYNC SYNC SYNC SYNC MCLK MCLK MCLK MCLK SYNC MCLK Figure 41. Writing to an AD7765 Daisy-Chain Configuration t 10 FSI 32 × t 32 × t 32 × t 31 × t SCO SCO SCO SCO SCO SDI (D) SDI (D) SDI (C) = SDO (D) SDI (C) SDI (B) = SDO (C) SDI (B) SDI (A) = SDO (B) SDI (A) Figure 42. Daisy-Chain Write Timing Diagram; Writing to Four AD7765 Devices Rev. A | Page 24 of 32 06519-020 06519-021 AD7765 CLOCKING THE AD7765 The AD7765 requires an external low jitter clock source. This 256 t = = 470 ps j(rms) 3 5.45 signal is applied to the MCLK pin. An internal clock signal 2×π×19.2×10 ×10 (ICLK) is derived from the MCLK input signal. The ICLK The input amplitude also has an effect on these jitter figures. controls the internal operation of the AD7765. The maximum For example, if the input level is 3 dB below full scale, the ICLK frequency is 20 MHz. To generate the ICLK, allowable jitter is increased by a factor of √2, increasing the first ICLK = MCLK/2 example to 144.65 ps rms. This happens when the maximum slew rate is decreased by a reduction in amplitude. For output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 6, Figure 43 and Figure 44 illustrate this point, showing the maxi- output data rates of 96 kHz and 48 kHz are achievable with this mum slew rate of a sine wave of the same frequency but with ICLK frequency. different amplitudes. 1.0 MCLK JITTER REQUIREMENTS The MCLK jitter requirements depend on a number of factors and are given by 0.5 OSR t = j(rms) SNR (dB) 2×π× f ×10 IN 0 20 where: OSR = oversampling ratio = f /ODR. ICLK –0.5 f = maximum input frequency. IN SNR (dB) = target SNR. –1.0 Example 1 Figure 43. Maximum Slew Rate of a Sine Wave This example can be taken from Table 6, where: with an Amplitude of 2 V p-p ODR = 156.25 kHz. 1.0 f = 20 MHz. ICLK f (max) = 78.625 kHz. IN SNR = 104 dB. 0.5 128 t = = 102.29ps j(rms) 3 5.35 2×π× 78.625×10 ×10 0 This is the maximum allowable clock jitter for a full-scale, 78.625 kHz input tone with the given ICLK and output data rate. –0.5 Example 2 This second example can also be taken from Table 6, where: –1.0 ODR = 48 kHz. fICLK = 12.288 MHz. Figure 44. Maximum Slew Rate of the Same Frequency Sine Wave as in Figure 43 with an Amplitude of 1 V p-p fIN (max) = 19.2 kHz. SNR = 109 dB. Rev. A | Page 25 of 32 06519-023 06519-022 AD7765 DECOUPLING AND LAYOUT INFORMATION ADR444 SUPPLY DECOUPLING 200Ω 2 6 V + REF 7.5V V V IN OUT PIN 27 The decoupling of the supplies applied to the AD7765 is + + GND 10µF 100nF important in achieving maximum performance. Each supply 4 100µF 100nF pin must be decoupled to the correct ground pin with a 100 nF, 0603 case size capacitor. Figure 46. Reference Connection Pay particular attention to decoupling Pin 7 (AVDD2) directly to DIFFERENTIAL AMPLIFIER COMPONENTS the nearest ground pin (Pin 8). The digital ground pin, AGND2 (Pin 20) is routed directly to ground. Also, connect REFGND The correct components for use around the on-chip differential (Pin 26) directly to ground. amplifier are detailed in Table 7. Matching the components on both sides of the differential amplifier is important to minimize The DV (Pin 17) and AV 3 (Pin 28) supplies should be DD DD distortion of the signal applied to the amplifier. A tolerance of decoupled to the ground plane at a point away from the device. 0.1% or better is required for these components. Symmetrical It is advised to decouple the supplies that are connected to the routing of the tracks on both sides of the differential amplifier following supply pins through 0603 size, 100 nF capacitors to a also assists in achieving stated performance. Figure 47 shows a star ground point linked to Pin 23 (AGND1). typical layout for the components around the differential • VREF+ (Pin 27) amplifier. Note that the traces for both differential paths are made as symmetrical as possible and that the feedback resistors • AVDD4 (Pin 25) and capacitors are placed on the underside of the PCB to enable • AVDD1 (Pin 24) the simplest routing. • AVDD2 (Pin 21) R IN R FB A layout decoupling scheme for these supplies, which connect C FB to the right side of the AD7765, is shown in Figure 45. Note the V A– IN star-point ground created at Pin 23. V A+ IN AV 4 DD (PIN 25) GND R IN AV 3 (PIN 28) DD PIN 23 Figure 47. Typical Layout Structure for Surrounding Components V + (PIN 27) REF STAR-POINT GND LAYOUT CONSIDERATIONS AV 1 (PIN 24) DD AV 2 (PIN 21) DD While using the correct components is essential to achieving GND optimum performance, the correct layout is just as important. VIA TO GND PIN 15 FROM PIN 20 The AD7765 product page on www.analog.com contains the Figure 45. AD7765 Supply Decoupling Gerber files for the AD7765 evaluation board. These files should be downloaded and used as a reference when designing REFERENCE VOLTAGE FILTERING any system using the AD7765. A low noise reference source, such as the ADR444 or ADR434 The use of ground planes should also be carefully considered. (4.096 V), is suitable for use with the AD7765. The reference To ensure that the return currents through the decoupling voltage supplied to the AD7765 should be decoupled and capacitors are flowing to the correct ground pin, the ground filtered, as shown in Figure 46. side of the capacitors should be as close to the ground pin The recommended scheme for the reference voltage supply associated with that supply as recommended in the Supply is a 200 Ω series resistor connected to a 100 μF tantalum Decoupling section. capacitor, followed by a 10 nF decoupling capacitor very close to the VREF+ pin. Rev. A | Page 26 of 32 06519-133 06519-135 06519-134 AD7765 Data can then be read from the device using the default gain USING THE AD7765 and overrange threshold values. The conversion data read is not The following is the recommended sequence for powering up valid, however, until the settling time of the filter has elapsed. and using the AD7765: Once this has occurred, the FILTER-SETTLE status bit is set, 1. Apply power to the device. indicating that the data is valid. 2. Apply the MCLK signal. Values for gain and overrange thresholds can be written to or RESET 3. Take low for a minimum of one MCLK cycle, read from the respective registers at this stage. preferably synchronous to the falling MCLK edge. If BIAS RESISTOR SELECTION multiple parts are to be synchronized, apply a common RESET to all devices. The AD7765 requires a resistor to be connected between the 4. Wait a minimum of two MCLK cycles after RESET has RBIAS and AGNDx pins. The resistor value should be selected to been released. give a current of 25 µA through the resistor to ground. For a SYNC 5. If multiple parts are being synchronized, a pulse 4.096 V reference voltage, the correct resistor value is 160 kΩ. must be applied to the parts, preferably synchronous with the MCLK rising edge. In the case where devices are not SYNC being synchronized, no pulse is required; a logic high signal should simply be applied to the SYNC pin. When applying the SYNC pulse, SYNC • The issue of a pulse to the device must not coincide with a write to the device. • Ensure that the SYNC pulse is taken low for a minimum of four MCLK periods. Rev. A | Page 27 of 32 AD7765 AD7765 REGISTERS The AD7765 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and differential amplifier and provides an option to power down the AD7765. There are also digital gain and overrange threshold registers. Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual bits, and default values are provided in this section. CONTROL REGISTER Table 13. Control Register (Address 0x0001, Default Value 0x0000) MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 RD RD 0 RD 0 SYNC 0 BYPASS 0 0 0 PWR LPWR REF BUF AMP OVR GAIN STAT REF DOWN OFF OFF Table 14. Bit Descriptions of the Control Register Bit Mnemonic Comment 1, 2 14 RD OVR Read overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register instead of a conversion result. 13 RD GAIN Read gain. If this bit is set, the next read operation outputs the contents of the digital gain register. 11 RD STAT Read status. If this bit is set, the next read operation outputs the contents of the status register. 9 SYNC Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple devices synchronizes all filters. 7 BYPASS REF Bypass reference. Setting this bit bypasses the reference buffer if the buffer is off. 3 PWR DOWN Power-down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up. 2 LPWR Low power mode. Set to Logic 1 when AD7765 is in low power mode. 1 REF BUF OFF Reference buffer off. Asserting this bit powers down the reference buffer. 0 AMP OFF Amplifier off. Asserting this bit switches the differential amplifier off. 1 Bit 14 to Bit 11 and Bit 9 are self-clearing bits. 2 Only one of the bits can be set in any write operation because it determines the contents of the next read operation. STATUS REGISTER Table 15. Status Register (Read Only) MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PARTNO 1 0 0 0 FILTER- 0 OVR 0 1 0 REF BUF AMP LPWR DEC 1 DEC 0 SETTLE ON ON Table 16. Bit Descriptions of the Status Register Bit Mnemonic Comment 15 PARTNO Part number. This bit is set to 1 for the AD7765. 10 FILTER- Filter settling bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read SETTLE operation. It indicates when data is valid. 9 0 Zero. This bit is set to Logic 0. 8 OVR Overrange. If the current analog input exceeds the current overrange threshold, this bit is set. 4 REF BUF ON Reference buffer on. This bit is set when the reference buffer is in use. 3 AMP ON Amplifier on. This bit is set when the input amplifier is in use. 2 LPWR Low power mode. This bit is set when operating in low power mode. 1 to 0 DEC[1:0] Decimation rate. These bits correspond to the decimation rate in use. Rev. A | Page 28 of 32 AD7765 GAIN REGISTER—ADDRESS 0x0004 OVERRANGE REGISTER—ADDRESS 0x0005 Non-Bit-Mapped, Default Value 0xA000 Non-Bit-Mapped, Default Value 0xCCCC The gain register is scaled such that 0x8000 corresponds to a The overrange register value is compared with the output of the gain of 1.0. The default value of this register is 1.25 (0xA000). first decimation filter to obtain an overload indication with This results in a full-scale digital output when the input is at minimum propagation delay. This is prior to any gain scaling or 80% of VREF+, tying in with the maximum analog input range offset adjustment. The default value is 0xCCCC, which corre- of ±80% of VREF+ p-p. sponds to 80% of VREF+ (the maximum permitted analog input voltage). Assuming VREF+ = 4.096 V, the bit is then set when the input voltage exceeds approximately 6.55 V p-p differential. The overrange bit is set immediately if the analog input voltage exceeds 100% of V + for more than four consecutive samples REF at the modulator rate. Rev. A | Page 29 of 32 AD7765 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 0.19 SEATING COPLANARITY 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 48. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7765BRUZ −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 1 AD7765BRUZ-REEL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 1 EVAL-AD7765EDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 30 of 32 AD7765 NOTES Rev. A | Page 31 of 32 AD7765 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06519-0-8/09(A) Rev. A | Page 32 of 32