ANALOG DEVICES AD7764

24-Bit, 312 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface AD7764 FEATURES FUNCTIONAL BLOCK DIAGRAM V A– V A+ V + V – MCLK GND OUT OUT IN IN High performance 24-bit ∑-∆ ADC 115 dB dynamic range at 78 kHz output data rate AV 1 DD V A+ IN AV 2 DIFF DD 109 dB dynamic range at 312 kHz output data rate MULTIBIT V A– IN Σ-Δ AV 3 DD 312 kHz maximum fully filtered output word rate MODULATOR AV 4 DD DV DD Pin-selectable oversampling rate (64×, 128×, and 256×) V + REF BUF Low power mode RECONSTRUCTION OVERRANGE Flexible SPI REFGND DECIMATION DEC_RATE Fully differential modulator input SYNC INTERFACE LOGIC AND OFFSET AND GAIN On-chip differential amplifier for signal buffering FIR FILTER ENGINE R CORRECTION REGISTERS BIAS RESET/PWRDWN On-chip reference buffer AD7764 Full band low-pass finite impulse response (FIR) filter FSO SCO SDI SDO FSI Overrange alert pin Figure 1. Digital gain correction registers Table 1. Related Devices Power-down mode Synchronization of multiple devices via SYNC pin Part No. Description Daisy chaining AD7760 2.5 MSPS, 100 dB, parallel output on-chip buffers AD7762 625 kSPS, 109 dB, parallel output on-chip buffers APPLICATIONS AD7763 625 kSPS, 109 dB, serial output, on-chip buffers Data acquisition systems AD7765 156 kSPS, 112 dB, serial output, on-chip buffers Vibration analysis AD7766 128/64/32 kSPS, 8.5 mW, 109 dB SNR Instrumentation AD7767 128/64/32 kSPS, 8.5 mW, 109 dB SNR GENERAL DESCRIPTION The AD7764 is a high performance, 24-bit sigma-delta (Σ-Δ) The differential input is sampled at up to 40 MSPS by an analog analog-to-digital converter (ADC). It combines wide input modulator. The modulator output is processed by a series of bandwidth, high speed, and performance of 109 dB dynamic low-pass filters. The external clock frequency applied to the range at a 312 kHz output data rate. With excellent dc AD7764 determines the sample rate, filter corner frequencies, and output word rate. specifications, the converter is ideal for high speed data acquisition of ac signals where dc data is also required. The AD7764 device boasts a full band on-board FIR filter. The Using the AD7764 eases the front-end antialias filtering full stop-band attenuation of the filter is achieved at the Nyquist requirements, simplifying the design process significantly. The frequency. This feature offers increased protection from signals AD7764 offers pin-selectable decimation rates of 64×, 128×, that lie above the Nyquist frequency being aliased back into the and 256×. Other features include an integrated buffer to drive input signal bandwidth. the reference, as well as a fully differential amplifier to buffer The reference voltage supplied to the AD7764 determines the and level shift the input to the modulator. input range. With a 4 V reference, the analog input range is An overrange alert pin indicates when an input signal has ±3.2768 V differential, biased around a common mode of exceeded the acceptable range. The addition of internal gain 2.048 V. This common-mode biasing can be achieved using and internal overrange registers makes the AD7764 a compact, the on-chip differential amplifier, further reducing the external highly integrated data acquisition device requiring minimal signal conditioning requirements. peripheral components. The AD7764 is available in a 28-lead TSSOP package and is The AD7764 also offers a low power mode, significantly specified over the industrial temperature range of −40°C reducing power dissipation without reducing the output data to +85°C. rate or available input bandwidth. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06518-001 AD7764 TABLE OF CONTENTS Synchronization ...........................................................................22 Features .............................................................................................. 1 Overrange Alerts .........................................................................22 Applications ....................................................................................... 1 Power Modes ................................................................................23 General Description ......................................................................... 1 Decimation Rate Pin ...................................................................23 Functional Block Diagram .............................................................. 1 Daisy Chaining ................................................................................24 Revision History ............................................................................... 2 Reading Data in Daisy-Chain Mode.........................................24 Specifications ..................................................................................... 3 Writing Data in Daisy-Chain Mode .........................................25 Timing Specifications .................................................................. 6 Clocking the AD7764 .....................................................................26 Timing Diagrams.......................................................................... 7 MCLK Jitter Requirements ........................................................26 Absolute Maximum Ratings ............................................................ 8 Decoupling and Layout Information ............................................27 ESD Caution .................................................................................. 8 Supply Decoupling ......................................................................27 Pin Configuration and Function Descriptions ............................. 9 Reference Voltage Filtering ........................................................27 Typical Performance Characteristics ........................................... 11 Differential Amplifier Components .........................................27 Terminology .................................................................................... 15 Layout Considerations ................................................................27 Theory of Operation ...................................................................... 16 Using the AD7764 .......................................................................28 Σ-Δ Modulation and Digital Filtering ..................................... 16 Bias Resistor Selection ................................................................28 AD7764 Antialias Protection .................................................... 17 AD7764 Registers ............................................................................29 AD7764 Input Structure ................................................................ 18 Control Register...........................................................................29 On-Chip Differential Amplifier ............................................... 19 Status Register ..............................................................................29 Modulator Input Structure ........................................................ 20 Gain Register—Address 0x0004 ................................................30 Driving the Modulator Inputs Directly ................................... 20 Overrange Register—Address 0x0005 ......................................30 AD7764 Interface............................................................................ 21 Outline Dimensions ........................................................................31 Reading Data ............................................................................... 21 Ordering Guide............................................................................31 Reading Status and Other Registers ......................................... 21 Writing to the AD7764 .............................................................. 21 AD7764 Functionality .................................................................... 22 REVISION HISTORY 11/09—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 4 Added Driving the Modulator Inputs Directly Section, Including Changes to Table 3 ............................................................................ 6 Figure 39 and Figure 40, Renumbered Subsequent Figures ......20 Changes to Table 4 ............................................................................ 8 Changes to Synchronization Section, Added Figure 41 .............22 Changes to Typical Performance Characteristics Section, Changes to Power Modes Section, Added Figure 44 ..................23 Introductory Text............................................................................ 11 Changes to Example 2 Section .......................................................26 Changes to Σ-Δ Modulation and Digital Filtering Section ....... 16 Changes to Using the AD7764 Section.........................................28 Added AD7764 Antialias Protection Section ............................. 17 6/07—Revision 0: Initial Version Changes to Figure 35 ...................................................................... 19 Rev. A | Page 2 of 32 AD7764 SPECIFICATIONS AV 1 = DV = 2.5 V, AV 2 = AV 3 = AV 4 = 5 V, V + = 4.096 V, MCLK amplitude = 5 V, T = 25°C, normal power mode, using DD DD DD DD DD REF A 1 the on-chip amplifier with components, as shown in the Optimal row in Table 7, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Specification Unit DYNAMIC PERFORMANCE Decimate 256× Normal Power Mode MCLK = 40 MHz, ODR = 78.125 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 115 dB typ 110 dB min Differential amplifier inputs shorted 113.4 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 109 dB typ 106 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 130 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −103 dB typ Input amplitude = −60 dB −71 dB typ Low Power Mode MCLK = 40 MHz, ODR = 78.125 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 113 dB typ 110 dB min Differential amplifier inputs shorted 112 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 109 dB typ 106 dB min Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −111 dB typ Input amplitude = −6 dB −100 dB max Input amplitude = −60 dB −76 dB typ Decimate 128× Normal Power Mode MCLK = 40 MHz, ODR = 156.25 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 112 dB typ 108 dB min Differential amplifier inputs shorted 110.4 dB typ 2 Signal-to-Noise Ratio (SNR) 107 dB typ 105 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 130 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −103 dB typ Intermodulation Distortion (IMD) Input amplitude = −6 dB, f A = 50.3 kHz, f B = 47.3 kHz IN IN Second-order terms −117 dB typ Third-order terms −108 dB typ Low Power Mode MCLK = 40 MHz, ODR = 156.25 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 110 dB typ 109 dB min Differential amplifier inputs shorted 109 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 107 dB typ 105 dB min Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −111 dB typ Input amplitude = −6 dB −100 dB max Intermodulation Distortion (IMD) Input amplitude = −6 dB, f A = 50.3 kHz, f B = 47.3 kHz IN IN Second-order terms −134 dB typ Third-order terms −110 dB typ Rev. A | Page 3 of 32 AD7764 Parameter Test Conditions/Comments Specification Unit Decimate 64× Normal Power Mode MCLK = 40 MHz, ODR = 312.5 kHz, f = 1 kHz sine wave IN Dynamic Range Modulator inputs shorted 109 dB typ 105 dB min Differential amplifier inputs shorted 107.3 dB typ 2 Signal-to-Noise Ratio (SNR) 104 dB typ 102.7 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 130 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −103 dB typ Intermodulation Distortion (IMD) Input amplitude = −6 dB, f A = 100.3 kHz, f B = 97.3 kHz IN IN Second-order terms −118 dB Third-order terms −108 dB Low Power Mode Dynamic Range Modulator inputs shorted 106 dB typ 105 dB min Differential amplifier inputs shorted 105.3 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dB 103 dB typ 102 dB min Spurious-Free Dynamic Range (SFDR) Nonharmonic 110 dBFS typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dB −105 dB typ Input amplitude = −6 dB −111 dB typ −100 dB max DC ACCURACY Resolution Guaranteed monotonic to 24 bits 24 Bits Integral Nonlinearity Normal power mode 0.0036 % typ Low power mode 0.0014 % typ Zero Error Normal power mode 0.006 % typ 0.03 % max Including on-chip amplifier 0.04 % typ Low power mode 0.002 % typ 0.024 % max Gain Error 0.018 % typ Including on-chip amplifier 0.04 % typ Zero Error Drift 0.00006 %FS/°C typ Gain Error Drift 0.00005 %FS/°C typ DIGITAL FILTER CHARACTERISTICS Pass-Band Ripple 0.1 dB typ 3 Pass Band −1 dB frequency ODR × 0.4016 kHz 3 −3 dB Bandwidth ODR × 0.4096 kHz 3 Stop Band Beginning of stop band ODR × 0.5 kHz Stop-Band Attenuation Decimate 64× and decimate 128× modes −120 dB typ Decimate 256× −115 dB typ Group Delay Decimate 64× MCLK = 40 MHz 89 µs typ Decimate 128× MCLK = 40 MHz 177 µs typ Decimate 256× MCLK = 40 MHz 358 µs typ ANALOG INPUT Differential Input Voltage Modulator input pins: V + − V −, V + = 4.096 V ±3.2768 V p-p IN IN REF Input Capacitance At on-chip differential amplifier inputs 5 pF typ At modulator inputs 29 pF typ Rev. A | Page 4 of 32 AD7764 Parameter Test Conditions/Comments Specification Unit REFERENCE INPUT/OUTPUT V Input Voltage AV 3 = 5 V ± 5% 4.096 V REF+ DD V Input DC Leakage Current ±1 µA max REF+ V Input Capacitance 5 pF typ REF+ DIGITAL INPUT/OUTPUT MCLK Input Amplitude 2.25 to 5.25 V Input Capacitance 7.3 pF typ Input Leakage Current ±1 μA/pin max V 0.8 × DV V min INH DD V 0.2 × DV V max INL DD 4 V 2.2 V min OH V 0.1 V max OL ON-CHIP DIFFERENTIAL AMPLIFIER Input Impedance >1 MΩ Bandwidth for 0.1 dB Flatness 125 kHz Common-Mode Input Voltage Voltage range at input pins: V A+ and V A− −0.5 to +2.2 V IN IN Common-Mode Output Voltage On-chip differential amplifier pins: V A+ and V A− 2.048 V OUT OUT POWER REQUIREMENTS AV 1 (Modulator Supply) ±5% 2.5 V DD AV 2 (General Supply) ±5% 5 V DD AV 3 (Differential Amplifier Supply) ±5% 5 V min/max DD AV 4 (Ref Buffer Supply) ±5% 5 V min/max DD DV ±5% 2.5 V DD Normal Power Mode AI 1 (Modulator) 19 mA typ DD 5 AI 2 (General) MCLK = 40 MHz 13 mA typ DD AI 3 (Differential Amplifier) AV 3 = 5 V 10 mA typ DD DD AI 4 (Reference Buffer) AV 4 = 5 V 9 mA typ DD DD 5 DI MCLK = 40 MHz 37 mA typ DD Low Power Mode AI 1 (Modulator) 10 mA typ DD 5 AI 2 (General) MCLK = 40 MHz 7 mA typ DD AI 3 (Differential Amplifier) AV 3 = 5 V 5.5 mA typ DD DD AI 4 (Reference Buffer) AV 4 = 5 V 5 mA typ DD DD 5 DI MCLK = 40 MHz 20 mA typ DD POWER DISSIPATION Normal Power Mode MCLK = 40 MHz, decimate 64× 300 mW typ 371 mW max Low Power Mode MCLK = 40 MHz, decimate 64× 160 mW typ 215 mW max 6 Power-Down Mode PWRDWN held logic low 1 mW typ 1 See the Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7764 = [(40 MHz)/2)/64] = 312.5 kHz. 4 Tested with a 400 µA load current. 5 Tested at MCLK = 40 MHz. This current scales linearly with the MCLK frequency applied. 6 Tested at 125°C. Rev. A | Page 5 of 32 AD7764 TIMING SPECIFICATIONS AV 1 = DV = 2.5 V, AV 2 = AV 3 = AV 4 = 5 V, V + = 4.096 V, T = 25°C, C = 25 pF. DD DD DD DD DD REF A LOAD Table 3. Parameter Limit at T , T Unit Description MIN MAX f 500 kHz min Applied master clock frequency MCLK 40 MHz max f 250 kHz min Internal modulator clock derived from MCLK ICLK 20 MHz max t 1 × t typ SCO high period 1 ICLK t 1 × t typ SCO low period 2 ICLK t 1 ns typ SCO rising edge to falling edge FSO 3 t 2 ns typ Data access time, FSO falling edge to data active 4 t 8 ns max MSB data access time, SDO active to SDO valid 5 t 40 ns min Data hold time (SDO valid to SCO rising edge) 6 t 9.5 ns max Data access time (SCO rising edge to SDO valid) 7 t 2 ns typ SCO rising edge to rising edge FSO 8 t 32 × t max low period FSO 9 SCO t 12 ns min Setup time from FSI falling edge to SCO falling edge 10 t 1 × t min FSI low period 11 SCO 1 t 32 × t max FSI low period 12 SCO t 12 ns min SDI setup time for the first data bit 13 t 12 ns min SDI setup time 14 t 0 ns max SDI hold time 15 t 1 × t min Minimum time for a valid RESET pulse R MIN MCLK t 5 ns min Minimum time between the MCLK rising edge and RESET rising edge R HOLD t 5 ns min Minimum time between the rising edge and MCLK rising edge RESET R SETUP t 4 × t min Minimum time for a valid pulse SYNC S MIN MCLK t 5 ns min Minimum time between the MCLK falling edge and rising edge SYNC S HOLD t 5 ns min Minimum time between the rising edge and MCLK falling edge SYNC S SETUP 1 This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained). Rev. A | Page 6 of 32 AD7764 TIMING DIAGRAMS 32 × t SCO t 1 SCO (O) t 8 t 2 t 9 t 3 FSO (O) t 4 t 6 t 5 t 7 SDO (O) D23 D22 D21 D20 D19 D1 D0 ST4 ST3 ST2 ST1 ST0 0 0 0 Figure 2. Serial Read Timing Diagram t 1 SCO (O) t 2 t 12 t 10 t FSI (I) 11 t 14 t 13 t 15 SDI (I) RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA1 RA0 D15 D14 D1 D0 Figure 3. AD7764 Register Write SCO (O) ≥8 × t SCO FSO (O) STATUS REGISTER DON’T CARE SDO (O) CONTENTS [31:16] BITS [15:0] NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER FSI (I) CONTROL REGISTER CONTROL REGISTER SDI (I) ADDR (0x0001) INSTRUCTION Figure 4. AD7764 Status Register Read Cycle Rev. A | Page 7 of 32 06518-004 06518-003 06518-002 AD7764 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings T = 25°C, unless otherwise noted. A may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any other conditions above those listed in the operational sections Parameter Rating of this specification is not implied. Exposure to absolute AV 1 to GND −0.3 V to +2.8 V DD maximum rating conditions for extended periods may affect AV 2, AV 3, AV 4 to GND −0.3 V to +6 V DD DD DD device reliability. DV to GND −0.3 V to +2.8 V DD 1 V A+, V A− to GND −0.3 V to +6 V IN IN 1 V +, V − to GND −0.3 V to +6 V IN IN 2 ESD CAUTION Digital Input Voltage to GND −0.3 V to +2.8 V 3 V + to GND −0.3 V to +6 V REF 4 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV 1 Absolute maximum voltage for V −, V +, V A−, and V A+ is 6.0 V or IN IN IN IN AV 3 + 0.3 V, whichever is lower. DD 2 Absolute maximum voltage on digital input is 3.0 V or DV + 0.3 V, DD whichever is lower. 3 Absolute maximum voltage on V + input is 6.0 V or AV 4 + 0.3 V, REF DD whichever is lower. 4 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 8 of 32 AD7764 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V A– 1 28 AV 3 IN DD V A+ 2 27 V + OUT REF V A+ 3 26 REFGND IN V A– 4 25 AV 4 OUT DD 5 24 V – AV 1 IN DD 6 AD7764 23 V + AGND1 IN TOP VIEW 7 22 AV 2 R DD BIAS (Not to Scale) 8 21 AGND3 AV 2 DD 20 OVERRANGE 9 AGND2 SCO 10 19 MCLK FSO 11 18 DEC_RATE SDO 12 17 DV DD SDI 13 16 RESET/PWRDWN FSI 14 15 SYNC Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 24 AV 1 2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor. DD 7 and 21 AV 2 5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be DD decoupled to AGND1 (Pin 23) with a 100 nF capacitor. 28 AV 3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with DD a 100 nF capacitor. 25 AV 4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF DD capacitor. 17 DV 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with DD a 100 nF capacitor. 22 R Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the BIAS Bias Resistor Selection section. 23 AGND1 Power Supply Ground for Analog Circuitry. 20 AGND2 Power Supply Ground for Analog Circuitry. 8 AGND3 Power Supply Ground for Analog Circuitry. 26 REFGND Reference Ground. Ground connection for the reference voltage. 27 V + Reference Input. REF 1 V A− Negative Input to Differential Amplifier. IN 2 V A+ Positive Output from Differential Amplifier. OUT 3 V A+ Positive Input to Differential Amplifier. IN 4 V A− Negative Output from Differential Amplifier. OUT 5 V − Negative Input to the Modulator. IN 6 V + Positive Input to the Modulator. IN 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7764 section for further details. 11 Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. FSO 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7764 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address, and the second word contains the data. See the AD7764 Interface section for further details. Rev. A | Page 9 of 32 06518-005 AD7764 Pin No. Mnemonic Description 14 FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. See the Synchronization section for further details. 16 RESET/ Reset/Power-Down Pin. When a logic low is sensed on this pin, the part is powered down and all internal PWRDWN circuitry is reset. 19 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the AD7764 section for more details. 18 DEC_RATE Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a decimation rate of 64× is selected. A decimation rate of 128× is selected by leaving the pin floating. A decimation rate of 256× is selected by setting the pin to ground. Rev. A | Page 10 of 32 AD7764 TYPICAL PERFORMANCE CHARACTERISTICS AV 1 = DV = 2.5 V, AV 2 = AV 3 = AV 4 = 5 V, V + = 4.096 V, MCLK amplitude = 5 V, T = 25°C. Linearity plots measured to DD DD DD DD DD REF A 16-bit accuracy. Input signal reduced to avoid modulator overload and digital clipping; fast Fourier transforms (FFTs) of −0.5 dB tones are generated from 262,144 samples in normal power mode. All other FFTs are generated from 8192 samples. 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 50k 100k 156.249k 0 25k 50k 75k 100k 125k 150k FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Normal Power Mode, FFT,1 kHz, −0.5 dB Input Tone, Figure 9. Low Power Mode, FFT,1 kHz, −0.5 dB Input Tone, 64× Decimation Rate 64× Decimation Rate 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 20k 40k 60k 78.124k 0 10k 20k 30k 40k 50k 60k 70k FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Normal Power Mode, FFT,1 kHz, −0.5 dB Input Tone, Figure 10. Low Power Mode, FFT,1 kHz, −0.5 dB Input Tone, 128× Decimation Rate 128× Decimation Rate 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 10k 20k 30k 39.062k 0 5k 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Normal Power Mode, FFT,1 kHz, −0.5 dB Input Tone, Figure 11. Low Power Mode, FFT,1 kHz, −0.5 dB Input Tone, 256× Decimation Rate 256× Decimation Rate Rev. A | Page 11 of 32 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06518-008 06518-007 06518-006 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06518-210 06518-211 06518-212 AD7764 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 50k 100k 150k 0 50k 100k 150k FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Normal Power Mode, FFT,1 kHz, −6 dB Input Tone, Figure 15. Low Power Mode, FFT,1 kHz, −6 dB Input Tone, 64× Decimation Rate 64× Decimation Rate 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 25k 50k 75k 0 25k 50k 75k FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Normal Power Mode, FFT,1 kHz, −6 dB Input Tone, Figure 16. Low Power Mode, FFT,1 kHz, −6 dB Input Tone, 128× Decimation Rate 128× Decimation Rate 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 0 5k 10k 15k 20k 25k 30k 35k 0 5k 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Normal Power Mode, FFT,1 kHz, −6 dB Input Tone, Figure 17. Low Power Mode, FFT,1 kHz, −6 dB Input Tone, 256× Decimation Rate 256× Decimation Rate Rev. A | Page 12 of 32 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06518-202 06518-201 06518-200 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 06518-205 06518-204 06518-203 AD7764 40 25 35 DV DD 20 30 DV DD 25 15 AV 1 DD AV 1 DD 20 AV 2 DD 10 15 AV 3 AV 2 DD DD 10 5 5 AV 3 AV 4 DD DD AV 4 DD 0 0 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 45 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 18. Normal Power Mode, Current Consumption vs. MCLK Frequency, Figure 21. Low Power Mode, Current Consumption vs. MCLK Frequency, 64× Decimation Rate 64× Decimation Rate 40 25 DV DD 35 DV DD 20 30 25 15 AV 1 DD 20 AV 1 DD AV 2 DD 10 15 AV 2 DD 10 5 AV 3 DD 5 AV 3 DD AV 4 AV 4 DD DD 0 0 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 19. Normal Power Mode, Current Consumption vs. MCLK Frequency, Figure 22. Low Power Mode, Current Consumption vs. MCLK Frequency, 128× Decimation Rate 128× Decimation Rate 40 20 18 35 DV DD DV DD 16 30 14 25 AV 1 AV 1 12 DD DD 20 10 AV 2 15 AV 2 8 DD DD 6 10 4 AV 3 DD AV 3 DD 5 2 AV 4 DD AV 4 DD 0 0 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 20. Normal Power Mode, Current Consumption vs. MCLK Frequency, Figure 23. Low Power Mode, Current Consumption vs. MCLK Frequency, 256× Decimation Rate 256× Decimation Rate Rev. A | Page 13 of 32 CURRENT (mA) CURRENT (mA) CURRENT (mA) 06518-112 06518-114 06518-010 CURRENT (mA) CURRENT (mA) CURRENT (mA) 06518-113 06518-115 06518-011 AD7764 2.0 0 –20 1.5 –40 1.0 –60 0.5 –80 0 –100 –0.5 –120 –1.0 –140 –1.5 –160 –2.0 –180 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 0 20k 40k 60k 78,124 CODE FREQUENCY (Hz) Figure 24. DNL Plot Figure 27. Normal Power Mode, IMD, f A = 49.7 kHz, f B = 50.3 kHz, IN IN 50 kHz Center Frequency, 128× Decimation Rate 0.003225 0.00300 –40°C 0.003000 +85°C 0.00225 0.00150 0.00225 +25°C 0.00075 +25°C 0 0.00150 –0.00075 +85°C –40°C 0.00075 –0.00150 –0.00225 0 –0.00300 –0.00012 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 6k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 59,535 16-BIT CODE SCALING 16-BIT CODE SCALING Figure 25. Normal Power Mode INL Figure 28. Low Power Mode INL 110 109 108 107 106 NORMAL SNR 105 104 LOW SNR 103 102 0 64 128 192 256 DECIMATION RATE Figure 26. Normal and Low Power Mode, SNR vs. Decimation Rate, 1 kHz, −0.5 dB Input Tone Rev. A | Page 14 of 32 INL (%) DNL (LSB) SNR (dB) 06518-009 06518-208 06518-206 INL (%) AMPLITUDE (dB) 06518-209 06518-207 AD7764 TERMINOLOGY Signal-to-Noise Ratio (SNR) Integral Nonlinearity (INL) The ratio of the rms value of the actual input signal to the rms The maximum deviation from a straight line passing through sum of all other spectral components below the Nyquist fre- the endpoints of the ADC transfer function. quency, excluding harmonics and dc. The value for SNR is Differential Nonlinearity (DNL) expressed in decibels (dB). The difference between the measured and the ideal 1 LSB Total Harmonic Distortion (THD) change between any two adjacent codes in the ADC. The ratio of the rms sum of harmonics to the fundamental. Zero Error For the AD7764, it is defined as The difference between the ideal midscale input voltage (when 2 2 2 2 2 both inputs are shorted together) and the actual voltage V +V +V +V +V 2 3 4 5 6 THD(dB)= 20 log producing the midscale output code. V 1 Zero Error Drift where: The change in the actual zero error value due to a temperature V is the rms amplitude of the fundamental. 1 change of 1°C. It is expressed as a percentage of full scale at V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 room temperature. to the sixth harmonics. Gain Error Nonharmonic Spurious-Free Dynamic Range (SFDR) The first transition (from 100…000 to 100…001) should occur The ratio of the rms signal amplitude to the rms value of the for an analog voltage 1/2 LSB above the nominal negative full peak spurious spectral component, excluding harmonics. scale. The last transition (from 011…110 to 011…111) should occur for an analog voltage 1 1/2 LSB below the nominal full Dynamic Range The ratio of the rms value of the full scale to the rms noise scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the measured with the inputs shorted together. The value for first transition, from the difference between the ideal levels. dynamic range is expressed in decibels. Gain Error Drift Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and The change in the actual gain error value due to a temperature fb, any active device with nonlinearities creates distortion products change of 1°C. It is expressed as a percentage of full scale at room temperature. at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second- order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7764 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Rev. A | Page 15 of 32 AD7764 THEORY OF OPERATION The AD7764 features an on-chip fully differential amplifier to The digital filtering that follows the modulator removes the feed the Σ-Δ modulator pins, an on-chip reference buffer, and large out-of-band quantization noise (see Figure 31) while also a FIR filter block to perform the required digital filtering of the reducing the data rate from f at the input of the filter to ICLK Σ-Δ modulator output. Using this Σ-Δ conversion technique f /64 or less at the output of the filter, depending on the ICLK with the added digital filtering, the analog input is converted to decimation rate used. an equivalent digital word. The AD7764 employs three FIR filters in series. By using different combinations of decimation ratios, data can be Σ-Δ MODULATION AND DIGITAL FILTERING obtained from the AD7764 at three data rates. The input waveform applied to the modulator is sampled, and an equivalent digital word is output to the digital filter at a rate The first filter receives data from the modulator at ICLK MHz equal to ICLK. By employing oversampling, the quantization where it is decimated 4× to output data at (ICLK/4) MHz. The noise is spread across a wide bandwidth from 0 to f . This second filter allows the decimation rate to be chosen from ICLK means that the noise energy contained in the signal band of 8× to 32×. interest is reduced (see Figure 29). To further reduce the The third filter has a fixed decimation rate of 2×. Table 6 shows quantization noise, a high-order modulator is employed to some characteristics of the digital filtering where ICLK = shape the noise spectrum so that most of the noise energy is MCLK/2. The group delay of the filter is defined to be the delay shifted out of the signal band (see Figure 30). to the center of the impulse response and is equal to the compu- tation plus the filter delays. The delay until valid data is available (the FILTER-SETTLE status bit is set) is approximately twice QUANTIZATION NOISE the filter delay plus the computation delay. This is listed in terms of MCLK periods in Table 6. f /2 ICLK BAND OF INTEREST 0 PASS-BAND RIPPLE = 0.05dB –0.1dB FREQUENCY = 125.1kHz Figure 29. Σ-Δ ADC, Quantization Noise –3dB FREQUENCY = 128kHz –20 STOP BAND = 156.25kHz –40 –60 NOISE SHAPING –80 f /2 ICLK BAND OF INTEREST –100 Figure 30. Σ-Δ ADC, Noise Shaping –120 –140 –160 DIGITAL FILTER CUTOFF FREQUENCY 0 50 100 150 200 250 300 FREQUENCY (kHz) f /2 ICLK Figure 32. Filter Frequency Response (312.5 kHz ODR) BAND OF INTEREST Figure 31. Σ-Δ ADC, Digital Filter Cutoff Frequency Table 6. Configuration with Default Filter SYNC ICLK Decimation Computation to Pass-Band Output Data Rate Frequency Rate Data State Delay Filter Delay FILTER-SETTLE Bandwidth (ODR) 20 MHz 64× Fully filtered 2.25 µs 87.6 µs 7122 × t 125 kHz 312.5 kHz MCLK 20 MHz 128× Fully filtered 3.1 µs 174 µs 14217 × t 62.5 kHz 156.25 kHz MCLK 20 MHz 256× Fully filtered 4.65 µs 346.8 µs 27895 × t 31.25 kHz 78.125 kHz MCLK 12.288 MHz 64× Fully filtered 3.66 µs 142.6 µs 7122 × t 76.8 kHz 192 kHz MCLK 12.288 MHz 128× Fully filtered 5.05 µs 283.2 µs 14217 × t 38.4 kHz 96 kHz MCLK 12.288 MHz 256× Fully filtered 7.57 µs 564.5 µs 27895 × t 19.2 kHz 48 kHz MCLK Rev. A | Page 16 of 32 06518-014 06518-013 06518-012 AMPLITUDE (dB) 06518-015 AD7764 Figure 32 shows the frequency response of the decimation filter AD7764 ANTIALIAS PROTECTION when the AD7764 is operated with a 40 MHz MCLK in The decimation of the AD7764, along with its counterparts in decimate × 128 mode. Note that the first stop-band frequency the AD776x family, namely the AD7760, AD7762, AD7763, and occurs at Nyquist. The frequency response of the filter scales AD7765, provides top of the range antialias protection. with both the decimation rate chosen and the MCLK frequency The decimation filter of the AD7764 features more than 115 dB applied. When using low power mode, the modulator sample of attenuation across the full stop band, which ranges from the rate is MCLK/4. Nyquist frequency, namely ODR/2, up to ICLK – ODR/2 Taking as an example the AD7764 in normal power and in (where ODR is the output data rate). Starting the stop band at decimate × 128 mode, the first possible alias frequency is at the the Nyquist frequency prevents any signal component above ICLK frequency minus the pass band of the digital filter (see Nyquist (and up to ICLK – ODR/2) from aliasing into the Figure 33). desired signal bandwidth. NO ALIASING OF SIGNALS INTO PASSBAND AROUND NYQUIST FREQUENCY SIMPLFIES ANTIALIAS DIGITAL FILTER FILTER ROLL-OFF REQUIRED RESPONSE IMAGE DIGITAL FILTER RESPONSE NOISE SHAPING FREQUENCY (Hz) NYQUIST = 78kHz ODR = 156kHz FIRST ALIAS POINT MODULATOR 20MHz TO 78kHz SAMPLING RATE = MCLK/2 = 20MHz Figure 33. Antialias Example Using the AD7764 in Normal Mode, Decimate × 128 Using MCLK/2 = ICLK = 20 MHz Rev. A | Page 17 of 32 AMPLITUDE (dB) 06518-213 AD7764 AD7764 INPUT STRUCTURE The AD7764 requires a 4.096 V input to the reference pin, Modulator _ Input = 8.192 V× 0.8= 6.5536V FULLSCALE V +, supplied by a high precision reference, such as the REF This means that a maximum of ±3.2768 V p-p full-scale can be ADR444. Because the input to the device’s Σ-Δ modulator is applied to each of the AD7764 modulator inputs (Pin 5 and fully differential, the effective differential reference range is Pin 6), with the AD7764 being specified with an input −0.5 dB 8.192 V. down from full scale (−0.5 dBFS). The AD7764 modulator V =2× 4.096= 8.192V inputs must have a common-mode input of 2.048 V. REF+(Diff ) Figure 34 shows the relative scaling between the differential As is inherent in Σ-Δ modulators, only a certain portion of this voltages applied to the modulator pins and the respective 24-bit full reference may be used. With the AD7764, 80% of the full twos complement digital outputs. differential reference can be applied to the modulator’s differ- ential inputs. TWOS COMPLEMENT INPUT VOLTAGE (V) DIGITAL OUTPUT OVERRANGE REGION +4.096V +3.2768V = MODULATOR FULL-SCALE = 80% OF 4.096V V + = 3.6855V IN 0111 1111 1111 1111 1111 1111 V – = 0.4105V IN 0111 1000 1101 0110 1111 1101 –0.5dBFS INPUT INPUT TO MODULATOR DIGITAL OUTPUT 0000 0000 0000 0000 0000 0001 PIN 5 AND PIN 6 V + = 2.048V ON SDO PIN V – AND V + IN 0000 0000 0000 0000 0000 0000 IN IN V – = 2.048V IN 1111 1111 1111 1111 1111 1111 –0.5dBFS INPUT 1000 0111 0010 1001 0000 0010 V + = 0.4105V IN 1000 0000 0000 0000 0000 0000 V – = 3.6855V IN 80% OF 4.096V = MODULATOR FULL-SCALE = –3.2768V –4.096V OVERRANGE REGION Figure 34. AD7764 Scaling: Modulator Input Voltage vs. Digital Output Code Rev. A | Page 18 of 32 06518-120 AD7764 The common-mode input at each of the differential amplifier ON-CHIP DIFFERENTIAL AMPLIFIER inputs (Pin V A+ and Pin V A−) can range from −0.5 V dc to IN IN The AD7764 contains an on-board differential amplifier that is 2.2 V dc. The amplifier has a constant output common-mode recommended to drive the modulator input pins. Pin 1, Pin 2, voltage of 2.048 V, that is, V /2, the requisite common mode REF Pin 3, and Pin 4 on the AD7764 are the differential input and voltage for the modulator input pins (V + and V −). IN IN output pins of the amplifier. The external components, R , R , IN FB Figure 36 shows the signal conditioning that occurs using the C , C , and R , are placed around Pin 1 through Pin 6 to create FB S M differential amplifier configuration detailed in Table 7 with a the recommended configuration. ±2.5 V input signal to the differential amplifier. The amplifier in To achieve the specified performance, the differential amplifier this example is biased around ground and is scaled to provide should be configured as a first-order antialias filter, as shown in ±3.168 V p-p (−0.5 dBFS) on each modulator input with a Figure 35, using the component values listed in Table 7. The 2.048 V common mode. inputs to the differential amplifier are then routed through the +3.632V +2.5V external component network before being applied to the mod- ulator inputs, V − and V + (Pin 5 and Pin 6). Using the IN IN V + IN 0V +2.048V optimal values in the table as an example yields a 25 dB A attenuation at the first alias point of 19.6 MHz. +0.464V C –2.5V FB R FB +2.5V +3.632V V A– V A+ IN OUT B R R M V – IN IN A V – 1 2 5 IN 0V +2.048V DIFF C C S M AMP B 3 4 6 V + IN R R IN M –2.5V +0.464V R FB V A+ V A– IN OUT Figure 36. Differential Amplifier Signal Conditioning C FB To obtain maximum performance from the AD7764, it is advisable to drive the ADC with differential signals. Figure 37 Figure 35. Differential Amplifier Configuration shows how a bipolar, single-ended signal biased around ground Table 7. On-Chip Differential Filter Component Values can drive the AD7764 with the use of an external op amp, such R R R C C C as the AD8021. IN FB M S FB M (kΩ) (kΩ) (Ω) (pF) (pF) (pF) C FB Optimal 4.75 3.01 43 8.2 47 33 Tolerance 2.37 to 2.4 to 36 to 0 to 20 to 33 to R 2R FB 1 Range 5.76 4.87 47 10 100 56 2R 1 V IN Values shown are the acceptable tolerances for each component when R R IN M altered relative to the optimal values used to achieve the stated AD8021 V – IN DIFF specifications of the device. C S C M AMP R M R V + IN The range of values for each of the components in the differ- ential amplifier configuration is listed in Table 7. When using R R IN FB the differential amplifier to gain the input voltages to the C FB required modulator input range, it is advisable to implement the gain function by changing R and leaving R as the listed IN FB Figure 37. Single-Ended-to-Differential Conversion optimal value. Rev. A | Page 19 of 32 06518-024 06518-026 06518-122 AD7764 SCO (O) MODULATOR INPUT STRUCTURE 32 × t SCO The AD7764 employs a double-sampling front end, as shown in FSI (I) Figure 38. For simplicity, only the equivalent input circuitry for V + is shown. The equivalent circuitry for V − is the same. IN IN SDI (I) CONTROL REGISTER AMP OFF MODE V + IN ADDRESS 0x0001 DATA 0x0001 CS1 SS1 Figure 39. Writing to the AD7764 Control Register Turning Off the On-Board SH3 CPA Differential Amplifier SS3 SH1 CPB1 The AD7764 modulator inputs must have a common-mode ANALOG MODULATOR voltage of 2.048 V and adhere to the amplitudes as described in the AD7764 Input Structure section. CS2 SS2 An example of a typical circuit to drive the AD7764 for applica- SH4 tions requiring excellent ac and dc performance is shown in SS4 SH2 CPB2 Figure 40. Either the AD8606 or AD8656 can be used to drive the AD7764 modulator inputs directly. Figure 38. Equivalent Input Circuit Best practice is to short the differential amplifier inputs to The SS1 and SS3 sampling switches are driven by ICLK, ground through the typical input resistors and leave the typical whereas the SS2 and SS4 sampling switches are driven by ICLK. feedback resistors in place. When ICLK is high, the analog input voltage is connected to 2 C2 CS1. On the falling edge of ICLK, the SS1 and SS3 switches 10kΩ open, and the analog input is sampled on CS1. Similarly, when 10kΩ 51Ω 2 0Ω C1 ICLK is low, the analog input voltage is connected to CS2. On U1 4.99kΩ ANALOG 1 the rising edge of ICLK, the SS2 and SS4 switches open, and the INPUT AD8606 10kΩ 2.048V AD8655 analog input is sampled on CS2. 10kΩ 5 V – U2 6 IN 4.99kΩ V + IN The CPA, CPB1, and CPB2 capacitors represent parasitic 51Ω 0Ω AD8606 1.024V capacitances that include the junction capacitances associated AD8655 AD7764 with the MOS switches. V A– V A+ V A+ V A– IN OUT IN OUT 1 2 3 4 Table 8. Equivalent Component Values R R FB FB CS1 CS2 CPA CPB1/CPB2 R R IN IN 13 pF 13 pF 13 pF 5 pF 1 –0.5dBFS INPUT SIGNAL AS DESCRIBED IN INPUT STRUCTURE SECTION. 2 SET C1 AND C2 AS REQUIRED FOR APPLICATION INPUT BW AND DRIVING THE MODULATOR INPUTS DIRECTLY ANTI-ALIAS REQUIREMENT. Figure 40. Driving the AD7764 Modulator Inputs Directly from a Single- The AD7765 can be configured so that the on-board differential Ended Source (On-Board Differential Amplifier Powered Down) amplifier can be disabled and the modulator can be driven directly using discrete amplifiers. This allows the user to lower the power dissipation. To power down the on board differential amplifier, the user issues a write to set the AMP OFF bit in the control register to logic high (see Figure 39). Rev. A | Page 20 of 32 06518-027 06518-302 06518-301 AD7764 AD7764 INTERFACE READING STATUS AND OTHER REGISTERS READING DATA The AD7764 features a gain correction register, an overrange The AD7764 uses an SPI-compatible serial interface. The register, and a read-only status register. To read back the timing diagram in Figure 2 shows how the AD7764 transmits its contents of these registers, the user must first write to the con-version results. control register of the device and set the bit that corresponds to The data read from the AD7764 is clocked out using the serial the register to be read. The next read operation outputs the clock output (SCO). The SCO frequency is half that of the contents of the selected register (on the SDO pin) instead of a MCLK input to the AD7764. conversion result. The conversion result output on the serial data output (SDO) To ensure that the next read cycle contains the contents of the line is framed by the frame synchronization output, , which FSO register written to, the write operation to that register must be is sent logic low for 32 SCO cycles. Each bit of the new conversion completed a minimum of 8 × t before the falling edge of FSO, SCO result is clocked onto the SDO line on the rising SCO edge and which indicates the start of the next read cycle. See Figure 4 for is valid on the falling SCO edge. The 32-bit result consists of the further details. 24 data bits followed by five status bits followed further by three The AD7764 Registers section provides more information on zeros. The five status bits are listed in Table 9 and described the relevant bits in the control register. below the table. WRITING TO THE AD7764 Table 9. Status Bits During Data Read A write operation to the AD7764 is shown in Figure 3. The D7 D6 D5 D4 D3 serial writing operation is synchronous to the SCO signal. The FILTER-SETTLE OVR LPWR DEC_RATE 1 DEC_RATE 0 FSI status of the frame synchronization input, , is checked on the • The FILTER-SETTLE bit indicates whether the data output FSI falling edge of the SCO signal. If the line is low, then the from the AD7764 is valid. After resetting the device (using first data bit on the serial data in (SDI) line is latched in on the the pin) or clearing the digital filter (using the RESET SYNC next SCO falling edge. pin), the FILTER-SETTLE bit goes logic low to indicate Set the active edge of the FSI signal to occur at a position when that the full settling time of the filter has not yet passed and the SCO signal is high or low to allow setup and hold times that the data is not yet valid. The FILTER-SETTLE bit also from the SCO falling edge to be met. The width of the FSI goes to zero when the input to the part has asserted the signal can be set to between 1 and 32 SCO periods wide. A overrange alerts. second, or subsequent, falling edge that occurs before 32 SCO • The OVR (overrange) bit is described in the Overrange periods have elapsed is ignored. Alerts section. • The LPWR bit is set to logic high when the AD7764 is Figure 3 details the format for the serial data being written to operating in low power mode. See the Power Modes the AD7764 through the SDI pin. Thirty-two bits are required section for further details. for a write operation. The first 16 bits are used to select the • The DEC_RATE 1 and DEC_RATE 0 bits indicate the register address that the data being read is intended for. The decimation ratio used. Table 10 is a truth table for the second 16 bits contain the data for the selected register. decimation rate bits. Writing to the AD7764 is allowed at any time, even while reading a conversion result. Note that, after writing to the Table 10. Decimation Rate Status Bits devices, valid data is not output until after the settling time Decimate DEC_RATE 1 DEC_RATE 0 for the filter has elapsed. The FILTER-SETTLE status bit is 64× 0 1 asserted at this point to indicate that the filter has settled and 1 128× 1 X that valid data is available at the output. 256× 0 0 1 Don’t care. If the DEC_RATE 1 bit is set to 1, AD7764 is in decimate 128× mode. Rev. A | Page 21 of 32 AD7764 AD7764 FUNCTIONALITY OVERRANGE ALERTS SYNCHRONIZATION The AD7764 offers an overrange function in both a pin and SYNC The input to the AD7764 provides a synchronization status bit output. The overrange alerts indicate when the voltage function that allows the user to begin gathering samples of the applied to the AD7764 modulator input pins exceeds the limit analog front-end input from a known point in time. set in the overrange register, indicating that the voltage applied The SYNC function allows multiple AD7764 devices, operated is approaching a level where the modulator will be overranged. from the same master clock that use common SYNC and To set this limit, the user must program the register. The default RESET signals, to be synchronized so that each ADC overrange limit is set to 80% of the V voltage (see the REF simultaneously updates its output register. Note that all devices AD7764 Registers section). being synchro-nized must operate in the same power mode and The OVERRANGE pin outputs logic high to alert the user at the same decimation rate. that the modulator has sampled an input voltage greater in In the case of a system with multiple AD7764s, connect magnitude than the overrange limit as set in the overrange common MCLK, SYNC and RESET signals to each AD7764. register. The OVERRANGE pin is set to logic high when the modulator samples an input above the overrange limit. After The AD7764 SYNC pin is polled by the falling edge of MCLK. the input returns below the limit, the OVERRANGE pin returns The AD7764 device goes into SYNC when an MCLK falling to zero. The OVERRANGE pin is updated after the first FIR edge senses that the SYNC input signal is logic low. At this filter stage. Its output changes at the ICLK/4 frequency. point, the digital filter sequencer is reset to 0. The filter is held The OVR status bit is output as Bit D6 on SDO during a data SYNC in a reset state (in mode) until the first MCLK falling conversion and can be checked in the AD7764 status register. edge senses SYNC to be logic high This bit is less dynamic than the OVERRANGE pin output. It is Where possible, ensure that all transitions of SYNC occur updated on each conversion result output; that is, the bit changes synchronously with the rising edge of MCLK (that is, as far at the output data rate. If the modulator has sampled a voltage away as possible from the MCLK falling edge, or decision edge). input that exceeded the overrange limit during the process of Otherwise, abide by the timing specified in Figure 41, which gathering samples for a particular conversion result output, SYNC excludes the rising edge from occurring in a 10 ns then the OVR bit is set to logic high. window centered around the MCLK fallings edge. LOGIC LEVEL SYNC Keep logic low for a minimum of four MCLK periods. HIGH When the MCLK falling edge senses that SYNC has returned to LOW logic high, the AD7764 filters begin to gather input samples t simultaneously. The FSO falling edges are also synchronized, OVERRANGE OUTPUT FREQUENCY LIMIT allowing for simultaneous output of conversion data. OF FIR FILTER 1 = ICLK/4 OBSOLUTE INPUT TO AD7764 MCLK [(V +) – (V –)] IN IN OUTPUT DATA RATE (ODR) (ICLK/DECIMATION RATE t OVERRANGE S SETUP LIMIT LOGIC SYNC LEVEL t S MIN 4 × t t HIGH MCLK S HOLD LOW SYNC Figure 41. Timing Relative to MCLK t Following a SYNC, the digital filter needs time to settle before Figure 42. OVERRANGE Pin and OVR Bit vs. Absolute Voltage Applied to the Modulator valid data can be read from the AD7764. The user knows there is valid data on the SDO line by checking the FILTER-SETTLE The output points from FIR Filter 1 in Figure 42 are not drawn status bit (see D7 in Table 9) that is output with each conversion to scale relative to the output data rate points. The FIR Filter 1 result. The time from the rising edge of SYNC until the FILTER- output is updated either 16×, 32×, or 64× faster than the output SETTLE bit asserts depends on the filter configuration used. See data rate, depending on the decimation rate in operation. the Theory of Operation section and the values listed in Table 6 for details on calculating the time until FILTER-SETTLE asserts. Note that the FILTER_SETTLE bit is designed as a reactionary flag to indicate when the conversion data output is valid. Rev. A | Page 22 of 32 06518-303 OVERRANGE PIN OVR BIT OUTPUT 06518-016 AD7764 RESET POWER MODES should be kept at logic low for a minimum of one MCLK period for a valid reset to occur. Low Power Mode In cases where multiple AD7764 devices are being synchronized During power-up, the AD7764 defaults to operate in normal using the SYNC pulse and in the case of daisy chaining multiple power mode. There is no register write required. AD7764 devices, a common RESET pulse must be provided in The AD7764 also offers low power mode. To operate the device addition to the common SYNC and MCLK signals. in low power mode, the user sets the LPWR bit in the control register to logic high (see Figure 43). Operating the AD7764 in low power mode has no impact on the output data rate or MCLK available bandwidth. SCO (O) t R SETUP 32 × t SCO RESET FSI (I) t R MIN 1 × t SDI (I) MCLK t R HOLD CONTROL REGISTER LOW POWER MODE ADDRESS 0x0001 DATA 0x0010 RESET Figure 44. Timing Synchronous to MCLK Figure 43. Write Scheme for Low Power Mode DECIMATION RATE PIN RESET/PWRDWN Mode The decimation rate of the AD7764 is selected using the The AD7764 features a RESET/PWRDWN pin. Holding the DEC_RATE pin. Table 11 shows the voltage input settings input to this pin logic low places the AD7764 in power-down required for each of the three decimation rates. RESET mode. All internal circuitry is reset. Apply a pulse to the Table 11. DEC_RATE Pin Settings AD7764 after initial power-up of the device. Decimate DEC_RATE Pin Maximum Output Data Rate The AD7764 RESET pin is polled by the rising edge of MCLK. 64× DV 312.5 kHz DD The AD7764 device goes into reset when an MCLK rising 128× Floating 156.25 kHz senses the RESET input signal to be logic low. AD7764 comes 256× GND 78.125 kHz out of RESET on the first MCLK rising edge that senses RESET to be logic high. RESET The best practice is to ensure that all transitions of occur synchronously with the falling edge of MCLK; otherwise, adhere to the timing requirements shown in Figure 44. Rev. A | Page 23 of 32 06518-017 06518-304 AD7764 DAISY CHAINING Daisy chaining allows numerous devices to use the same digital output from the device labeled AD7764 (A). This 32-bit interface lines. This feature is especially useful for reducing conversion result is then followed by the conversion results component count and wiring connections, such as in isolated from the AD7764 (B), AD7764 (C), and AD7764 (D) devices multiconverter applications or for systems with a limited with all conversion results output in an MSB-first sequence. interfacing capacity. Data readback is analogous to clocking a The signals output from the daisy chain are the stream of shift register. When daisy chaining is used, all devices in the conversion results from the SDO pin of AD7764 (A) and the chain must operate in a common power mode and at a common FSO signal output by the first device in the chain, AD7764 (A). decimation rate. The falling edge of FSO signals the MSB of the first conversion The block diagram in Figure 45 shows how to connect devices output in the chain. FSO stays logic low throughout the 32 SCO to achieve daisy-chain functionality. Figure 45 shows four clock periods needed to output the AD7764 (A) result and then AD7764 devices daisy-chained together with a common goes logic high during the output of the conversion results from MCLK signal applied. This can work in decimate 128× or the AD7764 (B), AD7764 (C), and AD7764 (D devices. decimate 256× mode only. The maximum number of devices that can be daisy-chained is READING DATA IN DAISY-CHAIN MODE dependent on the decimation rate selected. Calculate the maximum number of devices that can be daisy-chained by Referring to Figure 45, note that the SDO line of AD7764 (A) simply dividing the chosen decimation rate by 32 (the number provides the output data from the chain of AD7764 converters. of bits that must be clocked out for each conversion). Table 12 Also, note that for the last device in the chain, AD7764 (D), the provides the maximum number of chained devices for each SDI pin is connected to ground. All of the devices in the chain decimation rate. must use common MCLK and SYNC signals. To enable the daisy-chain conversion process, apply a common Table 12. Maximum Chain Length for all Decimation Rates SYNC pulse to all devices (see the Synchronization section). Decimation Rate Maximum Chain Length 256× 8 After a SYNC pulse is applied to all devices, the filter settling 128× 4 time must pass before the FILTER-SETTLE bit is asserted, 64× 2 indicating valid conversion data at the output of the chain of devices. As shown in Figure 46, the first conversion result is FSI AD7764 AD7764 AD7764 AD7764 (D) (C) (B) (A) FSI FSI FSI FSI FSO SDI SDO SDI SDO SDI SDO SDI SDO SYNC SYNC SYNC SYNC MCLK MCLK MCLK MCLK SYNC MCLK Figure 45. Daisy Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal 32 × t 32 × t 32 × t 32 × t SCO SCO SCO SCO SCO AD7764 (A) AD7764 (B) AD7764 (C) AD7764 (D) AD7764 (A) AD7764 (B) SDO (A) 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT 32-BIT OUTPUT FSO (A) SDI (A) = SDO (B) AD7764 (B) AD7764 (C) AD7764 (D) AD7764 (B) AD7764 (C) AD7764 (C) AD7764 (D) AD7764 (C) AD7764 (D) SDI (B) = SDO (C) SDI (C) = SDO (D) AD7764 (D) AD7764 (D) Figure 46. Daisy-Chain Mode, Data Read Timing Diagram (for the Daisy-Chain Configuration Shown in Figure 45) Rev. A | Page 24 of 32 06518-018 06518-019 AD7764 FSI WRITING DATA IN DAISY-CHAIN MODE rising edge of must be between 32 × (n − 1) to 32 × n SCO periods. For example, if three AD7764 devices are being written Writing to AD7764 devices in daisy-chain mode is similar to to in daisy-chain mode, FSI is logic low for between 32 × (3 − 1) writing to a single device. The serial writing operation is syn- to 32 × 3 SCO pulses. This means that the rising edge of FSI chronous to the SCO signal. The status of the frame synchro- th th must occur between the 64 and 96 SCO periods. nization input, FSI, is checked on the falling edge of the SCO signal. If the FSI line is low, then the first data bit on the serial The AD7764 devices can be written to at any time. The falling FSI data in the SDI line is latched in on the next SCO falling edge. edge of overrides all attempts to read data from the SDO FSI pin. In the case of a daisy chain, the signal remaining logic Writing data to the AD7764 in daisy-chain mode operates with low for more than 32 SCO periods indicates to the AD7764 the same timing structure as writing to a single device (see device that there are more devices further on in the chain. This Figure 3). The difference between writing to a single device and means that the AD7764 directs data that is input on the SDI pin writing to a number of daisy-chained devices is in the imple- to its SDO pin. This ensures that data is passed to the next FSI mentation of the signal. The number of devices that are in device in the chain. the daisy chain determines the period for which the FSI signal must remain logic low. To write to n number of devices in the daisy chain, the period between the falling edge of FSI and the FSI AD7764 AD7764 AD7764 AD7764 (D) (C) (B) (A) FSI FSI FSI FSI FSO SDI SDO SDI SDO SDI SDO SDI SDO SDI SYNC SYNC SYNC SYNC SCO MCLK MCLK MCLK MCLK SYNC MCLK Figure 47. Writing to an AD7764 Daisy-Chain Configuration t 10 FSI 32 × t 32 × t 32 × t 31 × t SCO SCO SCO SCO SCO SDI (D) SDI (D) SDI (C) = SDO (D) SDI (C) SDI (B) = SDO (C) SDI (B) SDI (A) = SDO (B) SDI (A) Figure 48. Daisy-Chain Write Timing Diagram; Writing to Four AD7764 Devices Rev. A | Page 25 of 32 06518-020 06518-021 AD7764 CLOCKING THE AD7764 The AD7764 requires an external low jitter clock source. This 256 t = = 470 ps j(rms) 3 5.45 signal is applied to the MCLK pin. An internal clock signal 2×π×19.2×10 ×10 (ICLK) is derived from the MCLK input signal. The ICLK The input amplitude also has an effect on these jitter figures. controls the internal operation of the AD7764. The maximum For example, if the input level is 3 dB below full scale, the allow- ICLK frequency is 20 MHz. To generate the ICLK, able jitter is increased by a factor of √2, increasing the first ICLK = MCLK/2 example to 144.65 ps rms. This happens when the maximum slew rate is decreased by a reduction in amplitude. For output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 6, Figure 49 and Figure 50 illustrate this point, showing the output data rates of 96 kHz and 48 kHz are achievable with this maximum slew rate of a sine wave of the same frequency but ICLK frequency. with different amplitudes. MCLK JITTER REQUIREMENTS The MCLK jitter requirements depend on a number of factors 1.0 and are given by OSR 0.5 t = j(rms) SNR (dB) 2×π× f ×10 IN 20 0 where: OSR = oversampling ratio = f /ODR. ICLK f = maximum input frequency. IN –0.5 SNR(dB) = target SNR. Example 1 This example can be taken from Table 6, where: –1.0 ODR = 312.5 kHz. Figure 49. Maximum Slew Rate of a Sine Wave with an Amplitude of 2 V p-p f = 20 MHz. ICLK 1.0 f (max) = 156.25 kHz. IN SNR = 104 dB. 64 0.5 t = = 51.41ps j(rms) 3 5.2 2×π×156.25×10 ×10 This is the maximum allowable clock jitter for a full-scale, 0 156.25 kHz input tone with the given ICLK and output data rate. Example 2 –0.5 This second example can also be taken from Table 6, where: ODR = 48 kHz. –1.0 = 12.288 MHz. f ICLK Figure 50. Maximum Slew Rate of the Same Frequency Sine Wave f (max) = 19.2 kHz. IN as in Figure 49 with an Amplitude of 1 V p-p SNR = 109 dB. Rev. A | Page 26 of 32 06518-023 06518-022 AD7764 DECOUPLING AND LAYOUT INFORMATION ADR444 SUPPLY DECOUPLING 200Ω 2 6 V + REF 7.5V V V IN OUT PIN 27 The decoupling of the supplies applied to the AD7764 is + + GND 10µF 100nF important in achieving maximum performance. Each supply 4 100µF 100nF pin must be decoupled to the correct ground pin with a 100 nF, 0603 case size capacitor. Figure 52. Reference Connection Pay particular attention to decoupling Pin 7 (AV 2) directly to DD the nearest ground pin (Pin 8). The digital ground pin AGND2 DIFFERENTIAL AMPLIFIER COMPONENTS (Pin 20) is routed directly to ground. Also, connect REFGND The components recommended for use around the on-chip (Pin 26) directly to ground. differential amplifier are detailed in Table 7. Matching the The DV (Pin 17) and AV 3 (Pin 28) supplies should be components on both sides of the differential amplifier is DD DD decoupled to the ground plane at a point away from the device. important to minimize distortion of the signal applied to the amplifier. A tolerance of 0.1% or better is required for these It is advised to decouple the supplies that are connected to the components. Symmetrical routing of the tracks on both sides following supply pins through 0603 size, 100 nF capacitors to a of the differential amplifier also assists in achieving stated star ground point linked to Pin 23 (AGND1): performance. Figure 53 shows a typical layout for the com- • V + (Pin 27) REF ponents around the differential amplifier. Note that the traces • AV 4 (Pin 25) DD for both differential paths are made as symmetrical as possible • AV 1 (Pin 24) and that the feedback resistors and capacitors are placed on the DD • AV 2 (Pin 21) underside of the PCB to enable the simplest routing. DD R IN A layout decoupling scheme for these supplies, which connect R FB C to the right side of the AD7764, is shown in Figure 51. Note the FB V A– IN star-point ground created at Pin 23. V A+ IN AV 4 DD (PIN 25) GND R IN AV 3 (PIN 28) DD PIN 23 V + (PIN 27) REF Figure 53. Typical Layout Structure for Surrounding Components STAR-POINT GND AV 1 (PIN 24) DD LAYOUT CONSIDERATIONS AV 2 (PIN 21) DD Whereas using the correct components is essential to achieve GND optimum performance, the correct layout is equally as VIA TO GND PIN 15 FROM PIN 20 important. The AD7764 product page on www.analog.com Figure 51. Supply Decoupling contains the Gerber files for the AD7764 evaluation board. The Gerber files should be used as a reference when designing any REFERENCE VOLTAGE FILTERING system using the AD7764. A low noise reference source, such as the ADR444 or ADR434 The use of ground planes should be carefully considered. To (4.096 V), is suitable for use with the AD7764. The reference ensure that the return currents through the decoupling voltage supplied to the AD7764 should be decoupled and capacitors are flowing to the correct ground pin, the ground filtered as shown in Figure 52. side of the capacitors should be as close to the ground pin The recommended scheme for the reference voltage supply is a associated with that supply, as recommended in the Supply 200 Ω series resistor connected to a 100 μF tantalum capacitor, Decoupling section. followed by a 10 nF decoupling capacitor very close to the V + pin. REF Rev. A | Page 27 of 32 06518-133 06518-135 06518-134 AD7764 Data can then be read from the device using the default gain USING THE AD7764 and overrange threshold values. The conversion data read is not Step1 through Step 5 detail the sequence for powering up and valid, however, until the settling time of the filter has elapsed. using the AD7764. Once this has occurred, the FILTER-SETTLE status bit is set, 1. Apply power to the device. indicating that the data is valid. 2. Apply the MCLK signal. Values for gain and overrange thresholds can be written to or RESET 3. Take low for a minimum of one MCLK cycle, read from the respective registers at this stage. preferably synchronous to the falling MCLK edge. If BIAS RESISTOR SELECTION multiple parts are to be synchronized, apply a common RESET to all devices. The AD7764 requires a resistor to be connected between the RESET 4. Wait a minimum of two MCLK cycles after is R and AGNDx pins. The resistor value should be selected to BIAS released. give a current of 25 µA through the resistor to ground. For a SYNC 5. If multiple parts are being synchronized, a pulse 4.096 V reference voltage, the correct resistor value is 160 kΩ. must be applied to the parts, preferably synchronous with the MCLK rising edge. In the case where devices are not being synchronized, no SYNC pulse is required; a logic high signal should simply be applied to the SYNC pin. When applying the SYNC pulse, SYNC • The issue of a pulse to the device must not coincide with a write to the device. • Ensure that the SYNC pulse is taken low for a minimum of four MCLK periods. Rev. A | Page 28 of 32 AD7764 AD7764 REGISTERS The AD7764 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and differential amplifier and provides the option to power down the AD7764. There are also digital gain and overrange threshold registers. Writing to these registers involves writing the register address followed by a 16-bit data-word. The register addresses, details of individual bits, and default values are provided in this section. CONTROL REGISTER Table 13. Control Register (Address 0x0001, Default Value 0x0000) MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SYNC 0 0 0 0 LPWR RD RD RD BYPASS PWR REF BUF AMP OVR GAIN STAT REF DOWN OFF OFF Table 14. Bit Descriptions of Control Register Bit Mnemonic Comment 1, 2 14 RD OVR Read overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register instead of a conversion result. 13 RD GAIN Read gain. If this bit is set, the next read operation outputs the contents of the digital gain register. 11 RD STAT Read status. If this bit is set, the next read operation outputs the contents of the status register. 9 SYNC Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple devices synchronizes all filters. 7 BYPASS REF Bypass reference. Setting this bit bypasses the reference buffer if the buffer is off. 3 PWR DOWN Power-down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up. 2 LPWR Low power mode. Set to Logic 1 when AD7764 is in low power mode. 1 REF BUF OFF Reference buffer off. Asserting this bit powers down the reference buffer. 0 AMP OFF Amplifier off. Asserting this bit switches the differential amplifier off. 1 Bit 14 to Bit 11 and Bit 9 are self-clearing bits. 2 Only one of the bits can be set in any write operation because it determines the contents of the next read operation. STATUS REGISTER Table 15. Status Register (Read Only) MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PARTNO 1 0 0 0 FILTER- 0 OVR 0 1 0 REF BUF AMP LPWR DEC 1 DEC 0 SETTLE ON ON Table 16. Bit Descriptions of the Status Register Bit Mnemonic Comment 15 PARTNO Part number. This bit is set to 1 for the AD7764. 10 FILTER-SETTLE Filter settling bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read operation. It indicates when data is valid. 9 0 Zero. This bit is set to Logic 0. 8 OVR Overrange. If the current analog input exceeds the current overrange threshold, this bit is set. 4 REF BUF ON Reference buffer on. This bit is set when the reference buffer is in use. 3 AMP ON Amplifier on. This bit is set when the input amplifier is in use. 2 LPWR Low power mode. This bit is set when operating in low power mode. 1 to 0 DEC_RATE[1:0] Decimation rate. These bits correspond to the decimation rate in use. Rev. A | Page 29 of 32 AD7764 OVERRANGE REGISTER—ADDRESS 0x0005 GAIN REGISTER—ADDRESS 0x0004 Non-Bit-Mapped, Default Value 0xCCCC Non-Bit-Mapped, Default Value 0xA000 The overrange register value is compared with the output of the The gain register is scaled such that 0x8000 corresponds to a first decimation filter to obtain an overload indication with gain of 1.0. The default value of this register is 1.25 (0xA000). minimum propagation delay. This is prior to any gain scaling. This results in a full-scale digital output when the input is at The default value is 0xCCCC, which corresponds to 80% of 80% of V +, tying in with the maximum analog input range of REF V + (the maximum permitted analog input voltage). Assuming REF ±80% of V + p-p. REF V + = 4.096 V, the bit is then set when the input voltage exceeds REF approximately 6.55 V p-p differential. The over-range bit is set immediately if the analog input voltage exceeds 100% of V + REF for more than four consecutive samples at the modulator rate. Rev. A | Page 30 of 32 AD7764 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 0.19 SEATING COPLANARITY 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 54. 28-Lead Thin Shrink Small Outline [TSSOP] (RU-28) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7764BRUZ –40°C to +85°C 28-Lead Thin Shrink Small Outline [TSSOP] RU-28 1 AD7764BRUZ-REEL7 –40°C to +85°C 28-Lead Thin Shrink Small Outline [TSSOP] RU-28 1 EVAL-AD7764EDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 31 of 32 AD7764 NOTES ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06518-0-11/09(A) Rev. A | Page 32 of 32