ANALOG DEVICES AD7762

625 kSPS, 24-Bit, 109 dB Σ−Δ ADC With On-Chip Buffer AD7762 FEATURES FUNCTIONAL BLOCK DIAGRAM V V 120 dB dynamic range at 78 kHz output data rate IN– IN+ 109 dB dynamic range at 625 kHz output data rate 112 dB SNR at 78 kHz output data rate MULTIBIT AV DD1 DIFF Σ-Δ AV 106 dB SNR at 625 kHz output data rate MODULATOR DD2 AV 625 kHz maximum fully filtered output word rate DD3 V REF+ AV RECONSTRUCTION DD4 Programmable over-sampling rate (32× to 256×) BUF DECAPA/B Fully differential modulator input R BIAS On-chip differential amplifier for signal buffering PROGRAMMABLE AD7762 AGND Low-pass finite impulse response (FIR) filter with default or DECIMATION V DRIVE user-programmable coefficients MCLK CONTROL LOGIC DV DD Overrange alert bit I/O SYNC DGND OFFSET AND GAIN Digital offset and gain correction registers REGISTERS FIR FILTER RESET ENGINE Filter bypass modes Low power and power-down modes Synchronization of multiple devices via SYNC pin CS RD/WR DRDY DB0 TO DB15 Figure 1. APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION The AD7762 is a high performance, 24-bit Σ-Δ analog-to- coefficients. The sample rate, filter corner frequencies, and output digital converter (ADC). It combines wide input bandwidth word rate are set by a combination of the external clock frequency and high speed with the benefits of Σ-Δ conversion with a and the configuration registers of the AD7762. performance of 106 dB SNR at 625 kSPS, making it ideal for The reference voltage supplied to the AD7762 determines the high speed data acquisition. Wide dynamic range combined analog input range. With a 4 V reference, the analog input range with significantly reduced antialiasing requirements simplify is ±3.2 V differential biased around a common mode of 2 V. the design process. An integrated buffer to drive the reference, This common-mode biasing can be achieved using the on-chip a differential amplifier for signal buffering and level shifting, an differential amplifier, further reducing the external signal overrange flag, internal gain and offset registers, and a low-pass conditioning requirements. digital FIR filter make the AD7762 a compact, highly integrated data acquisition device requiring minimal peripheral com- The AD7762 is available in an exposed paddle, 64-lead TQFP ponent selection. In addition, the device offers programmable and is specified over the industrial temperature range from decimation rates, and the digital FIR filter can be adjusted if −40°C to +85°C. the default characteristics are not appropriate to the application. The AD7762 is ideal for applications demanding high SNR Table 1. Related Devices without a complex front end signal processing design. Part No. Description AD7760 24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface The differential input is sampled at up to 40 MSPS by an analog AD7763 24-bit, 625 kSPS, 109 dB Σ-Δ, serial interface modulator. The modulator output is processed by a series of low- pass filters, the final filter having default or user-programmable Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05477-001 AD7762 TABLE OF CONTENTS General Description ......................................................................... 1 Bias Resistor Selection ............................................................... 17 Specifications..................................................................................... 3 Decoupling and Layout Recommendations................................ 18 Timing Specifications....................................................................... 5 Supply Decoupling ..................................................................... 19 Timing Diagrams.......................................................................... 5 Additional Decoupling .............................................................. 19 Absolute Maximum Ratings............................................................ 6 Reference Voltage Filtering ....................................................... 19 ESD Caution.................................................................................. 6 Differential Amplifier Components ........................................ 19 Pin Configuration and Function Descriptions............................. 7 Layout Considerations............................................................... 19 Terminology ...................................................................................... 9 Programmable FIR Filter............................................................... 20 Typical Performance Characteristics ........................................... 10 Downloading a User-Defined Filter ............................................ 21 Theory of Operation ...................................................................... 13 Example Filter Download ......................................................... 21 AD7762 Interface............................................................................ 14 AD7762 Registers ........................................................................... 23 Reading Data............................................................................... 14 Control Register 1—Reg 0x0001 .............................................. 23 Sharing the Parallel Bus............................................................. 14 Control Register 2—Address 0x0002 ...................................... 23 Writing to the AD7762 .............................................................. 14 Status Register (Read Only) ...................................................... 24 Reading Status and Other Registers......................................... 14 Offset Register—Address 0x0003............................................. 24 Clocking the AD7762 ................................................................ 15 Gain Register—Address 0x0004............................................... 24 Example 1 .................................................................................... 15 Overrange Register—Address 0x0005..................................... 24 Example 2 .................................................................................... 15 Outline Dimensions....................................................................... 25 Driving the AD7762....................................................................... 16 Ordering Guide .......................................................................... 25 Using the AD7762 ...................................................................... 17 REVISION HISTORY 8/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7762 SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode, 1 using on-chip amplifier with components as shown in Table 8, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Specification Unit DYNAMIC PERFORMANCE Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz Dynamic Range Modulator inputs shorted 119 dB min dB typ 120.5 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dBFS 112 dB typ Input amplitude = −60 dBFS 59 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ Input amplitude = −60 dBFS 77 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ Input amplitude = −6 dBFS −106 dB typ Input amplitude = −60 dBFS −75 dB typ Decimate by 64 MCLK = 40 MHz, ODR = 312.5 kHz, F = 1 kHz IN Dynamic Range Modulator inputs shorted 112 dB min dB typ 114 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dBFS 109.5 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, FIN =100 kHz Dynamic Range Modulator inputs shorted 108 dB min dB typ 109.5 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dBFS 107 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −108 dB typ Input amplitude = −6 dBFS −106 dB typ DC ACCURACY Resolution 24 Bits Differential Nonlinearity Guaranteed monotonic to 24 bits Integral Nonlinearity 0.00076 % typ Zero Error 0.014 % typ 0.02 % max Gain Error 0.015 % typ Zero Error Drift 0.019 %/°C typ Gain Error Drift 0.0002 %/°C typ DIGITAL FILTER RESPONSE Decimate by 32 Group Delay MCLK = 40 MHz 47 μs typ Decimate by 64 Group Delay MCLK = 40 MHz 91.5 μs typ Decimate by 256 Group Delay MCLK = 40 MHz 358 μs typ ANALOG INPUT Differential Input Voltage V (+) – V (−), V = 2.5 V ±2 V p-p IN IN REF V (+) – V (−), V = 4.096 V ±3.25 V p-p IN IN REF Input Capacitance At internal buffer inputs 5 pF typ At modulator inputs 55 pF typ Rev. 0 | Page 3 of 28 AD7762 Parameter Test Conditions/Comments Specification Unit REFERENCE INPUT/OUTPUT VREF Input Voltage VDD3 = 3.3 V ± 5% +2.5 V max VDD3 = 5 V ± 5% +4.096 V max V Input DC Leakage Current ±6 μA max REF V Input Capacitance 5 pF max REF POWER DISSIPATION Total Power Dissipation Normal mode 958 mW max Low power mode 661 mW max Standby Mode Clock stopped 6.35 mW max POWER REQUIREMENTS AV (Modulator Supply) ±5% +2.5 V DD1 AVDD2 (General Supply) ±5% +5 V AVDD3 (Diff Amp Supply) +3.15/+5.25 V min/max AVDD4 (Ref Buffer Supply) +3.15/+5.25 V min/max DV ±5% +2.5 V DD V +1.65/+2.7 V min/max DRIVE Normal Mode AIDD1 (Modulator) 49/51 mA typ/max AIDD2 (General) 40/42 mA typ/max AIDD4 (Reference Buffer) AVDD4 = 5 V 34/36 mA typ/max Low Power Mode AI (Modulator) 26/28 mA typ/max DD1 AIDD2 (General) 20/23 mA typ/max AIDD4 (Reference Buffer) AVDD4 = 5 V 9/10 mA typ/max AI (Diff Amp) AV = 5 V, both modes 41/44 mA typ/max DD3 DD3 DI Both modes 63/70 mA typ/max DD DIGITAL I/O 3 MCLK Input Amplitude 5 V typ Input Capacitance 7.3 pF typ Input Leakage Current ±5 μA max Three-State Leakage Current (D15:D0) ±5 μA max VINH 0.7 × VDRIVE V min VINL 0.3 × VDRIVE V max 4 V 1.5 V min OH 4 V 0.1 V max OL 1 See the Terminology section. 2 SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 While the AD7762 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 4 Tested with a 400 μA load current. Rev. 0 | Page 4 of 28 AD7762 TIMING SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description f 1 MHz min Applied master clock frequency MCLK 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max 1, 2 t1 0.5 × tICLK typ DRDY pulse width t 10 ns min DRDY falling edge to CS falling edge 2 t 3 ns min RD/WR setup time to CS falling edge 3 t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t 3 ns min RD/WR hold time to CS rising edge 7 t 11 ns max Bus relinquish time 8 t 4 × t min CS low write pulse width 9 ICLK t10 4 × tICLK min CS high period between address and data t11 5 ns min Data setup time t12 0 ns min Data hold time 1 tICLK = 1/fICLK. 2 DRDY When ICLK = MCLK, pulse width depends on the mark/space ratio of applied MCLK. TIMING DIAGRAMS DRDY t t t 1 5 6 CS t 2 t 7 t 3 RD/WR t t 4 8 D[0:15] DATA MSW LSW + STATUS Figure 2. Parallel Interface Timing Diagram CS t t 9 10 RD/WR t t 11 12 D[0:15] REGISTER ADDRESS REGISTER DATA Figure 3. AD7762 Register Write Rev. 0 | Page 5 of 28 05477-004 05477-002 AD7762 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameters Rating may cause permanent damage to the device. This is a stress AV to GND −0.3 V to +3 V DD1 rating only; functional operation of the device at these or any AV –AV to GND −0.3 V to +6 V DD2 DD4 other conditions above those listed in the operational sections DVDD to GND −0.3 V to +3 V of this specification is not implied. Exposure to absolute VDRIVE to GND −0.3 V to +3 V maximum rating conditions for extended periods may affect VIN+, VIN– to GND −0.3 V to +6 V device reliability. 1 Digital input voltage to GND −0.3 V to DV + 0.3 V DD MCLK to MCLKGND −0.3 V to +6 V 2 V to GND −0.3 V to AV + 0.3 V REF DD4 AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin ±10 mA 3 Except Supplies Operating Temperature Range Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TQFP Exposed Paddle Package θ Thermal Impedance 92.7°C/W JA θ Thermal Impedance 5.1°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 600 V 1 Absolute maximum voltage on digital inputs is 3.0 V or DV + 0.3 V, DD whichever is lower. 2 Absolute maximum voltage on V input is 6.0 V or AV + 0.3 V, REF DD4 whichever is lower. 3 Transient currents of up to 200 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 28 AD7762 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DGND DB12 PIN 1 2 47 MCLKGND DB13 3 46 MCLK DB14 AV 4 45 DB15 DD2 AGND2 5 44 V DRIVE AV 6 43 DGND DD1 AD7762 7 42 AGND1 TOP VIEW DGND (Not to Scale) DECAPA 8 41 DV DD 9 40 REFGND CS 10 39 V RD/WR REF+ AGND4 11 38 DRDY AV 12 37 RESET DD4 AGND2 13 36 SYNC AV 14 35 DGND DD2 15 34 AV AGND1 DD2 16 33 AGND2 AV DD1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 4. 64-Lead TQFP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 6, 33 AVDD1 2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 with 100 nF and 10 μF capacitors on each pin. 4, 14, 15, 27 AV 5 V Power Supply. These pins should be decoupled to AGND2 with 100 nF capacitors on each of Pin 4, DD2 Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via a 15 nH inductor. 24 AV DD3 3.3 V to 5 V Power Supply for Differential Amplifier. These pins should be decoupled to AGND3 with a 100 nF capacitor. 12 AVDD4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND4 with a 10 nF capacitor in series with a 10 Ω resistor. 7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AV . DD1 5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AV . DD2 23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3. 11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4. 9 REFGND Reference Ground. Ground connection for the reference voltage. 41 DV 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a DD 100 nF capacitor. 44, 63 V DRIVE Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating voltage of the logic interface. Both these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a100 nF capacitor. 1, 35, 42, 43, DGND Ground Reference for Digital Circuitry. 53, 62, 64 19 V A+ Positive Input to Differential Amplifier. IN 20 VINA− Negative Input to Differential Amplifier. 21 VOUTA− Negative Output from Differential Amplifier. 22 VOUTA+ Positive Output from Differential Amplifier. 25 V + Positive Input to the Modulator. IN 26 V − Negative Input to the Modulator. IN 10 V Reference Input. The input range of this pin is determined by the reference buffer supply voltage REF+ (AVDD4). See the Reference Voltage Filtering section for more details. 8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1. Rev. 0 | Page 7 of 28 DGND R BIAS V AGND2 DRIVE DGND V A+ IN DB0 V A– IN DB1 V A– OUT DB2 V A+ OUT DB3 AGND3 DB4 AV DD3 DB5 V + IN DB6 V – IN DB7 AV DD2 DGND AGND2 DB8 AGND3 DB9 DECAPB DB10 AGND3 DB11 AGND3 05477-005 AD7762 Pin No. Mnemonic Description 30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3. 17 RBIAS Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see the Bias Resistor Selection section. 45 to 52, DB15 to DB8 16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR 54 to 61 DB7 to DB0 pin. The operating voltage for these pins is determined by the V voltage. See the AD7762 Interface DRIVE section for more details. 37 RESET A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low keeps the AD7762 in a reset state. 3 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the section Clocking the AD7762 for more details. 2 MCLKGND Master Clock Ground Sensing Pin. 36 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. 39 RD/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a write occurs. See the AD7762 Interface section for more details. 38 DRDY Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ ICLK period wide, is produced on this pin. See the AD7762 Interface section for more details. 40 CS Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the AD7762. See the AD7762 Interface section for more details. Rev. 0 | Page 8 of 28 AD7762 TERMINOLOGY Signal-to-Noise Ratio (SNR) Differential Nonlinearity (DNL) SNR is the ratio of the rms value of the actual input signal to the The difference between the measured and the ideal 1-LSB rms sum of all other spectral components below the Nyquist change between any two adjacent codes in the ADC. frequency, excluding harmonics and dc. The value for SNR is Zero Error expressed in decibels. The zero error is the difference between the ideal midscale Total Harmonic Distortion (THD) input voltage (0 V) and the actual voltage producing the The ratio of the rms sum of harmonics to the fundamental. For midscale output code. the AD7762, it is defined as Zero Error Drift 2 2 2 2 2 The change in the actual zero error value due to a temperature V + V + V + V + V 2 3 4 5 6 THD() dB = 20 log change of 1°C. It is expressed as a percentage of the zero error at V 1 room temperature. where: Gain Error V1 is the rms amplitude of the fundamental. The first transition (from 100…000 to 100…001) should occur V2, V3, V4, V5,.and V6 are the rms amplitudes of the second to for an analog voltage 1/2 LSB above the nominal negative full the sixth harmonics. scale. The last transition (from 011…110 to 011…111) should occur for an analog voltage 1 1/2 LSB below the nominal full Nonharmonic Spurious-Free Dynamic Range (SFDR) scale. The gain error is the deviation of the difference between The ratio of the rms signal amplitude to the rms value of the the actual level of the last transition and the actual level of the peak spurious spectral component, excluding harmonics. first transition, from the difference between the ideal levels. Dynamic Range Gain Error Drift Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The The change in the actual gain error value due to a temperature value for dynamic range is expressed in decibels. change of 1°C. It is expressed as a percentage of the gain error at room temperature. Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Rev. 0 | Page 9 of 28 AD7762 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All FFTs are generated from 65536 samples using a 7-term Blackman-Harris window. 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Normal Mode FFT, 1 kHz, −6 dB Input Tone, 256× Decimation Figure 9. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation Figure 10. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation Rev. 0 | Page 10 of 28 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 05477-008 05477-007 05477-006 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 05477-011 05477-010 05477-009 AD7762 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 60000 120000 180000 240000 300000 0 60000 120000 180000 240000 300000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation Figure 14. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 60000 120000 180000 240000 300000 0 60000 120000 180000 240000 300000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 32× Decimation 120 116 –60dB 118 –60dB 116 112 –6dB –6dB 114 –0.5dB 112 108 –0.5dB 110 108 106 104 0 64 128 192 256 0 64 128 192 256 DECIMATION RATE (x) DECIMATION RATE (x) Figure 13. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone Rev. 0 | Page 11 of 28 SNR (dBFS) AMPLITUDE (dB) AMPLITUDE (dB) 05477-062 05477-061 05477-060 SNR (dBFS) AMPLITUDE (dB) AMPLITUDE (dB) 05477-065 05477-064 05477-063 AD7762 4500 3000 4000 2500 3500 3000 2000 2500 1500 2000 1500 1000 1000 500 500 0 0 8385222 8385238 8385254 8385270 8383530 83835246 8383562 8383578 8383594 8383610 24-BIT CODE 24-BIT CODE Figure 17. Normal Mode, 24-Bit Histogram, 256× Decimation Figure 20. Low Power, 24-Bit Histogram, 256× Decimation 0.0010 0.0015 +85°C +85°C 0.0010 0.0005 0.0005 +25°C +25°C 0 0 –40°C –40°C –0.0005 –0.0005 –0.0010 –0.0010 0 4194304 8388608 12582912 16777216 0 4194304 8388608 12582912 16777216 24-BIT CODE 24-BIT CODE Figure 18. 24-Bit INL, Normal Mode Figure 21. 24-Bit INL, Low Power Mode 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 4194304 8388608 12582912 16777216 24-BIT CODE Figure 19. 24-Bit DNL Rev. 0 | Page 12 of 28 DNL (LSB) INL (%) OCCURRENCE 05477-057 05477-056 05477-055 INL (%) OCCURRENCE 05477-059 05477-058 AD7762 THEORY OF OPERATION The AD7762 employs a Σ-Δ conversion technique to convert rate to be chosen from 4× to 32×. The third filter has a fixed the analog input into an equivalent digital word. The modulator decimation rate of 2×, is user programmable, and has a default samples the input waveform and outputs an equivalent digital configuration. It is described in detail in the Programmable FIR word to the digital filter at a rate equal to ICLK. Filter section. This filter can be bypassed. Due to the high oversampling rate, that spreads the Table 6 lists some characteristics of the default filter. The group quantization noise from 0 to f , the noise energy contained in delay of the filter is defined to be the delay to the center of the ICLK the band of interest is reduced (Figure 22 a). To further reduce impulse response and is equal to the computation + filter delays. the quantization noise, a high order modulator is employed to The delay until valid data is available (the DVALID status bit is shape the noise spectrum; so that most of the noise energy is set) is equal to 2× the filter delay + the computation delay. shifted out of the band of interest (Figure 22 b). a. The digital filtering that follows the modulator removes the large out-of-band quantization noise (Figure 22 c) while also QUANTIZATION NOISE reducing the data rate from f at the input of the filter to ICLK f \2 ICLK f /8 or less at the output of the filter, depending on the BAND OF INTEREST ICLK decimation rate used. b. Digital filtering has certain advantages over analog filtering. It does not introduce significant noise or distortion and can be NOISE SHAPING made perfectly linear phase. f \2 ICLK The AD7762 employs three FIR filters in series. By using BAND OF INTEREST different combinations of decimation ratios and filter selection and bypassing, data can be obtained from the AD7762 at a large c. range of data rates. The first filter receives data from the modulator at ICLK MHz where it is decimated by four to DIGITAL FILTER CUTOFF FREQUENCY output data at ICLK/4 MHz. This partially filtered data can also f \2 ICLK be output at this stage. The second filter allows the decimation BAND OF INTEREST Figure 22. Σ-Δ ADC Table 6. Configuration with Default Filter ICLK Computation Pass-Band Output Data Frequency Filter 1 Filter 2 Filter 3 Data State Delay Filter Delay Bandwidth Rate (ODR) 20 MHz 4× 4× 2× Fully filtered 1.775 μs 44.4 μs 250 kHz 625 kHz 20 MHz 4× 8× Bypassed Partially filtered 2.6 μs 10.8 μs 140.625 kHz 625 kHz 20 MHz 4× 8× 2× Fully filtered 2.25 μs 87.6 μs 125 kHz 312.5 kHz 20 MHz 4× 16× Bypassed Partially filtered 4.175 μs 20.4 μs 70.3125 kHz 312.5 kHz 20 MHz 4× 16× 2× Fully filtered 3.1 μs 174 μs 62.5 kHz 156.25 kHz 20 MHz 4× 32× Bypassed Partially filtered 7.325 μs 39.6 μs 35.156 kHz 156.25 kHz 20 MHz 4× 32× 2× Fully filtered 4.65 μs 346.8 μs 31.25 kHz 78.125 kHz 12.288 MHz 4× 8× 2× Fully filtered 3.66 μs 142.6 μs 76.8 kHz 192 kHz 12.288 MHz 4× 16× 2× Fully filtered 5.05 μs 283.2 μs 38.4 kHz 96 kHz 12.288 MHz 4× 32× Bypassed Partially filtered 11.92 μs 64.45 μs 21.6 kHz 96 kHz 12.288 MHz 4× 32× 2× Fully filtered 7.57 μs 564.5 μs 19.2 kHz 48 kHz Rev. 0 | Page 13 of 28 04975-037 AD7762 AD7762 INTERFACE READING DATA WRITING TO THE AD7762 The AD7762 uses a 16-bit bidirectional parallel interface. This While the AD7762 is configured to convert analog signals with interface is controlled by the RD/WR and CS pins. the default settings on reset, there are many features and parameters on this part that the user can change by writing to When a new conversion result is available, an active low pulse is the device. Because some of the programmable registers are output on the pin. To read a conversion result from the DRDY 16 bits wide, two write operations are required to program a AD7762, two 16-bit read operations are performed. The DRDY register. The first write contains the register address while the pulse indicates that a new conversion result is available. Both second write contains the register data. An exception is when a RD/WR and CS go low to perform the first read operation. user filter is being downloaded to the AD7762. This is described in detail in the Downloading a User-Defined Filter Shortly after both these lines go low, the data bus becomes section. The AD7762 Registers section contains the register active and the 16 most significant bits (MSBs) of the conversion addresses and more details. result are output. The /WR and lines must return high RD CS for a full ICLK period before the second read is performed. This Figure 3 shows a write operation to the AD7762. The /WR RD second read contains the 8 least significant bits (LSBs) of the line is held high while the CS line is brought low for a minimum conversion result along with 6 status bits. These status bits are of 4 ICLK periods. The register address is latched during this shown in Table 7. Descriptions of the other status bits are in period. The line is brought high again for a minimum of CS Table 15. 4 ICLK periods before the register data is put onto the data bus. Table 7. Status Bits During Data Read If a read operation occurs between the writing of the register D7 D0 address and the register data, the register address is cleared and DValid Ovr UFilt LPwr FiltOk DLOk 0 0 the next write must be the register address again. This also provides a method to get back to a known situation if the user forgets whether the next write is an address or data. Shortly after /WR and return high, the data bus returns RD CS to a high impedance state. Both read operations must be Generally, the AD7762 is written to and configured on power- completed before a new conversion result is available because up and very infrequently, if at all, after that. Following any write the new result overwrites the contents on the output register. operation, the full group delay of the filter must pass before If a DRDY pulse occurs during a read operation, the data read valid data is output from the AD7762. is invalid. READING STATUS AND OTHER REGISTERS SHARING THE PARALLEL BUS The AD7762 features a number of programmable registers. To By its nature, the high accuracy of the AD7762 makes it read back the contents of these registers or the status register, the sensitive to external noise sources. These include digital activity user must first write to the control register of the device, setting on the parallel bus. For this reason, it is recommended that the a bit corresponding to the register to be read. The next read AD7762 data lines are isolated from the system data bus by operation outputs the contents of the selected register instead means of a latch or buffer to ensure that there is no digital of a conversion result. The AD7762 Registers section provides activity on the D0 to D15 pins that is not controlled by the more information on the relevant bits in the control register. AD7762. If multiple, synchronized AD7762 parts that share a properly distributed common MCLK signal exist in a system, these parts can share a common bus without being isolated from each other. This bus can then be isolated from the system bus by a single latch or buffer. Rev. 0 | Page 14 of 28 AD7762 CLOCKING THE AD7762 EXAMPLE 2 The AD7762 requires an external low jitter clock source. This Take a second example from Table 6, where: signal is applied to the MCLK pin, and the MCLKGND pin is ODR = 48 kHz used to sense the ground from the clock source. An internal f = 12.288 MHz ICLK clock signal (ICLK) is derived from the MCLK input signal. f (max) = 19.2 kHz IN The ICLK controls the internal operations of the AD7762. The SNR = 120 dB maximum ICLK frequency is 20 MHz, but due to an internal clock divider, a range of MCLK frequencies can be used. There 256 t = = 133 ps j(rms) 3 6 are two ways to generate the ICLK: 2×π×19.2×10 ×10 ICLK = MCLK (CDIV = 1) The input amplitude also has an effect on these jitter figures. ICLK = MCLK/2 ( = 0) CDIV If, for example, the input level was 3 dB below full scale, the allowable jitter would be increased by a factor of √2, increasing These options are selected from the control register (see the the first example to 2.53 ps rms. This happens when the AD7762 Registers section for more details). On power-up, the maximum slew rate is decreased by a reduction in amplitude. default is ICLK = MCLK/2 to ensure that the part can handle Figure 23 and Figure 24 illustrate this point, showing the the maximum MCLK frequency of 40 MHz. For output data maximum slew rate of a sine wave of the same frequency but rates equal to those used in audio systems, a 12.288 MHz ICLK with different amplitudes. frequency can be used. As shown in Table 6, output data rates 1 of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK frequency. As mentioned previously, this ICLK frequency can be derived from different MCLK frequencies. 0.5 The MCLK jitter requirements depend on a number of factors and are given by 0 OSR t = j(rms) SNR(dB) 20 2×π× f ×10 IN –0.5 where: f ICLK OSR = Over-sampling ratio = ODR –1.0 f = Maximum input frequency IN Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p SNR(dB) = Target SNR EXAMPLE 1 1 This example can be taken from Table 6, where: ODR = 625 kHz fICLK = 20 MHz 0.5 fIN (max) = 250 kHz SNR = 108 dB 0 32 t = = 3.6ps j(rms) 3 6 2×π× 250×10 ×10 –0.5 This is the maximum allowable clock jitter for a full-scale, 250 kHz input tone with the given ICLK and output data rate. –1.0 Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with Amplitude of 1 V p-p Rev. 0 | Page 15 of 28 04975-039 04975-038 AD7762 DRIVING THE AD7762 +2.5V +3.685V The AD7762 has an on-chip differential amplifier that operates with a supply voltage (AV ) from 3.15 V to 5.25 V. For a 4.096 DD3 V + IN V reference, the supply voltage must be 5 V. 0V +2.048V A To achieve the specified performance in normal mode, the –2.5V +0.410V differential amplifier should be configured as a first-order antialias filter, as shown in Figure 25. Any additional filtering should be carried out in previous stages using low noise, high +2.5V +3.685V performance op amps, such as the AD8021. B V – IN 0V +2.048V Suitable component values for the first-order filter are listed in Table 8. The values in Table 8 yield a 10 dB attenuation at the –2.5V +0.410V first alias point of 19 MHz. C Figure 26. Differential Amplifier Signal Conditioning FB C FB R FB 2R R FB R R IN M A V – IN 2R V IN C A1 S R R IN M R M AD8021 V – IN B V + IN R C A1 IN S R M R R FB V + IN R R C IN FB FB C FB Figure 25. Differential Amplifier Configuration Table 8. Normal Mode Component Values Figure 27. Single-Ended-to-Differential Conversion VREF RIN RFB RM CS CFB 4.096 V 1 kΩ 655 Ω 18 Ω 5.6 pF 33 pF V + IN CS1 SS1 Figure 26 shows the signal conditioning that occurs using the SH3 CPA circuit in Figure 25 with a ±2.5 V input signal biased around SH1 SS3 CPB1 ground and having the component values and conditions in ANALOG Table 8. The differential amplifier always biases the output MODULATOR signal to sit on the optimum common mode of VREF/2, in this case 2.048 V. The signal is also scaled to give the maximum CS2 SS2 allowable voltage swing with this reference value. This is SH4 calculated as 80% of V , that is, 0.8 × 4.096 V ≈ 3.275 V p-p REF SS4 SH2 CPB2 on each input. To obtain maximum performance from the AD7762, it is Figure 28. Equivalent Input Circuit advisable to drive the ADC with differential signals. Figure 27 The AD7762 employs a double sampling front end, as shown in shows how a bipolar, single-ended signal biased around ground Figure 28. For simplicity, only the equivalent input circuit for VIN+ can drive the AD7762 with the use of an external op amp, such is shown. The equivalent input circuitry for VIN− is the same. as the AD8021. With a 4.096 V reference, a 5 V supply must be provided to the reference buffer (AV ). With a 2.5 V reference, a 3.3 V supply DD4 must be provided to AV . DD4 Rev. 0 | Page 16 of 28 04975-040 05477-043 04975-042 04975-041 AD7762 The sampling switches SS1 and SS3 are driven by ICLK, whereas Data can then be read from the part using the default filter, the sampling switches SS2 and SS4 are driven by . When offset, gain, and overrange threshold values. The conversion ICLK data read is not valid, however, until the group delay of the filter ICLK is high, the analog input voltage is connected to CS1. On has passed. When this has occurred, the DVALID bit read with the falling edge of ICLK, the SS1 and SS3 switches open, and the the data LSW is set, indicating that the data is indeed valid. analog input is sampled on CS1. Similarly, when ICLK is low, the analog input voltage is connected to CS2. On the rising edge of The user can then download a different filter, if required ICLK, the SS2 and SS4 switches open, and the analog input is (see Downloading a User-Defined Filter). Values for gain, offset, sampled on CS2. and overrange threshold registers can be written or read at this stage. Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances that include the junction capacitances associated with the MOS BIAS RESISTOR SELECTION switches. The AD7762 requires a resistor to be connected between the Table 9. Equivalent Component Values R pin and AGND1. The value for this resistor is dependant BIAS Mode CS1 CS2 CPA CPB1/2 on the reference voltage being applied to the device. The resistor Normal 51 pF 51 pF 12 pF 20 pF value should be selected to give a current of 25 μA through the Low Power 13 pF 13 pF 12 pF 5 pF resistor to ground. For a 2.5 V reference voltage, the correct resistor value is 100 kΩ and for a 4.096 V reference, the correct resistor value is 160 kΩ. USING THE AD7762 The following is the recommended sequence for powering up and using the AD7762. 1. Apply power. 2. Start the clock oscillator, applying MCLK. 3. Take low for a minimum of 1 MCLK cycle. RESET 4. Wait a minimum of 2 MCLK cycles after RESET has been released. 5. Write to Control Register 2 to power up the ADC and the differential amplifier as required. The correct clock divider (CDIV) ratio should be programmed now. 6. Write to Control Register 1 to set the output data rate. 7. Wait a minimum of 5 MCLK cycles after has been CS released. 8. Take low for a minimum of 4 MCLK cycles, if SYNC required, to synchronize multiple parts. Rev. 0 | Page 17 of 28 AD7762 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7762, correct decoupling and layout techniques are required to obtain the performance as stated within this datasheet. Figure 29 shows a simplified connection diagram for the AD7762. U2 DB (0:15) 19 61 DB0 INA+ V A+ DB0 IN 60 20 DB1 INA– V A– DB1 IN 21 59 DB2 OUTA– V A– DB2 OUT 22 58 DB3 OUTA+ V A+ DB3 OUT 57 DB4 DB4 56 DB5 DB5 55 8 DB6 DECAPA DB6 30 54 DB7 DECAPB DB7 52 DB8 DB8 51 DB9 DB9 25 50 DB10 VIN+ V + DB10 IN 49 C7 C64 26 DB11 VIN– V – DB11 IN 100nF 33pF 48 DB12 DB12 AD7762BSV 47 DB13 DB13 10 46 DB14 VREF V + DB14 REF 9 45 DB15 REFGND DB15 17 40 R CS CS BIAS 39 RD/WR RD/WR 1 DGND 35 37 DGND RESET RESET 42 36 DGND SYNC SYNC 43 38 DGND DRDY DRDY 53 R19 DGND 62 3 160kΩ DGND MCLK MCLK 64 2 DGND MCLKGND AV AV AV AV V DV DD2 DD4 DD1 DD3 DRIVE DD PIN 12 L4 (VBUF) L1 L3 L2 L5 L11 L6 L7 L12 L8 PIN 4 PIN 15 PIN 14 PIN 5 PIN 33 PIN 24 PIN 44 PIN 63 PIN 41 (RHS) (VBIAS) (LHS) PIN 27 (VMOD1) (VMOD2) (VDIF1) (VDRV1) (VDRV2) (DVDD) L9 R38 10Ω C48 C50 C62 C59 C52 C53 C54 C56 C57 C58 100nF 100nF 100nF 10nF 100nF 100nF 100nF 100nF 100nF 100nF Figure 29. Simplified Connection Diagram Rev. 0 | Page 18 of 28 7 AGND1 34 4 AGND1 AV PIN 4 DD2 14 AV PIN 14 DD2 15 AV PIN 15 DD2 5 AGND2 13 12 AGND2 AV PIN 12 DD4 16 AGND2 18 6 AGND2 AV PIN 6 DD1 28 33 AGND2 AV PIN 33 DD1 24 AV PIN 24 DD3 23 27 AGND3 AV PIN 27 DD2 29 AGND3 31 44 AGND3 V PIN 44 DRIVE 32 63 AGND3 V PIN 63 DRIVE 11 41 AGND4 DV PIN 41 DD 05477-046 AD7762 SUPPLY DECOUPLING DIFFERENTIAL AMPLIFIER COMPONENTS Every supply pin must be connected to the appropriate supply The correct components for use around the on-chip differential via a ferrite bead and decoupled to the correct ground pin with amplifier are detailed in Table 8. Matching the components on a 100 nF, 0603 case size, X7R dielectric capacitor. There are two both sides of the differential amplifier is important to minimize exceptions to this: distortion of the signal applied to the amplifier. A tolerance of 0.1% or better is required for these components. Symmetrical • Pin 12 (AV ) must have a 10 Ω resistor inserted between DD4 routing of the tracks on both sides of the differential amplifier the pin and a 10 nF decoupling capacitor. also assists in achieving stated performance. • Pin 27 (AV ) does not require a separate decoupling DD2 LAYOUT CONSIDERATIONS capacitor or a direct connection to the supply, but instead While using the correct components is essential to achieve is connected to Pin 14 via a 15 nH inductor. optimum performance, the correct layout is just as important. ADDITIONAL DECOUPLING The Design Tools section of the AD7762 product page on the Analog Devices website contains the gerber files for the There are two other decoupling pins on the AD7762—Pin 8 AD7762 evaluation board. These files should be used as a (DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled reference when designing any system using the AD7762. with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor. The location and orientation of some of the components REFERENCE VOLTAGE FILTERING mentioned in previous sections is critical, and particular A low noise reference source, such as the ADR431 (2.5 V) or attention must be paid to the components which are located ADR434 (4.096 V), is suitable for use with the AD7762. The close to the AD7762. Locating these components further away reference voltage supplied to the AD7762 should be decoupled from the devices can have a direct impact on the maximum and filtered, as shown in Figure 30. performance achievable. The recommended scheme for the reference voltage supply The use of ground planes also should be carefully considered. is a 100 Ω series resistor connected to a 100 μF tantalum To ensure that the return currents through the decoupling capacitor, followed by series resistor of 10 Ω, and finally a capacitors are flowing to the correct ground pin, the ground 10 nF decoupling capacitor very close to the V pin. REF+ side of the capacitors should be as close to the ground pin U3 associated with that supply. A ground plane should not be relied ADR434 R30 R17 100Ω 10Ω on as the sole return path for decoupling capacitors because the 2 6 +12V +VIN VOUT PIN10 return current path using ground planes is not easily + + GND C15 C9 C10 C11 C46 10μF 100nF 4 100nF 100μF 10nF predictable. Figure 30. Reference Connection Rev. 0 | Page 19 of 28 04975-047 AD7762 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7762 is To create a filter, note the following: user programmable. The default coefficients that are loaded on • The filter must be even, symmetrical FIR. reset are given in Table 10 and the frequency responses are Figure 31. The frequencies quoted in Figure 31 scale shown in • The coefficients are in sign-and-magnitude format with directly with the output data rate. 26 magnitude bits and sign coded as positive = 0. Table 10. Default Filter Coefficients • The filter length must be between 12 taps and 96 taps in Dec. Hex Dec. Hex steps of 12. No. Value Value No. Value Value 0 53656736 332BCA0 24 700847 AB1AF • Because the filter is symmetrical, the number of 1 25142688 17FA5A0 25 −70922 401150A coefficients that must be downloaded is half the filter 2 −4497814 444A196 26 −583959 408E917 length. The default filter coefficients exemplify this with 3 −11935847 4B62067 27 −175934 402AF3E only 48 coefficients listed for a 96-tap filter. 4 −1313841 4140C31 28 388667 5EE3B 5 6976334 6A734E 29 294000 47C70 • Coefficients are written from the center of impulse 6 3268059 31DDDB 30 −183250 402CBD2 response (adjacent to the point of symmetry) outwards. 7 −3794610 439E6B2 31 −302597 4049E05 • The coefficients are scaled so that the in-band gain of the 8 −3747402 4392E4A 32 16034 3EA2 filter is equal to 134217726 with the coefficients rounded 9 1509849 1709D9 33 238315 3A2EB to the nearest integer. For a low-pass filter, this is the 10 3428088 344EF8 34 88266 158CA equivalent of having the coefficients sum arithmetically 11 80255 1397F 35 −143205 4022F65 (including sign) to a 67108863 (0x3FF FFFF) positive 12 −2672124 428C5FC 36 −128919 401F797 value over the half-impulse response coefficient set 13 −1056628 4101F74 37 51794 CA52 (maximum 48 coefficients). Any deviation from this 14 1741563 1A92FB 38 121875 1DC13 introduces a gain error. 15 1502200 16EBF8 39 16426 402A 16 −835960 40CC178 40 −90524 401619C 0 PASS-BAND RIPPLE = 0.05dB 17 −1528400 4175250 41 −63899 400F99B –0.1dB FREQUENCY = 251kHz –3dB FREQUENCY = 256kHz –20 18 93626 16DBA 42 45234 B0B2 STOP BAND = 312.5kHz 19 1269502 135EFE 43 114720 1C020 –40 20 411245 6466D 44 102357 18FD5 –60 21 −864038 40D2F26 45 52669 CDBD 22 −664622 40A242E 46 15559 3CC7 –80 23 434489 6A139 47 1963 7AB –100 –120 The default filter should be sufficient for almost all applications. –140 It is a standard brick wall filter with a symmetrical impulse response. The default filter has a length of 96 taps in non- –160 0 100 200 300 400 500 600 aliasing with 120 dB of attenuation at Nyquist. This filter not FREQUENCY (kHz) only performs signal antialiasing, but also suppresses out-of- band quantization noise produced by the analog-to-digital Figure 31. Default Filter Frequency Response (625 kHz ODR) conversion process. Any significant relaxation in the stop-band The procedure for downloading a user-defined filter is detailed attenuation or transition bandwidth relative to the default filter in the Downloading a User-Defined Filter section. can result in a failure to meet the SNR specifications. Rev. 0 | Page 20 of 28 AMPLITUDE (dB) 05477-044 AD7762 DOWNLOADING A USER-DEFINED FILTER As previously mentioned, the filter coefficients are 27 bits in EXAMPLE FILTER DOWNLOAD length; 1 sign and 26 magnitude bits. Because the AD7762 The following is an example of downloading a short user- has a 16-bit parallel bus, the coefficients are padded with defined filter with 24 taps. The frequency response is shown 5 MSB 0s to generate a 32-bit word and split into two 16-bit in Figure 32. words for downloading. The first 16-bit word for each coefficient 10 becomes (00000, Sign bit, Magnitude [25:16]), while the second word becomes (Magnitude [15:0]). To ensure that a filter is 0 down-loaded correctly, a checksum must also be generated and –10 then downloaded following the final coefficient. The checksum –20 is a 16-bit word generated by splitting each 32-bit word into 4 bytes and summing all bytes from all coefficients up to a –30 maximum of 192 bytes (48 coefficients × 4 bytes). The same –40 checksum is generated internally in the AD7762 and compared –50 with the checksum downloaded. The DL_OK bit in the status register is set if these two checksums agree. –60 –70 To download a user filter: –80 1. Write to Control Register 1, setting the DL_Filt bit and 0 100 200 300 400 500 600 FREQUENCY (kHz) also the correct filter length bits corresponding to the length of the filter to be downloaded (see Table 11). Figure 32. 24-Tap FIR Frequency Response 2. Write the first half of the current coefficient data The coefficients for the filter are listed in Table 12 and are (00000, Sign bit, Magnitude [25:16]). The first coefficient shown from the center of symmetry outwards. The raw to be written must be the one adjacent to the point of filter coefficients were generated using a commercial filter symmetry. design tool and scaled appropriately so their sum equals 67108863 (0x3FF FFFF). 3. Write the second half of the current coefficient data Table 12. 24-Tap FIR Coefficients (Magnitude [15:0]). Coefficient Raw Scaled 4. Repeat Step 2 and Step 3 for each coefficient. 1 0.365481974 53188232 2 0.201339905 29300796 5. Write the 16-bit checksum. 3 0.009636604 1402406 6. Use these methods to verify that the filter coefficients are 4 −0.075708848 −11017834 downloaded correctly: 5 −0.042856209 −6236822 6 0.019944246 2902466 a. Read the status register, checking the DL_OK bit. 7 0.036437914 5302774 b. Read data and observe the status of the DL_OK bit. 8 0.007592007 1104856 9 −0.021556583 −3137108 Note that because the user coefficients are stored in RAM, they 10 −0.024888355 −3621978 are cleared after a RESET operation or a loss of power. 11 −0.012379538 −1801582 Table 11. Filter Length Values 12 −0.001905756 −277343 FLEN[3:0] Number of Coefficients Filter Length 0000 Default Default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96 Rev. 0 | Page 21 of 28 AMPLITUDE (dB) 04975-045 AD7762 Table 13 shows the hex values (in sign and magnitude format) Table 14 lists the 16-bit words the user would write to the that are downloaded to the AD7762 to realize this filter. The AD7762 to set up the ADC and download this filter, assuming table is also split into the bytes that are all summed to produce an output data rate of 625 kHz has already been selected. the checksum. The checksum generated from these coefficients Table 14. is 0x0E6B. Word Description Table 13. Filter Hex Values 0x0001 Address of Control Register 1. Word 1 Word 2 0x8079 Control register data. DL filter, set filter length = 24, set output data rate = 625 kHz. Coefficient Byte 1 Byte 2 Byte 3 Byte 4 0x032B First coefficient, Word 1. 1 03 2B 96 88 0x9688 First coefficient, Word 2. 2 01 BF 18 3C 0x01BF Second coefficient, Word 1. 3 00 15 66 26 0x183C Second coefficient, Word 2. 4 04 A8 1E 6A … Other coefficients. 5 04 5F 2A 96 0x0404 Twelfth (final) coefficient, Word 1. 6 00 2C 49 C2 0x3B5F Final coefficient, Word 2. 7 00 50 E9 F6 0x0E6B Checksum. Wait (0.5 × tICLK × Number of Unused 8 00 10 DB D8 Coefficients) for AD7762 to fill remaining unused 9 04 2F DE 54 coefficients with 0s. 10 04 37 44 5A 0x0001 Address of control register. 11 04 1B 7D 6E 0x0879 Control register data. Set read status and maintain 12 04 04 3B 5F filter length and decimation settings. Read contents of status register. Check Bit 7 (DL_OK) to determine that the filter was downloaded correctly. Rev. 0 | Page 22 of 28 AD7762 AD7762 REGISTERS The AD7762 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are given here. CONTROL REGISTER 1—REG 0X0001 Default Value 0x001A MSB LSB BYP F3 DL_ Filt RD Ovr RD Gain RD Off RD Stat 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0 1 DEC2 DEC1 DEC0 Table 15. Bit Mnemonic Description 1 15 DL_Filt Download Filter. Before downloading a user-defined filter, this bit must be set. The Filter Length bits must also be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the coefficients and the checksum have been written. 1, 2 14 RD Ovr Read Overrange. If this bit has been set, the next read operation outputs the contents of the Overrange Threshold Register instead of a conversion result. 1, 2 13 RD Gain Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register. 1, 2 12 RD Off Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register. 1, 2 11 RD Stat Read Status. If this bit has been set, the next read operation outputs the contents of the status register. 10 0 0 must be written to this bit. 1 9 SYNC Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple devices synchronizes all filters. 8-5 FLEN3:0 Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded. 4 BYP F3 Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed. 3 1 1 must be written to this bit. 2-0 DEC2:0 Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1 corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on up to the maximum value of 5, corresponding to 32× decimation. 1 Bit 15 to Bit 9 are all self clearing bits. 2 Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation. CONTROL REGISTER 2—ADDRESS 0X0002 Default Value 0x009B MSB LSB 0 0 0 0 0 0 0 0 0 0 CDIV 0 PD LPWR 1 D1PD Table 16. Bit Mnemonic Description 5 CDIV Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the MCLK by 2. If CDIV = 1, then the ICLK frequency is equal to the MCLK. 3 PD Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW. 2 LPWR Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for a 6 dB reduction in noise performance. 1 1 Write 1 to this bit. 0 D1PD Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier. Rev. 0 | Page 23 of 28 AD7762 STATUS REGISTER (READ ONLY) MSB LSB PART 1 PART 0 DIE 2 DIE 1 DIE 0 DVALID LPWR OVR DL OK Filter OK U Filter BYP F3 1 DEC2 DEC1 DEC0 Table 17. Bit Mnemonic Comment 15, 14 PART1:0 Part Number. These bits are constant for the AD7762. 13 to 11 DIE2:0 Die Number. These bits reflect the current AD7762 die number for identification purposes within a system. 10 DVALID Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation. 9 LPWR Low Power. If the AD7762 is operating in low power mode, this bit is set to 1. 8 OVR If the current analog input exceeds the current overrange threshold, this bit is set. 7 DL OK When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. 6 Filter OK When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set. 5 U Filter If a user-defined filter is in use, this bit is set. 4 BYP F3 Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. 3 1 This bit is always set. 2-0 DEC2:0 Decimation Rate. These correspond to the bits set in Control Register 1. OFFSET REGISTER—ADDRESS 0X0003 Non-bitmapped, Default Value 0x0000 The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.78125% and −0.78125%, respectively. Offset correction is applied after any gain correction. Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25 mV. GAIN REGISTER—ADDRESS 0X0004 Non-bitmapped, Default Value 0xA000 The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a full-scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of ±80% of VREF p-p. OVERRANGE REGISTER—ADDRESS 0X0005 Non-bitmapped, Default Value 0xCCCC The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of V REF (the maximum permitted analog input voltage). Assuming V = 4.096 V, the bit is then set when the input voltage exceeds REF approximately 6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of VREF for more than four consecutive samples at the modulator rate. Rev. 0 | Page 24 of 28 AD7762 OUTLINE DIMENSIONS 12.20 12.00 SQ 1.20 0.75 11.80 MAX 0.60 0.45 64 49 49 64 1 48 48 1 PIN 1 10.20 10.00 SQ TOP VIEW EXPOSED 7.50 9.80 (PINS DOWN) PAD BSC SQ 0° MIN 1.05 0.20 1.00 BOTTOM VIEW 0.09 (PINS UP) 0.95 7° 16 16 33 33 3.5° 17 32 32 17 0.15 0° SEATING 0.05 0.08 MAX PLANE VIEW A 0.50 0.38 COPLANARITY BSC 0.32 LEAD PITCH 0.22 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD Figure 33. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7762BSVZ −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-4 1 AD7762BSVZ-REEL −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) SV-64-4 EVAL-AD7762EB Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 25 of 28 AD7762 NOTES Rev. 0 | Page 26 of 28 AD7762 Rev. 0 | Page 27 of 28 AD7762 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05477–0–8/05(0) Rev. 0 | Page 28 of 28