ANALOG DEVICES AD7760

2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer AD7760 FEATURES FUNCTIONAL BLOCK DIAGRAM V – V + 120 dB dynamic range at 78 kHz output data rate IN IN 100 dB dynamic range at 2.5 MHz output data rate 112 dB SNR at 78 kHz output data rate MULTIBIT AV 1 DD DIFF Σ-Δ MODULATOR AV 2 DD 100 dB SNR at 2.5 MHz output data rate AV 3 DD 2.5 MHz maximum fully filtered output word rate V REF+ AV 4 BUF RECONSTRUCTION DD Programmable oversampling rate (8× to 256×) DECAPA/B Fully differential modulator input R BIAS On-chip differential amplifier for signal buffering AD7760 PROGRAMMABLE AGND DECIMATION Low-pass finite impulse response (FIR) filter with default or V DRIVE MCLK user-programmable coefficients DV CONTROL LOGIC DD I/O Modulator output mode SYNC DGND OFFSET AND GAIN REGISTERS FIR FILTER Overrange alert bit RESET ENGINE Digital offset and gain correction registers Filter bypass modes CS RD/WR DRDY DB0 TO DB15 Low power and power-down modes Figure 1. pin Synchronization of multiple devices via SYNC APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION The AD7760 is a high performance, 24-bit Σ-Δ analog-to-digital coefficients. The sample rate, filter corner frequencies, and output converter (ADC). It combines wide input bandwidth and high word rate are set by a combination of the external clock frequency speed with the benefits of Σ-Δ conversion to achieve a perfor- and the configuration registers of the AD7760. mance of 100 dB SNR at 2.5 MSPS, making it ideal for high The reference voltage supplied to the AD7760 determines the speed data acquisition. Wide dynamic range combined with analog input range. With a 4 V reference, the analog input range significantly reduced antialiasing requirements simplify the is ±3.2 V differential biased around a common mode of 2 V. design process. An integrated buffer to drive the reference, a This common-mode biasing can be achieved using the on-chip differential amplifier for signal buffering and level shifting, an differential amplifier, further reducing the external signal overrange flag, internal gain and offset registers, and a low-pass conditioning requirements. digital FIR filter make the AD7760 a compact, highly integrated data acquisition device requiring minimal peripheral component The AD7760 is available in an exposed paddle, 64-lead TQFP selection. In addition, the device offers programmable decimation and is specified over the industrial temperature range from rates, and the digital FIR filter can be adjusted if the default −40°C to +85°C. characteristics are not appropriate for the application. The Table 1. Related Devices AD7760 is ideal for applications demanding high SNR Part No. Description without a complex front-end signal processing design. AD7762 24-bit, 625 kSPS, 109 dB, Σ-Δ parallel interface The differential input is sampled at up to 40 MSPS by an analog AD7763 24-bit, 625 kSPS, 109 dB, Σ-Δ serial interface modulator. The modulator output is processed by a series of low- pass filters, with the final filter having default or user-programmable Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04975-001 AD7760 TABLE OF CONTENTS Features .............................................................................................. 1 Writing to the AD7760 .............................................................. 23 Applications....................................................................................... 1 Clocking the AD7760 .................................................................... 24 Functional Block Diagram .............................................................. 1 Buffering the MCLK signal....................................................... 24 General Description ......................................................................... 1 MCLK Jitter Requirements ....................................................... 24 Revision History ............................................................................... 3 Driving the AD7760....................................................................... 26 Specifications..................................................................................... 4 Using the AD7760 ...................................................................... 27 Timing Specifications .................................................................. 6 Decoupling and Layout Recommendations................................ 28 Timing Diagrams.......................................................................... 7 Supply Decoupling ..................................................................... 29 Absolute Maximum Ratings............................................................ 8 Additional Decoupling .............................................................. 29 ESD Caution.................................................................................. 8 Reference Voltage Filtering ....................................................... 29 Pin Configuration and Function Descriptions............................. 9 Differential Amplifier Components ........................................ 29 Terminology .................................................................................... 11 Bias Resistor Selection ............................................................... 29 Typical Performance Characteristics ........................................... 12 Layout Considerations............................................................... 29 Theory of Operation ...................................................................... 18 Exposed Paddle........................................................................... 29 Modulator Data Output Mode...................................................... 19 Programmable FIR Filter............................................................... 30 Modulator Inputs........................................................................ 19 Downloading a User-Defined Filter ............................................ 31 Modulator Data Output Scaling ............................................... 19 Example Filter Download ......................................................... 31 Modulator Data Output Mode Interface ..................................... 20 AD7760 Registers ........................................................................... 33 Clock Divide-by-1 Mode (CDIV = 1) ..................................... 20 Control Register 1—Address 0x0001 ...................................... 33 Control Register 2—Address 0x0002 ...................................... 33 CDIV Clock Divide-by-2 Mode ( = 0) ..................................... 20 Status Register (Read Only) ...................................................... 34 Using the AD7760 in Modulator Output Mode..................... 21 Offset Register—Address 0x0003............................................. 34 AD7760 Interface............................................................................ 22 Gain Register—Address 0x0004............................................... 34 Reading Data............................................................................... 22 Overrange Register—Address 0x0005..................................... 34 Reading Status and Other Registers......................................... 22 Outline Dimensions....................................................................... 35 Sharing the Parallel Bus............................................................. 22 Ordering Guide .......................................................................... 35 Synchronization.......................................................................... 22 Rev. A | Page 2 of 36 AD7760 REVISION HISTORY 8/06—Rev. 0 to Rev. A Updated Package Option................................................... Universal Added MCLK Jitter Requirements Heading ...............................24 Change to Features............................................................................1 Changes to Driving the AD7760 Section.....................................26 Changes to Specifications.................................................................4 Changes to Figure 51 ......................................................................26 Changes to Absolute Maximum Ratings........................................8 Added Figure 52 ..............................................................................26 Changes to Terminology Section ..................................................11 Changes to Figure 55 ......................................................................28 Added Figure 36 Through Figure 39 ............................................17 Changes to Figure 56 ......................................................................29 Added Modulator Data Output Mode Section ...........................19 Added Exposed Paddle Section.....................................................29 Added Figure 41 Through Figure 47 ............................................19 Change to Control Register 2—Address 0x0002 Section ..........33 Added Modulator Data Output Mode Interface Section...........20 Changes to Status Register (Read Only) Section ........................34 Changes to Reading Data Section.................................................22 7/05—Revision 0: Initial Version Added Synchronization Section....................................................22 Changes to Clocking the AD7760 Section...................................24 Added Buffering the MCLK Signal Section.................................24 Rev. A | Page 3 of 36 AD7760 SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF+ = 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode, using 1 the on-chip amplifier with components as shown in Table 8, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Specification Unit DYNAMIC PERFORMANCE Decimate by 256 MCLK = 40 MHz, ODR = 78 kHz, fIN = 1 kHz Dynamic Range Modulator inputs shorted 119 dB min 120.5 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dBFS 112 dB typ Input amplitude = −60 dBFS 59 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 126 dBc typ Input amplitude = −60 dBFS 77 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ Input amplitude = −6 dBFS −106 dB typ Input amplitude = −60 dBFS −75 dB typ Decimate by 32 MCLK = 40 MHz, ODR = 625 kHz, f =100 kHz IN Dynamic Range Modulator inputs shorted 108 dB min 109.5 dB typ 2 Signal-to-Noise Ratio (SNR) Input amplitude = −0.5 dBFS 107 dB typ Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dBFS 120 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS −105 dB typ Input amplitude = −6 dBFS −106 dB typ Decimate by 8 MCLK = 40 MHz, ODR = 2.5 MHz Dynamic Range Modulator inputs shorted 99 dB min 100.5 dB typ 2 Signal-to-Noise Ratio (SNR) f = 1 kHz, input amplitude = −0.5 dBFS 100 dB typ IN f = 100 kHz, input amplitude = −0.5 dBFS 99 dB typ IN f = 1 MHz, input amplitude = −0.5 dBFS 98 dB typ IN Spurious-Free Dynamic Range (SFDR) Nonharmonic, fIN = 100 kHz, input amplitude = −6 dBFS 120 dBc typ Nonharmonic, fIN = 1 MHz, input amplitude = −6 dBFS 114 dBc typ Total Harmonic Distortion (THD) Input amplitude = −0.5 dBFS, fIN = 100 kHz −103 dB typ Input amplitude = −6 dBFS, f = 100 kHz −102 dB typ IN IMD Second Order f A = 989.95 kHz, f B = 999.95 kHz −115 dB typ IN IN IMD Third Order fIN A = 989.95 kHz, fIN B = 999.95 kHz −89 dB typ DC ACCURACY Resolution 24 Bits Differential Nonlinearity Guaranteed monotonic to 24 bits Integral Nonlinearity 0.00076 % typ Zero Error 0.014 % typ 0.02 % max Gain Error 0.016 % typ Zero Error Drift 0.00001 % FS/°C typ Gain Error Drift 0.0002 % FS/°C typ DIGITAL FILTER RESPONSE Decimate by 8 Group Delay MCLK = 40 MHz 12 μs typ Decimate by 32 Group Delay MCLK = 40 MHz 47 μs typ Decimate by 256 Group Delay MCLK = 40 MHz 358 μs typ Rev. A | Page 4 of 36 AD7760 Parameter Test Conditions/Comments Specification Unit ANALOG INPUT Differential Input Voltage VIN(+) – VIN(−), VREF = 2.5 V ±2 V p-p VIN(+) – VIN(−), VREF = 4.096 V ±3.25 V p-p Input Capacitance At internal buffer inputs 5 pF typ At modulator inputs 55 pF typ REFERENCE INPUT/OUTPUT V Input Voltage V 3 = 3.3 V ± 5% +2.5 V max REF DD V 3 = 5 V ± 5% +4.096 V max DD VREF Input DC Leakage Current ±6 μA max VREF Input Capacitance 5 pF max POWER DISSIPATION Total Power Dissipation Normal mode 958 mW max Low power mode 661 mW max Standby Mode Clock stopped 6.35 mW max POWER REQUIREMENTS AVDD1 (Modulator Supply) ±5% +2.5 V AVDD2 (General Supply) ±5% +5 V AV 3 (Differential Amplifier Supply) +3.15/+5.25 V min/max DD AV 4 (Reference Buffer Supply) +3.15/+5.25 V min/max DD DVDD ±5% +2.5 V VDRIVE +1.65/+2.7 V min/max Normal Mode AIDD1 (Modulator) 49/51 mA typ/max 3 AI 2 (General) 40/42 mA typ/max DD AI 4 (Reference Buffer) AV 4 = 5 V 34/36 mA typ/max DD DD Low Power Mode AIDD1 (Modulator) 26/28 mA typ/max 3 AIDD2 (General) 20/23 mA typ/max AI 4 (Reference Buffer) AV 4 = 5 V 9/10 mA typ/max DD DD AI 3 (Differential Amplifier) AV 3 = 5 V, both modes 41/44 mA typ/max DD DD DI Both modes 63/70 mA typ/max DD DIGITAL I/O 4 MCLK Input Amplitude 5 V typ Input Capacitance 7.3 pF typ Input Leakage Current ±5 μA max Three-State Leakage Current (D15:D0) ±5 μA max V 0.7 × V V min INH DRIVE V 0.3 × V V max INL DRIVE 5 V 1.5 V min OH 6 VOH 2.4 V typ 4 VOL 0.1 V max 1 See the Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Current scales with ICLK frequency. See the Typical Performance Characteristics section. 4 Although the AD7760 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 5 Tested using the minimum VDRIVE voltage of 1.65 V with a 400 μA load current. 6 Tested using V = 2.5 V with a 400 μA load current. DRIVE Rev. A | Page 5 of 36 AD7760 TIMING SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description f 1 MHz min Applied master clock frequency MCLK 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max 1, 2 t 0.5 × t typ DRDY pulse width 1 ICLK t 10 ns min DRDY falling edge to CS falling edge 2 t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t t min CS high pulse width between reads 6 ICLK t 3 ns min RD/WR hold time to CS rising edge 7 t 11 ns max Bus relinquish time 8 2 t9 0.5 × tICLK typ DRDY high period 2 t10 0.5 × tICLK typ DRDY low period t11 (0.5 × tICLK) + 16 ns max Data access time 3, 4 t 23 ns min Data valid prior to DRDY rising edge 12 3, 4 t 19 ns min Data valid after DRDY rising edge 13 t 11 ns max Bus relinquish time 14 t15 4 × tICLK min CS low write pulse width t16 4 × tICLK min CS high period between address and data t17 5 ns min Data setup time t 0 ns min Data hold time 18 4, 5 t 23 ns min Data valid prior to MCLK falling edge while DRDY is logic low 19 4, 5 t20 19 ns min Data valid after MCLK falling edge while DRDY is logic low 1 t = 1/f . ICLK ICLK 2 DRDY When ICLK = MCLK, pulse width depends on the mark-space ratio of applied MCLK. 3 Valid when using the modulator output mode with CDIV = 1. 4 See the Modulator Data Output Mode section for timing diagrams. 5 CDIV Valid when using the modulator output mode with = 0. Rev. A | Page 6 of 36 AD7760 TIMING DIAGRAMS DRDY t t t 5 6 1 CS t 2 t 7 t 3 RD/WR t t 4 8 D[0:15] DATA MSW LSW + STATUS Figure 2. Filtered Output—Parallel Interface Timing Diagram CS t t 15 16 RD/WR t t 17 18 D[0:15] REGISTER ADDRESS REGISTER DATA Figure 3. AD7760 Register Write Rev. A | Page 7 of 36 04975-004 04975-002 AD7760 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameters Rating may cause permanent damage to the device. This is a stress AV 1 to GND −0.3 V to +3 V DD rating only; functional operation of the device at these or any AV 2:AV 4 to GND −0.3 V to +6 V DD DD other conditions above those listed in the operational sections DVDD to GND −0.3 V to +3 V of this specification is not implied. Exposure to absolute VDRIVE to GND −0.3 V to +3 V maximum rating conditions for extended periods may affect 1 VIN+, VIN– to GND −0.3 V to +6 V device reliability. 1 V A+, V A− to GND −0.3 V to +6 V IN IN 2 Digital Input Voltage to GND −0.3 V to DV + 0.3 V DD MCLK to MCLKGND −0.3 V to +6 V 3 ESD CAUTION VREF+ to GND −0.3 V to AVDD4 + 0.3 V AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except ±10 mA 4 Supplies Operating Temperature Range Commercial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TQFP Exposed Paddle Package θ Thermal Impedance 92.7°C/W JA θJC Thermal Impedance 5.1°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 600 V 1 Absolute maximum voltage for V −, V + and V −, V + is 6.0 V or AV 3 + 0.3 V, IN IN INA INA DD whichever is lower. 2 Absolute maximum voltage on digital inputs is 3.0 V or DV + 0.3 V, DD whichever is lower. 3 Absolute maximum voltage on V input is 6.0 V or AV 4 + 0.3 V, REF+ DD whichever is lower. 4 Transient currents of up to 200 mA do not cause SCR latch-up. Rev. A | Page 8 of 36 AD7760 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DGND DB12 PIN 1 2 47 MCLKGND DB13 3 46 MCLK DB14 4 45 AV 2 DB15 DD AGND2 5 44 V DRIVE AV 1 6 43 DGND DD AGND1 7 42 DGND AD7760 DECAPA 8 41 DV TOP VIEW DD (Not to Scale) REFGND 9 40 CS 10 39 V RD/WR REF+ 11 38 AGND4 DRDY 12 37 AV 4 RESET DD AGND2 13 36 SYNC AV 2 14 35 DGND DD AV 2 15 34 AGND1 DD 16 33 AGND2 AV 1 DD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 4. 64-Lead TQFP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 6, 33 AVDD1 2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 (Pin 7 and Pin 34, respectively) with 100 nF and 10 μF capacitors on each pin. See the Decoupling and Layout Recommendations section for details. 4, 14, 15, 27 AV 2 5 V Power Supply. These pins should be decoupled to AGND2 (Pin 5 and Pin 13, with 100 nF capacitors DD on each of Pin 4, Pin 14, and Pin 15). Pin 27 should be connected to Pin 14 via a 15 nH inductor. See the Decoupling and Layout Recommendations section for details. 24 AVDD3 3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to AGND3 (Pin 23) with a 100 nF capacitor. See the Decoupling and Layout Recommendations section for details. 12 AV 4 3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to Pin 9 with a 10 nF capacitor DD in series with a 10 Ω resistor. 7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AV 1. DD 5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AVDD2. 23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AVDD3. 11 AGND4 Power Supply Ground for Analog Circuitry Powered by AVDD4. 9 REFGND Reference Ground. Ground connection for the reference voltage. 41 DV 2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a 100 nF DD capacitor. 44, 63 VDRIVE Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating voltage of the logic interface. Both of these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a 100 nF capacitor. 1, 35, 42, 43, DGND Ground Reference for Digital Circuitry. 53, 62, 64 19 VINA+ Positive Input to Differential Amplifier. 20 VINA− Negative Input to Differential Amplifier. 21 VOUTA− Negative Output from Differential Amplifier. 22 VA+ Positive Output from Differential Amplifier. OUT 25 V + Positive Input to the Modulator. IN 26 V − Negative Input to the Modulator. IN 10 VREF+ Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See the Reference Voltage Filtering section for more details. 8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND. Rev. A | Page 9 of 36 DGND R BIAS V AGND2 DRIVE DGND V A+ IN DB0 V A– IN V A– DB1 OUT V A+ DB2 OUT DB3 AGND3 AV 3 DB4 DD V + DB5 IN DB6 V – IN DB7 AV 2 DD DGND AGND2 DB8 AGND3 DB9 DECAPB DB10 AGND3 DB11 AGND3 04975-005 AD7760 Pin No. Mnemonic Description 30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3. 17 RBIAS Bias Current Setting Pin. A resistor must be inserted between this pin and AGND. For more details, see the Bias Resistor Selection section. 45 to 52, DB15:DB8, 16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR 54 to 61 DB7:DB0 pin. The operating voltage for these pins is determined by the V voltage. See the Modulator Data DRIVE Output Mode and AD7760 Interface sections for more details. 37 RESET A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin low keeps the AD7760 in a reset state. 3 MCLK Master Clock Input. A low jitter, buffered digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the AD7760 section for more details. 2 MCLKGND Master Clock Ground Sensing Pin. 36 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. See the Synchronization section for more details. 39 RD/WR Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and from the AD7760. If this pin is low when CS is low, a read takes place. If this pin is high when CS is low, a write occurs. See the Modulator Data Output Mode and AD7760 Interface sections for more details. 38 DRDY Data Ready Output. Each time new conversion data is available, an active low pulse, ½ ICLK period wide, is produced on this pin. See the Modulator Data Output Mode and AD7760 Interface sections for more details. 40 CS Chip Select Input. Used in conjunction with the RD/WR pin to read and write data from and to the AD7760. See the Modulator Data Output Mode and AD7760 Interface sections for more details. Rev. A | Page 10 of 36 AD7760 TERMINOLOGY Signal-to-Noise Ratio (SNR) Integral Nonlinearity (INL) SNR is the ratio of the rms value of the actual input signal to the INL is the maximum deviation from a straight line passing rms sum of all other spectral components below the Nyquist through the endpoints of the ADC transfer function. frequency, excluding harmonics and dc. The value for SNR is Differential Nonlinearity (DNL) expressed in decibels. DNL is the difference between the measured and the ideal Total Harmonic Distortion (THD) 1 LSB change between any two adjacent codes in the ADC. THD is the ratio of the rms sum of harmonics to the fundamental. Zero Error For the AD7760, it is defined as Zero error is the difference between the ideal midscale input 2 2 2 2 2 V + V + V + V + V voltage (when both inputs are shorted together) and the actual 2 3 4 5 6 THD() dB = 20 log voltage producing the midscale output code. V 1 Zero Error Drift where: Zero error drift is the change in the actual zero error value due V is the rms amplitude of the fundamental. 1 to a temperature change of 1°C. It is expressed as a percentage V2, V3, V4, V5, and V6 are the rms amplitudes of the second to of full scale at room temperature. the sixth harmonics. Gain Error Nonharmonic Spurious-Free Dynamic Range (SFDR) The first transition (from 100 … 000 to 100 … 001) should SFDR is the ratio of the rms signal amplitude to the rms value occur for an analog voltage ½ LSB above the nominal negative of the peak spurious spectral component, excluding harmonics. full scale. The last transition (from 011 … 110 to 011 … 111) Dynamic Range should occur for an analog voltage 1½ LSB below the nominal Dynamic range is the ratio of the rms value of the full scale to full scale. The gain error is the deviation of the difference the rms noise measured with the inputs shorted together. The between the actual level of the last transition and the actual value for the dynamic range is expressed in decibels. level of the first transition, from the difference between the ideal levels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and Gain Error Drift fb, any active device with nonlinearities creates distortion products Gain error drift is the change in the actual gain error value due at sum and difference frequencies of mfa ± nfb, where m, n = 0, to a temperature change of 1°C. It is expressed as a percentage 1, 2, 3, and so on. Intermodulation distortion terms are those of full scale at room temperature. for which neither m nor n are equal to 0. For example, the second- order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7760 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Rev. A | Page 11 of 36 AD7760 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All FFTs are generated from 65,536 samples using a 7-term Blackman-Harris window. 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Normal Mode FFT, 1 kHz, −6 dB Input Tone, 256× Decimation Figure 9. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 4000 8000 12000 16000 20000 24000 0 4000 8000 12000 16000 20000 24000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation Figure 10. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation Rev. A | Page 12 of 36 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-007 04975-006 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-011 04975-010 04975-009 - 04975 008 AD7760 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 8× Decimation Figure 14. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 8× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 250 500 750 1000 0 250 500 750 1000 1250 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 8× Decimation Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 8× Decimation 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 13. Normal Mode FFT, 1 MHz, −0.5 dB Input Tone, 8× Decimation Figure 16. Low Power FFT, 1 MHz, −0.5 dB Input Tone, 8× Decimation Rev. A | Page 13 of 36 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-014 04975-013 04975-012 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-017 04975-015 04975-016 AD7760 0 0 –25 –25 –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 17. Normal Mode FFT, 1 MHz, −6 dB Input Tone, 8× Decimation Figure 20. Low Power FFT, 1 MHz, −6 dB Input Tone, 8× Decimation 0 0 TONE A: 999.75kHz TONE A: 999.75kHz –25 TONE B: 1.00025MHz –25 TONE B: 1.00025MHz –50 –50 –75 –75 –100 –100 –125 –125 –150 –150 –175 –175 –200 –200 0 250 500 750 1000 1250 0 250 500 750 1000 1250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 18. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation Figure 21. Low Power IMD, 1 MHz Center Frequency, 8× Decimation 0 0 TONE A: 999.75kHz TONE A: 999.75kHz –20 TONE B: 1.00025MHz –20 TONE B: 1.00025MHz SECOND-ORDER IMD: –105.6dB SECOND-ORDER IMD: –115.7dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 2000 4000 6000 8000 10000 0 2000 4000 6000 8000 10000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 19. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation Figure 22. Low Power IMD, 1 MHz Center Frequency, 8× Decimation Rev. A | Page 14 of 36 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-020 04975-019 04975-018 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 04975-023 04975-022 04975-021 AD7760 0 0 TONE A: 999.75kHz TONE A: 999.75kHz TONE B: 1.00025MHz TONE B: 1.00025MHz –20 –20 THIRD-ORDER THIRD-ORDER IMD: –89.15dB IMD: –87.67dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 995 997 999 1001 1003 1005 995 997 999 1001 1003 1005 FREQUENCY (kHz) FREQUENCY (kHz) Figure 23. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation Figure 26. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation 100.5 –105 NORMAL MODE 100.0 –107 99.5 NORMAL MODE –109 99.0 –111 98.5 98.0 –113 LOW POWER MODE LOW POWER MODE 97.5 –115 97.0 96.5 –117 04 10 20 300 04 10 20 300 MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz) Figure 24. SNR vs. MCLK Frequency, 8× Decimation, −6 dB, 1 kHz Input Tone Figure 27. THD vs. MCLK Frequency, 8× Decimation, −6 dB, 1 kHz Input Tone 120 116 –60dB –60dB –6dB 115 112 –6dB –0.5dB –0.5dB 110 108 105 104 100 100 95 96 0 64 128 192 256 0 64 128 192 256 DECIMATION RATE DECIMATION RATE Figure 25. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone Figure 28. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone Rev. A | Page 15 of 36 SNR (dBFS) SNR (dBFS) AMPLITUDE (dB) 04975-026 04975-025 04975-024 SNR (dBFS) THD (dBc) AMPLITUDE (dB) 04975-029 04975-028 04975-027 AD7760 4500 3000 4000 2500 3500 3000 2000 2500 1500 2000 1500 1000 1000 500 500 0 0 8385222 8385238 8385254 8385270 8383530 83835246 8383562 8383578 8383594 8383610 24-BIT CODE 24-BIT CODE Figure 29. Normal Mode, 24-Bit Histogram, 256× Decimation Figure 32. Low Power, 24-Bit Histogram, 256× Decimation 600 450 400 500 350 400 300 250 300 200 200 150 100 100 50 0 0 8385016 8385116 8385216 8385316 8385416 8385516 8383236 8383386 8383536 8383686 8383836 24-BIT CODE 24-BIT CODE Figure 30. Normal Mode, 24-Bit Histogram, 8× Decimation Figure 33. Low Power, 24-Bit Histogram, 8× Decimation 0.0010 0.0015 +85°C +85°C 0.0010 0.0005 0.0005 +25°C +25°C 0 0 –40°C –40°C –0.0005 –0.0005 –0.0010 –0.0010 0 4194304 8388608 12582912 16777216 0 4194304 8388608 12582912 16777216 24-BIT CODE 24-BIT CODE Figure 31. 24-Bit INL, Normal Mode Figure 34. 24-Bit INL, Low Power Mode Rev. A | Page 16 of 36 INL (%) OCCURRENCE OCCURRENCE 04975-034 04975-031 04975-030 INL (%) OCCURRENCE OCCURRENCE 04975-036 04975-033 04975-032 AD7760 0.6 50 45 0.4 40 35 0.2 30 0 25 20 –0.2 15 10 –0.4 5 –0.6 0 0 4194304 8388608 12582912 16777216 02 2 4 6 8 10 12 14 16 180 ICLK FREQUENCY (MHz) 24-BIT CODE Figure 38. Decimate × 32, DIDD vs. ICLK Frequency (DVDD = 2.5 V) Figure 35. 24-Bit DNL 45 40 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 0 0 02 2 4 6 8 10 12 14 16 180 02 2 4 6 8 10 12 14 16 180 ICLK FREQUENCY (MHz) ICLK FREQUENCY (MHz) Figure 39. Decimate × 256, DI vs. ICLK Frequency (DV = 2.5 V) Figure 36. AIDD2 vs. ICLK Frequency (AVDD2 = 5 V) DD DD 60 50 40 30 20 10 0 02 2 4 6 8 10 12 14 16 180 ICLK FREQUENCY (MHz) Figure 37. Decimate × 8, DI vs. ICLK Frequency (DV = 2.5 V) DD DD Rev. A | Page 17 of 36 DNL (LSB) DI (mA) AI 2 (mA) DD DD 04975-035 04975-058 04975-057 DI (mA) DI (mA) DD DD 04975-060 04975-059 AD7760 THEORY OF OPERATION The AD7760 employs a Σ-Δ conversion technique to convert The third filter has a fixed decimation rate of 2×, is user the analog input into an equivalent digital word. The modulator programmable, and has a default configuration. It is described samples the input waveform and outputs an equivalent digital in detail in the Programmable FIR Filter section. This filter can word to the digital filter at a rate equal to ICLK. also be bypassed. By employing oversampling, the quantization noise is spread Table 6 shows some characteristics of the default filter. The across a wide bandwidth from 0 to f . This means that the group delay of the filter is defined to be the delay to the center ICLK noise energy contained in the signal band of interest is reduced of the impulse response and is equal to the computation plus (see Figure 40a). To further reduce the quantization noise in the the filter delays. The delay until valid data is available (the signal band of interest, a high order modulator is employed to DVALID status bit is set) is equal to twice the filter delay plus shape the noise spectrum so that most of the noise energy is the computation delay. shifted out of the signal band (see Figure 40b). a. The digital filtering that follows the modulator removes the large out-of-band quantization noise (see Figure 40c) while also QUANTIZATION NOISE reducing the data rate from f at the input of the filter to ICLK f \2 ICLK f /8 or less at the output of the filter, depending on the BAND OF INTEREST ICLK decimation rate used. b. Digital filtering has certain advantages over analog filtering: It does not introduce significant noise or distortion and can be NOISE SHAPING made perfectly linear in terms of phase. f \2 ICLK The AD7760 employs three FIR filters in series. By using BAND OF INTEREST different combinations of decimation ratios, filter selection, c. and bypassing, data can be obtained from the AD7760 at a large range of data rates. Multibit data from the modulator can be DIGITAL FILTER CUTOFF FREQUENCY obtained at the ICLK rate (see Modulator Data Output Mode section). The first filter receives the data from the modulator at f \2 ICLK a maximum frequency of 20 MHz and decimates it by 4 to output BAND OF INTEREST Figure 40. Σ-Δ ADC the data at 5 MHz. The partially filtered data can be output at this stage. The second filter allows the decimation rate to be chosen from 2× to 32× or to be completely bypassed. Table 6. Configuration with Default Filter ICLK Computation Pass-Band Output Data Frequency Filter 1 Filter 2 Filter 3 Data State Delay Filter Delay Bandwidth Rate (ODR) 20 MHz Bypassed Bypassed Bypassed Unfiltered 0 0 10 MHz 20 MHz 20 MHz 4× Bypassed Bypassed Partially filtered 0.325 μs 1.2 μs 1.35 MHz 5 MHz 20 MHz 4× Bypassed 2× Fully filtered 1.075 μs 10.8 μs 1 MHz 2.5 MHz 20 MHz 4× 2× Bypassed Partially filtered 1.35 μs 3.6 μs 562.5 kHz 2.5 MHz 20 MHz 4× 2× 2× Fully filtered 1.625 μs 22.8 μs 500 kHz 1.25 MHz 20 MHz 4× 4× Bypassed Partially filtered 1.725 μs 6 μs 281.25 kHz 1.25 MHz 20 MHz 4× 4× 2× Fully filtered 1.775 μs 44.4 μs 250 kHz 625 kHz 20 MHz 4× 8x Bypassed Partially filtered 2.6 μs 10.8 μs 140.625 kHz 625 kHz 20 MHz 4× 8× 2× Fully filtered 2.25 μs 87.6 μs 125 kHz 312.5 kHz 20 MHz 4× 16× Bypassed Partially filtered 4.175 μs 20.4 μs 70.3125 kHz 312.5 kHz 20 MHz 4× 16× 2× Fully filtered 3.1 μs 174 μs 62.5 kHz 156.25 kHz 20 MHz 4× 32× Bypassed Partially filtered 7.325 μs 39.6 μs 35.156 kHz 156.25 kHz 20 MHz 4× 32× 2× Fully filtered 4.65 μs 346.8 μs 31.25 kHz 78.125 kHz 12.288 MHz 4× 8× 2× Fully filtered 3.66 μs 142.6 μs 76.8 kHz 192 kHz 12.288 MHz 4× 16× 2× Fully filtered 5.05 μs 283.2 μs 38.4 kHz 96 kHz 12.288 MHz 4× 32× Bypassed Partially filtered 11.92 μs 64.45 μs 21.6 kHz 96 kHz 12.288 MHz 4× 32× 2× Fully filtered 7.57 μs 564.5 μs 19.2 kHz 48 kHz Rev. A | Page 18 of 36 04975-037 AD7760 MODULATOR DATA OUTPUT MODE scaled to 15 bits. The transfer function in Figure 42 shows the Operating the AD7760 in modulator output mode enables the scaling involved for the 16 data bits output from Modulator output of data directly from the Σ-Δ modulator. This mode of Pins D[15:0] vs. the maximum differential voltage input operation bypasses the AD7760 on-board digital filtering allowed for the modulator inputs (VIN+ and VIN−). capabilities, outputting data in its unfiltered form. D[15:0] As discussed in the Theory of Operation section, the AD7760 +4.096V 0011 1111 1111 1111 operates using oversampling, which spreads quantization noise +3.275V = MODULATOR FULL SCALE = 80% OF +4.096V V + = 3.6855V IN 0011 0011 0011 0010 over a wide bandwidth. The decrease in the quantization noise V – = 0.4105V IN energy in the resulting signal band is illustrated in Figure 40a. By coupling the use of oversampling with the use of a high order, multibit Σ-Δ modulator, the AD7760 further reduces the quantization noise in the signal band. Figure 41 is an FFT of V +=2.048V IN 0000 0000 0000 0000 V – = 2.048V IN unfiltered data output from the AD7760 when it is used in modulator output mode. This clearly demonstrates the shaping of the quantization noise performed by the AD7760’s Σ-Δ modulator. V + = 0.4105V IN 1100 1100 1100 1100 80% OF +4.096V = MODULATOR FULL SCALE = –3.275V V – = 3.6855V IN MODULATOR INPUTS 1100 0000 0000 0000 –4.096V The maximum voltage input to each differential modulator Figure 42. Modulator Output Data Scaling input pin is 0.8 × 4.096 V ≈ 3.275 V (80% of V ), which must REF sit on a common mode of V /2. This maximum differential REF As the nature of the modulator output is coarse relative to input voltage is shown as the conditioned output of the AD7760’s the fully filtered output of the AD7760 (due to the associated on-board differential amplifier in Figure 52 in the Driving the quantization noise of the modulator output), Bits D[3:0] of the AD7760 section. modulator output are zero when operating in modulator data output mode. Thus, the data outputs for the calculations listed Further details on the signal conditioning implemented by the in Example 1 and Example 2 for inputs to the modulator pins AD7760’s on-board differential amplifier and the recommended VIN+ and VIN− show Bits D[3:0] of the modulator output as zero. external circuitry that accompanies it is described in the Driving the AD7760 section. Example 1 V + = 3.5 V IN 0 V − = 0.595 V –10 IN –20 Modulator Output Code = ([V (+) − V (−)]/4.096 V) × 16384 IN IN –30 = [(3.5 V − 0.595 V)/4.096 V] × 16384 –40 –50 = +11620 –60 Direct Scaling: [0010 1101 0110 0100] –70 Value Output on Data Output Pins D[15:0]: –80 –90 D [15:0] = [0010 1101 0110 0000]. –100 Example 2 –110 –120 VIN+ = 0.595 V –130 VIN− = 3.5 V –140 Modulator Output Code = ([VIN(+) − VIN(−)]/4.096 V) × 16384 –150 –160 = [(0.595 V − 3.5 V)/4.096 V] × 16384 01 12 34 567 890 = −11620 FREQUENCY (MHz) Direct Scaling: [1101 0010 1001 1100] Figure 41. FFT of Data Output by the AD7760 in Modulator Output Mode Value Output on Data Output Pins D[15:0]: MODULATOR DATA OUTPUT SCALING D [15:0] = [1101 0010 1001 0000]. In modulator output mode, data is output in a 16-bit twos complement format on Pins D [15:0]; however, this data is Rev. A | Page 19 of 36 AMPLITUDE (dB) 04975-048 04975-049 AD7760 MODULATOR DATA OUTPUT MODE INTERFACE output mode when operating with = 1 (that is, ICLK = CDIV The AD7760 can be configured in modulator data output mode MCLK). A DRDY pulse is generated for each word. The data on (bypassing the default decimation filtering) by writing 0 to each each of the 16 data output pins, D [15:0], is valid on the rising of the bits contained in Control Register 1: BYP F1, BYP F3, edge of the DRDY pulse. The DRDY pulse can be used to latch and DEC [2:0]. This will bypass all digital decimation filtering the modulator data into a FIFO or as a DMA control signal. Shortly offered by the AD7760. See the AD7760 Registers section for after the /WR and lines return high, the AD7760 stops further details. RD CS outputting data and the data bus returns to high impedance. When the AD7760 is operating in modulator data output mode, a different parallel interfacing scheme than that used for config- CLOCK DIVIDE-BY-2 MODE (CDIV = 0) urations, where the AD7760’s data output is filtered is necessary. When operating in modulator output mode with CDIV = 0 (that is, ICLK = MCLK/2), the frequency of the DRDY signal The data output rate depends on the clock divider ratio that is created is half that of the MCLK frequency input to the device. used. When the CDIV bit in Control Register 2 is set to logic The timing scheme that is used when CDIV = 0 depends on the CDIV high, data is output at the MCLK frequency. If the bit is RESET SYNC number of MCLK cycles that occur between and . set to logic low, data is output at a frequency of MCLK/2. See If the number of MCLK cycles (n) between the rising edge of the Clocking the AD7760 section. RESET SYNC and the rising edge of (see Figure 44) is an even CLOCK DIVIDE-BY-1 MODE (CDIV = 1) value, use the interface timing shown in Figure 43. If n is an odd When obtaining data from the AD7760 in modulator output value, use the interface timing shown in Figure 45. mode, both the RD/WR and CS lines must be held low. This brings the data bus out of its high impedance state. Figure 43 shows the timing diagram for reading data in the modulator data t t 9 10 DRDY t 13 CS, RD/WR t 14 t 12 t 11 D[0:15] INVALID DATA MOD DATA M MOD DATA M + 1 MOD D... Figure 43. AD7760 Modulator Output Mode (CDIV = 1) and (CDIV = 0, n is even) RESET MCLK n× t MCLK SYNC RESET SYNC CDIV Figure 44. AD7760 Relative Timing Between and in Modulator Output Mode = 0 Rev. A | Page 20 of 36 04975-050 04975-051 AD7760 t t 9 10 DRDY t 20 D[0:15] INVALID DATA MOD DATA M MOD DATA M + 1 MOD D... t 19 MCLK t 14 t 11 CS, RD/WR CDIV Figure 45. AD7760 Modulator Output Mode ( = 0, n is odd) In the case where n is an odd number of MCLK cycles, the 5. Write to Control Register 2 to power up the ADC and the modulator data output on Pins D [15:0] is output on the rising differential amplifier as required. The correct clock divider ( ) ratio should be programmed at this time. edge of DRDY. In this case, the modulator data should be read CDIV on the falling edge of MCLK when DRDY is logic low. Figure 45 BYP F1 6. Write to Control Register 1 to set the bypass filter bits, shows timing details to be used when reading the modulator BYP F3 and , and the decimation rate bits, DEC [2:0], to 0. output data where CDIV = 0 and there is an odd number of RESET MCLK cycles between the rising edge of and the rising 7. Wait a minimum of six MCLK cycles after the rising edge SYNC edge of . The edge of MCLK that should be used under of has been released. CS these conditions is illustrated in Figure 45 by arrows on the MCLK falling edges in question. 8. Take SYNC low for a minimum of four MCLK cycles, if required, to synchronize multiple parts. USING THE AD7760 IN MODULATOR OUTPUT MODE Using this sequence results in an even number of MCLK cycles between the rising edge of RESET and the rising edge of SYNC. The following is the recommended sequence for powering up Therefore, when using this sequence with = 0, the interface CDIV and using the AD7760: timing shown in Figure 43 should be implemented. 1. Apply power. Note that whether the number of MCLK cycles between the 2. Start the clock oscillator, applying MCLK. rising edge of RESET and SYNC is odd or even is irrelevant when the AD7760 is operated with = 1. CDIV 3. Take low for a minimum of one MCLK cycle. RESET When using the AD7760 in modulator output mode, the offset, 4. Wait a minimum of two MCLK cycles after the rising edge gain, and overrange registers are not operational. The only of RESET. registers that can be used are Control Register 1 and Control Register 2. Rev. A | Page 21 of 36 04975-052 AD7760 AD7760 INTERFACE READING DATA If multiple synchronized AD7760 parts that share a properly distributed common MCLK signal exist in a system, these parts When the AD7760 is outputting data at a 5 MHz output data can share a common bus without being isolated from each rate or less, the interface operates in a conventional mode, as other. This bus can then be isolated from the system bus by a shown in Figure 2, using a 16-bit bidirectional parallel interface. single latch or buffer. This interface is controlled by the /WR and pins. The 24-bit RD CS conversion data is output in twos complement format. When a SYNCHRONIZATION new conversion result is available, an active low pulse is output The SYNC input to the AD7760 provides a synchronization on the pin. DRDY function that allows the user to begin gathering samples of the analog front-end input from a known point in time. To read a conversion result from the AD7760, two 16-bit read operations are performed. The DRDY pulse indicates that a new SYNC The function allows multiple AD7760s, operated from conversion result is available. Both /WR and go low to RD CS RESET SYNC the same MCLK, , and signals, to be synchronized perform the first read operation. Shortly after both lines go low, so that each ADC simultaneously updates its output register. the data bus becomes active and the 16 most significant bits The distribution of the signals that are common to each of the (MSBs) of the conversion result are output. The /WR and RD CS devices that are to be synchronized is extremely important in lines must return high for a full ICLK period before the second ensuring that the timing of each of the AD7760 devices is read is performed. This second read contains the eight least correct, that is, that each AD7760 device sees the same digital significant bits (LSBs) of the conversion result along with six edges synchronously. status bits. These status bits are shown in Table 7. Descriptions of the other status bits are found in Table 17. SYNC The signal is sensed on the falling edge of MCLK. On the SYNC first falling edge of MCLK after goes logic low, the digital Table 7. Status Bits During Data Read filter sequencer is reset to 0. The filter is held in a reset state until MSB LSB a falling edge of the MCLK senses SYNC logic high. The SYNC D7 D6 D5 D4 D3 D2 D1 D0 signal must remain logic low for a minimum of four MCLK DVALID OVR UFILT LPWR FILTOK DLOK 0 0 cycles. Figure 46 shows the recommended timing for the SYNC Shortly after RD/WR and CS return high, the data bus returns signal with respect to MCLK. to a high impedance state. Both read operations must be DEVICE SYNCHRONIZED completed before a new conversion result is available because FROM THIS POINT IN TIME the new result overwrites the contents of the output register. If a DRDY pulse occurs during a read operation, the data read MCLK is invalid. MINSYNCLOGICLOW 4× t MCLK SYNC READING STATUS AND OTHER REGISTERS Figure 46. Recommended SYNC Timing The AD7760 features a number of programmable registers. To read back the contents of these registers or the status register, The rising edge of SYNC should be coincident with the rising the user must first write to the control register of the device, edge of MCLK. Thus, the next falling edge of MCLK senses setting a bit that corresponds to the register to be read. The next SYNC logic high and takes the filter out of its reset state. By read operation outputs the contents of the selected register applying this signal scheme to multiple ADCs using the same instead of a conversion result. The AD7760 Registers section SYNC MCLK and signals, all of the devices will gather input provides more information on the relevant bits in the control samples synchronously. register. SYNC SHARING THE PARALLEL BUS Following a signal, the digital filter needs time to settle before valid data can be read from the AD7760. The DVALID By its nature, the high accuracy of the AD7760 makes it status bit (D7 in Table 7) output with each conversion indicates sensitive to external noise sources. These include digital activity when valid data is being output by the converter. The time from on the parallel bus. For this reason, it is recommended that the the rising edge of SYNC until the DVALID bit is asserted is AD7760 data lines be isolated from the system data bus by dependent on the filter configuration used. See the Theory of means of a latch or buffer to ensure all digital activity on the Operation section and the values listed in Table 6 for details on D0 to D15 pins is controlled by the AD7760. calculating the time until DVALID is asserted. Rev. A | Page 22 of 36 04975-053 AD7760 Figure 3 shows a write operation to the AD7760. The /WR RD WRITING TO THE AD7760 line is held high while the CS line is brought low for a minimum There are many features and parameters that the user can of four ICLK periods. The register address is latched during this change by writing to the AD7760 device. See the Using the period. The line is brought high again for a minimum of CS AD7760 section, which details the writing sequence needed to four ICLK periods before the register data is put onto the data initialize the operation of the part. bus. If a read operation occurs between the writing of the The AD7760 has programmable registers that are 16 bits wide. register address and the register data, the register address is This means that two write operations are required to program a cleared and the next write must be the register address. This register. The first write contains the register address, and the also provides a method to revert back to a known situation if second write contains the register data. An exception is when a the user forgets whether the next write is an address or data. user-defined filter is being downloaded to the AD7760. This is Generally, the AD7760 is written to and configured on power- described in detail in the Downloading a User-Defined Filter up and very infrequently, if at all, after that. Following any write section. The AD7760 Registers section contains the register operation, the full group delay of the filter must elapse before addresses and details. valid data is output from the AD7760. Rev. A | Page 23 of 36 AD7760 CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source. This MCLK JITTER REQUIREMENTS signal is applied to the MCLK pin, and the MCLKGND pin is The MCLK jitter requirements depend on a number of factors used to sense the ground from the clock source. An internal and are given by clock signal (ICLK) is derived from the MCLK input signal. The OSR ICLK controls all internal operations of the AD7760. The t = j(rms) SNR (dB) maximum ICLK frequency is 20 MHz, but due to an internal 2×π× f ×10 IN clock divider, a range of MCLK frequencies can be used. There 20 are two ways to generate the ICLK: where: ICLK = MCLK (CDIV = 1) OSR = oversampling ratio = fICLK/ODR. fIN = maximum input frequency. ICLK = MCLK/2 (CDIV = 0) SNR(dB) = target SNR. These options are selected from the control register (see the Example 1 AD7760 Registers section for more details). On power-up, the This example can be taken from Table 6, where: default is ICLK = MCLK/2 to ensure that the part can handle the maximum MCLK frequency of 40 MHz. For output data ODR = 2.5 MHz. rates equal to those used in audio systems, a 12.288 MHz ICLK fICLK = 20 MHz. frequency can be used. As shown in Table 6, output data rates of fIN (max) = 1 MHz. 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK SNR = 108 dB. frequency. As mentioned previously, this ICLK frequency can 8 t = = 1.79 ps be derived from different MCLK frequencies. j(rms) 6 5.4 2×π×10 ×10 It is recommended that the MCLK signal applied to the This is the maximum allowable clock jitter for a full-scale, AD7760 has a 50-50 mark-space ratio. When operating in clock 1 MHz input tone with the given ICLK and output data rate. divide-by-1 mode (that is, CDIV = 1), using higher mark-space ratios reduces the maximum MCLK frequency that can be Example 2 applied to the AD7760 yielding maximum performance. For Take a second example from Table 6, where: example, using a mark-space ratio of 60-40 (with CDIV = 1) ODR = 48 kHz. reduces the maximum MCLK frequency that will yield the f = 12.288 MHz. ICLK maximum INL and THD performance to 16 MHz. f (max) = 19.2 kHz. IN SNR = 120 dB. BUFFERING THE MCLK SIGNAL 256 The MCLK signal for the AD7760 must be buffered before t = = 133 ps j(rms) 3 6 2×π×19.2×10 ×10 being input to the MCLK pin on the AD7760 device. This can be done simply by routing the MCLK signal to both inputs of an The input amplitude also has an effect on these jitter figures. AND gate (see Figure 47). For example, if the input level was 3 dB below full-scale, the allowable jitter would be increased by a factor of √2, increasing The recommended buffer is the NC7SZ08M5, which is a two- the first example to 2.53 ps rms. This happens when the input AND gate from Fairchild Semiconductor. Using the buffer maximum slew rate is decreased by a reduction in amplitude. with a supply voltage of 5 V is advised to achieve optimum Figure 48 and Figure 49 illustrate this point, showing the performance from the AD7760. maximum slew rate of a sine wave of the same frequency but AD7760 with different amplitudes. MCLK 3 MCLK SOURCE NC7SZ08M5 (AND GATE) Figure 47. Buffering the MCLK Signal Using the NC7SZ08M5 AND Gate Rev. A | Page 24 of 36 04975-054 AD7760 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 Figure 48. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p Figure 49. Maximum Slew Rate of Sine Wave (with the Same Frequency as in Figure 48) with Amplitude of 1 V p-p Rev. A | Page 25 of 36 04975-038 04975-039 AD7760 DRIVING THE AD7760 signal to sit on the optimum common mode of VREF/2, in this The AD7760 has an on-chip differential amplifier that operates case 2.048 V. The signal is also scaled to give the maximum with a supply voltage (AVDD3) within the 3.15 V to 5.25 V range. allowable voltage swing with this reference value. This is For a 4.096 V reference, the supply voltage must be 5 V. calculated as 80% of VREF, that is, 0.8 × 4.096 V ≈ 3.275 V p-p To achieve the specified performance in normal mode, the on each input. differential amplifier should be configured as a first-order With a 4.096 V reference, a 5 V supply must be provided to the antialias filter, as shown in Figure 50. Any additional filtering reference buffer (AV 4). With a 2.5 V reference, a 3.3 V supply DD should be carried out in previous stages using low noise, high must be provided to AV 4. DD performance op amps, such as the AD8021. Figure 51 shows the transfer function in terms of the 24-bit Suitable component values for the first-order filter are listed in digital output codes (twos complement coding) of the AD7760 Table 8. Using the values in the table as an example yields a vs. the voltage signals VA and VB applied to the on-board 10 dB attenuation at the first alias point of 19 MHz. differential amplifier A1, as shown in Figure 52. C FB 24 BITS R 011…111 FB 011…110 R R IN M A V – IN 000…010 C A1 S R M B 000…001 V + IN AD7760 R IN 24-BIT 000…000 R OUTPUT FB 111…111 C 111…110 FB Figure 50. Differential Amplifier Configuration 100…001 100…000 Table 8. Normal Mode Component Values B= +2.5V A= 0V A= +2.5V VREF RIN RFB RM CS CFB A = –2.5V B= 0V B = –2.5V 4.096 V 1 kΩ 655 Ω 18 Ω 5.6 pF 33 pF Figure 51. Transfer Function for the AD7760 Filtered Output Where VA and VB are Inputs to the On-Board Differential Amplifier A1 Figure 52 shows the signal conditioning that occurs using the circuit shown in Figure 50 with a ±2.5 V input signal biased around ground and the component values and conditions listed in Table 8. The differential amplifier always biases the output +2.5V +3.685V V + IN 0V +2.048V A –2.5V +0.410V +2.5V +3.685V B V – IN 0V +2.048V –2.5V +0.410V INPUTS TO THE AD7760 DIFFERENTIAL AMPLIFIER OUTPUTS OF THE AD7760 DIFFERENTIAL AMPLIFIER Figure 52. Differential Amplifier Signal Conditioning Rev. A | Page 26 of 36 04975-040 04975-055 04975-056 AD7760 To obtain maximum performance from the AD7760, it is USING THE AD7760 advisable to drive the ADC with differential signals. Figure 53 The following is the recommended sequence for powering up shows how a bipolar, single-ended signal biased around ground and using the AD7760: can drive the AD7760 with the use of an external op amp, such 1. Apply power. as the AD8021. C FB 2. Start the clock oscillator, applying MCLK. 2R R FB 3. Take low for a minimum of one MCLK cycle. RESET 2R V IN R R IN M 4. Wait a minimum of two MCLK cycles after RESET has AD8021 V – IN been released. C A1 S R M R V + IN 5. Write to Control Register 2 to power up the ADC and the R R IN FB differential amplifier as required. The correct clock divider (CDIV) ratio should be programmed at this time. C FB 6. Write to Control Register 1 to set the output data rate. Figure 53. Single-Ended-to-Differential Conversion 7. Wait a minimum of five MCLK cycles after has been CS The AD7760 employs a double-sampling front end, as shown in released. Figure 54. For simplicity, only the equivalent input circuit for V + IN is shown. The equivalent input circuitry for V − is the same. IN 8. Take SYNC low for a minimum of four MCLK cycles, if V + required, to synchronize multiple parts. IN CS1 SS1 SH3 Data can then be read from the part using the default filter, CPA SH1 SS3 CPB1 offset, gain, and overrange threshold values. The conversion ANALOG data read is not valid, however, until the group delay of the filter MODULATOR has elapsed. Once this has occurred, the DVALID bit read with the data LSW is set, indicating that the data is indeed valid. CS2 SS2 The user can then download a different filter if required (see the SH4 SS4 SH2 Downloading a User-Defined Filter section). Values for gain, CPB2 offset, and overrange threshold registers can be written or read at this stage. Figure 54. Equivalent Input Circuit Sampling Switches SS1 and SS3 are driven by ICLK, whereas Sampling Switches SS2 and SS4 are driven by . When ICLK is ICLK high, the analog input voltage is connected to CS1. On the falling edge of ICLK, the SS1 and SS3 switches open and the analog input is sampled on CS1. Similarly, when ICLK is low, the analog input voltage is connected to CS2. On the rising edge of ICLK, the SS2 and SS4 switches open and the analog input is sampled on CS2. Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances that include the junction capacitances associated with the MOS switches. Table 9. Equivalent Component Values Mode CS1 (pF) CS2 (pF) CPA (pF) CPB1/2 (pF) Normal 51 51 12 20 Low Power 13 13 12 5 Rev. A | Page 27 of 36 04975-043 04975-042 AD7760 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet. Figure 55 shows a simplified connection diagram for the AD7760. U2 DB [0:15] 19 61 DB0 V A+ V A+ DB0 IN IN 20 60 DB1 V A– V A– DB1 IN IN 21 59 DB2 V A– V A– DB2 OUT OUT 58 22 DB3 V A+ V A+ DB3 OUT OUT 57 DB4 DB4 56 DB5 DB5 8 55 DB6 DECAPA DB6 30 54 DB7 DECAPB DB7 52 DB8 DB8 51 DB9 DB9 25 50 DB10 V + V + DB10 IN IN 49 C7 C64 26 DB11 V – V – DB11 IN IN 100nF 33pF 48 DB12 DB12 AD7760BSV 47 DB13 DB13 10 46 DB14 V V DB14 REFX REF+ 9 45 DB15 REFGND DB15 17 40 R CS CS BIAS 39 RD/WR RD/WR 1 DGND 35 37 DGND RESET RESET 42 36 DGND SYNC SYNC 43 38 DGND DRDY DRDY 53 R19 DGND 3 62 160kΩ DGND MCLK MCLK 64 2 DGND MCLKGND AV 2 AV 4 AV 1 AV 3 V DV DD DD DD DD DRIVE DD PIN 12 L4 (VBUF) L1 L3 L2 L5 L11 L6 L7 L12 L8 PIN 41 PIN 4 PIN 15 PIN 14 PIN 5 PIN 33 PIN 24 PIN 44 PIN 63 (RHS) (VBIAS) (LHS) L9 PIN 27 (VMOD1) (VMOD2) (VDIF1) (VDRV1) (VDRV2) (DV ) DD R38 10Ω C48 C50 C62 C59 C52 C53 C54 C56 C57 C58 100nF 100nF 100nF 10nF 100nF 100nF 100nF 100nF 100nF 100nF Figure 55. Simplified Connection Diagram Rev. A | Page 28 of 36 7 AGND1 34 4 AGND1 AV 2 PIN 4 DD 14 AV 2 PIN 14 DD 15 AV 2 PIN 15 DD 5 AGND2 13 12 AGND2 AV 4 PIN 12 DD 16 AGND2 18 6 AGND2 AV 1 PIN 6 DD 28 33 AGND2 AV 1 PIN 33 DD 24 AV 3 PIN 24 DD 23 27 AGND3 AV 2 PIN 27 DD 29 AGND3 31 44 AGND3 V PIN 44 DRIVE 32 63 AGND3 V PIN 63 DRIVE 11 41 AGND4 DV PIN 41 DD 04975-046 AD7760 SUPPLY DECOUPLING BIAS RESISTOR SELECTION Every supply pin must be connected to the appropriate supply The AD7760 requires a resistor to be connected between the via a ferrite bead and decoupled to the correct ground pin with RBIAS and AGND pins. The value of this resistor is dependent a 100 nF, 0603 case size, X7R dielectric capacitor. There are two on the reference voltage being applied to the device. The resistor exceptions to this: value should be selected to produce a current of 25 μA through the resistor to ground. For a 2.5 V reference voltage, the correct • Pin 12 (AV 4) must have a 10 Ω resistor inserted between DD resistor value is 100 kΩ, and for a 4.096 V reference, the correct the pin and a 10 nF decoupling capacitor, which is resistor value is 160 kΩ. connected to ground at Pin 9. LAYOUT CONSIDERATIONS • Pin 27 (AV 2) does not require a separate decoupling DD While using the correct components is essential to achieve capacitor or a direct connection to the supply, but instead optimum performance, the correct layout is just as important. is connected to Pin 14 via a 15 nH inductor. The AD7760 product page on the Analog Devices website contains the Gerber files for the AD7760 evaluation board. ADDITIONAL DECOUPLING These files should be used as a reference when designing any There are two other decoupling pins on the AD7760—Pin 8 system using the AD7760. (DECAPA) and Pin 30 (DECAPB). Pin 8 should be decoupled with a 100 nF capacitor, and Pin 30 requires a 33 pF capacitor. The location and orientation of some of the components mentioned in previous sections of this data sheet are critical, REFERENCE VOLTAGE FILTERING and particular attention must be paid to the components that A low noise reference source, such as the ADR431 (2.5 V) or are located close to the AD7760. Locating these components ADR434 (4.096 V), is suitable for use with the AD7760. The farther away from the device can have a direct impact on the reference voltage supplied to the AD7760 should be decoupled achievable maximum performance. and filtered as shown in Figure 56. The use of ground planes should also be carefully considered. The recommended scheme for the reference voltage supply is a To ensure that the return currents through the decoupling 100 Ω series resistor connected to a 100 μF tantalum capacitor, capacitors are flowing to the correct ground pin, the ground side followed by a series resistor of 10 Ω, and finally a 10 nF capacitor of the capacitors should be as close as possible to the ground pin placed as close as possible to the V pin, decoupling this REF+ associated with that supply. A ground plane should not be relied capacitor to the associated ground pin, Pin 11. on as the sole return path for decoupling capacitors because the U3 return current path using ground planes is not easily predictable. R30 R17 ADR434 100Ω 10Ω 2 6 7.5V V V PIN 10 EXPOSED PADDLE IN OUT + + GND C15 C9 C11 C46 The AD7760 64-lead TQFP employs a 6 mm × 6 mm exposed 10µF 100nF 4 100µF 10nF paddle (see Figure 59). The paddle reduces the thermal resistance of the package by providing a path for heat energy to Figure 56. Reference Connection flow between the package and the PCB and, in turn, increases the heat transfer efficiency from the AD7760 package. DIFFERENTIAL AMPLIFIER COMPONENTS Connecting the exposed paddle to the AGND plane of the PCB The correct components for use around the on-chip differential is essential in creating the conditions that allow the AD7760 amplifier are detailed in Table 8. Matching the components on package to perform to the highest specifications possible. The both sides of the differential amplifier is important to minimize exposed paddle should not be connected directly to any of the distortion of the signal applied to the amplifier. A tolerance of ground pins on the AD7760 and should only be connected to 0.1% or better is required for these components. Symmetrical the analog ground plane. Best practice is to use multiple vias routing of the tracks on both sides of the differential amplifier connecting the exposed paddle to the AGND plane of the PCB. also assists in achieving the stated performance. Rev. A | Page 29 of 36 04975-047 AD7760 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7760 To create a filter, note the following: is user programmable. The default coefficients that are loaded • The filter must be an even, symmetrical FIR. upon reset are given in Table 10, and the frequency responses are shown in Figure 57. The frequencies quoted in Figure 57 • The coefficients are in sign-and-magnitude format, with scale directly with the output data rate. 26 magnitude bits and sign coded as positive = 0. Table 10. Default Filter Coefficients • The filter length must be between 12 taps and 96 taps in Dec Hex Dec Hex No. Value Value No. Value Value steps of 12. 0 53656736 332BCA0 24 700847 AB1AF • Because the filter is symmetrical, the number of 1 25142688 17FA5A0 25 −70922 401150A coefficients that must be downloaded is half the filter 2 −4497814 444A196 26 −583959 408E917 length. The default filter coefficients exemplify this with 3 −11935847 4B62067 27 −175934 402AF3E only 48 coefficients listed for a 96-tap filter. 4 −1313841 4140C31 28 388667 5EE3B 5 6976334 6A734E 29 294000 47C70 • Coefficients are written from the center of the impulse 6 3268059 31DDDB 30 −183250 402CBD2 response (adjacent to the point of symmetry) outwards. 7 −3794610 439E6B2 31 −302597 4049E05 8 −3747402 4392E4A 32 16034 3EA2 • The coefficients are scaled so that the in-band gain of the 9 1509849 1709D9 33 238315 3A2EB filter is equal to 134,217,726, with the coefficients rounded 10 3428088 344EF8 34 88266 158CA to the nearest integer. For a low-pass filter, this is the 11 80255 1397F 35 −143205 4022F65 equivalent of having the coefficients summed arithmetically 12 −2672124 428C5FC 36 −128919 401F797 (including sign) to a +67,108,863 (0x3FF FFFF) positive 13 −1056628 4101F74 37 51794 CA52 value over the half-impulse-response coefficient set (a 14 1741563 1A92FB 38 121875 1DC13 maximum of 48 coefficients). Any deviation from this 15 1502200 16EBF8 39 16426 402A introduces a gain error. 16 −835960 40CC178 40 −90524 401619C 0 PASS-BAND RIPPLE = 0.05dB 17 −1528400 4175250 41 −63899 400F99B –0.1dB FREQUENCY = 1.004MHz –3dB FREQUENCY = 1.06MHz –20 18 93626 16DBA 42 45234 B0B2 STOP BAND = 1.25MHz 19 1269502 135EFE 43 114720 1C020 –40 20 411245 6466D 44 102357 18FD5 –60 21 −864038 40D2F26 45 52669 CDBD 22 −664622 40A242E 46 15559 3CC7 –80 23 434489 6A139 47 1963 7AB –100 –120 The default filter should be sufficient for most applications. It is a standard brick wall filter with a symmetrical impulse response. –140 The default filter has a length of 96, is nonaliasing, and provides –160 120 dB of attenuation at Nyquist. This filter not only performs 0 500 1000 1500 2000 2500 FREQUENCY (kHz) signal antialiasing, but also suppresses out-of-band quantization Figure 57. Default Filter Frequency Response (2.5 MHz ODR) noise produced by the analog-to-digital conversion process. Any significant relaxation in the stop-band attenuation or transition The procedure for downloading a user-defined filter is detailed bandwidth relative to the default filter can result in a failure to in the Downloading a User-Defined Filter section. meet the SNR specifications. The default filter characteristics scale with both the MCLK frequency applied and the decimation rate chosen by the user. Rev. A | Page 30 of 36 AMPLITUDE (dB) 04975-044 AD7760 DOWNLOADING A USER-DEFINED FILTER As previously mentioned, the filter coefficients are 27 bits in EXAMPLE FILTER DOWNLOAD length—one sign and 26 magnitude bits. Because the AD7760 The following is an example of downloading a short user- has a 16-bit parallel bus, the coefficients are padded with 5 MSB defined filter with 24 taps. The frequency response is shown in 0s to generate a 32-bit word, split into two 16-bit words for Figure 58. downloading. The first 16-bit word for each coefficient becomes 10 (00000, sign bit, Magnitude [25:16]), whereas the second word 0 becomes (Magnitude [15:0]). To ensure that a filter is downloaded correctly, a checksum must also be generated and then downloaded –10 following the final coefficient. The checksum is a 16-bit word –20 generated by splitting each 32-bit word into four bytes and –30 summing the bytes from all coefficients up to a maximum of 192 bytes (48 coefficients × four bytes). The same checksum –40 is generated internally in the AD7760 and compared with the –50 downloaded checksum. The DL_OK bit in the status register is –60 set if these two checksums agree. –70 To download a user filter –80 06 100 200 300 400 50000 1. Write to Control Register 1, setting the DL_FILT bit and FREQUENCY (kHz) the correct filter length bits corresponding to the length of Figure 58. 24-Tap FIR Frequency Response the filter to be downloaded (see Table 11). The coefficients for the filter are listed in Table 12 and are 2. Write the first half of the current coefficient data shown from the center of symmetry outwards. The raw (00000, sign bit, Magnitude [25:16]). The first coefficient coefficients were generated using a commercial filter design to be written must be the one adjacent to the point of filter tool and were scaled appropriately so that their sum equals symmetry. 67,108,863 (0x3FF FFFF). 3. Write the second half of the current coefficient data Table 12. 24-Tap FIR Coefficients (Magnitude [15:0]). Coefficient Raw Scaled 1 0.365481974 53188232 4. Repeat Step 2 and Step 3 for each coefficient. 2 0.201339905 29300796 5. Write the 16-bit checksum. 3 0.009636604 1402406 4 −0.075708848 −11017834 6. Use the following methods to verify that the filter coefficients 5 −0.042856209 −6236822 are downloaded correctly: 6 0.019944246 2902466 7 0.036437914 5302774 a. Read the status register, checking the DL_OK bit. 8 0.007592007 1104856 b. Read data and observe the status of the DL_OK bit. 9 −0.021556583 −3137108 10 −0.024888355 −3621978 Note that because the user coefficients are stored in RAM, they 11 −0.012379538 −1801582 are cleared after a RESET operation or a loss of power. 12 −0.001905756 −277343 Table 11. Filter Length Values FLEN [3:0] Number of Coefficients Filter Length 0000 Default Default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96 Rev. A | Page 31 of 36 AMPLITUDE (dB) 04975-045 AD7760 Table 13 shows the hexadecimal values (in sign-and-magnitude Table 14 lists the 16-bit words the user would write to the format) that are downloaded to the AD7760 to realize this filter. AD7760 to set up the ADC and download this filter, assuming The table is also split into the bytes that are summed to produce an output data rate of 1.25 MHz has been selected. the checksum. The checksum generated from these coefficients Table 14. Sequence of Write Instructions to Set Up Device is 0x0E6B. and Download the Filter Example Table 13. Filter Hexadecimal Values Word Description Word 1 Word 2 0x0001 Address of Control Register 1. 0x8079 Control register data. DL filter: set filter length = 24, Coefficient Byte 1 Byte 2 Byte 3 Byte 4 set output data rate = 1.25 MHz. 1 03 2B 96 88 0x032B First coefficient, Word 1. 2 01 BF 18 3C 0x9688 First coefficient, Word 2. 3 00 15 66 26 0x01BF Second coefficient, Word 1. 4 04 A8 1E 6A 0x183C Second coefficient, Word 2. 5 04 5F 2A 96 … Other coefficients. 6 00 2C 49 C2 0x0404 Twelfth (final) coefficient, Word 1. 7 00 50 E9 F6 0x3B5F Final coefficient, Word 2. 8 00 10 DB D8 0x0E6B Checksum. Wait (0.5 × t × number of unused ICLK 9 04 2F DE 54 coefficients) for AD7760 to write 0s to the remaining 10 04 37 44 5A unused coefficients. 11 04 1B 7D 6E 0x0001 Address of control register. 12 04 04 3B 5F 0x0879 Control register data. Set read status and maintain filter length and decimation settings. Read contents of status register. Check Bit 7 (DL_OK) to determine if the filter was downloaded correctly. Rev. A | Page 32 of 36 AD7760 AD7760 REGISTERS The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are given in this section. CONTROL REGISTER 1—ADDRESS 0x0001 Default Value 0x001A MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DL_ RD RD RD RD 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3 BYP F1 DEC2 DEC1 DEC0 FILT OVR GAIN OFF STAT Table 15. Bit Descriptions of Control Register 1 Bit Mnemonic Description 1 15 DL_FILT Download Filter. Before downloading a user-defined filter, this bit must be set. The filter length bits must also be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the coefficients and the checksum have been written. 1, 2 14 RD OVR Read Overrange. If this bit has been set, the next read operation outputs the contents of the overrange threshold register instead of a conversion result. 1, 2 13 RD GAIN Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register. 1, 2 12 RD OFF Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register. 1, 2 11 RD STAT Read Status. If this bit has been set, the next read operation outputs the contents of the status register. 10 0 0 must be written to this bit. 1 9 SYNC Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple devices synchronizes all filters. 8 to 5 FLEN [3:0] Filter Length Bits. These bits must be set when the DL_FILT bit is set before a user-defined filter is downloaded. 4 Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed. BYP F3 3 BYP F1 Bypass Filter 1. If this bit is 0, Filter 1 is bypassed. This should only occur when the user requires unfiltered modulator data to be output. 2 to 0 DEC [2:0] Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1 corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on, up to the maximum value of 5, corresponding to 32× decimation. 1 Bit 15 to Bit 9 are self-clearing bits. 2 Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation. CONTROL REGISTER 2—ADDRESS 0x0002 RESET Default Value After : 0x009B Recommended register setting for power-up and normal operation using clock divide-by-2 (CDIV = 0) mode: 0x0002 MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CDIV 0 0 0 0 0 0 0 0 0 0 0 PD LPWR 1 D1PD Table 16. Bit Descriptions of Control Register 2 Bit Mnemonic Description 5 CDIV Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the MCLK by 2. If CDIV = 1, the ICLK frequency is equal to the MCLK. 3 PD Power Down. Setting this bit powers down the AD7760, reducing the power consumption to 6.35 mW. 2 LPWR Low Power. If this bit is set, the AD7760 is operating in a low power mode. The power consumption is reduced for a 6 dB reduction in noise performance. 1 1 Write 1 to this bit. 0 D1PD Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier. Rev. A | Page 33 of 36 AD7760 STATUS REGISTER (READ ONLY) MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BYP F3 BYP F1 PART 1 PART 0 DIE 2 DIE 1 DIE 0 0 LPWR OVR DL_OK FILTOK UFILT DEC2 DEC1 DEC0 Table 17. Bit Descriptions of Status Register Bit Mnemonic Comment 15, 14 PART [1:0] Part Number. These bits are constant for the AD7760. 13 to 11 DIE [2:0] Die Number. These bits reflect the current AD7760 die number for identification purposes within a system. 10 0 This bit is set to 0. 9 LPWR Low Power. If the AD7760 is operating in low power mode, this bit is set to 1. 8 OVR If the current analog input exceeds the current overrange threshold, this bit is set. 7 DL_OK When downloading a user filter to the AD7760, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. 6 FILTOK When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set. 5 UFILT If a user-defined filter is in use, this bit is set. 4 BYP F3 Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. 3 BYP F1 Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. 2 to 0 DEC [2:0] Decimation Rate. These bits correspond to the bits set in Control Register 1. OFFSET REGISTER—ADDRESS 0x0003 OVERRANGE REGISTER—ADDRESS 0x0005 Non-bit-mapped, Default Value 0x0000 Non-bit-mapped, Default Value 0xCCCC The offset register uses twos complement notation and is scaled The overrange register value is compared with the output of such that 0x7FFF (maximum positive value) and 0x8000 (max- the first decimation filter to obtain an overload indication with imum negative value) correspond to an offset of +0.78125% and minimum propagation delay. This is prior to any gain scaling −0.78125%, respectively. Offset correction is applied after any or offset adjustment. The default value is 0xCCCC, which gain correction. Using the default gain value of 1.25 and assuming corresponds to 80% of V (the maximum permitted analog REF a reference voltage of 4.096 V, the offset correction range is input voltage). Assuming V = 4.096 V, the bit is then set when REF approximately ±25 mV. the input voltage exceeds approximately 6.55 V p-p differential. Once the overrange bit is set, the DVALID bit in the status bits GAIN REGISTER—ADDRESS 0x0004 of the AD7760 ouptut is set to zero, providing another indication Non-bit-mapped, Default Value 0xA000 that an input overrange has occurred. Note that the overrange bit is set immediately if the analog input voltage exceeds 100% of The gain register is scaled such that 0x8000 corresponds to a V for more than four consecutive samples at the modulator rate. REF gain of 1.0. The default value of this register is 1.25 (0xA000). This results in a full-scale digital output when the input is at 80% of V , tying in with the maximum analog input range of REF ±80% of V p-p. REF Rev. A | Page 34 of 36 AD7760 OUTLINE DIMENSIONS 12.20 12.00 SQ 1.20 0.75 11.80 MAX 0.60 0.45 64 49 49 64 1 48 48 1 PIN 1 10.20 10.00 SQ TOP VIEW EXPOSED 6.00 (PINS DOWN) 9.80 PAD BSC SQ 0° MIN 1.05 0.20 1.00 BOTTOM VIEW 0.09 (PINS UP) 0.95 7° 16 16 33 33 3.5° 17 32 32 17 0.15 0° SEATING 0.05 0.08 MAX PLANE VIEW A 0.50 0.38 COPLANARITY BSC 0.32 LEAD PITCH 0.22 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD Figure 59. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7760BSVZ −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-64-2 1 AD7760BSVZ-REEL −40°C to +85°C 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-64-2 EVAL-AD7760EB Evaluation Board 1 Z = Pb-free part. Rev. A | Page 35 of 36 AD7760 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04975-0-8/06(A) Rev. A | Page 36 of 36