ANALOG DEVICES AD7739

8-Channel, High Throughput, ∑ 24-Bit -∆ ADC AD7739 FEATURES FUNCTIONAL BLOCK DIAGRAM High resolution ADC REFIN(–) REFIN(+) 24 bits no missing codes REFERENCE ±0.0015% nonlinearity AIN0 DETECT Optimized for fast channel switching AIN1 18-bit p-p resolution (21 bits effective) at 500 Hz AIN2 BUFFER 16-bit p-p resolution (19 bits effective) at 4 kHz AIN3 On-chip per channel system calibration 24-BIT MUX Σ-∆ ADC AIN4 Configurable inputs 8 single-ended or 4 fully differential AIN5 Input ranges AIN6 AD7739 +625 mV, ±625 mV, +1.25 V, ±1.25 V, +2.5 V, ±2.5 V AIN7 CS 3-wire serial interface SCLK CALIBRATION SERIAL SPI®, QSPI™, MICROWIRE™, and DSP compatible AINCOM/P0 CIRCUITRY INTERFACE DOUT Schmitt trigger on logic inputs DIN Single-supply operation 5 V analog supply RESET CLOCK CONTROL 3 V or 5 V digital supply I/O PORT GENERATOR LOGIC SYNC/P1 RDY Package: 24-lead TSSOP APPLICATIONS AGND AV MCLKOUT MCLKIN DGND DV DD DD 03742-0-001 PLCs/DCSs Figure 1. Multiplexing applications Process control The digital serial interface can be configured for 3-wire Industrial instrumentation operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. GENERAL DESCRIPTION The part is specified for operation over the extended industrial temperature range of –40°C to +105°C. The AD7739 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total Other parts in the AD7739 family are the AD7738, AD7734, conversion time of 250 µs (4 kHz channel switching), making it and AD7732. ideally suited to high resolution multiplexing applications. The AD7738 is similar to the AD7739 but has higher speed The part can be configured via a simple digital interface, which (8.5 kHz channel switching for 16-bit performance) and higher allows users to balance the noise performance against data AIN leakage current. The AD7738 multiplexer output is pinned throughput up to 15 kHz. out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the ADC. The analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mV, The AD7734 analog front end features four single-ended input 1.25 V, and 2.5 V input ranges. It accepts a common-mode input channels with unipolar or true bipolar input ranges to ±10 V voltage from 200 mV above AGND to AVDD – 300 mV. while operating from a single +5 V analog supply. The AD7734 accepts an analog input overvoltage to ±16.5 V without The differential reference input features “No-Reference” detect degrading the performance of the adjacent channels. capability. The ADC also supports per channel system calibration options. The AD7732 is similar to the AD7734, but its analog front end features two fully differential input channels. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7739 TABLE OF CONTENTS AD7739—Specifications.................................................................. 3 Digital Interface Description ........................................................ 22 Timing Specifications....................................................................... 6 Hardware ..................................................................................... 22 Absolute Maximum Ratings............................................................ 8 Reset ............................................................................................. 23 Typical Performance Characteristics ............................................. 9 Access the AD7739 Registers.................................................... 23 Output Noise and Resolution Specification................................ 10 Single Conversion and Reading Data ...................................... 23 Chopping Enabled...................................................................... 10 Dump Mode................................................................................ 23 Chopping Disabled..................................................................... 11 Continuous Conversion Mode ................................................. 24 Pin Configuration and Function Descriptions........................... 12 Continuous Read (Continuous Conversion) Mode .............. 25 Register Descriptions ..................................................................... 14 Circuit Description......................................................................... 26 Register Access............................................................................ 15 Analog Inputs.............................................................................. 26 Communications Register......................................................... 15 Sigma-Delta ADC....................................................................... 26 I/O Port Register......................................................................... 16 Chopping..................................................................................... 26 Revision Register ........................................................................ 16 Multiplexer, Conversion, and Data Output Timing............... 27 Test Register ................................................................................ 16 Frequency Response .................................................................. 28 ADC Status Register................................................................... 17 Analog Input’s Extended Voltage Range ................................. 29 Checksum Register..................................................................... 17 Voltage Reference Inputs........................................................... 29 ADC Zero-Scale Calibration Register ..................................... 17 Reference Detect......................................................................... 29 ADC Full-Scale Calibration Register....................................... 17 I/O Port........................................................................................ 29 Channel Data Registers ............................................................. 17 Calibration................................................................................... 30 Channel Zero-Scale Calibration Registers .............................. 18 ADC Zero-Scale Self-Calibration ........................................ 30 Channel Full-Scale Calibration Registers................................ 18 ADC Full-Scale Self-Calibration.......................................... 30 Channel Status Registers ........................................................... 18 Per Channel System Calibration .......................................... 30 Channel Setup Registers ............................................................ 19 Outline Dimensions ....................................................................... 32 Channel Conversion Time Registers ....................................... 20 ESD Caution................................................................................ 32 Mode Register ............................................................................. 20 Ordering Guide .......................................................................... 32 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7739 AD7739—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; REFIN(+) = 2.5 V; REFIN(–) = 0 V, AINCOM = 2.5 V; Internal Buffer On, AIN Range = ±1.25 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate 372 11840 Hz Configure via Conv. Time Register 1, 2 No Missing Codes 24 Bits FW ≥ 12 (Conversion Time ≥ 290 µs) Output Noise See Table 4 Resolution See Table 5 and Table 6 2 Integral Nonlinearity (INL) ±5 ±0.0015 % of FSR 3 Offset Error (Unipolar, Bipolar) ±10 µV Before Calibration 1 Offset Drift vs. Temperature ±25 nV/°C 3 Gain Error ±0.2 % Before Calibration 1 Gain Drift vs. Temperature ±2.5 ppm of FS/°C 3 Positive Full-Scale Error ±0.2 % of FSR Before Calibration 1 Positive Full-Scale Drift vs. Temp. ±2.5 ppm of FS/°C 4 Bipolar Negative Full-Scale Error ±0.0030 % of FSR After Calibration Common-Mode Rejection 80 95 dB At DC, AIN = 1 V Power Supply Rejection 70 80 dB At DC, AIN = 1 V ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate 737 15133 Hz Configure via Conv. Time Register 1, 2 No Missing Codes 24 Bits FW ≥ 12 (Conversion Time ≥ 290 µs) Output Noise See Table 7 Resolution See Table 8 and Table 9 2 Integral Nonlinearity (INL) ±0.0015 % of FSR 5 Offset Error (Unipolar, Bipolar) ±1mV mV Before Calibration Offset Drift vs. Temperature ±1.5 µV/°C 3 Gain Error ±0.2 % Before Calibration Gain Drift vs. Temperature ±2.5 ppm of FS/°C 3 Positive Full-Scale Error ±0.2 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp. ±2.5 ppm of FS/°C 4 Bipolar Negative Full-Scale Error ±0.0030 % of FSR After Calibration Common-Mode Rejection 75 dB At DC, AIN = 1 V Power Supply Rejection 65 dB At DC, AIN = 1 V ANALOG INPUTS 1, 6 Analog Input Voltage ±2.5 V Range ±2.5 V +2.5 V Range 0 to +2.5 V ±1.25 V Range ±1.25 V +1.25 V Range 0 to +1.25 V ±0.625 V Range ±0.625 V +0.625 V Range 0 to +0.625 V AIN, AINCOM Common-Mode/ 0.2 AVDD – 0.3 V 1 Absolute Voltage 1, 7 Analog Input Slew Rate 0.5 V/Conv. Time AIN Absolute Voltage > 3 V 1, 8 AIN, AINCOM Input Current 1 5 nA Only One Channel, Chop Disabled Rev. 0 | Page 3 of 32 AD7739 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS 1, 9 REFIN(+) to REFIN(–) Voltage 2.475 2.5 2.525 V NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register REFIN(+), REFIN(–) Common-Mode/ 0 AV V DD 1 Absolute Voltage 10 Reference Input DC Current 400 µA 1, 11 SYSTEM CALIBRATION Full-Scale Calibration Limit V +1.05 × FS Zero-Scale Calibration Limit V –1.05 × FS Input Span V 0.8 × FS 2.1 × FS LOGIC INPUTS Input Current µA ±1 Input Current CS µA CS = DV ±10 DD –40 µA CS = DGND, Internal Pull-Up Resistor Input Capacitance 5 pF 1 VT+ 1.4 2 V DVDD = 5 V 1 V 0.8 1.4 V DV = 5 V T– DD 1 V – V 0.3 0.85 V DV = 5 V T+ T– DD 1 V 0.95 2 V DV = 3 V T+ DD 1 VT– 0.4 1.1 V DVDD = 3 V 1 VT+ – VT– 0.3 0.85 V DVDD = 3 V MCLK IN ONLY Input Current µA ±10 Input Capacitance 5 pF V Input Low Voltage 0.8 V DV = 5 V INL DD V Input High Voltage 3.5 V DV = 5 V INH DD V Input Low Voltage 0.4 V DV = 3 V INL DD VINH Input High Voltage 2.5 V DVDD = 3 V 12 LOGIC OUTPUTS V Output Low Voltage 0.4 V I = 800 µA, DV = 5 V OL SINK DD VOH Output High Voltage 4.0 V ISOURCE = 200 µA, DVDD = 5 V VOL Output Low Voltage 0.4 V ISINK = 100 µA, DVDD = 3 V V Output High Voltage DV – 0.6 V I = 100 µA, DV = 3 V OH DD SOURCE DD Floating State Leakage Current µA ±1 Floating State Leakage Capacitance 3 pF P0, P1 INPUTS/OUTPUTS Levels Referenced to Analog Supplies Input Current µA ±10 VINL Input Low Voltage 0.8 V AVDD = 5 V VINH Input High Voltage 3.5 V AVDD = 5 V VOL Output Low Voltage 0.4 V ISINK = 8 mA, AVDD = 5 V V Output High Voltage 4.0 V I = 200 µA, AV = 5 V OH SOURCE DD Rev. 0 | Page 4 of 32 AD7739 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS AVDD to AGND Voltage 4.75 5.25 V DVDD to DGND Voltage 4.75 5.25 V 2.70 3.60 V AV Current (Normal Mode) 13.6 16 mA DD AV Current (Reduced Power Mode) 9.2 11 mA MCLK = 4 MHz DD AVDD Current (Internal Buffer Off) 8.5 mA 13 DVDD Current (Normal Mode) 2.7 3 mA DVDD = 5 V 13 DV Current (Normal Mode) 1.0 1.5 mA DV = 3 V DD DD 13 Power Dissipation (Normal Mode) 85 100 mW Power Dissipation 60 70 mW DV = 5 V, MCLK = 4 MHz DD 13 (Reduced Power Mode) Power Dissipation 50 mW DVDD = 3 V, MCLK = 4 MHz 13 (Reduced Power Mode) AV + DV Current 80 µA DD DD 14 (Standby Mode) 14 Power Dissipation (Standby Mode) 500 µW 1 Specification is not production tested, but is supported by characterization data at initial product release. 2 See Typical Performance Characteristics. 3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details. 7 For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V. 8 If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details. 9 For specified performance. Part is functional with lower V . REF 10 Dynamic current charging the sigma-delta modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DV , digital inputs = 0 V or DV , P0 and P1 = 0 V or AV . DD DD DD Rev. 0 | Page 5 of 32 AD7739 TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; 1 unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments Master Clock Range 1 6.144 MHz 1 4 MHz Reduced Power Mode t1 50 ns SYNC Pulsewidth t2 500 ns RESET Pulsewidth Read Operation t4 0 ns CS Falling Edge to SCLK Falling Edge Setup Time 2 t5 SCLK Falling Edge to Data Valid Delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DV of 2.7 V to 3.3 V DD 2, 3 t CS Falling Edge to Data Valid Delay 5A 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t6 50 ns SCLK High Pulsewidth t 50 ns SCLK Low Pulsewidth 7 t 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 8 4 t 10 80 ns Bus Relinquish Time after SCLK Rising Edge 9 Write Operation t 0 ns CS Falling Edge to SCLK Falling Edge Setup 11 t 30 ns Data Valid to SCLK Rising Edge Setup Time 12 t13 25 ns Data Valid after SCLK Rising Edge Hold Time t14 50 ns SCLK High Pulsewidth t 50 ns SCLK Low Pulsewidth 15 t 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 16 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. 2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 CS This specification is relevant only if goes low while SCLK is low. 4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Rev. 0 | Page 6 of 32 AD7739 CS t t 4 t 8 6 SCLK t 7 t 5 t t 9 5A DOUT MSB LSB 03742-0-002 Figure 2. Read Cycle Timing Diagram CS t t 11 t 16 14 SCLK t 15 t 12 t 13 DIN MSB LSB 03742-0-003 Figure 3. Write Cycle Timing Diagram I (800µA AT DV = 5V SINK DD 100µA AT DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA AT DV = 5V SOURCE DD 100µA AT DV = 3V) DD 03742-0-004 Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev. 0 | Page 7 of 32 AD7739 ABSOLUTE MAXIMUM RATINGS Table 3. (TA = 25°C, unless otherwise noted.) Parameter Rating AV to AGND, DV to DGND –0.3 V to +7 V DD DD AGND to DGND –0.3 V to +0.3 V AV to DV –5 V to +5 V DD DD AIN, AINCOM to AGND –0.3 V to AV + 0.3 V DD REFIN+, REFIN– to AGND –0.3 V to AVDD + 0.3 V P0, P1 Voltage to AGND –0.3 V to AV + 0.3 V DD Digital Input Voltage to DGND –0.3 V to DV + 0.3 V DD Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V ESD Rating (ESD Association Human Body Model, S5.1) 4000 V Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 128°C/W TSSOP Package θ Thermal Impedance JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 32 AD7739 TYPICAL PERFORMANCE CHARACTERISTICS 25 24 CHOP = 1 24 22 23 20 CHOP = 1 22 EFFECTIVE (rms) 18 21 p-p 16 20 14 19 12 18 10 17 16 8 0 24 68 10 121416 5 6 7 8 9 10 1112 1314 15 OUTPUT DATA RATE (kHz) 03742-0-008 FILTER WORD 03742-0-005 Figure 8. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V, Figure 5. No Missing Codes Performance, Chopping Enabled AIN Range ±1.25 V, Chopping Enabled, MCLK = 6.144 MHz 25 24 CHOP = 0 24 22 23 20 CHOP = 0 EFFECTIVE (rms) 22 18 p-p 21 16 20 14 19 12 18 10 17 16 8 5 6 7 8 9 10 1112 1314 15 0 24 68 10 121416 FILTER WORD OUTPUT DATA RATE (kHz) 03742-0-009 03742-0-006 Figure 9. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V, Figure 6. No Missing Codes Performance, Chopping Disabled AIN Range ±1.25 V, Chopping Disabled, MCLK = 6.144 MHz 0 120 CHOP = 1 –20 110 –40 THD = 110dB –60 100 –80 90 –100 –120 80 –140 70 –160 –180 60 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 0 200 400 600 800 1000 1200 1400 INPUT FREQUENCY (Hz) 03742-0-007 AIN DIFFERENTIAL VOLTAGE (V) 03742-0-010 Figure 7. Typical FFT Plot; Input Sine Wave 183 Hz,1.2 V Peak, AIN Range Figure 10. Typical Common-Mode Rejection vs. AIN Voltage; AIN Range ±1.25 V, Conversion Time 397 µs, Chopping Enabled, MCLK = 6.144 MHz ±1.25 V, Conversion Time 397 µs, Chopping Enabled, MCLK = 6.144 MHz Rev. 0 | Page 9 of 32 GAIN (dB) NO MISSING CODES NO MISSING CODES CMR (dB) RESOLUTION (bits) RESOLUTION (bits) AD7739 OUTPUT NOISE AND RESOLUTION SPECIFICATION Table 4 to Table 6 show the –3 dB frequencies and typical The AD7739 can be operated with chopping enabled or performance versus the channel conversion time and equivalent disabled, allowing the ADC to be programmed to optimize output data rate, respectively. either the offset drift performance or the throughput rate and channel switching time. Noise tables for these two primary Table 4 shows the typical output rms noise. Table 5 shows the modes of operation are outlined below for a selection of output typical effective resolution based on rms noise. Table 6 shows rates and settling times. the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The AD7739 noise performance depends on the selected The peak-to-peak resolutions are not calculated based on rms chopping mode, the filter word (FW) value, and the selected noise but on peak-to-peak noise. analog input range. The AD7739 noise will not vary significantly with MCLK frequency. These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input CHOPPING ENABLED voltage set to 0 V and MCLK = 6.144 MHz. The conversion The first mode, in which the AD7739 is configured with time is selected via the channel conversion time register. chopping enabled (CHOP = 1), provides very low noise with lower output rates. Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Conversion Output Data –3 dB Input Range / RMS Noise (µV) Time Time Rate Frequency ±2.5 V, +2.5 V ±1.25 V, +1.25 V, ±0.625 V, +0.625 V Register (µs) (Hz) (Hz) 127 0xFF 2689 372 200 1.8 1.1 46 0xAE 1001 999 500 2.7 1.7 17 0x91 397 2519 1325 4.8 2.7 10 0x8A 251 3982 2209 9.3 4.7 9 0x89 230 4342 2450 10.8 6.3 2 0x82 84 11838 9500 600 460 Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Conversion Output Data –3 dB Input Range / Effective Resolution (Bits) Time Time Rate Frequency ±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V Register (µs) (Hz) (Hz) 127 0xFF 2689 372 200 21.4 20.4 21.2 20.2 20.2 19.2 46 0xAE 1001 999 500 20.8 19.8 20.5 19.5 19.5 18.5 17 0x91 397 2519 1325 20.0 19.0 19.8 18.8 18.8 17.8 10 0x8A 251 3982 2209 19.0 18.0 19.0 18.0 18.0 17.0 9 0x89 230 4342 2450 18.8 17.8 18.6 17.6 17.6 16.6 2 0x82 84 11838 9500 12.9 11.9 12.4 11.4 11.4 10.4 Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Conversion Output Data –3 dB Input Range / Peak-to-Peak Resolution (Bits) Time Time Rate Frequency ±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V Register (µs) (Hz) (Hz) 127 0xFF 2689 372 200 18.6 17.6 18.3 17.3 17.3 16.3 46 0xAE 1001 999 500 17.9 16.9 17.6 16.6 16.6 15.6 17 0x91 397 2519 1325 17.1 16.1 16.9 15.9 15.9 14.9 10 0x8A 251 3982 2209 16.2 15.2 16.2 15.2 15.2 14.2 9 0x89 230 4342 2450 16.0 15.0 15.8 14.8 14.8 13.8 2 0x82 84 11838 9500 10.7 9.7 9.7 8.7 8.7 7.7 Rev. 0 | Page 10 of 32 AD7739 CHOPPING DISABLED Table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker The second mode, in which the AD7739 is configured with within a 6-sigma limit. The peak-to-peak resolutions are not chopping disabled (CHOP = 0), provides faster conversion time calculated based on rms noise but on peak-to-peak noise. while maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the channel These typical numbers are generated from 4096 data samples conversion time and equivalent output data rate, respectively. acquired in continuous conversion mode with an analog input Table 7 shows the typical output rms noise. Table 8 shows the voltage set to 0 V and MCLK = 6.144 MHz. The conversion typical effective resolution based on the rms noise. time is selected via the channel conversion time register. Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Conversion Output Data –3 dB Input Range / RMS Noise (µV) Time Time Rate Frequency ±2.5 V, +2.5 V ±1.25 V, +1.25 V, ±0.625 V, +0.625 V Register (µs) (Hz) (Hz) 127 0x7F 1358 737 675 2.4 1.5 92 0x5C 993 1007 950 3.0 1.8 35 0x23 399 2504 2500 4.5 2.7 16 0x10 201 4963 5400 6.9 4.1 12 0x0C 160 6257 7250 9.6 5.3 11 0x0B 149 6693 7900 11.4 6.9 3 0x03 66 15133 29000 200 90 Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Conversion Output Data –3 dB Input Range / Effective Resolution (Bits) Time Time Rate Frequency ±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V Register (µs) (Hz) (Hz) 127 0x7F 1358 737 675 21.0 20.0 20.6 19.6 19.6 18.6 92 0x5C 993 1007 950 20.7 19.7 20.4 19.4 19.4 18.4 35 0x23 399 2504 2500 20.1 19.1 19.8 18.8 18.8 17.8 16 0x10 201 4963 5400 19.4 18.4 19.2 18.2 18.2 17.2 12 0x0C 160 6257 7250 18.9 17.9 18.8 17.8 17.8 16.8 11 0x0B 149 6693 7900 18.8 17.8 18.5 17.5 17.5 16.5 3 0x03 66 15133 29000 14.6 13.6 14.7 13.7 13.7 12.7 Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Conversion Output Data –3 dB Input Range / Peak-to-Peak Resolution (Bits) Time Time Rate Frequency ±2.5 V +2.5 V ±1.25 V +1.25 V ±0.625 V +0.625 V Register (µs) (Hz) (Hz) 127 0x7F 1358 737 675 18.2 17.2 17.8 16.8 16.8 15.8 92 0x5C 993 1007 950 17.8 16.8 17.6 16.6 16.6 15.6 35 0x23 399 2504 2500 17.2 16.2 17.0 16.0 16.0 15.0 16 0x10 201 4963 5400 16.6 15.6 16.4 15.4 15.4 14.4 12 0x0C 160 6257 7250 16.1 15.1 16.0 15.0 15.0 14.0 11 0x0B 149 6693 7900 16.0 15.0 15.7 14.7 14.7 13.7 3 0x03 66 15133 29000 11.7 10.7 12.0 11.0 11.0 10.0 Rev. 0 | Page 11 of 32 AD7739 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REFIN(–) REFIN(+) REFERENCE DETECT AIN0 AIN1 BUFFER SCLK 1 24 DGND AIN2 2 24-BIT MCLKIN 23 DV DD AIN3 Σ-∆ ADC 3 MCLKOUT 22 DIN MUX AIN4 4 CS 21 DOUT 5 RESET 20 RDY AIN5 DV DD 6 AD7739 AV 19 AGND DD AD7739 AIN6 TOP VIEW 7 AINCOM/P0 18 REFIN(–) (Not to Scale) AIN7 8 SYNC/P1 17 REFIN(+) CS AIN7 9 16 AIN0 SCLK CALIBRATION SERIAL AINCOM/P0 CIRCUITRY INTERFACE 10 15 AIN6 AIN1 DOUT 11 14 DIN AIN5 AIN2 AV DD 12 13 AIN4 AIN3 03742-0-011 RESET CLOCK CONTROL I/O PORT GENERATOR LOGIC SYNC/P1 Figure 11. Pin Configuration (24-Lead TSSOP) RDY AGND AV MCLKOUT MCLKIN DGND DV DD DD 03742-0-012 Figure 12. Block Diagram Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7739. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be left unconnected. 3 MCLKOUT Master Clock Signal for the ADC. When the master clock for the device is a crystal/ resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLKOUT can drive one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AV Analog Positive Supply Voltage, 5 V to AGND Nominal. DD 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The function of this pin is determined by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7 (AIN0–AIN7) can be referenced to this pin’s voltage level. Rev. 0 | Page 12 of 32 AD7739 Pin No. Mnemonic Description 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the SYNC bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low. 9–16 AIN0–AIN7 Analog Inputs. 17 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. 18 REFIN(–) Negative Terminal of the Differential Reference Input. REFIN(–) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. 19 AGND Ground Reference Point for Analog Circuitry. 20 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available, according to the RDYFN bit in the I/O port register. In calibration mode, a falling edge on this output indicates that calibration is complete (see the Digital Interface Description section for details). 21 DOUT Serial Data Output. Serial data is read from the output shift register on the part. This output shift register can contain information from any AD7739 register, depending on the address bits of the communications register. 22 DIN Serial Data Input (Schmitt Triggered). Serial data is written to the input shift register on the part. Data from this input shift register is transferred to any AD7739 register, depending on the address bits of the communications register. 23 DV Digital Supply Voltage, 3 V or 5 V Nominal. DD 24 DGND Ground Reference Point for Digital Circuitry. Rev. 0 | Page 13 of 32 AD7739 REGISTER DESCRIPTIONS Table 11. Register Summary Register Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Default Value 0 R/W 6-Bit Register Address Communications 0x00 W P0 P1 P0 DIR P1 DIR RDYFN REDPWR 0 SYNC I/O Port 0x01 R/W P0 Pin P1 Pin 1 1 0 0 0 0 Chip Revision Code Chip Generic Code Revision 0x02 R x x x x 1 0 0 1 24-Bit Manufacturing Test Register Test 0x03 R/W RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 ADC Status 0x04 R 0 0 0 0 0 0 0 0 16-Bit Checksum Register Checksum 0x05 R/W 24-Bit ADC Zero-Scale Calibration Register ADC Zero-Scale Calibration 0x06 R/W 0x80 0000 24-Bit ADC Full-Scale Register ADC Full-Scale Calibration 0x07 R/W 0x80 0000 16-/24-Bit Data Registers 1 Channel Data 0x08–0x0F R 0x8000 24-Bit Channel Zero-Scale Calibration Registers 1 Channel Zero-Scale Cal. 0x10–0x17 R/W 0x80 0000 24-Bit Channel Full-Scale Calibration Registers 1 Channel Full-Scale Cal. 0x18–0x1F R/W 0x20 0000 CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR 1 Channel Status 0x20–0x27 R Channel Number 0 0 0 0 0 BUFOFF COM1 COM0 Stat OPT ENABLE RNG2 RNG1 RNG0 1 Channel Setup 0x28–0x2F R/W 0 0 0 0 0 0 0 0 CHOP FW (7-Bit Filter Word) 1 Channel Conversion Time 0x30–0x37 R/W 1 0x11 MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP 2 Mode 0x38–0x3F R/W 0 0 0 0 0 0 0 0 1 The three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the communications register, specify the channel number of the register being accessed. 2 The AD7739 has only one mode register, although the mode register can be accessed in one of eight address locations. The address used to write the mode register specifies the ADC channel on which the mode will be applied. Only address 0x38 must be used for reading from the mode register. Table 12. Operational Mode Summary Table 13. Input Range Summary MD2 MD1 MD0 Mode RNG2 RNG1 RNG0 Nominal Input Voltage Range 0 0 0 Idle 1 0 0 ±2.5 V 0 0 1 Continuous Conversion 1 0 1 +2.5 V 0 1 0 Single Conversion 0 0 0 ±1.25 V 0 1 1 Power-Down (Standby) 0 0 1 +1.25 V 1 0 0 ADC Zero-Scale Self-Calibration 0 1 0 ±0.625 V 1 0 1 ADC Full-Scale Self-Calibration (for 2.5 V) 0 1 1 +0.625 V 1 1 0 Channel Zero-Scale System Calibration 1 1 1 Channel Full-Scale System Calibration Rev. 0 | Page 14 of 32 AD7739 REGISTER ACCESS the communications register determines whether the subsequent operation will be a read or write and to which The AD7739 is configurable through a series of registers. Some register this operation will be directed. The digital interface of them configure and control general AD7739 features, while others are specific to each channel. The register data widths defaults to expect a write operation to the communications vary from 8 bits to 24 bits. All registers are accessed through the register after power-on, after reset, or after the subsequent read communications register, i.e., any communication to the or write operation to the selected register is complete. If the AD7739 must start with a write to the communications register interface sequence is lost, the part can be reset by writing at CS specifying which register will be subsequently read or written. least 32 serial clock cycles with DIN high and low. (Note that all of the parts, including the modulator, filter, interface, and all COMMUNICATIONS REGISTER registers are reset in this case.) Remember to keep DIN low 8 Bits, Write-Only Register, Address 0x00 while reading 32 bits or more either in continuous read mode or with the DUMP bit and 24/16 bit in the mode register set. All communications to the part must start with a write operation to the communications register. The data written to Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 R/W 6-Bit Register Address Bit Mnemonic Description 7 0 This bit must be 0 for proper operation. 6 R/W A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates that the next operation will be a read from a specified register. 5–0 Address These bits specify to which register the read or write operation will be directed. For channel specific registers, the three LSBs, i.e., Bit2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes to the mode register, the three LSBs specify the channel selected for the operation determined by the mode register value. The analog inputs configuration depends on the COM1 and COM0 bits in the channel setup register. Bit 2 Bit 1 Bit 0 Channel Single Input Differential Input 0 0 0 0 AIN0–AINCOM AIN0–AIN1 0 0 1 1 AIN1–AINCOM AIN2–AIN3 0 1 0 2 AIN2–AINCOM AIN4–AIN5 0 1 1 3 AIN3–AINCOM AIN6–AIN7 1 0 0 4 AIN4–AINCOM AIN0–AIN1 1 0 1 5 AIN5–AINCOM AIN2–AIN3 1 1 0 6 AIN6–AINCOM AIN4–AIN5 1 1 1 7 AIN7–AINCOM AIN6–AIN7 Rev. 0 | Page 15 of 32 AD7739 I/O PORT REGISTER 8 Bits, Read/Write Register, Address 0x01, Default Value 0x30 + Digital Input Value × 0x40 The bits in this register are used to configure and access the digital I/O port on the AD7739. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic P0 P1 P0 DIR P1 DIR RDYFN REDPWR 0 SYNC Default P0 Pin P1 Pin 1 1 0 0 0 0 Bit Mnemonic Description 7, 6 P0, P1 When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins’ output level. When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins. 5, 4 P0 DIR, P1 DIR These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the corresponding pin will be an input; when reset to 0, the corresponding pin will be an output. 3 RDYFN This bit is used to control the function of the RDY pin on the AD7739. When this bit is reset to 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will go low only if all enabled channels have unread data. 2 REDPWR Reduced Power. If this bit is set to 1, the AD7739 works in the reduced power mode. The maximum MCLK frequency is limited to 4 MHz in the reduced power mode. 1 0 This bit must be 0 for proper operation. 0 SYNC This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC bit is set to 1, the SYNC pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system. REVISION REGISTER 8 Bits, Read-Only Register, Address 0x02, Default Value 0x09 + Chip Revision × 0x10 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Chip Revision Code Chip Generic Code Default x x x x 1 0 0 1 Bit Mnemonic Description 7–4 Chip Revision Code 4-Bit Factory Chip Revision Code 3–0 Chip Generic Code On the AD7739, these bits will read back as 0x09. TEST REGISTER 24 Bits, Read/Write Register, Address 0x03 This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register. Rev. 0 | Page 16 of 32 AD7739 ADC STATUS REGISTER 8 Bits, Read-Only Register, Address 0x04, Default Value 0x00 In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. The bit is reset to 0 also when no read operation has taken place and the result of the next conversion is being updated to the channel data register. Writing to the mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0 bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 Default 0 0 0 0 0 0 0 0 CHECKSUM REGISTER CHANNEL DATA REGISTERS 16 Bits, Read/Write Register, Address 0x05 16 Bit/24 Bit, Read-Only Registers, Address 0x08–0x0F, Default Width 16 Bits, Default Value 0x8000 This register is described in the Using the AD7732/AD7734/ AD7738/AD7739 Checksum Register application note These registers contain the most up-to-date conversion results (www.analog.com/UploadedFiles/Application_Notes/71751876 corresponding to each analog input channel. The 16-bit or AN626_0.pdf). 24-bit data width can be configured by setting the 24/16 bit in the mode register. The relevant RDY bit in the channel status ADC ZERO-SCALE CALIBRATION REGISTER register goes high when the result is updated. The RDY bit will 24 Bits, Read/Write Register, Address 0x06, return low once the data register reading has begun. The RDY Default Value 0x80 0000 pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any This register holds the ADC zero-scale calibration coefficient. channel data register read operation is in progress when a new The value in this register is used in conjunction with the value result is updated, no update of the data register will occur. This in the ADC full-scale calibration register and the corresponding avoids having corrupted data. Reading the status registers can channel zero-scale and channel full-scale calibration registers to be associated with reading the data registers in the dump mode. scale digitally the conversion results of all channels. The value Reading the status registers is always associated with reading in this register is updated automatically following the execution the data registers in the continuous read mode (see the Digital of an ADC zero-scale self-calibration. Writing this register is Interface Description section for details). possible in the idle mode only (see the Calibration section for details). ADC FULL-SCALE CALIBRATION REGISTER 24 Bits, Read/Write Register, Address 0x07, Default Value 0x80 0000 This register holds the ADC full-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC zero-scale and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels. The value in this register is updated automatically following the execution of an ADC full-scale self-calibration. Writing this register is possible in the idle mode only. The ADC full-scale self-calibration should be used only on +2.5 V and ±2.5 V input voltage ranges (see the Calibration section for details). Rev. 0 | Page 17 of 32 AD7739 CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS 24 Bits, Read/Write Registers, Address 0x10–0x17, 24 Bits, Read/Write Registers, Address 0x18–0x1F, Default Value 0x80 0000 Default Value 0x20 0000 These registers hold the particular channel zero-scale These registers hold the particular channel full-scale calibration calibration coefficients. The value in these registers is used in coefficients. The value in these registers is used in conjunction conjunction with the value in the corresponding channel full- with the value in the corresponding channel zero-scale scale calibration register, the ADC zero-scale calibration calibration register, the ADC zero-scale calibration register, and register, and the ADC full-scale calibration register to digitally the ADC full-scale calibration register to digitally scale the scale the particular channel conversion results. The value in this particular channel conversion results. The value in this register register is updated automatically following the execution of a is updated automatically following the execution of a channel channel zero-scale system calibration. full-scale system calibration. Writing this register is possible in the idle mode only (see the Calibration section for details). The format of the channel zero-scale calibration register is a sign bit and a 22-bit unsigned value. Writing this register is possible in the idle mode only (see the Calibration section for details). CHANNEL STATUS REGISTERS 8 Bits, Read-Only Registers, Address 0x20–0x27, Default Value 0x20 × Channel Number These registers contain individual channel status information and some general AD7739 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for details). Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Default Channel Number 0 0 0 0 0 Bit Mnemonic Description 7–5 CH2–CH0 These bits reflect the channel number. This can be used for current channel identification and easier operation of the dump mode and continuous read mode. 4 0/P0 When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a 0. When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an input or an output. 3 RDY/P1 When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the state of the P1 pin, whether it is configured as an input or an output. 2 NOREF This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than NOREF, the trigger voltage, and a conversion is executed, then the NOREF bit goes to 1. 1 SIGN This bit reflects the voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage. 0 OVR This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage Range section). Rev. 0 | Page 18 of 32 AD7739 CHANNEL SETUP REGISTERS 8 Bits, Read/Write Registers, Address 0x28–0x2F, Default Value 0x00 These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic BUFOFF COM1 COM0 Stat OPT ENABLE RNG2 RNG1 RNG0 Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7 BUFOFF Buffer Off. If reset to 0, then the internal buffer is enabled. Operation only with the internal buffer enabled is recommended. 6–5 COM1, COM0 Analog inputs configuration: Channel COM1 COM0 COM1 COM0 0 0 1 1 0 AIN0–AINCOM AIN0–AIN1 1 AIN1–AINCOM AIN2–AIN3 2 AIN2–AINCOM AIN4–AIN5 3 AIN3–AINCOM AIN6–AIN7 4 AIN4–AINCOM AIN0–AIN1 5 AIN5–AINCOM AIN2–AIN3 6 AIN6–AINCOM AIN4–AIN5 7 AIN7–AINCOM AIN6–AIN7 4 Stat OPT Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register. 3 ENABLE Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single conversion will take place regardless of this bit’s value. 2–0 RNG2–RNG0 This is the channel input voltage range: RNG2 RNG1 RNG0 Nominal Input Voltage Range 1 0 0 ±2.5 V 1 0 1 +2.5 V 0 0 0 ±1.25 V 0 0 1 +1.25 V 0 1 0 ±0.625 V 0 1 1 +0.625 V Rev. 0 | Page 19 of 32 AD7739 CHANNEL CONVERSION TIME REGISTERS 8 Bits, Read/Write Registers, Address 0x30–0x37h, Default Value 0x91 The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CHOP FW (7-Bit Filter Word) Default 1 0x11 Bit Mnemonic Description 7 CHOP Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel. 6–0 FW CHOP = 1, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 128 + 262)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 1, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 128 + 263)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 0, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 64 + 213)/MCLK Frequency (MHz), the FW range is 3 to 127. CHOP = 0, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 64 + 214)/MCLK Frequency (MHz), the FW range is 3 to 127. MODE REGISTER 8 Bits, Read/Write Register, Address 0x38–0x3F, Default Value 0x00 The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. The AD7739 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. Only the address 0x38 must be used for reading from the mode register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7–5 MD2–MD0 Mode Bits. These three bits determine the AD7739 operation mode. Writing a new value to the mode bits will exit the part from the mode in which it has been operating and place it in the newly requested mode immediately. The function of the mode bits is described in more detail below. MD2 MD1 MD0 Mode Address Used for Mode Register Write Specifies: 0 0 0 Idle 0 0 1 Continuous Conversion First Channel to Start Converting 0 1 0 Single Conversion Channel to Convert 0 1 1 Power-Down (Standby) 1 0 0 ADC Zero-Scale Self-Calibration Conversion Time for Calibration 1 0 1 ADC Full-Scale Self-Calibration (for 2.5 V) Conversion Time for Calibration 1 1 0 Channel Zero-Scale System Calibration Channel to Calibrate 1 1 1 Channel Full-Scale System Calibration Channel to Calibrate Rev. 0 | Page 20 of 32 AD7739 Bit Mnemonic Description 4 CLKDIS Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7739 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7739 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7739 digital interface can still be accessed using the SCLK pin. 3 DUMP Dump Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communications register. The continuous read mode will always be dump mode reading the channel status and channel data registers, regardless of the DUMP bit value (see the Digital Interface Description section for details). 2 Cont RD When this bit is set to 1, the AD7739 will operate in the continuous read mode (see the Digital Interface Description section for details). 1 24/16 BIT Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide. When set to 0, the channel data registers will be 16 bits wide. 0 CLAMP This bit determines the channel data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the Analog Input’s Extended Voltage Range section). MD2 MD1 MD0 Operating Mode Description 0 0 0 Idle The default mode after power-on or reset. The AD7739 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 Continuous The AD7739 performs a conversion on the specified channel. After the conversion is complete, the Conversion relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers. 0 1 0 Single The AD7739 performs a conversion on the specified channel. After the conversion is complete, the Conversion relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 Power-Down The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7739 (Standby) digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not affected by the power-down (standby) mode. 1 0 0 ADC Zero-Scale A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is Self-Calibration complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode. 1 0 1 ADC Full-Scale A full-scale self-calibration is performed on an internally generated full-scale signal. After the Self-Calibration calibration is complete, the contents of the ADC full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode. 1 1 0 Channel Zero- A zero-scale system calibration is performed on the selected channel. An external system zero-scale Scale System voltage should be provided at the AD7739 analog input and this voltage should remain stable for the Calibration duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode. 1 1 1 Channel Full- A full-scale system calibration is performed on the selected channel. An external system full-scale Scale System voltage should be provided at the AD7739 analog input and this voltage should remain stable for the Calibration duration of the calibration. After the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode. Rev. 0 | Page 21 of 32 AD7739 DIGITAL INTERFACE DESCRIPTION HARDWARE The RESET pin can be used to reset the AD7739. When not used, connect this pin to DVDD. The AD7739 serial interface can be connected to the host device via the serial interface in several different ways. The AD7739 interface can be reduced to just two wires connecting the DIN and DOUT pins to a single bidirectional The pin can be used to select the AD7739 as one of several CS data line. The second signal in this 2-wire configuration is the circuits connected to the host serial interface. When CS is high, SCLK signal. The host system should change the data line the AD7739 ignores the SCLK and DIN signals and the DOUT direction with reference to the AD7739 timing specification pin goes to the high impedance state. When the signal is not CS (see the Bus Relinquish Time in Table 2). The AD7739 cannot used, connect the CS pin to DGND. operate in the continuous read mode in 2-wire serial interface configuration. The pin can be polled for high-to-low transition or can RDY drive the host device interrupt input to indicate that the All the digital interface inputs are Schmitt triggered; therefore, AD7739 has finished the selected operation and/or new data the AD7739 interface features higher noise immunity and can from the AD7739 is available. The host system can also wait a be easily isolated from the host system via optocouplers. designated time after a given command is written to the device Figure 13, Figure 14, and Figure 15 outline some of the possible before reading. Alternatively, the AD7739 status can be polled. host device interfaces: SPI without using the CS signal When the RDY pin is not used in the system, it should be left as (Figure 13), a DSP interface (Figure 14), and a 2-wire an open circuit. (Note that the pin is always an active RDY configuration (Figure 15). digital output, i.e., it never goes into a high impedance state.) DV DV DV DD DD DD AD7739 68HC11 AD7739 8xC51 SS RESET RESET SCK P3.1/TxD SCLK SCLK DOUT MISO DOUT P3.0/RxD MOSI DIN DIN INT RDY CS CS 03742-0-015 DGND 03742-0-013 DGND Figure 13. AD7739 to Host Device Interface, SPI Figure 15. AD7739 to Host Device Interface, 2-Wire Configuration DV DD AD7739 ADSP-2105 RESET SCLK SCLK CS DOUT DR SCLK DT DIN DIN INT RDY DOUT TFS CS WRITE READ COMMUNICATIONS ADC STATUS RFS REGISTER REGISTER 03742-0-016 03742-0-001 Figure 14. AD7739 to Host Device Interface, DSP Figure 16. Serial Interface Signals—Registers Access Rev. 0 | Page 22 of 32 AD7739 RESET SINGLE CONVERSION AND READING DATA The AD7739 can be reset by the RESET pin or by writing a reset When the mode register is being written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous sequence to the AD7739 serial interface. The reset sequence is N × 0 + 32 × 1, which could be the data sequence 0x00 + 0xFF + state. When the single conversion command is written to the 0xFF + 0xFF + 0xFF in a byte-oriented interface. mode register, the ADC starts the conversion on the channel selected by the address of the mode register. After the The AD7739 also features a power-on reset with a trip point conversion is completed, the data register is updated, the mode of 2 V and goes to the defined default state after power-on. register is changed to idle mode, the relevant RDY bit is set, and the RDY pin goes low. The RDY bit is reset and the RDY It is the system designer’s responsibility to prevent an unwanted pin returns high when the relevant channel data register is write operation to the AD7739. The unwanted write operation being read. could happen when a spurious clock appears on the SCLK while the pin is low. Note that if the AD7739 interface signals are CS Figure 17 shows the digital interface signals executing a single floating or undefined at system power-on, the part can be conversion on Channel 0, waiting for the RDY pin to go low, inadvertently configured into an unknown state. This could be and reading the Channel 0 data register. easily overcome by initiating either a hardware reset event or a 32 ones reset sequence as the first step in the system DUMP MODE configuration. When the DUMP bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel ACCESS THE AD7739 REGISTERS data register, regardless of whether the status or the data register All communications to the part start with a write operation to has been addressed through the communications register. The the communications register followed by either reading or DIN pin should not be high while reading 24-bit data in dump writing the addressed register. In a simultaneous read-write mode; otherwise, the AD7739 will be reset. interface (such as SPI), write 0 to the AD7739 while reading data. Figure 18 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin to go low, Figure 16 shows the AD7739 interface read sequence for the and reading the Channel 0 status register and data register in ADC status register. the dump mode. CS SCLK DIN 0x38 0x40 0x48 (0x00) (0x00) DOUT DATA DATA RDY WRITE WRITE CONVERSION TIME WRITE READ DATA REGISTER COMMUNICATIONS MODE COMMUNICATIONS REGISTER REGISTER REGISTER 03742-0-017 Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading CS SCLK DIN 0x38 0x48 0x48 (0x00) (0x00) (0x00) DOUT STATUS DATA DATA RDY WRITE WRITE CONVERSION TIME WRITE READ READ DATA COMMUNICATIONS MODE COMMUNICATIONS CHANNEL REGISTER REGISTER REGISTER REGISTER STATUS 03742-0-018 Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode Rev. 0 | Page 23 of 32 AD7739 CONTINUOUS CONVERSION MODE If an ADC conversion result has not been read before a new ADC conversion is completed, the new result will overwrite the When the mode register is being written, the ADC status byte is previous one. The relevant RDY bit goes low and the pin cleared and the RDY pin goes high, regardless of its previous RDY state. When the continuous conversion command is written to goes high for at least 163 MCLK cycles (~26.5 µs), indicating the mode register, the ADC starts conversion on the channel when the data register is updated, and the previous conversion selected by the address of the mode register. data is lost. After the conversion is complete, the relevant channel data If the data register is being read as an ADC conversion completes, the data register will not be updated with the new register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 result (to avoid data corruption) and the new conversion continues converting on the next enabled channel. The part will data is lost. cycle through all enabled channels until put into another mode Figure 19 shows the digital interface signal’s sequence for the or reset. The cycle period will be the sum of all enabled continuous conversion mode with Channels 0 and 1 enabled channels’ conversion times, set by the corresponding channel and the RDYFN bit set to 0. The RDY pin goes low and the data conversion time registers. register is read after each conversion. Figure 20 shows a similar The RDY bit is reset when the relevant channel data register is sequence but with the RDYFN bit set to 1. The RDY pin goes being read. The behavior of the RDY pin depends on the low and all data registers are read after all conversions are RDYFN bit in the I/O port register. When the RDYFN bit is 0, completed. Figure 21 shows the pin when no data is read RDY the pin goes low when any channel has unread data. When RDY from the AD7739. the RDYFN bit is set to 1, the RDY pin will go low only if all enabled channels have unread data. START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION 03742-0-019 Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0 START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION 03742-0-020 Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION 03742-0-021 Figure 21. Continuous Conversion, CH0 and CH1, No Data Read Rev. 0 | Page 24 of 32 AD7739 CONTINUOUS READ (CONTINUOUS CONVERSION) Note that the last completed conversion result is being read. MODE Therefore, the RDYFN bit in the I/O port register should be 0, and reading the result should always start before the next When the Cont RD bit in the mode register is set, the first write conversion is completed. of 0x48 to the communications register starts the continuous read mode. As shown in Figure 22, subsequent accesses to the The AD7739 will stay in continuous read mode as long as the part sequentially read the channel status and data registers of DIN pin is low while the CS pin is low; therefore, write 0 to the the last completed conversion without any further configuration AD7739 while reading in continuous read mode. To exit of the communications register being required. continuous read mode, take the DIN pin high for at least 100 ns Note that the continuous conversion bit in the mode register after a read is complete. (Write 0x80 to the AD7739 to exit should be set when entering the continuous read mode. continuous reading.) Note that the continuous read mode is a dump mode reading of Taking the DIN pin high does not change the Cont RD bit in the channel status and data registers regardless of the dump bit the mode register. Therefore, the next write of 0x48 starts the value. Use the channel bits in the channel status register to continuous read mode again. To completely stop the continuous check/recognize which channel data is actually being read mode, write to the mode register to clear the Cont RD bit. shifted out. CS SCLK DIN 0x38 0x48 0x48 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) DOUT STATUS DATA DATA STATUS DATA DATA RDY WRITE WRITE WRITE CONVERSION READ READ CONVERSION READ READ COMM. MODE COMM. ON CH0 CH0 CH0 ON CH1 CH1 CH1 REGISTER REGISTER REGISTER COMPLETE STATUS DATA COMPLETE STATUS DATA 03742-0-022 Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read Rev. 0 | Page 25 of 32 AD7739 CIRCUIT DESCRIPTION external input resistance. To avoid additional gain errors, offset The AD7739 is a high precision analog-to-digital converter that errors, and channel-to-channel crosstalk due to this effect, low is intended for the measurement of wide dynamic range, low resistor values should be used in the low-pass RC filter for the frequency signals in industrial process control, instrumentation, AD7739. The recommended low-pass RC filter for the analog and PLC systems. inputs is 100 Ω and 100 nF. It contains a multiplexer, an input buffer, a sigma-delta The average (dc) current, charging the capacitance on the (or charge balancing) ADC, a digital filter, a clock oscillator, multiplexer output, is related to the equation: a digital I/O port, and a serial communications interface. I ≈ CMUX × VMUX × FS ANALOG INPUTS The AD7739 has nine analog input pins connected to the ADC Where CMUX is the capacitance on the multiplexer output, through the internal multiplexer. The analog front end can be approximately 10 pF , VMUX is the voltage difference on the configured as eight single-ended inputs or four differential multiplexer output between two subsequent conversions, which inputs or any combination of these (via the channel setup can be up to 5 V, and F is the channel sampling frequency, S registers). which relates to the sum of conversion times on all subsequently sampled channels. The AD7739 contains a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of SIGMA-DELTA ADC a high speed sigma-delta modulator. With the internal buffer The AD7739 core consists of a charge balancing sigma-delta enabled, the analog inputs feature high input impedance. modulator and a digital filter. The architecture is optimized for fast, fully settled conversion. This allows for fast channel-to- If chopping is enabled or when switching between channels, channel switching while maintaining inherently excellent there is a dynamic current on analog inputs charging the linearity, high resolution, and low noise. internal capacitance of the multiplexer and input buffer. The capacitance is approximately 10 pF. CHOPPING With chopping enabled, the multiplexer repeatedly reverses the At the start of each conversion, there is a delay to allow the capacitance to be charged (see the Multiplexer, Conversion, and ADC inputs. Every output data result is then calculated as an Data Output Timing section). If the analog inputs resistive average of two conversions, the first with the positive and the source impedance does not exceed 50 kΩ, the internal second with the negative offset term included. This effectively capacitance is charged fast enough and the AD7739 removes any offset error of the input buffer and sigma-delta performance is not affected at the 16-bit level. modulator. Figure 23 shows the channel signal chain with chopping enabled. An external RC filter connected to the analog inputs would average the multiplexer channel-to-channel switching dynamic currents to a dc current leading to a dc voltage drop across the MULTIPLEXER BUFFER AIN(+) + SCALING OUTPUT DATA Σ-∆ DIGITAL DIGITAL ARITHMETIC AT THE SELECTED MODULATOR FILTER INTERFACE – AIN(–) (CALIBRATIONS) DATA RATE CHOP CHOP f /2 CHOP 03742-0-023 MCLK Figure 23. Channel Signal Chain Diagram with Chopping Enabled Rev. 0 | Page 26 of 32 AD7739 With chopping disabled (Figure 25), only one sampling time is MULTIPLEXER, CONVERSION, AND DATA preceded by a settling time of 43 MCLK or 44 MCLK cycles and OUTPUT TIMING followed by a scaling time of 163 MCLK cycles. The specified conversion time includes one or two settling and sampling periods and a scaling time. pin goes high during the scaling time, regardless of its The RDY previous state. The relevant RDY bit is set in the ADC status With chopping enabled (Figure 24), a conversion cycle starts register and in the channel status register, and the pin goes RDY with a settling time of 43 MCLK cycles or 44 MCLK cycles low when the channel data register is updated and the channel (~7 µs with a 6.144 MHz MCLK) to allow the circuits following conversion cycle is finished. If in continuous conversion mode, the multiplexer to settle. The sigma-delta modulator then the part will automatically continue with a conversion cycle on samples the analog signals and the digital filter processes the the next enabled channel. digital data stream. The sampling time depends on FW, i.e., on the channel conversion time register contents. After another Note that every channel can be configured independently for settling of 42 MCLK cycles (~6.8 µs), the sampling time is conversion time and chopping mode. The overall cycle and repeated with a reversed (chopped) analog input signal. Then, effective per channel data rates depend on all enabled during the scaling time of 163 MCLK cycles (~26.5 µs), the two channel settings. results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register. MULTIPLEXER – CHANNEL 0 + CHANNEL 1 – CHANNEL 1 RDY SETTLING SAMPLING SETTLING SAMPLING SCALING TIME TIME TIME TIME TIME CONVERSION TIME 03742-0-024 Figure 24. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled MULTIPLEXER CHANNEL 0 CHANNEL 1 RDY SETTLING SAMPLING SCALING TIME TIME TIME CONVERSION TIME 03742-0-025 Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled Rev. 0 | Page 27 of 32 AD7739 Preliminary Technical Data The typical ADC frequency response plots are given in FREQUENCY RESPONSE Figure 26 and Figure 27. The plots are normalized to 1/channel The sigma-delta modulator runs at ½ the MCLK frequency, conversion time. which is effectively the sampling frequency. Therefore, the modulator Nyquist frequency is ¼ of the MCLK. Note that these figures apply to each channel separately and are based on individual channel conversion time. The signal is If chopping is enabled, the input signal is resampled by effectively resampled once more in the multiplexer by switching chopping. Therefore, the overall frequency response features between enabled analog inputs. notches close to the frequency of 1/channel conversion time. 0 –20 –40 –60 CHOP = 1 –80 –100 –120 01 1 0 100 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY× CONVERSION TIME) 03742-0-026 Figure 26. Typical ADC Frequency Response, Chopping Enabled 0 –20 –40 –60 CHOP = 0 –80 –100 –120 01 10 100 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY× CONVERSION TIME) 03742-0-027 Figure 27. Typical ADC Frequency Response, Chopping Disabled Rev. 0 | Page 28 of 32 GAIN (dB) GAIN (dB) AD7739 ANALOG INPUT’S EXTENDED VOLTAGE RANGE VOLTAGE REFERENCE INPUTS The AD7739 output data code span corresponds to the nominal The AD7739 has a differential reference input, REF IN(+) and input voltage range. The ADC is functional outside the nominal REF IN(–). The common-mode range for these inputs is from input voltage range, but the performance might degrade. The AGND to AVDD. The nominal differential reference voltage for sigma-delta modulator was designed to fully cover 16% analog specified operation is 2.5 V. Both reference inputs feature input overrange; outside this range, the performance might dynamic load. Therefore, the reference inputs should be degrade more rapidly. connected to a low impedance reference voltage source. External resistance/capacitance combinations may result in gain When the CLAMP bit in the mode register is set to 1, the errors on the part. channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal The output noise performance outlined in Table 4 through input voltage range. Table 9 is for an analog input of 0 V and is unaffected by noise on the reference. Obtaining the same noise performance as As shown in Table 14 and Table 15, when CLAMP = 0, the data shown in the noise tables over the full input range requires a reflects the analog input voltage outside the nominal voltage low noise reference source for the AD7739. If the reference range. In this case, the SIGN and OVR bits in the channel status noise in the bandwidth of interest is excessive, it will degrade register should be considered along with the data register value the performance of the AD7739. to decode the actual conversion result. Recommended reference voltage sources for the AD7739 Note that the OVR bit in the channel status register is generated include the ADR421, AD780, REF43, and REF192. digitally from the conversion result and indicates the sigma- delta modulator (nominal) overrange. The OVR bit DOES NOT REFERENCE DETECT indicate exceeding the AIN pin’s absolute voltage limits. The AD7739 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the Table 14. Extended Input Voltage Range, REFIN(+) and REFIN(–) pins goes below the NOREF trigger Nominal Voltage Range ±1.25 V, 16 Bits, CLAMP = 0 voltage (0.5 V typ.) and the AD7739 is performing a conversion, Input (V) Data (hex) SIGN OVR the NOREF bit in the channel status register is set. +1.45000 0x147B 0 1 I/O PORT +1.25008 0x0001 0 1 +1.25004 0x0000 0 1 The AD7739 P0 pin can be used as a general-purpose digital +1.25000 0xFFFF 0 0 output or as a common analog input. +0.00004 0x8001 0 0 The P1 pin ( /P1) can be used as a general-purpose digital SYNC 0.00000 0x8000 0 0 –0.00004 0x7FFF 1 0 I/O pin or to synchronize the AD7739 with other devices in the –1.25000 0x0000 1 0 system. When the SYNC bit in the I/O port register is set and –1.25004 0xFFFF 1 1 the SYNC pin is low, the AD7739 does not process any –1.25008 0xFFFE 1 1 conversion. If it is put into single conversion mode, continuous –1.45000 0xEB85 1 1 conversion mode, or any calibration mode, the AD7739 waits until the SYNC pin goes high and then starts operation. This Table 15. Extended Input Voltage Range, allows conversion to start from a known point in time, i.e., the Nominal Voltage Range +1.25 V, 16 Bits, CLAMP = 0 rising edge of the pin. When configured as input, the SYNC SYNC pin should be tied high or low. Input (V) Data (hex) SIGN OVR +1.45000 0x28F5 0 1 The digital P0 and P1 voltage is referenced to the analog +1.25004 0x0001 0 1 supplies. +1.25002 0x0000 0 1 +1.25000 0xFFFF 0 0 +0.00002 0x0001 0 0 +0.00000 0x0000 0 0 –0.00002 0x0000 1 1 Rev. 0 | Page 29 of 32 AD7739 ADC Full-Scale Self-Calibration CALIBRATION The ADC full-scale self-calibration can reduce the ADC full- The AD7739 provides zero-scale self-calibration, and zero- and scale error for the +2.5 V and ±2.5 V input range. If repeated full-scale system calibration capability that can effectively after a temperature change, it can also reduce the full-scale drift. reduce the offset error and gain error to the order of the noise. After each conversion, the ADC conversion result is scaled The ADC full-scale self-calibration is performed with a +2.5 V using the ADC calibration registers and the relevant channel input voltage range on internally generated full-scale voltage calibration registers before being written to the data register. (V ), regardless of the input voltage range set in the channel REF setup register. Full-scale errors in the ±1.25 V, +1.25 V, ±0.625 V, For unipolar ranges: and +0.625 V ranges are not calibrated as this would require an Data = ((ADC result – R × ADC ZS Cal. reg.) accurate low voltage source other than the reference. × ADC FS reg./(0x20 0000) – R × Ch. ZS Cal. reg.) If the 1.25 V or 0.625 V ranges are used on any channel, the × Ch. FS Cal. reg./(0x20 0000) ADC full-scale self-calibration is not recommended. A system For bipolar ranges: full-scale calibration should be performed if accurate gains need to be achieved on these ranges. Data = ((ADC result – R × ADC ZS Cal. reg.) × ADC FS reg./(0x40 0000) + (0x80 0000) – R × Ch. ZS Cal. reg.) It is recommended that the ADC full-scale calibration register × Ch. FS Cal. reg./(0x20 0000) be updated only as part of an ADC full-scale self-calibration for the +2.5 V and ±2.5 V input range. where the ADC result is in the range of 0 to 0xFF FFFF. Per Channel System Calibration R = 1 for input ranges +1.25 V, ±1.25 V, +2.5 V, and ±2.5 V The per channel system calibration can reduce the system offset R = 2 for input ranges +0.625 V, and ±0.625 V error and the system gain error. If repeated after a temperature Note that the channel zero-scale calibration register has the change, it can also reduce the system offset and gain drifts. format of a sign bit and a 22-bit channel offset value. If the per channel system calibrations are used, these should be To start any calibration, write the relevant mode bits to the initiated in the following order: a channel zero-scale system AD7739 mode register. After the calibration is complete, the calibration, followed by a channel full-scale system calibration. contents of the corresponding calibration registers are updated, The system calibration is affected by the ADC zero-scale and all RDY bits in the ADC status register are set, the SYNC pin full-scale calibration registers. Therefore, if both self-calibration goes low, and the AD7739 reverts to idle mode. The calibration and system calibration are used in the system, an ADC self- duration is the same as the conversion time configured on the calibration should be performed first, followed by a system selected channel. A longer conversion time gives less noise and calibration cycle. yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration. The voltage range in the channel setup register should be set ADC Zero-Scale Self-Calibration before executing the channel system calibration. The ADC zero-scale self-calibration can reduce the ADC offset While executing a system calibration, the fully settled system error in the chopping disabled mode. If repeated after a zero-scale voltage signal or system full-scale voltage signal must temperature change, it can also reduce the offset drift error in be connected to the selected channel analog inputs. the chopping disabled mode. The per channel calibration registers can be read, stored, or The zero-scale self-calibration is performed on internally modified and written back to the AD7739. Note that when shorted ADC inputs. The negative analog input terminal on the writing the calibration registers, the AD7739 must be in idle selected channel is used to set the ADC zero-scale calibration mode. Note that outside the specified calibration range, common mode. Therefore, either the negative terminal of the calibration is possible, but the performance may degrade selected differential pair or the AINCOM on the single-ended (see the System Calibration section in Table 1). channel configuration should be driven to a proper common- mode voltage. It is recommended that the ADC zero-scale calibration register be updated only as part of an ADC zero-scale self-calibration. Rev. 0 | Page 30 of 32 AD7739 AV DV DD DD + + 10µF 0.1µF 0.1µF 10µF AV DV DD DD MCLKIN 100Ω AIN0 CLOCK 6.144MHz 0.1µF GENERATOR MCLKOUT 33pF 33pF ANALOG 24-BIT INPUTS MUX Σ-∆ ADC DV DD BUFFER 100Ω AIN7 RESET 0.1µF SCLK 100Ω SERIAL AINCOM DIN INTERFACE HOST 0.1µF AND DOUT SYSTEM AV DD CONTROL REFIN(+) RDY AD7739 LOGIC ADR421 CS REFIN(-) + 10µF 0.1µF 0.1µF AGND DGND Figure 28. Typical Connections for the AD7739 Application Rev. 0 | Page 31 of 32 AD7739 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 0.75 8° 0.30 0° 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MS-153AD Figure 29. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Description Package Outline AD7739BRU –40°C to +105°C TSSOP-24 RU-24 AD7739BRU-REEL –40°C to +105°C TSSOP-24 RU-24 AD7739BRU-REEL7 –40°C to +105°C TSSOP-24 RU-24 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03742–0–5/03(0) Rev. 0 | Page 32 of 32