ANALOG DEVICES AD7738

8-Channel, High Throughput, a 24-Bit �-� ADC AD7738 FUNCTIONAL BLOCK DIAGRAM FEATURES High Resolution ADC MUXOUT ADCIN REFIN– REFIN+ 24 Bits No Missing Codes �0.0015% Nonlinearity REFERENCE DETECT Optimized for Fast Channel Switching AIN0 18-Bits p-p Resolution (21 Bits Effective) at 500 Hz AIN1 16-Bits p-p Resolution (19 Bits Effective) at 8.5 kHz AIN2 BUFFER 15-Bits p-p Resolution (18 Bits Effective) at 15 kHz AIN3 On-Chip Per Channel System Calibration 24-BIT MUX �-� ADC Configurable Inputs AIN4 8 Single-Ended or 4 Fully Differential AIN5 Input Ranges AIN6 +625 mV, +1.25 V, +2.5 V, �625 mV, �1.25 V, �2.5 V AD7738 3-Wire Serial Interface AIN7 SCLK SPI™, QSPI™, MICROWIRE™ and DSP Compatible DOUT CALIBRATION SERIAL Schmitt Trigger on Logic Inputs AINCOM/P0 CIRCUITRY INTERFACE DIN Single-Supply Operation CS 5 V Analog Supply 3 V or 5 V Digital Supply RDY Package: 28-Lead TSSOP CLOCK CONTROL I/O PORT GENERATOR LOGIC SYNC/P1 RESET APPLICATIONS PLCs/DCS AGND AV MCLKOUT MCLKIN DGND DV Multiplexing Applications DD DD Process Control Industrial Instrumentation GENERAL DESCRIPTION The differential reference input features “No-Reference” detect The AD7738 is a high precision, high throughput analog front capability. The ADC also supports per channel system calibra- end. True 16-bit p-p resolution is achievable with a total con- tion options. version time of 117 µs (8.5 kHz channel switching), making it The digital serial interface can be configured for 3-wire opera- ideally suitable for high resolution multiplexing applications. tion and is compatible with microcontrollers and digital signal The part can be configured via a simple digital interface, which processors. All interface inputs are Schmitt triggered. allows users to balance the noise performance against data The part is specified for operation over the extended industrial throughput up to a 15.4 kHz. temperature range of –40�C to +105�C. The analog front end features eight single-ended or four fully Other parts in the AD7738 family are the AD7734 and the differential input channels with unipolar or bipolar 625 mV, AD7732. 1.25 V, and 2.5 V input ranges and accepts a common-mode The AD7734 analog front end features four single-ended input input voltage from 200 mV above AGND to AV – 300 mV. DD channels with unipolar or true bipolar input ranges to ±10 V The multiplexer output is pinned out externally, allowing the while operating from a single 5 V analog supply. The AD7734 user to implement programmable gain or signal conditioning accepts an analog input overvoltage to ±16.5 V while not before applying the input to the ADC. degrading the performance of the adjacent channels. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/326-8703 © Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices. AD7738–SPECIFICATIONS (–40�C to +105�C, AV = 5 V � 5%, DV = 2.7 V to 3.6 V or 5 V � 5%, DD DD REFIN(+) = 2.5 V, REFIN(–) = 0 V, AINCOM = 2.5 V, MUXOUT(+) = ADCIN(+), MUXOUT(–) = ADCIN(–), Internal Buffer ON, AIN Range = �1.25 V, f = 6.144 MHz; unless otherwise noted.) MCLK Parameter Min Typ Max Unit Test Conditions/Comment ADC PERFORMANCE— CHOPPING ENABLED Conversion Time Rate 372 12190 Hz Configure via Conversion Time Register 1 No Missing Codes 24 Bits FW ≥ 6 (Conversion Time ≥ 165 µs) See Typical Performance Characteristics Output Noise See Table I Resolution See Tables II and III Integral Nonlinearity (INL) ±0.0015 % of FSR AIN Range = ±2.5 V ±0.0015 % of FSR AIN Range = ±1.25 V 2 Offset Error (Unipolar, Bipolar) ±10 µV Before Calibration 1 Offset Drift vs. Temperature ±280 nV/°C 2 Gain Error ±0.2 % Before Calibration 1 Gain Drift vs. Temperature ±2.5 ppm of FS/�C 2 Positive Full-Scale Error ±0.2 % of FSR Before Calibration 1 Positive Full-Scale Drift vs. Temperature ±2.5 ppm of FS/�C 3 3 Bipolar Negative Full-Scale Error ±0.0030 % of FSR After Calibration Common-Mode Rejection 80 100 dB At DC, AIN = 1 V Power Supply Rejection 70 80 dB At DC, AIN = 1 V ADC PERFORMANCE— CHOPPING DISABLED Conversion Time Rate 737 15437 Hz Configure via Conversion Time Register 1 No Missing Codes 24 Bits FW ≥ 8 (Conversion Time ≥ 117 µs) See Typical Perfomance Charateristics Output Noise See Table IV Resolution See Tables V and VI Integral Nonlinearity (INL) ±0.0015 % of FSR 4 Offset Error (Unipolar, Bipolar) ±1mV Before Calibration Offset Drift vs. Temperature ±1.5 µV/�C 2 Gain Error ±0.2 % Before Calibration Gain Drift vs. Temperature ±2.5 ppm of FS/�C 2 Positive Full-Scale Error ±0.2 % of FSR Before Calibration Positive Full-Scale Drift vs. Temperature ±2.5 ppm of FS/�C 3 3 Bipolar Negative Full-Scale Error ±0.0030 % of FSR After Calibration Common-Mode Rejection 75 dB At DC, AIN = 1 V Power Supply Rejection 65 dB At DC, AIN = 1 V ANALOG INPUTS 1, 5 Analog Input Voltage Ranges ±2.5 V Range –2.9 ±2.5 +2.9 V +2.5 V Range 0 0 to 2.5 2.9 V ±1.25 V Range –1.45 ±1.25 +1.45 V +1.25 V Range 0 0 to 1.25 1.45 V ±0.625 V Range –725 ±625 +725 mV +0.625 V Range 0 0 to 625 725 mV 1 AIN, AINCOM Common-Mode Voltage 0.2 AV – 0.3 V DD 6 AIN, AINCOM Input Current 200 nA Only One Channel, Chop Disabled 1 AIN to MUXOUT On Resistance 200 Ω REFERENCE INPUT 1, 7 REFIN(+) to REFIN(–) Voltage 2.475 2.5 2.525 V NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register REFIN(+), REFIN(–) 1 Common-Mode Voltage 0AV V DD 8 Reference Input Current 400 µA 1, 9 SYSTEM CALIBRATION Full Scale Calibration Limit +1.05 � FS V Zero Scale Calibration Limit –1.05 � FS V Input Span 0.8 � FS 2.1 � FS V –2– REV. 0 AD7738 Parameter Min Typ Max Unit Test Conditions/Comment LOGIC INPUTS SCLK, DIN, CS, and RESET Inputs Input Current ±1 µA Input Current CS ±10 µA CS = AV DD –40 µA Internal Pull-Up Resistor Input Capacitance 4 pF 1 V 1.4 2 V DV = 5 V T+ DD 1 0.8 1.4 V DV = 5 V V T– DD 1 V – V 0.3 0.85 V DV = 5 V T+ T– DD 1 V 0.95 2 V DV = 3 V T+ DD 1 V 0.4 1.1 V DV = 3 V T– DD 1 V – V 0.3 0.85 V DV = 3 V T+ T– DD MCLK IN Only Input Current ±10 µA Input Capacitance 4 pF V Input Low Voltage 0.8 V DV = 5 V INL DD V Input High Voltage 3.5 V DV = 5 V INH DD V Input Low Voltage 0.4 V DV = 3 V INL DD V Input High Voltage 2.5 V DV = 3 V INH DD LOGIC OUTPUTS 10 MCLKOUT , DOUT, RDY V Output Low Voltage 0.4 V I = 800 µA, DV = 5 V OL SINK DD V Output High Voltage 4.0 V I = 200 µA, DV = 5 V OH SOURCE DD V Output Low Voltage 0.4 V I = 100 µA, DV = 3 V OL SINK DD V Output High Voltage DV – 0.6 V I = 100 µA, DV = 3 V OH DD SOURCE DD Floating State Leakage Current ±1 µA Floating State Leakage Capacitance 3 pF P1 INPUT Levels Referenced to Analog Supplies Input Current ±10 µA V Input Low Voltage 0.8 V AV = 5 V INL DD V Input High Voltage 3.5 V AV = 5 V INH DD P0, P1 OUTPUT V Output Low Voltage 0.4 V I = 8 mA, T = 70°C, AV = 5 V OL SINK MAX DD 0.4 V I = 5 mA, T = 85°C, AV = 5 V SINK MAX DD 0.4 V I = 2.5 mA, T = 105°C, AV = 5 V SINK MAX DD V Output High Voltage 4.0 V I = 200 µA, AV = 5 V OH SOURCE DD POWER REQUIREMENTS AV – AGND Voltage 4.75 5.25 V DD DV – DGND Voltage 4.75 5.25 V DD 2.70 3.60 V AV Current (Normal Mode) 13.6 16 mA AV = 5 V DD DD AV Current (Internal Buffer Off ) 8.5 mA AV = 5 V DD DD 11 DV Current (Normal Mode) 2.7 3 mA DV = 5 V DD DD 11 Current (Normal Mode) 1.0 1.5 mA DV = 3 V DV DD DD 12 AV + DV Current (Standby Mode) 80 µAAV = DV = 5 V DD DD DD DD 11 Power Dissipation (Normal Mode) 85 100 mW 12 Power Dissipation (Standby Mode) 500 µWAV = DV = 5 V DD DD NOTES 1 Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release. 2 Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise. 3 Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error. 4 Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise. 5 The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max. Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the Mode register. See the register description and circuit description for more details. 6 If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. See the circuit description for more details. 7 For specified performance. Part is functional with Lower V REF 8 Dynamic current charging the sigma-delta modulator input switching capacitor. 9 Outside the specified calibration range, calibration is possible but the performance may degrade. 10 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 11 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register). 12 External MCLKIN = 0 V or DV , Digital Inputs = 0 V or DV , P0 and P1 = 0 V or AV . DD DD DD Specifications are subject to change without notice. REV. 0 –3– AD7738 1, 2, 3 TIMING SPECIFICATIONS (AV = 5 V � 5%; DV = 2.7 V to 3.6 V or 5 V � 5%; Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted.) DD DD DD Parameter Min Typ Max Unit Test Conditions/Comment MASTER CLOCK RANGE 1 6.144 MHz t 50 ns SYNC Pulsewidth 1 t 500 ns RESET Pulsewidth 2 READ OPERATION t 0ns CS Falling Edge to SCLK Falling Edge Setup Time 4 4 t SCLK Falling Edge to Data Valid Delay 5 060nsDV of 4.75 V to 5.25 V DD 080nsDV of 2.7 V to 3.3 V DD 4, 5 t CS Falling Edge to Data Valid Delay 5A 060nsDV of 4.75 V to 5.25 V DD 080nsDV of 2.7 V to 3.3 V DD t 50 ns SCLK High Pulsewidth 6 t 50 ns SCLK Low Pulsewidth 7 t 0ns CS Rising Edge after SCLK Rising Edge Hold Time 8 6 t 10 80 ns Bus Relinquish Time after SCLK Rising Edge 9 WRITE OPERATION t 0ns CS Falling Edge to SCLK Falling Edge Setup 11 t 30 ns Data Valid to SCLK Rising Edge Setup Time 12 t 25 ns Data Valid after SCLK Rising Edge Hold Time 13 t 50 ns SCLK High Pulsewidth 14 t 50 ns SCLK Low Pulsewidth 15 t 0ns CS Rising Edge after SCLK Rising Edge Hold Time 16 NOTES 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 3 See Figures 1 and 2. 4 These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V or V limits. OL OH 5 This specification is relevant only if CS goes low while SCLK is low. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications are subject to change without notice. –4– REV. 0 AD7738 CS t t t 8 4 6 SCLK t 7 t 5 t t 9 5A DOUT MSB LSB Figure 1. Read Cycle Timing Diagram CS t t 11 16 t 14 SCLK t 15 t 12 t 13 DIN MSB LSB Figure 2. Write Cycle Timing Diagram I (800�A AT DV = 5V SINK DD 100�A AT DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I ( 200�A AT DV = 5V SOURCE DD 100�A AT DV = 3V) DD Figure 3. Load Circuit for Access Time and Bus Relinquish Time REV. 0 –5– AD7738 ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range . . . . . . . . . . –40�C to +105�C (T = 25�C unless otherwise noted.) Storage Temperature Range . . . . . . . . . . . . –65�C to +150�C A AV to AGND, DV to DGND . . . . . . . . . –0.3 V to +7 V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150�C DD DD AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V TSSOP Package, Power Dissipation . . . . . . . . . . . . . 660 mW AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9�C/W DD DD JA AIN, AINCOM to AGND . . . . . . . . . –0.3 V to AV + 0.3 V Lead Temperature, Soldering DD REFIN(+), REFIN(–) to AGND . . . . . –0.3 V to AV + 0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215�C DD MUXOUT(+) to AGND . . . . . . . . . . . –0.3 V to AV + 0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220�C DD MUXOUT(–) to AGND . . . . . . . . . . . –0.3 V to AV + 0.3 V DD *Stresses above those listed under Absolute Maximum Ratings may cause perma- ADCIN(+), ADCIN(–) to AGND . . . . –0.3 V to AV + 0.3 V DD nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational P1 Voltage to AGND . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD section of this specification is not implied. Exposure to absolute maximum rating Digital Input Voltage to DGND . . . . . –0.3 V to AV + 0.3 V DD conditions for extended periods may affect device reliability. Digital Output Voltage to DGND . . . . –0.3 V to AV + 0.3 V DD ORDERING GUIDE Temperature Package Package Model Range Description Options AD7738BRU –40�C to +105�CTSSOP 28 RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7738 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. MUXOUT ADCIN REFIN– REFIN+ REFERENCE DETECT AIN0 AIN1 BUFFER AIN2 AIN3 24-BIT MUX �-� ADC AIN4 AIN5 DV DD AIN6 AD7738 AIN7 CS SCLK CALIBRATION SERIAL AINCOM/P0 CIRCUITRY INTERFACE DOUT DIN AV DD RDY CLOCK CONTROL I/O PORT GENERATOR LOGIC SYNC/P1 RESET AGND AV MCLKOUT MCLKIN DGND DV DD DD Figure 4. Block Diagram –6– REV. 0 AD7738 PIN CONFIGURATION 1 SCLK 28 DGND 2 MCLKIN 27 DV DD 3 MCLKOUT 26 DIN 4 25 DOUT CS 5 24 RESET RDY 6 23 AV AGND DD AD7738 7 22 AINCOM/P0 REFIN(–) TOP VIEW (Not to Scale) 8 21 REFIN(+) SYNC/P1 9 20 AIN7 AIN0 10 19 AIN6 AIN1 11 18 AIN5 AIN2 12 17 AIN4 AIN3 13 16 MUXOUT(+) ADCIN(+) 14 15 MUXOUT(–) ADCIN(–) PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7738. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected. 3MCLKOUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to lower the device power consumption. MCLKOUT is capable of driving one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7738 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt-Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6AV Analog Positive Supply Voltage. 5 V to AGND nominal. DD 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The pin is determined by the P0 Dir bit; the digital value can be written as the P0 bit in the I/O Port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 Dir bit set to 1), the single-ended Analog Inputs 0 to 7 can be referenced to this pin’s voltage level. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 Dir bit; the digital value can be read/written as the P1 bit in the I/O Port register. When the SYNC Enable bit in the I/O Port register is set to 1, the SYNC/P1 pin can be used to synchronize the AD7738 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low. 9–12, AIN0–AIN7 Analog Inputs 17–20 13 MUXOUT(+) Analog Multiplexer Positive Output 14 MUXOUT(–) Analog Multiplexer Negative Output REV. 0 –7– AD7738 PIN FUNCTION DESCRIPTION (continued) Pin No. Mnemonic Pin Description 15 ADCIN(–) ADC Negative Input. In normal circuit configuration, this pin should be connected to the MUXOUT– pin. 16 ADCIN(+) ADC Positive Input. In normal circuit configuration, this pin should be connected to the MUXOUT+ pin. 21 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN+ voltage potential can lie any where between AV and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. DD 22 REFIN(–) Negative Terminal of the Differential Reference Input. REFIN– voltage potential can lie any where between AV and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. DD 23 AGND Ground Reference Point for Analog Circuitry 24 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available—according to the RDY function bit in the I/O Port register. In calibration mode, a falling edge on this output indicates that calibration is complete. See more details in Digital Interface Description section later in this data sheet. 25 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from any AD7738 register depending on the address bits of the Communications register. 26 DIN Serial Data Input (Schmitt triggered) with serial data being written to the input shift register on the part. Data from this input shift register is transferred to any AD7738 register depending on the address bits of the Communications register. 27 DV Digital Supply Voltage, 3 V or 5 V Nominal DD 28 DGND Ground Reference Point for Digital Circuitry –8– REV. 0 AD7738 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. CHOPPING ENABLED The first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register. Table I. Typical Output RMS Noise in �V vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V, +2.5 V �1.25 V, +1.25 V, �625 mV, +625 mV 127 FFh 2686 372 194 1.8 1.1 46 AEh 999 1001 521 3.0 1.8 17 91h 395 2534 1317 5.1 3.0 8 88h 207 4826 2510 8.1 4.5 4 84h 124 8074 4198 9.3 5.3 2 82h 82 12166 6326 17.0 10.6 Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V +2.5 V �1.25 V +1.25 V �625 mV +625 mV 127 FFh 2686 372 194 21.4 20.4 21.1 20.1 20.1 19.1 46 AEh 999 1001 521 20.6 19.6 20.4 19.4 19.4 18.4 17 91h 395 2534 1317 19.9 18.9 19.6 18.6 18.6 17.6 8 88h 207 4826 2510 19.2 18.2 19.0 18.0 18.0 17.0 4 84h 124 8074 4198 19.0 18.0 18.8 17.8 17.8 16.8 2 82h 82 12166 6326 18.1 17.1 17.8 16.8 16.8 15.8 Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V +2.5 V �1.25 V +1.25 V �625 mV +625 mV 127 FFh 2686 372 194 18.4 17.4 18.2 17.2 17.2 16.2 46 AEh 999 1001 521 17.8 16.8 17.5 16.5 16.5 15.5 17 91h 395 2534 1317 16.8 15.8 16.7 15.7 15.7 14.7 8 88h 207 4826 2510 16.5 15.5 16.2 15.2 15.2 14.2 4 84h 124 8074 4198 16.0 15.0 16.0 15.0 15.0 14.0 2 82h 82 12166 6326 15.0 14.0 15.0 14.0 14.0 13.0 REV. 0 –9– AD7738 CHOPPING DISABLED The second mode, in which the AD7738 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still maintaining high resolution. Tables IV to VI show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table IV shows the typical output rms noise. Table V shows the typical effective resolution based on the rms noise. Table VI shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register. Table IV. Typical Output RMS Noise in �V vs. Conversion Time and Input Range with Chopping Disabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V, +2.5 V �1.25 V, +1.25 V, �625 mV, +625 mV 127 7Fh 1357 737 671 2.7 1.5 92 5Ch 992 1008 917 3.0 1.8 35 23h 398 2511 2285 5.1 3.0 16 10h200 4991 2510 7.5 4.5 99h127 7847 7141 10.2 5.9 88h 117 8545 7776 11.4 6.5 33h65 15398 14013 15.5 10.3 Table V. Typical RMS Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V +2.5 V �1.25 V +1.25 V �625 mV +625 mV 127 7Fh 1357 737 671 20.8 19.8 20.6 19.6 19.6 18.6 92 5Ch 992 1008 917 20.6 19.6 20.4 19.4 19.4 18.4 35 23h 398 2511 2285 19.9 18.9 19.6 18.6 18.6 17.6 16 10h200 4991 2510 19.3 18.3 19.0 18.0 18.0 17.0 99h127 7847 7141 18.9 17.9 18.7 17.7 17.7 16.7 88h 117 8545 7776 18.7 17.7 18.5 17.5 17.5 16.5 33h65 15398 14013 18.0 16.7 17.8 17.1 17.1 16.1 Table VI. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register (�s) (Hz) (Hz) �2.5 V +2.5 V �1.25 V +1.25 V �625 mV +625 mV 127 7Fh 1357 737 671 17.9 16.9 17.8 16.8 16.8 15.8 92 5Ch 992 1008 917 17.8 16.8 17.4 16.4 16.4 15.4 35 23h 398 2511 2285 17.0 16.0 16.8 15.8 15.8 14.8 16 10h200 4991 2510 16.3 15.3 16.2 15.2 15.2 14.2 99h127 7847 7141 16.1 15.1 15.9 14.9 14.9 13.9 88h 117 8545 7776 16.0 15.0 15.7 14.7 14.7 13.7 33h65 15398 14013 15.0 14.0 14.8 13.8 13.8 12.8 –10– REV. 0 Typical Performance Characteristics–AD7738 25 0 THD = 115dB 24 –20 CHOP = 1 23 –40 22 –60 21 –80 20 –100 19 –120 18 –140 17 –160 16 –180 11 2 34567890 0 200 400 600 800 1000 1200 1400 FILTER WORD INPUT FREQUENCY TPC 1. No Missing Codes Performance, Chopping Enabled TPC 3. Typical FFT Plot; Input Sinewave 183 Hz, 1.2 V Peak, Range ±1.25 V, Conversion Time 394 µs, Chopping Enabled 140 25 EFFECTIVE RES. 19.9 BITS 24 P-P RES. 17.0 BITS 120 CHOP = 0 23 100 22 80 21 20 60 19 40 18 20 17 0 16 –80 –60 –40 –20 0 20 40 60 80 11 2 34567890 VALUE FILTER WORD TPC 4. Typical Histogram; Analog Inputs Shorted; TPC 2. No Missing Codes Performance, Chopping Disabled Range ±2.5 V, Conversion Time 394 µs; Chopping Enabled REV. 0 –11– NO MISSING CODES NO MISSING CODES GAIN – dB NUMBER OF CODES AD7738 Table VII. Register Summary Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register hex Default Value Communications 00 W 0 R/W 6-Bit Register Address I/O Port 01 R/W P0 P1 P0 DIR P1 DIR RDY FN 0 0 SYNC P0 Pin P1 Pin 1 1 0 0 0 0 Revision 02 R Chip Revision Code Chip Generic Code xx x x 0 0 0 1 Test 03 R/W 24 Bits Manufacturing Test Register ADC Status 04 R RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00 0 0 0 0 00 Checksum 05 R/W 16-Bit Checksum Register ADC ZS Calibration 06 R/W 24-Bit ADC Zero-Scale Calibration Register 800000h ADC FS 07 R/W 24-Bit ADC Full-Scale Register 800000h 1 Channel Data 08-0F R 16-/24-Bit Data Registers 8000h 1 Channel ZS Calibration 10–17 R/W 24-Bit Channel Zero-Scale Calibration Registers 800000h 1 Channel FS Calibration 18–1F R/W 24-Bits Channel Full-Scale Calibration Registers 200000h 1 Channel Status 20–27 R CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Channel Number 0 0 0 0 0 1 Channel Setup 28–2F R/W BUF OFF COM1 COM0 Stat. Opt. ENABLE RNG2 RNG1 RNG0 00 0 0 0 0 00 1 Channel Conv. Time 30–37 R/W CHOP FW (7-Bit Filter Word) 1 11h 2 Mode 38–3F R/W MD2 MD1 MD0 CLKDIS DUMP Cont. RD 24/16 Bits CLAMP 00 0 0 0 0 00 NOTES 1 The three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the Communication register, specify the channel number of the register being accessed. 2 There is only one Mode register, although the Mode register can be accessed in one of eight address locations The address used to write the Mode register specifies the ADC channel on which the mode will be applied. Address 38h only must be used for reading from the Mode register. Table VIII. Operational Mode Summary Table IX. Input Range Summary MD2 MD1 MD0 Mode RNG2 RNG1 RNG0 Nominal Input Voltage Range 000 Idle Mode 10 0 ±2.5 V 001 Continuous Conversion Mode 10 10 V to +2.5 V 010 Single Conversion Mode 00 0 ±1.25 V 011 Power-Down (Standby) Mode 00 10 V to +1.25 V 100 ADC Zero-Scale Self Calibration 01 0 ±0.625 V 101 For Future Use 01 10 V to +0.625 V 110 Channel Zero-Scale System Calibration 111 Channel Full-Scale System Calibration –12– REV. 0 AD7738 REGISTER DESCRIPTION The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communication register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register will be subsequently read or written. Communications Register 8 Bits, Write-Only Register, Address 00h All communications to the part must start with a write operation to the Communications register. The data written to the Commu- nications register determines whether the subsequent operation will be a read or write and to which register this operation will be directly placed. The digital interface defaults to expect write operation to the Communication register after power on, after reset, or after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low (Note that all of the parts including modulator, filter, interface and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or with the DUMP bit and “24/16” bit in the Mode register set. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 R/W 6-Bit Register Address Bit Mnemonic Description 70 This bit must be zero for proper operation. 6R/W A zero in this bit indicates that the next operation will be a write to a specified register. A one in this bit indicates that the next operation will be a read from a specified register. 5–0 Address Address specifying to which register the read or write operation will be directed. For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes to the Mode register, then the three LSBs specify the channel selected for operation determined by the Mode register value. See Table X. (The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.) Table X. Bit 2 Bit 1 Bit 0 Channel Single Input Differential Input 000 0 AIN0 AIN0–AIN1 001 1 AIN1 AIN2–AIN3 010 2 AIN2 AIN4–AIN5 011 3 AIN3 AIN6–AIN7 100 4 AIN4 AIN0–AIN1 101 5 AIN5 AIN2–AIN3 110 6 AIN6 AIN4–AIN5 111 7 AIN7 AIN6–AIN7 REV. 0 –13– AD7738 I/O Port Register 8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value � 40h The bits in this register are used to configure and access the digital I/O pin on the AD7738. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic P0 P1 P0 DIR P1 DIR RDY FN 0 0 SYNC Default P0 Pin P1 Pin 1 1 0 0 0 0 Bit Mnemonic Description 7P0 When the AINCOM/P0 pin is configured as a digital output, the P0 bit determines the pin’s output level. 6P1When the P1 pin is configured as an output, the P1 bit determines the pin’s output level. When the P1 pin is configured as an input, the P1 bit reflects the current input level on the pin. 5 P0 DIRWhen set to 1, the AINCOM/P0 pin is configured as an analog input. When set to 0, the AINCOM/P0 pin is configured as a digital output. 4 P1 DIRThis bit determines whether P1 pin is configured as an input or an output. When set to 1, the P1 pin will be a digital input; when reset to 0, the pin will be a digital output. 3 RDY FN This bit is used to control the function of the RDY pin on the AD7738. When this bit is reset to 0 the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. 2, 1 0 These bits must be zero for proper operation. 0 SYNC This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC EN bit is set to 1, the SYNC pin can be used to synchronize the AD7738 modulator and digital filter with other devices in the system. Revision Register 8 Bits, Read-Only Register, Address 02h, Default Value 01h + Chip Revision � 10h Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Chip Revision Code Chip Generic Code Default x x x x 0 0 0 1 Bit Mnemonic Description 7–4 Chip Revision Code 4-Bit Factory Chip Revision Code 3–0 Chip Generic Code On the AD7738, these bits will read back as 01h. Test Register 24 Bits, Read/Write Register, Address 03h This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register. ADC Status Register 8 Bits, Read-Only Register, Address 04h, Default Value 00h In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding Channel Data register is updated and the corresponding RDY bit is set to 1. When the Channel Data register is read, the corresponding bit is reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the Channel Data register. Writing to the Mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress and all the bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of ADC Status register as defined by the RDY Function bit in the I/O Port register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 Default 0 0 0 0 0 0 0 0 The RDY0 bit corresponds to Channel 0, RDY1 bit to Channel 1, and so on. –14– REV. 0 AD7738 Checksum Register 16 Bits, Read/Write Register, Address 05h This register is described in the “AD7732/34/38 Checksum Register” Technical Note. ADC Zero Scale Calibration Register 24 Bits, Read/Write Register, Address 06h, Default Value 800000h The register holds the ADC Zero-Scale Calibration coefficient. The value in this register is used in conjunction with the value in the ADC Full-Scale Calibration register and corresponding Channel Zero-Scale and Channel Full-Scale Calibration registers to scale digitally all channels’ conversion results. The value in this register is updated automatically following the execution of an ADC Zero- Scale ADC Self-Calibration. Writing to this register is possible in the Idle Mode only. See the calibration description for more details. ADC Full-Scale Register 24 Bits, Read/Write Register, Address 07h, Default Value 800000h The register holds the ADC Full-Scale coefficient. The user is advised not to change the default configuration of this register. Channel Data Registers 16/24 Bits, Read-Only Registers, Address 08h–0Fh, Default Width 16 Bits, Default Value 8000h These registers contain the most up-to-date conversion results corresponding to each analog input channel. The 16- or 24-bit data width can be configured by setting the “16/24” bit in the Mode register. The relevant RDY bit in the Channel Status register goes high when the result is updated. The RDY bit will return low once the Data register reading has begun. The RDY pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any Channel Data Register read operation is in progress when the new result is updated, then no update of the Data register occurs. This is to avoid getting corrupted data. Reading the Status registers can be associated with reading the Data registers in the Dump mode. Reading the Status registers is always associated with reading the Data registers in the Continuous Read mode. See the digital interface description for more details. Channel Zero-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 10h–17h, Default Value 800000h These registers hold the particular channel Zero-Scale Calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding Channel Full-Scale Calibration register, the ADC Zero-Scale Calibration register, and ADC Full-Scale Calibration register to scale digitally the particular channel conversion results. The value in this register is updated auto- matically following the execution of a Channel Zero-Scale System Calibration. The format of the Channel Zero-Scale Calibration register is a sign bit and 22 bits unsigned value. Writing this register is possible in the Idle Mode only. See the calibration description for more details. Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 18h–1Fh, Default Value 200000h These registers hold the particular channel Full-Scale Calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding Channel Zero-Scale Calibration register, the ADC Zero-Scale Calibration register, and ADC Full Scale Calibration register to scale digitally the particular channel conversion results. The value in this register is updated automati- cally following the execution of a Channel Full-Scale System Calibration. Writing this register is possible in the Idle mode only. See the calibration description for more details. REV. 0 –15– AD7738 Channel Status Registers 8 Bits, Read-Only Register, Address 20h–27h, Default Value 20h � Channel Number These registers contain individual channel status information and some general AD7738 status information. Reading the Status registers can be associated with reading the Data registers in the Dump mode. Reading the Status registers is always associated with reading the Data registers in the Continuous Read mode. See the Digital Interface Description section for more details. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Default Channel Number 0 0 0 0 0 Bit Mnemonic Description 7–5 CH2–CH0 These bits reflect the channel number. This can be used for current channel identification and easier operation in the Dump mode and Continuous Read mode. 40/P0 When the Status Option bit in the corresponding Channel Setup register is reset to 0, this bit is read as a zero. When the Status Option bit in set to 1, this bit reflects the state of the P0 output pin. 3 RDY/P1 When the Status Option bit in the corresponding Channel Setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC Status register. When the Status Option bit is set to 1, this bit reflects the state of the P1 pin whether it is configured as an input or output. 2 NOREF This bit indicates the reference input status. If the voltage between the REFIN+ and REFIN– pins is less than the NOREF trigger voltage, then the NOREF bit goes to a 1. 1 SIGN The voltage polarity at the analog input. Will be 0 for a positive voltage; will be 1 for a negative voltage. 0 OVR This bit reflects either overrange or underrange on an analog input. The bit is set to 1 when the analog input voltage goes over or under the Nominal Voltage Range. See the Analog Inputs Extended Voltage Range section. –16– REV. 0 AD7738 Channel Setup Registers 8 Bits, Read/Write Register, Address 28h–2Fh, Default Value 00h These registers are used to configure the selected channel, its input voltage range, and set up the corresponding Channel Status register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic BUF OFF COM1 COM0 Stat. Opt. ENABLE RNG2 RNG1 RNG0 Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7 BUF OFF Buffer Off. If reset to 0, then internal buffer is enabled. Only operation with internal buffer enabled is recommended. 6, 5 COM1, COM0 Analog Input Configuration. See Table XI. 4 Stat. Opt. Status Option. When this bit is set to 1, the P1 bit in the Status Channel register will reflect the state of the P1 pin. When this bit is reset to 0, the P1 bit in the Status Channel register bit will reflect the channel corresponding RDY bit in the ADC Status register. 3 ENABLE Channel Enable. Set this bit to 1 to enable the channel in the Continuous Conversion mode. A single conversion will take place regardless of this bit value. 2–0 RNG2–0 The Channel Input Voltage Range. See Table XII. Table XI. Table XII. COM1 COM0 COM1 COM0 Nominal Input RNG2 RNG1 RNG0 Voltage Range Channel 0 0 1 1 10 0 ±2.5 V 0 AIN0–AINCOM AIN0–AIN1 10 10 V to +2.5 V 1 AIN1–AINCOM AIN2–AIN3 00 0 ±1.25 V 2 AIN2–AINCOM AIN4–AIN5 00 10 V to +1.25 V 3 AIN3–AINCOM AIN6–AIN7 01 0 ±0.625 V 4 AIN4–AINCOM AIN0–AIN1 01 10 V to +0.625 V 5 AIN5–AINCOM AIN2–AIN3 6 AIN6–AINCOM AIN4–AIN5 7 AIN7–AINCOM AIN6–AIN7 Channel Conversion Time Registers 8 Bits, Read/Write Register, Address 30h–37h, Default Value 91h The Conversion Time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CHOP FW (7-Bit Filter Word) Default 1 11h Bit Mnemonic Description 7 CHOP Chop Enable Bit. Set to 1 to apply chopping mode for a particular channel. 6–0 FW CHOP = 1, Single Conversion or Continuous Conversion with one channel enabled. Conversion Time (µs) = (FW � 128 + 248)/MCLK Frequency (MHz), the FW in range of 2 to 127. CHOP = 1, Continuous Conversion with two or more channels enabled. Conversion Time (µs) = (FW � 128 + 249)/MCLK Frequency (MHz), the FW in range of 2 to 127. CHOP = 0, Single Conversion or Continuous Conversion with one channel enabled. Conversion Time (µs) = (FW � 64 + 206)/MCLK Frequency (MHz), the FW in range of 3 to 127. CHOP = 0, Single Conversion or Continuous Conversion with two or more channels enabled. Conversion Time (µs) = (FW � 64 + 207)/MCLK Frequency (MHz), the FW in range of 3 to 127. REV. 0 –17– AD7738 Mode Register 8 Bits Read/Write Register, Address 38h–3Fh, Default Value 00h The Mode register configures the part and determines the part’s operating mode. Writing to the Mode register will clear the ADC Status register, set the RDY pin to logic high level, exit all current operations, and start the mode specified by the Mode bits. The AD7738 contains only one Mode register. The three LSBs of the address used for writing to the Mode register specify the channel selected for operation determined by the MD2 to MD0 bits. The address 38h only must be used for reading from the Mode register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic MD2 MD1 MD0 CLKDIS DUMP CONT RD 24/16 BIT CLAMP Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7–5 MD2–MD0 Mode Bits. These three bits determine the AD7738 operation mode. Writing a new value to the Mode bits will exit the part from the mode in which it has been operating and place it in the new requested mode immediately. The function of the Mode bits is described in more detail below. 4 CLKDIS Master Clock Output Disable. When this bit is set to 1 the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7738 continues to have internal clocks and will convert normally regardless of CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7738 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7738 digital interface can still be accessed using the SCLK pin. 3 DUMP DUMP Mode. When this bit is reset to 0, the Channel Status register and Channel Data register will be addressed and read separately. When the DUMP bit is set to 1, the Channel Status register will be followed immediately by a read of the Channel Data register regardless of whether the Status or Data register has been addressed through the Communication register. The Continuous Read mode will always be a “Dump Mode” reading of the Channel Status and Data register regardless of the Dump Bit value. See the Digital Interface Description section for more details. 2 CONT RD When this bit is set to 1, the AD7738 will operate in the Continuous Read mode. See the Digital Interface Description section for more details. 1 24/16 BIT The Channel Data Register Data Width Selection Bit. When set to 1, the Channel Data registers will be 24 bits wide. When set to 0, then the Channel Data registers will be 16 bits wide. 0 CLAMP This bit determines the Channel Data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the Channel Data register will be digitally clamped either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the Data registers reflect the analog input voltage even outside the nominal voltage range. See the Analog Inputs Extended Voltage Range section. MD2 MD1 MD0 Mode Address Used for Mode Register Write Specify 000 Idle Mode 001Continuous Conversion Mode The First Channel to Start Converting 010 Single Conversion Mode Channel to Convert 011Power Down (Standby) Mode 100 ADC Zero-Scale Self Calibration Channel Conversion Time Used for the ADC Self-Calibration 101For Future Use 110Channel Zero-Scale System Calibration Channel to Calibrate 111Channel Full-Scale System Calibration Channel to Calibrate –18– REV. 0 AD7738 MD2 MD1 MD0 Operating Mode 000 Idle Mode The default mode after Power-On or Reset. The AD7738 returns to this mode automatically after any calibration or after a single conversion. 001 Continuous Conversion Mode The AD7738 performs a conversion on the specified channel. After the conversion is complete, the relevant Channel Data register and Channel Status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7738 continues converting on the next enabled channel. The AD7738 will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by corresponding Channel Conversion Time registers. 010 Single Conversion Mode The AD7738 performs a conversion on the specified channel. After the conversion is complete, the relevant Channel Data register and Channel Status register are updated, the relevant RDY bit in the ADC status register is set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. Requesting a single conversion ignores the Channel Setup registers’ Enable bits and a conversion will be performed even if that channel is disabled. 011 Power-Down (Standby) Mode The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7738 digital interface can still be accessed. The CLKDIS bit works separately, the MCLKOUT mode is not affected by Power-Down (Standby) mode. 100 ADC Zero-Scale Self-Calibration Mode A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is complete, the contents of the ADC Zero-Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and the AD7738 returns to the Idle mode. 101 For Future Use 110 Channel Zero-Scale System Calibration Mode A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be provided at the AD7738 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding Channel Zero Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. 111 Channel Full-Scale System Calibration Mode A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7738 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding Channel Full-Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. REV. 0 –19– AD7738 DIGITAL INTERFACE DESCRIPTION Relinquish Time in the Timing Characteristics). The AD7738 Hardware cannot operate in the Continuous Read mode in 2-wire serial The AD7738 serial interface can be connected to the host interface configuration. device via the serial interface in several different ways. All the digital interface inputs are Schmitt-Triggered. There- The CS pin can be used to select the AD7738 as one of several fore, the AD7738 interface features higher noise immunity circuits connected to the host serial interface. When the CS is and the AD7738 can be easily isolated from the host system via high, the AD7738 ignores the SCLK and DIN signals and optocouplers. the DOUT pin goes to the high impedance state. When the CS Figure 5 outlines some of the possible host device interfaces: signal is not used, connect the CS pin to DGND. (a) SPI without using the CS signal, (b) DSP interface, and The RDY pin can be either polled for high to low transition or (c) 2-wire configuration. can drive the host device interrupt input to indicate that the Reset AD7738 has finished the selected operation and/or new data The AD7738 can be reset by the RESET pin or by writing a from the AD7738 are available. The host system can also wait a reset sequence to the AD7738 serial interface. The reset designated time after a given command is written to the device sequence is N � “0” + 32 � “1”, which could be the data before reading. Alternatively, the AD7738 status can be polled. sequence 00h + FFh + FFh + FFh + FFh in a byte oriented When the RDY pin is not used in the system, it should be left as interface. The AD7738 also features a power-on reset with a an open circuit. (Note that the RDY pin is always an active trip point of 2 V and goes to the defined default state after digital output, i.e., never goes into a high impedance state). power on. The RESET pin can be used to reset the AD7738. When not It is the system designer’s responsibility to prevent an unwanted used, connect this pin to DV . DD write operation to the AD7738. The unwanted write operation The AD7738 interface can be reduced to just two wires con- could happen when a spurious clock appears on the SCLK necting DIN and DOUT pins to a single bidirectional data line. while the CS pin is low. It should be noted that on system The second signal in this 2-wire configuration is the SCLK power-on, if the AD7738 interface signals are floating or unde- signal. The host system should change the data line direction fined, the part can be inadvertently configured into an unknown with reference to the AD7738 timing specification (see the Bus state. This could be easily overcome by initiating either a HW reset event or a 32 ones reset sequence as the first step in the system configuration. DV DV DV DV DD DD DD DD AD7738 68HC11 AD7738 ADSP-2105 AD7738 8xC51 RESET SS RESET RESET SCLK SCK SCLK SCLK SCLK P3.1/TXD DOUT MISO DOUT DR DOUT P3.0/RXD DIN MOSI DIN DT DIN RDY INT RDY INT CS CS TFS CS RFS DGND DGND a. b. c. Figure 5. AD7738 to Host Device Possible Interface Access the AD7738 Registers CS All communications to the part start with a write operation to SCLK the Communications register followed by either reading or writing the addressed register. DIN In a simultaneous read-write interface (such as SPI), write “0” DOUT to the AD7738 while reading data. WRITE READ Figure 6 shows the AD7738 interface read sequence for the COMMUNICATIONS ADC STATUS REGISTER REGISTER ADC Status register. Figure 6. The Serial Interface Signals—Register Access –20– REV. 0 AD7738 Dump Mode Single Conversion and Reading Data When the Mode register is being written, the ADC Status Byte When the DUMP bit in the Mode register is set to 1, the Chan- is cleared and the RDY pin goes high regardless of its previous nel Status register will be read immediately by a read of the Channel Data register regardless of whether the Status or the state. When the single conversion command is written to the Mode register, the ADC starts the conversion on the channel Data register has been addressed through the Communication register. The DIN pin should not be high while reading 24-bit selected by the address of the Mode register. After the conversion data in Dump mode. Otherwise the AD7738 will be reset. is completed, the Data register is updated, the Mode register is changed to Idle mode, the relevant RDY bit is set, and the RDY Figure 8 shows the digital interface signals executing a single pin goes low. The RDY bit is reset and the RDY pin returns conversion on Channel 0, waiting for for the RDY pin low, and high when the relevant Channel Data register is being read. reading the Channel 0 Status register and Data register in the Dump mode. Figure 7 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin low, and reading the Channel 0 Data register. CS SCLK (00h) (00h) DIN 38h 40h 48h DOUT DATA DATA RDY READ DATA WRITE WRITE CONVERSION WRITE REGISTER COMMUNICATIONS MODE TIME COMMUNICATIONS REGISTER REGISTER REGISTER Figure 7. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading CS SCLK (00h) (00h) (00h) DIN 38h 48h 48h DOUT DATA DATA CH. STAT RDY READ DATA WRITE WRITE CONVERSION WRITE READ REGISTER COMMUNICATIONS MODE TIME COMMUNICATIONS CHANNEL REGISTER REGISTER REGISTER STATUS Figure 8. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode REV. 0 –21– AD7738 Continuous Conversion Mode If an ADC conversion result has not been read before a new When the Mode register is being written, the ADC Status Byte ADC conversion is completed, then the new result will overwrite is cleared and the RDY pin goes high regardless of its previous the previous one. The relevant RDY bit goes low and the RDY state. When the continuous conversion command is written to pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating the Mode register, the ADC starts conversion on the channel when the Data register is updated and the previous conversion selected by the address of the Mode register. data is lost. After the conversion is complete, the relevant Channel Data If the Data register is being read as an ADC conversion completes, register and Channel Status register are updated, the relevant then the Data Register will not be updated with the new result (to RDY bit in the ADC Status register is set, and the AD7738 avoid data corruption) and the new conversion data is lost. continues converting on the next enabled channel. The Figure 9 shows the digital interface signals sequence for the AD7738 will cycle through all enabled channels until put Continuous Conversion mode with Channels 0 and 1 enabled into another mode or reset. The cycle period will be the sum of and the RDYFN bit set to 0. The RDY pin goes low and the all enabled channels’ conversion times, set by corresponding Data Register is read after each conversion. Figure 10 shows a Channel Conversion Time registers. similar sequence, but with the RDYFN bit set to 1. The RDY The RDY bit is reset when the relevant Channel Data register is pin goes low and the Data register is read after all conversions being read. The behavior of the RDY pin depends on the are completed. Figure 11 shows the RDY pin when no data are RDYFN bit in the I/O Port register. When RDYFN bit is 0, the read from the AD7738. RDY pin goes low when any channel has unread data. When this bit is set to 1 the RDY pin will only go low if all enabled channels have unread data. START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 9. Continuous Conversion, CH0 and CH1, RDYFN = 0 START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 10. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 11. Continuous Conversion, CH0 and CH1, No Data Read –22– REV. 0 AD7738 CS SCLK DIN 38h 48h 00h 00h 00h 48h 00h 00h 00h DOUT CH.STAT. DATA DATA CH.STAT. DATA DATA RDY WRITE WRITE CONVERSION WRITE READ READ CH0 CONVERSION READ READ CH1 DATA COMM. MODE ON CH0 COMM. CH0 DATA REGISTER ON CH1 CH1 REGISTER REGISTER REGISTER COMPLETE REGISTER STATUS COMPLETE STATUS Figure 12. Continuous Conversion CH0 and CH1, Continuous Read Continuous Read (Continuous Conversion) Mode The AD7738 contains a wide bandwidth, fast settling time When the Continuous RD bit in the Mode register is set, the differential input buffer capable of driving the dynamic load of a first write “48h” to the communication register starts the Continu- high speed sigma-delta modulator. With the internal buffer ous Read mode. As shown in Figure 12, subsequent accesses enabled, the analog inputs feature relatively high input imped- to the part sequentially reads the Channel Status and Data ance. However, if chopping is enabled and/or when switching registers of the last completed conversion without any further between channels, there is a dynamic current charging the configuration of the Communication register being required. capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. In typical Note that the Continuous Conversion bit in the Mode register configurations with MUXOUT connected directly to the should be set when entering the Continuous Read mode. ADCIN, this capacitance could be approximately 20 pF. The Note that the Continuous Read mode is “Dump Mode” reading AD7738 has been designed to provide adequate settling time of the Channel Status and Data register regardless of the Dump after a multiplexer switch and before the actual sampling starts bit value. Use the Channel bits in the Channel Status register to only if the analog inputs resistive source impedance does not check/recognize which channel data is actually being shifted out. exceed 10 kΩ. Note that the last completed conversion result is being read. An RC connected to the analog inputs may convert the dynamic Therefore, the RDYFN bit in the I/O Port register should be 0, charging currents to a dc voltage and cause additional gain or and reading the result should always start before the next con- offset errors. The recommended low-pass RC filter on the version is completed. AD7738 analog inputs is 20 Ω and 100 nF. The AD7738 will stay in Continuous Read mode as long as the The multiplexer output and the ADC input are pinned out DIN pin is low while the CS pin is low. Therefore, write 0 to externally. This facilitates shared signal conditioning between the AD7738 while reading in Continuous Read mode. To the multiplexer and the ADC. Please note that if chop is enabled exit Continuous Read mode, take the DIN pin high for at least and/or when switching between channels, any circuit connected 100 ns after a read is complete. (Write “80h” to the AD7738 to between MUXOUT and ADCIN should be fully settled within exit continuous reading.) the settling time provided by the AD7738. See the Multiplexer, Conversion, and Data Output Timing section. The Continuous RD bit in the Mode register is not changed by taking the DIN pin high. Therefore, the next write “48h” �-� ADC starts the Continuous Read mode again. To completely stop The AD7738 core consists of a charge balancing sigma-delta the continuous read mode, write to the Mode register to clear modulator and a digital filter. The architecture is optimized for the Continuous RD bit. fast fully settled conversion. This allows for fast channel-to-channel switching while maintaining inherently excellent linearity, high CIRCUIT DESCRIPTION resolution, and low noise. The AD7738 is a sigma-delta A/D converter, intended for the Chopping measurement of wide dynamic range, low frequency signals in With chopping enabled, the multiplexer repeatedly reverses the industrial process control, instrumentation, PLC, and DSC. ADC inputs. Every output data result is then calculated as an It contains a multiplexer, an input buffer, a sigma-delta (or average of two conversions, the first with positive and the sec- charge-balancing) ADC, digital filter, clock oscillator, digital I/O ond with negative offset term included. This effectively removes port, and a serial communications interface. any offset error of the input buffer and sigma-delta modulator, resulting in excellent dc offset and offset drift specifications. Analog Front End The AD7738 has nine analog input pins connected to the Figure 13 shows the channel signal chain with chopping enabled. ADC through the internal multiplexer. The analog front end can be configured as eight single-ended inputs four differen- tial inputs, or any combination of these. Selection of ADC inputs is determined via the COM0 and COM1 bits in the Channel Setup registers. REV. 0 –23– AD7738 MULTIPLEXER BUFFER MUXOUT ADCIN AIN(+) + SCALING �-� OUTPUT DATA DIGITAL DIGITAL ARITHMETIC AT THE SELECTED MODULATOR FILTER INTERFACE AIN(– ) - (CALIBRATIONS) DATA RATE CHOP CHOP f /2 f /2 MCLK MCLK Figure 13. Channel Signal Chain Diagram with Chopping Enabled Multiplexer, Conversion, and Data Output Timing channel conversion cycle is finished. If in Continuous Conversion The specified “Conversion Time” includes one or two “Settling” mode, the part will automatically continue with a conversion and “Sampling” periods and a “Scaling” time. cycle on the next enabled channel. With chopping enabled (Figure 14), a conversion cycle starts Note, that every channel can be configured independently for with a “Settling” time of 43 or 44 MCLK cycles (~7 µs with conversion time and chopping mode. The overall cycle and effec- 6.144 MHz MCLK) to allow the circuits following the multiplexer tive per channel data rate depends on all enabled channel settings. to settle. Then the sigma-delta modulator samples the analog Frequency Response signals, and the digital filter processes the digital data stream. The sigma-delta modulator runs at 1/2 of MCLK frequency, The “Sampling” time depends on FW, i.e., on the Channel which is effectively the sampling frequency. Therefore, the Conversion Time register contents. After another “Settling” of Nyquist frequency is 1/4 of the MCLK frequency. The digital 42 MCLK cycles (~6.8 µs), the “Sampling” time is repeated filter, in association with the modulator, features frequency with a reversed (chopped) analog input signal. Then, during the response of a first order low-pass filter. The –3 dB point is close “Scaling” time of 163 MCLK cycles (~26.5 µs), the two results to the frequency of 1/Channel Conversion Time. The roll-off is from the digital filter are averaged, scaled using the Calibration –20 dB/dec up to the Nyquist frequency. If chopping is enabled, registers, and written into the Channel Data register. the input signal is resampled by chopping. Therefore, the over- With chopping disabled (Figure 15), there is only one “Sampling” all frequency response features notches close to the frequency of time preceded by a “Settling” time of 43 or 44 MCLK cycles 1/Channel Conversion Time. The top envelope is again the and followed by a “Scaling” time of 163 MCLK cycles. ADC response of –20 dB/dec. The RDY pin goes high during the “Scaling time” regardless of The typical frequency response plots are in Figure 16. The plots its previous state. The relevant RDY bit is set in the ADC Sta- are normalized to 1/Channel Conversion Time. tus register, and in the Channel Status register the RDY pin goes low when the Channel Data register is updated and the -CHANNEL 0 +CHANNEL 1 -CHANNEL 1 +CHANNEL 2 MULTIPLEXER RDY SETTLING SAMPLING SETTLING SAMPLING SCALING TIME TIME TIME TIME TIME CONVERSION TIME Figure 14. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled +CHANNEL 0 +CHANNEL 1 +CHANNEL 2 MULTIPLEXER RDY SETTLING SAMPLING SCALING TIME TIME TIME CONVERSION TIME Figure 15. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled –24– REV. 0 AD7738 0 0 –10 –10 CHOP = 0 CHOP = 1 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 0.1 1 10 100 1000 0.1 1 10 NORMALIZED INPUT FREQUENCY NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY � CONVERSION TIME) (INPUT FREQUENCY � CONVERSION TIME) b. Chopping Disabled a. Chopping Enabled Figure 16. Typical ADC Frequency Response Analog Inputs Voltage Range Table XIII. Input Voltage Range �1.25 V, 16 Bits, CLAMP = 0 The absolute input voltage range with input the buffer enabled is restricted from AGND + 200 mV to AV – 300 mV, which DD Input (V) Data (Hex) SIGN OVR also places restrictions on the common-mode range. Care must be taken in setting up the common-mode voltage and input +1.45000 147B 0 1 voltage range so that these limits are not exceeded, otherwise +1.25008 0001 0 1 there will be degradation in linearity performance. +1.25004 0000 0 1 +1.25000 FFFF 0 0 The analog inputs on the AD7738 can accept either unipolar or +0.00004 8001 0 0 bipolar input voltage ranges. Bipolar input ranges do not imply 0.00000 8000 0 0 that the part can handle negative voltages with respect to system –0.00004 7FFF 1 0 ground on its analog inputs. Unipolar and bipolar signals on the –1.25000 0000 1 0 AIN(+) input are referenced to the voltage on the respective –1.25004 FFFF 1 1 AIN(–) input. –1.25008 FFFE 1 1 For example, if AINCOM is 2.5 V and CH0 is configured to –1.45000 EB85 1 1 measure AIN0 – AINCOM, 0 V to 1.25 V, the input voltage range on the AIN0 input is 2.5 V to 3.75 V. If CH0 is config- ured to measure AIN0 – AINCOM, ±1.25 V, the input voltage Table XIV. Input Voltage Range 0 V to 1.25 V, 16 Bits, range on the AIN0 input is 1.25 V to 3.75 V. CLAMP = 0 Analog Inputs Extended Voltage Range Input (V) Data (Hex) SIGN OVR The AD7738 output data code span corresponds to the nominal input voltage range. However, the correct operation of the ADC 1.45000 28F5 0 1 is guaranteed within the min/max input voltage range. 1.25004 0001 0 1 1.25002 0000 0 1 When the CLAMP bit of the Mode register is set to 1, the 1.25000 FFFF 0 0 Channel Data register will be digitally clamped either to all 0.00002 0001 0 0 zeros or all ones when the analog input voltage goes outside 0.00000 0000 0 0 the nominal input voltage range. –0.00002 0000 1 1 As shown in Tables XIII and XIV, when CLAMP = 0, the data reflect the analog input voltage outside the nominal voltage range. In this case, the SIGN and OVR bits in the Channel Status register should be considered along with the Data register value to decode the actual conversion result. REV. 0 –25– GAIN – dB GAIN – dB AD7738 Voltage Reference Inputs Reference Detect The AD7738’s reference inputs, REFIN(+) and REFIN(–), The AD7738 includes on-chip circuitry to detect if the part has provide a differential reference input capability. The common- a valid reference for conversions. mode range for these differential inputs is from AGND to AV . DD If the voltage between the REFIN(+) and REFIN(–) pins goes The nominal reference voltage for specified operation is 2.5 V. below the NOREF Trigger Voltage (0.5 V typ) and the AD7738 is Both reference inputs feature a high impedance, dynamic load. performing conversion, the NOREF bit in the Channel Status Because the input impedance on each reference input is dynamic, register is set. external resistance/capacitance combinations may result in gain I/O Port errors on the part. The AD7738 Pin SYNC/P1 can be used as a general-purpose The output noise performance outlined in Tables I to VI is for digital I/O pin or to synchronize the AD7738 with other devices an analog input of 0 V and is unaffected by noise on the reference. in the system. When the SYNC bit in the I/O Port register is set To obtain the same noise performance as shown in the noise tables and the SYNC pin is low, the AD7738 doesn’t process any over the full input range requires a low noise reference source for conversion. If it is put into single conversion mode, Continuous the AD7738. If the reference noise in the bandwidth of interest Conversion mode, or any Calibration mode, the AD7738 waits is excessive, it will degrade the performance of the AD7738. until the SYNC pin goes high and then starts operation. This Recommended reference voltage sources for the AD7738 include allows the user to start conversion from a known point in time, the ADR421, AD780, REF43, and REF192. It is generally i.e., the rising edge of the SYNC pin. recommended to decouple the output of these references to further reduce the noise level. AV DV DD DD MUXOUT - ADCIN + + 10�F 0.1�F 0.1�F 10�F AV DV DD DD 6.144MHz MCLKIN 20� AIN0 CLOCK GENERATOR 0.1�F MCLKOUT 33pF 33pF ANALOG INPUTS 24-BIT MUX �-� ADC DV BUFFER DD 20� AIN7 RESET 0.1�F SCLK 20� SERIAL AINCOM DIN INTERFACE HOST 0.1�F AD7738 AND DOUT SYSTEM AV DD CONTROL VIN VOUT REFIN(+) LOGIC RDY ADR421 CS REFIN(–) + 10�F 0.1�F 0.1�F GND AGND DGND Figure 17. Typical Connection for the AD7738 Application –26– REV. 0 AD7738 CALIBRATION ADC Zero-Scale Self-Calibration The AD7738 provides zero-scale self-calibration, and zero and The ADC Zero-Scale Self-Calibration can effectively remove full system calibration capability, which can effectively reduce the offset error in Chopping Disabled mode. If repeated after a the offset error and gain error to the order of the noise. After temperature change, it can also remove the offset drift error in each conversion, the ADC conversion result is scaled using the Chopping Disabled mode. ADC Calibration Registers and the relevant Channel Calibration The zero-scale self-calibration is performed on internally shorted registers before being written to the Data register. See the equa- ADC inputs. The negative Analog Input terminal on the selected tions shown below. channel is used to set the ADC ZS Calibration common mode. For unipolar ranges: Therefore, either the negative terminal on selected differential pair or AINCOM on single-ended channel configuration should be Data = ((ADC result – ADC ZS Cal. reg.) � ADC FS reg./ driven to a proper commwon-mode voltage. 200000h – Ch. ZS Cal. reg.) � Ch. FS Cal. reg./200000h It is strongly recommended that the ADC ZS Calibration register For bipolar ranges: should only be updated as part of a zero-scale self-calibration. Data = ((ADC result – ADC ZS Cal. reg.) � ADC FS reg./ Per Channel System Calibration 400000h + 800000h – Ch. ZS Cal. reg.) � Ch. FS Cal. reg./ If the per channel system calibrations are used, these should be 200000h initiated in the following order: first a Channel ZS System Cali- Where the ADC result is in the range of 0 to FFFFFFh. bration followed by a Channel FS System Calibration. Note that the Channel ZS Calibration register has the format of The System Calibration is affected by the ADC ZS and FS Cali- a sign bit + 22 bits Channel offset value. bration registers; therefore, if both Self-Calibration and System Calibration are used in a system, an ADC Self-Calibration cycle It is strongly recommended that the user does not change the should be performed first followed by a System Calibration cycle. ADC FS register. While executing a system calibration, the fully settled system To start any calibration, write the relevant mode bits to the zero-scale voltage signal or system full-scale voltage signal must AD7738 Mode register. After the calibration is complete, the be connected to the selected channel analog inputs. contents of the corresponding Calibration registers are updated, all RDY bits in the ADC Status register are set, the RDY pin goes The per channel Calibration registers can be read, stored, or low, and the AD7738 reverts to Idle mode. modified and written back to the AD7738. Note, when writing the Calibration registers the AD7738 must be in the idle mode. The calibration duration is the same as conversion time configured Note that outside the specified calibration range, the calibration on the selected channel. The longer conversion time gives less is possible but the performance may degrade. (See the System noise and yields a more exact calibration. Therefore, use at least Calibration section in the specification pages of this data sheet.) the default conversion time to initiate any calibration. REV. 0 –27– AD7738 OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) Dimensions shown in millimeters 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8� 0.75 0.30 0.20 0� 0.60 0.19 COPLANARITY SEATING 0.09 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153AE –28– REV. 0 PRINTED IN U.S.A. C03072–0–11/02(0)