ANALOG DEVICES AD7734

DIN 4-Channel, ±10 V Input Range, High Throughput, 24-Bit ∑-∆ ADC AD7734 FEATURES FUNCTIONAL BLOCK DIAGRAM High resolution ADC REFIN(–) REFIN(+) 24 bits no missing codes AIN0 REFERENCE ±0.0025% nonlinearity DETECT Optimized for fast channel switching AIN1 BUFFER 18-bit p-p resolution (21 bits effective) at 500 Hz MUX 16-bit p-p resolution (19 bits effective) at 2 kHz 24-BIT AIN2 Σ−∆ ADC 14-bit p-p resolution (18 bits effective) at 15 kHz On-chip per channel system calibration AIN3 4 single-ended analog inputs AD7734 Input ranges +5 V, ±5 V, +10 V, ±10 V BIASHI Overvoltage tolerant BIASLO SCLK Up to ±16.5 V not affecting adjacent channel DOUT CALIBRATION SERIAL Up to ±50 V absolute maximum CIRCUITRY INTERFACE 3-wire serial interface CS SPI™, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on logic inputs P0 RDY CLOCK CONTROL I/O PORT Single-supply operation GENERATOR LOGIC RESET SYNC/P1 5 V analog supply 3 V or 5 V digital supply AGND AV MCLKOUT MCLKIN DGND DV DD DD Package: 28-lead TSSOP Figure 1. APPLICATIONS The differential reference input features “No-Reference” detect PLCs/DCS capability. The ADC also supports per channel system Multiplexing applications calibration options. The digital serial interface can be Process control configured for 3-wire operation and is compatible with Industrial instrumentation microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. GENERAL DESCRIPTION The part is specified for operation over the extended industrial The AD7734 is a high precision, high throughput analog front temperature range of –40°C to +105°C. end. True 16-bit p-p resolution is achievable with a total conversion time of 500 µs (2 kHz channel switching), making it Other parts in the AD7734 family are the AD7732 and ideally suitable for high resolution multiplexing applications. the AD7738. The part can be configured via a simple digital interface, which The AD7732 is similar to AD7734, but its analog front end allows users to balance the noise performance against data features two fully differential input channels. throughput up to a 15.4 kHz. The AD7738 analog front end is configurable for four fully The analog front end features four single-ended input channels differential or eight single-ended input channels, features with unipolar or true bipolar input ranges to ±10 V while 0.625 V to 2.5 V bipolar/unipolar input ranges, and accepts a operating from a single +5 V analog supply. The part has an common-mode input voltage from 200 mV to AVDD–300 mV. overrange and underrange detection capability and accepts an The AD7738 multiplexer output is pinned out externally, analog input overvoltage to ±16.5 V without degrading the allowing the user to implement programmable gain or signal performance of the adjacent channels. conditioning before being applied to the ADC. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7734 TABLE OF CONTENTS AD7734—Specifications.................................................................. 3 Mode Register ............................................................................. 20 Timing Specifications....................................................................... 6 Digital Interface Description ........................................................ 22 Absolute Maximum Ratings............................................................ 8 Hardware ..................................................................................... 22 Typical Performance Characteristics ............................................. 9 Reset ............................................................................................. 23 Output Noise and Resolution Specification................................ 10 Access the AD7734 Registers.................................................... 23 Chopping Enabled...................................................................... 10 Single Conversion and Reading Data ...................................... 23 Chopping Disabled..................................................................... 11 Dump Mode................................................................................ 24 Pin Configurations and Functional Descriptions ...................... 12 Continuous Conversion Mode ................................................. 24 Register Description....................................................................... 14 Continuous Read (Continuous Conversion) Mode .............. 25 Register Access............................................................................ 15 Circuit Description......................................................................... 26 Communications Register......................................................... 15 Analog Front End....................................................................... 26 I/O Port Register......................................................................... 16 Analog Input’s Extended Voltage Range ................................. 27 Revision Register ........................................................................ 16 Chopping..................................................................................... 27 Test Register ................................................................................ 16 Multiplexer, Conversion, and Data Output Timing............... 28 ADC Status Register................................................................... 17 Sigma-Delta ADC....................................................................... 28 Checksum Register..................................................................... 17 Frequency Response .................................................................. 29 ADC Zero-Scale Calibration Register ..................................... 17 Voltage Reference Inputs........................................................... 29 ADC Full-Scale Register............................................................ 17 Reference Detect......................................................................... 29 Channel Data Registers ............................................................. 17 I/O Port........................................................................................ 30 Channel Zero-Scale Calibration Registers .............................. 18 Calibration................................................................................... 30 Channel Full-Scale Calibration Registers................................ 18 ADC Zero-Scale Self-Calibration ............................................ 30 Channel Status Registers ........................................................... 18 Per Channel System Calibration .............................................. 30 Channel Setup Registers ............................................................ 19 Outline Dimensions ....................................................................... 32 Channel Conversion Time Registers ....................................... 19 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7734 AD7734—SPECIFICATIONS Table 1. (–40°C to +105°C; AV = 5 V ± 5%; DV = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS0 to BIAS3, BIASHI, REFIN(+) = 2.5 V; DD DD BIASLO, REFIN(–) = AGND; AIN Range = ±10 V; f = 6.144 MHz; unless otherwise noted.) MCLKIN Parameter Min Typ Max Unit Test Conditions/Comments ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate 372 12190 Hz Configure via Conv. Time Register 1, 2 No Missing Codes 24 Bits FW ≥ 6 (Conversion Time ≥ 165 µs) Output Noise See Table 4 Resolution See Table 5 and Table 6 1, 2 Integral Nonlinearity (INL) ±0.0010 ±0.0030 % of FSR f = 2.5 MHz MCLKIN 2 Integral Nonlinearity (INL) ±0.0025 ±0.0045 % of FSR f = 6.144 MHz MCLKIN 3 Offset Error (Unipolar, Bipolar) ±10 mV Before Calibration 1 Offset Drift vs. Temperature ±2.5 µV/°C 3 Gain Error ±0.35 % Before Calibration 1 Gain Drift vs. Temperature ±3.2 ppm of FS/°C 3 Positive Full-Scale Error ±0.5 % of FSR Before Calibration 1 Positive Full-Scale Drift vs. Temp. ±3 ppm of FS/°C 4 Bipolar Negative Full-Scale Error ±0.0050 % of FSR After Calibration Power Supply Sensitivity ±4 ±10 LSB16 At DC, AIN = 7 V, AVDD = 5 V ± 5% Channel-to-Channel Isolation 100 dB At DC, Maximum ±16.5 V AIN Voltage ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate 737 15437 Hz Configure via Conv. Time Register 1, 2 No Missing Codes 24 Bits FW ≥ 8 (Conversion Time ≥ 117 µs) Output Noise See Table 7 Resolution See Table 8 and Table 9 2 Integral Nonlinearity (INL) ±0.0025 % of FSR 5 Offset Error (Unipolar, Bipolar) ±15 mV Before Calibration Offset Drift vs. Temperature ±25 µV/°C 3 Gain Error ±0.1 % Before Calibration Gain Drift vs. Temperature ±5.3 ppm of FS/°C 3 Positive Full-Scale Error ±0.2 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp. ±4 ppm of FS/°C 4 Bipolar Negative Full-Scale Error ±0.0050 % of FSR After Calibration Power Supply Sensitivity ±4 LSB16 At DC, AIN = 7 V, AVDD = 5 V ± 5% Channel-to-Channel Isolation 100 dB At DC, Maximum ±16.5 V AIN Voltage ANALOG INPUTS 1, 6, 7 Analog Input Voltage ±10 V Range V ±10 0 V to +10 V Range 0 to +10 V ±5 V Range V ±5 0 V to +5 V Range 0 to +5 V BIASLO Voltage 0 V BIAS0 to 3, BIASHI Voltage 2.5 V 1, 8 AIN Impedance 100 124 kΩ 1, 8 AIN Pin, BIASLO Pin Impedance 87.5 108.5 kΩ Rev. 0 | Page 3 of 32 AD7734 Parameter Min Typ Max Unit Test Conditions/Comments 1, 8 BIAS0 to 3, BIASHI Pin Impedance 12.5 15.5 kΩ Input Resistor Matching 0.2 % Input Resistor Temp. Coefficient –30 ppm/°C REFERENCE INPUTS 1, 9 REFIN(+) to REFIN(–) Voltage 2.475 2.5 2.525 V NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register REFIN(+), REFIN(–) 1 Common-Mode Voltage 0 AVDD V 10 Reference Input DC Current 400 µA 1, 11 SYSTEM CALIBRATION Full-Scale Calibration Limit V +1.05 × FS Zero-Scale Calibration Limit V –1.05 × FS Input Span V 0.8 × FS 2.1 × FS LOGIC INPUTS Input Current µA ±1 Input Current CS µA CS = DVDD ±10 –40 µA CS = DGND, Internal Pull-Up Resistor Input Capacitance 5 pF 1 V 1.4 2 V DV = 5 V T+ DD 1 VT– 0.8 1.4 V DVDD = 5 V 1 VT+ – VT– 0.3 0.85 V DVDD = 5 V 1 V 0.95 2 V DV = 3 V T+ DD 1 V 0.4 1.1 V DV = 3 V T– DD 1 V – V 0.3 0.85 V DV = 3 V T+ T– DD MCLK IN ONLY Input Current µA ±10 Input Capacitance 5 pF VINL Input Low Voltage 0.8 V DVDD = 5 V VINH Input High Voltage 3.5 V DVDD = 5 V V Input Low Voltage 0.4 V DV = 3 V INL DD V Input High Voltage 2.5 V DV = 3 V INH DD 12 LOGIC OUTPUTS V Output Low Voltage 0.4 V I = 800 µA, DV = 5 V OL SINK DD V Output High Voltage 4.0 V I = 200 µA, DV = 5 V OH SOURCE DD V Output Low Voltage 0.4 V I = 100 µA, DV = 3 V OL SINK DD VOH Output High Voltage DVDD – 0.6 V ISOURCE = 100 µA, DVDD = 3 V Floating State Leakage Current µA ±1 Floating State Leakage Capacitance 3 pF P0, P1 INPUTS/OUTPUTS Levels Referenced to Analog Supplies Input Current µA ±10 V Input Low Voltage 0.8 V AV = 5 V INL DD V Input High Voltage 3.5 V AV = 5 V INH DD VOL Output Low Voltage 0.4 V ISINK = 7 mA, See Abs. Max. Ratings VOH Output High Voltage 4.0 V ISOURCE = 200 µA, AVDD = 5 V POWER REQUIREMENTS AVDD–AGND Voltage 4.75 5.25 V DVDD–DGND Voltage 4.75 5.25 V 2.70 3.60 V AV Current (Normal Mode) 13.5 15.9 mA AV = 5 V DD DD 13 DV Current (Normal Mode) 2.8 3.1 mA DV = 5 V DD DD 13 DVDD Current (Normal Mode) 1.0 1.5 mA DVDD = 3 V Rev. 0 | Page 4 of 32 AD7734 Parameter Min Typ Max Unit Test Conditions/Comments 13 Power Dissipation (Normal Mode) 85 100 mW 14 AVDD+DVDD Current (Standby Mode) 100 µA 14 Power Dissipation (Standby Mode) 525 µW 1 Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. 2 See Typical Performance Characteristics. 3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 7 The adjacent channels are not affected by AIN voltage up to ±16.5 V. 8 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ. 9 For specified performance. Part is functional with lower V . REF 10 Dynamic current charging the sigma-delta modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DV , digital inputs = 0 V or DV , P0 and P1 = 0 V or AV . DD DD DD Rev. 0 | Page 5 of 32 AD7734 TIMING SPECIFICATIONS Table 2. (AV = 5 V ± 5%; DV = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DV ; DD DD DD 1 unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments Master Clock Range 1 6.144 MHz t 50 ns SYNC Pulsewidth 1 t 500 ns RESET Pulsewidth 2 Read Operation t 0 ns CS Falling Edge to SCLK Falling Edge Setup Time 4 2 t SCLK Falling Edge to Data Valid Delay 5 0 60 ns DV of 4.75 V to 5.25 V DD 0 80 ns DVDD of 2.7 V to 3.3 V 2, 3 t5A CS Falling Edge to Data Valid Delay 0 60 ns DV of 4.75 V to 5.25 V DD 0 80 ns DV of 2.7 V to 3.3 V DD t 50 ns SCLK High Pulsewidth 6 t7 50 ns SCLK Low Pulsewidth t8 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 4 t9 10 80 ns Bus Relinquish Time after SCLK Rising Edge Write Operation t11 0 ns CS Falling Edge to SCLK Falling Edge Setup t12 30 ns Data Valid to SCLK Rising Edge Setup Time t 25 ns Data Valid after SCLK Rising Edge Hold Time 13 t 50 ns SCLK High Pulsewidth 14 t 50 ns SCLK Low Pulsewidth 15 t16 0 ns CS Rising Edge after SCLK Rising Edge Hold Time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. 2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 CS This specification is relevant only if goes low while SCLK is low. 4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Rev. 0 | Page 6 of 32 AD7734 CS t t 4 t 8 6 SCLK t 7 t 5 t t 9 5A DOUT MSB LSB Figure 2. Read Cycle Timing Diagram CS t t 11 t 16 14 SCLK t 15 t 12 t 13 DIN MSB LSB Figure 3. Write Cycle Timing Diagram I (800µA AT DV = 5V SINK DD 100µA AT DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA AT DV = 5V SOURCE DD 100µA AT DV = 3V) DD Figure 4. Load Circuit for Access Time and Bus Relinquish Time Rev. 0 | Page 7 of 32 AD7734 ABSOLUTE MAXIMUM RATINGS Table 3. T = 25°C, unless otherwise noted. A Parameter Rating AV to AGND, DV to DGND –0.3 V to +7 V DD DD AGND to DGND –0.3 V to +0.3 V AVDD to DVDD –5 V to +5 V AIN to AGND –50 V to +50 V BIAS to AGND –0.3 V to AV + 0.3 V DD REFIN+, REFIN– to AGND –0.3 V to AVDD + 0.3 V MUX0, INTBIAS to AGND –0.3 V to AV + 0.3 V DD P0, P1 Voltage to AGND –0.3 V to AV + 0.3 V DD P0, P1 Current (TMAX = 70°C) 8 mA P0, P1 Current (T = 85°C) 5 mA MAX P0, P1 Current (T = 105°C) 2.5 mA MAX Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C TSSOP Package, Power Dissipation 660 mW 97.9°C/W θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 32 AD7734 TYPICAL PERFORMANCE CHARACTERISTICS 25 300 24 MCLK = 6.144MHz CHOP = 1 250 23 22 200 21 150 20 19 100 18 50 17 16 0 –20 –15 –10 –50 510 15 20 1 2 3 45 6 7 89 10 AIN DIFFERENTIAL VOLTAGE – V FILTER WORD Figure 8. Typical INL vs. AIN Voltage, AIN Range =±10 V, Figure 5. No Missing Codes Performance, Chopping Enabled BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = O V 25 300 24 CHOP = 0 MCLK = 6.144MHz 250 23 22 200 21 150 20 19 100 18 50 17 16 0 –20 –15 –10 –50 510 15 20 1 2 3 45 6 7 89 10 FILTER WORD AIN DIFFERENTIAL VOLTAGE – V Figure 6. No Missing Codes Performance, Chopping Disabled Figure 9. Typical INL vs. AIN Voltage, AIN Range = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V 30 20 25 15 20 15 10 10 5 5 0 0 01234 567 01234 567 MCLK FREQUENCY – MHz MCLK FREQUENCY – MHz Figure 7. Typical INL vs. MCLK Frequency, Figure 10. Typical Supply Current vs. MCLK Frequency, AIN = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V Normal Operation, Converting Rev. 0 | Page 9 of 32 INL – ppm NO MISSING CODES NO MISSING CODES AV + DV CURRENT – mA INL – ppm INL – ppm DD DD AD7734 OUTPUT NOISE AND RESOLUTION SPECIFICATION frequencies and typical performance versus the channel The AD7734 can be operated with chopping enabled or conversion time and equivalent output data rate, respectively. disabled, allowing the ADC to be programmed to either optimize the throughput rate and channel switching time or to Table 4 shows the typical output rms noise. Table 5 shows the optimize the offset drift performance. Noise tables for these two typical effective resolution based on rms noise. Table 6 shows primary modes of operation are outlined below for a selection the typical output peak-to-peak resolution, representing values of output rates and settling times. for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms The AD7734 noise performance depends on the selected noise but on peak-to-peak noise. chopping mode, the filter word (FW) value, and the selected analog input range. The AD7734 noise will not vary These typical numbers are generated from 4096 data samples significantly with MCLK frequency. acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion Chopping Enabled time is selected via the channel conversion time register. The first mode, in which the AD7734 is configured with chopping enabled (CHOP = 1), provides very low noise with lower output rates. Table 4 to Table 6 show the –3 dB Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency RMS Noise Register (µs) (Hz) (Hz) (µV) 127 FFh 2686 372 200 9.6 46 AEh 999 1001 520 15.5 22 96h 499 2005 1040 22.7 17 91h 395 2534 1300 26.1 8 88h 207 4826 2500 39.2 6 86h 166 6041 3100 46.0 2 82h 82 12166 6300 120.0 Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency Input Range/Effective Resolution (Bits) Register (µs) (Hz) (Hz) ±10 V 0 V to +10 V ±5 V 0 V to +5 V 127 FFh 2686 372 200 21.0 20.0 20.0 19.0 46 AEh 999 1001 520 20.3 19.3 19.3 18.3 22 96h 499 2005 1040 19.7 18.7 18.7 17.7 17 91h 395 2534 1300 19.5 18.5 18.5 17.5 8 88h 207 4826 2500 19.0 18.0 18.0 17.0 6 86h 166 6041 3100 18.7 17.7 17.7 16.7 2 82h 82 12166 6300 17.3 16.3 16.3 15.3 Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency Input Range/Peak-to-Peak Resolution (Bits) Register (µs) (Hz) (Hz) ±10 V 0 V to +10 V ±5 V 0 V to +5 V 127 FFh 2686 372 200 18.1 17.1 17.1 16.1 46 AEh 999 1001 520 17.4 16.4 16.4 15.4 22 96h 499 2005 1040 16.9 15.9 15.9 14.9 17 91h 395 2534 1300 16.7 15.7 15.7 14.7 8 88h 207 4826 2500 16.2 15.2 15.2 14.2 6 86h 166 6041 3100 15.8 14.8 14.8 13.8 2 82h 82 12166 6300 15.0 13.4 13.4 12.4 Rev. 0 | Page 10 of 32 AD7734 Chopping Disabled representing values for which there will be no code flicker The second mode, in which the AD7734 is configured with within a 6-sigma limit. The peak-to-peak resolutions are not chopping disabled (CHOP = 0), provides faster conversion time calculated based on rms noise but on peak-to-peak noise. while still maintaining high resolution. Table 7 to Table 9 show the –3 dB frequencies and typical performance versus the These typical numbers are generated from 4096 data samples channel conversion time and equivalent output data rate, acquired in continuous conversion mode with an analog input respectively. Table 7 shows the typical output rms noise. Table 8 voltage set to 0 V and MCLK = 6.144 MHz. The conversion shows the typical effective resolution based on the rms noise. time is selected via the channel conversion time register. Table 9 shows the typical output peak-to-peak resolution, Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency RMS Noise Register (µs) (µV) (Hz) (Hz) 127 7Fh 1357 737 670 13.2 92 5Ch 992 1008 920 15.5 44 2Ch 492 2032 1850 22.7 35 23h 398 2511 2290 26.3 16 10h 200 4991 2500 39.0 8 08h 117 8545 7780 57.0 3 03h 65 15398 14000 132 Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency Input Range/Effective Resolution (Bits) Register (µs) (Hz) (Hz) ±10 V 0 V to +10 V ±5 V 0 V to +5 V 127 7Fh 1357 737 670 20.5 19.5 19.5 18.5 92 5Ch 992 1008 920 20.3 19.3 19.3 18.3 44 2Ch 492 2032 1850 19.7 18.7 18.7 17.7 35 23h 398 2511 2290 19.5 18.5 18.5 17.5 16 10h 200 4991 2500 19.0 18.0 18.0 17.0 8 08h 117 8545 7780 18.4 17.4 17.4 16.4 3 03h 65 15398 14000 17.2 16.2 16.2 15.2 Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Conversion Time Output Data Rate –3 dB Frequency Input Range/Peak-to-Peak Resolution (Bits) Register (µs) (Hz) (Hz) ±10 V 0 V to +10 V ±5 V 0 V to +5 V 127 7Fh 1357 737 670 17.6 16.6 16.6 15.6 92 5Ch 992 1008 920 17.4 16.4 16.4 15.4 44 2Ch 492 2032 1850 16.8 15.8 15.8 14.8 35 23h 398 2511 2290 16.6 15.6 15.6 14.6 16 10h 200 4991 2500 16.1 15.1 15.1 14.1 8 08h 117 8545 7780 15.5 14.5 14.5 13.5 3 03h 65 15398 14000 14.3 13.3 13.3 12.3 Rev. 0 | Page 11 of 32 AD7734 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS REFIN(–) REFIN(+) 7R AIN0 REFERENCE R=15.5kΩ DETECT BIAS0 SCLK 1 28 DGND MUX0 2 27 MCLKIN DV BUFFER DD 7R AIN1 3 26 MCLKOUT DIN R 24-BIT BIAS1 4 25 CS DOUT Σ-∆ ADC 5 24 RESET RDY 7R AIN2 MUX 6 23 AV AGND R DD AD7734 BIAS2 7 22 P0 REFIN(–) TOP VIEW AD7734 DV 7R DD (Not to Scale) SYNC/P1 8 21 REFIN(+) AIN3 R INTBIAS 9 20 BIASHI BIAS3 CS MUX0 10 19 BIASLO R SCLK BIASHI CALIBRATION SERIAL BIAS0 11 18 BIAS3 7R CIRCUITRY INTERFACE DIN BIASLO AIN0 12 17 AIN3 DOUT INTBIAS AIN1 13 16 AIN2 AV DD BIAS1 14 15 BIAS2 P0 RESET CLOCK CONTROL I/O PORT Figure 11. 28-Lead TSSOP GENERATOR LOGIC SYNC/P1 RDY AGND AV MCLKOUT MCLKIN DGND DV DD DD Figure 12. Block Diagram Table 10. Pin Function Descriptions—28-Lead TSSOP Pin No. Mnemonic Description 1 SCLK Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7734. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected. 3 MCLKOUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLK OUT is capable of driving one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7734 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AVDD Analog Positive Supply Voltage. 5 V to AGND nominal. 7 P0 Digital Input/Output. The pin direction is determined by the P0 DIR bit; the digital value can be read/written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input, the pin should be tied high or low. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the SYNC bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7734 modulator and digital filter with other devices in the system. The digital voltage is referenced to analog supplies. When configured as an input, the pin should be tied high or low. Rev. 0 | Page 12 of 32 AD7734 Pin No. Mnemonic Description 9 INTBIAS This pin provides direct access to the analog input’s common node, bypassing the input resistor divider. In normal circuit configuration, this pin is left open circuit. 10 MUX0 This pin provides direct access to the multiplexer input of Channel 0, bypassing the input resistor divider. The input voltage range is 0 V to +0.625 V, ±0.625 V, 0 V to +1.25 V, or ±1.25 V referenced to the INTBIAS pin. In normal circuit configuration, this pin is left open circuit. 11, 14, 15, 18 BIAS0–BIAS3 These inputs are used to level shift the analog inputs. These signals are used to ensure that the differential signal seen by the internal buffer amplifier is within its common- mode range. The BIAS0 to BIAS3 pins will normally be connected to 2.5 V. 12, 13, 16, 17 AIN0–AIN3 Analog Inputs. 19 BIASLO BIASLO, in association with BIASHI, is used to set the analog input common-mode voltage. Assuming the BIAS0 to BIAS3 and BIASHI pins are connected to 2.5 V, the analog input voltages are referenced to the voltage at BIASLO. In normal circuit configuration, this pin should be connected to 0 V. 20 BIASHI BIASHI, in association with BIASLO, is used to set the analog input common-mode voltage. In normal circuit configuration, this pin should be connected to 2.5 V. 21 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. 22 REFIN(–) Negative Terminal of the Differential Reference Input. REFIN(–) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. 23 AGND Ground Reference Point for Analog Circuitry. 24 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available, according to the RDYFN bit in the I/O port register. In calibration mode, a falling edge on this output indicates that calibration is complete (see the Digital Interface Description section for more details). 25 DOUT Serial data output with serial data being read from the output shift register on the part. This output shift register can contain information from any AD7734 register, depending on the address bits of the communications register. 26 DIN Serial data input (Schmitt triggered) with serial data being written to the input shift register on the part. Data from this input shift register is transferred to any AD7734 register, depending on the address bits of the communications register 27 DVDD Digital Supply Voltage, 3 V or 5 V Nominal. 28 DGND Ground Reference Point for Digital Circuitry. Rev. 0 | Page 13 of 32 AD7734 REGISTER DESCRIPTION Table 11. Register Summary Register Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Default Value Communications 00 W 0 R/W 6-Bit Register Address I/O Port 01 R/W P0 P1 P0 DIR P1 DIR RDYFN 0 0 SYNC P0 Pin P1 Pin 1 1 0 0 0 0 Revision 02 R Chip Revision Code Chip Generic Code x x x x 0 0 1 0 Test 03 R/W 24-Bit Manufacturing Test Register ADC Status 04 R – – – – RDY3 RDY2 RDY1 RDY0 0 0 0 0 0 0 0 0 Checksum 05 R/W 16-Bit Checksum Register ADC Zero-Scale Calibration 06 R/W 24-Bit ADC Zero-Scale Calibration Register 800000h ADC Full-Scale 07 R/W 24-Bit ADC Full-Scale Register 800000h 1 Channel Data 08–0B R 16-/24-Bit Data Registers 8000h 1 Channel Zero-Scale Cal. 10–13 R/W 24-Bit Channel Zero-Scale Calibration Registers 800000h 1 Channel Full-Scale Cal. 18–1B R/W 24-Bit Channel Full-Scale Calibration Registers 200000h 1 Channel Status 20–23 R 0 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Channel Number 0 0 0 0 0 1 Channel Setup 28–2B R/W 0 0 0 Stat OPT ENABLE 0 RNG1 RNG0 0 0 0 0 0 0 0 0 1 Channel Conversion Time 30–33 R/W CHOP FW (7-Bit Filter Word) 1 11h 2 Mode 38–3B R/W MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP 0 0 0 0 0 0 0 0 1 The two LSBs of the register address, i.e., Bit 1 and Bit 0 in the communication register, specify the channel number of the register being accessed. 2 There is only one mode register, although the mode register can be accessed in one of four address locations. The address used to write the mode register specifies the ADC channel on which the mode will be applied. Only address 38h must be used for reading from the mode register. Table 12. Operational Mode Summary Table 13. Input Range Summary MD2 MD1 MD0 Mode RNG1 RNG0 Nominal Input Voltage Range 0 0 0 Idle Mode 0 0 ±10 V 0 0 1 Continuous Conversion Mode 0 1 0 V to +10 V 0 1 0 Single Conversion Mode 1 0 ±5 V 0 1 1 Power-Down (Standby) Mode 1 1 0 V to +5 V 1 0 0 ADC Zero-Scale Self-Calibration 1 0 1 For Future Use 1 1 0 Channel Zero-Scale System Calibration 1 1 1 Channel Full-Scale System Calibration Rev. 0 | Page 14 of 32 AD7734 Register Access the communications register determines whether the The AD7734 is configurable through a series of registers. Some subsequent operation will be a read or write and to which of them configure and control general AD7734 features, while register this operation will be directed. The digital interface others are specific to each channel. The register data widths defaults to expect write operation to the communications vary from 8 bits to 24 bits. All registers are accessed through the register after power-on, after reset, or after the subsequent read communications register, i.e., any communication to the or write operation to the selected register is complete. If the AD7734 must start with a write to the communications register interface sequence is lost, the part can be reset by writing at specifying which register will be subsequently read or written. CS least 32 serial clock cycles with DIN high and low. (Note that all of the parts, including the modulator, filter, interface, and all Communications Register registers are reset in this case.) Remember to keep DIN low 8 Bits, Write-Only Register, Address 00h while reading 32 bits or more either in continuous read mode or with the DUMP bit and “24/16” bit in the mode register set. All communications to the part must start with a write operation to the communications register. The data written to Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 R/W 6-Bit Register Address Bit Mnemonic Description 7 0 This bit must be 0 for proper operation. 6 R/W A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates that the next operation will be a read from a specified register. 5–0 Address Address specifying to which register the read or write operation will be directed. For channel specific registers, two LSBs, i.e., Bit 1 and Bit 0, specify the channel number. When the subsequent operation writes to the Mode register, two LSBs specify the channel selected for operation determined by the mode register value (see Table 14). Table 14. Bit 2 Bit 1 Bit 0 Channel Input 0 0 0 0 AIN0 0 0 1 1 AIN1 0 1 0 2 AIN2 0 1 1 3 AIN3 Rev. 0 | Page 15 of 32 AD7734 I/O Port Register 8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value × 40h The bits in this register are used to configure and access the digital I/O port on the AD7734. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic P0 P1 P0 DIR P1 DIR RDYFN 0 0 SYNC Default P0 Pin P1 Pin 1 1 0 0 0 0 Bit Mnemonic Description 7, 6 P0, P1 When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins’ output level. When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins. 5, 4 P0 DIR, P1 DIR These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the corresponding pin will be an input; when reset to 0, the corresponding pin will be an output. 3 RDYFN This bit is used to control the function of the RDY pin on the AD7734. When this bit is reset to 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. 2, 1 0 These bits must be 0 for proper operation. 0 SYNC This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC bit is set to 1, the SYNC pin can be used to synchronize the AD7734 modulator and digital filter with other devices in the system. Revision Register 8 Bits, Read-Only Register, Address 02h, Default Value 02h + Chip Revision × 10h Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Chip Revision Code Chip Generic Code Default x x x x 0 0 1 0 Bit Mnemonic Description 7–4 Chip Revision Code 4-Bit Factory Chip Revision Code 3–0 Chip Generic Code On the AD7734, these bits will read back as 02h. Test Register 24 Bits, Read/Write Register, Address 03h This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register. Rev. 0 | Page 16 of 32 AD7734 ADC Status Register 8 Bits, Read-Only Register, Address 04h, Default Value 00h In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel data register. Writing to the mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0 bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic – – – – RDY3 RDY2 RDY1 RDY0 Default 0 0 0 0 0 0 0 0 Checksum Register Channel Data Registers 16 Bits, Read/Write Register, Address 05h 16 Bit/24 Bit, Read-Only Registers, Address 08h–0Bh, Default Width 16 Bits, Default Value 8000h This register is described in the Using the AD7734/AD7734/AD7738 Checksum Register application note These registers contain the most up-to-date conversion results (www.analog.com/UploadedFiles/Application_Notes/71751876 corresponding to each analog input channel. The 16-bit or 24- AN626_0.pdf). bit data width can be configured by setting the 24/16 bit in the mode register. The relevant RDY bit in the channel status ADC Zero-Scale Calibration Register register goes high when the result is updated. The RDY bit will return low once the data register reading has begun. The RDY 24 Bits, Read/Write Register, Address 06h, Default Value 800000h pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any The register holds the ADC zero-scale calibration coefficient. channel data register read operation is in progress when a new The value in this register is used in conjunction with the value result is updated, no update of the data register will occur. This in the ADC full-scale calibration register and the corresponding avoids having corrupted data. Reading the status registers can channel zero-scale and channel full-scale calibration registers to be associated with reading the data registers in the dump mode. scale digitally all channels’ conversion results. The value in this Reading the status registers is always associated with reading register is updated automatically following the execution of an the data registers in the continuous read mode (see the Digital ADC zero-scale self-calibration. Writing this register is Interface Description section for more details). possible in the idle mode only (see the Calibration section for more details). ADC Full-Scale Register 24 Bits, Read/Write Register, Address 07h, Default Value 800000h This register holds the ADC full-scale coefficient. The user is advised not to change the default configuration of this register. Rev. 0 | Page 17 of 32 AD7734 Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 10h–13h, Default Value 24 Bits, Read/Write Registers, Address 18h–1Bh, Default Value 800000h 200000h These registers hold the particular channel zero-scale These registers hold the particular channel full-scale calibration calibration coefficients. The value in these registers is used in coefficients. The value in these registers is used in conjunction conjunction with the value in the corresponding channel full- with the value in the corresponding channel zero-scale scale calibration register, the ADC zero-scale calibration calibration register, the ADC zero-scale calibration register, and register, and the ADC full-scale register to digitally scale the the ADC full-scale register to digitally scale the particular particular channel conversion results. The value in this register channel conversion results. The value in this register is updated is updated automatically following the execution of a channel automatically following the execution of a channel full-scale zero-scale system calibration. system calibration. Writing this register is possible in the idle mode only (see the Calibration section for more details). The format of the channel zero-scale calibration register is a sign bit and 22 bits unsigned value. Writing this register is possible in the idle mode only (see the Calibration section for more details). Channel Status Registers 8 Bits, Read-Only Register, Address 20h–23h, Default Value 20h × Channel Number These registers contain individual channel status information and some general AD7734 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for more details). Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Default Channel Number 0 0 0 0 0 Bit Mnemonic Description 7–5 CH1–CH0 These bits reflect the channel number. This can be used for current channel identification and easier operation of the dump mode and continuous read mode. 4 0/P0 When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a zero. When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an input or an output. 3 RDY/P1 When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the state of the P1 pin, whether it is configured as an input or an output. 2 NOREF This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than NOREF, the trigger voltage and a conversion is executed, then the NOREF bit goes to 1. 1 SIGN The voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage. 0 OVR This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage Range section). Rev. 0 | Page 18 of 32 AD7734 Channel Setup Registers 8 Bits, Read/Write Register, Address 28h–2Bh, Default Value 00h These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic 0 0 0 Stat OPT ENABLE 0 RNG1 RNG0 Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7–5 0 These bits must be 0 for proper operation. 4 Stat OPT Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register. 3 ENABLE Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single conversion will take place regardless of this bit’s value. 2 0 This bit must be 0 for proper operation. 1–0 RNG1–RNG0 This is the channel input voltage range (see Table 15). Table 15. RNG1 RNG0 Nominal Input Voltage Range 0 0 ±10 V 0 1 0 V to +10 V 1 0 ±5 V 1 1 0 V to +5 V Channel Conversion Time Registers 8 Bits, Read/Write Register, Address 30h–33h, Default Value 91h The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CHOP FW (7-Bit Filter Word) Default 1 11h Bit Mnemonic Description 7 CHOP Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel. 6–0 FW CHOP = 1, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 128 + 248)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 1, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 128 + 249)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 0, single conversion or continuous conversion with one channel enabled. Conversion Time (µs) = (FW × 64 + 206)/MCLK Frequency (MHz), the FW range is 3 to 127. CHOP = 0, continuous conversion with two or more channels enabled. Conversion Time (µs) = (FW × 64 + 207)/MCLK Frequency (MHz), the FW range is 3 to 127. Rev. 0 | Page 19 of 32 AD7734 Mode Register 8 Bits, Read/Write Register, Address 38h–3Bh, Default Value 00h The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. RDY The AD7734 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. Only the address 38h must be used for reading from the mode register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7–5 MD2–MD0 Mode Bits. These three bits determine the AD7734 operation mode. Writing a new value to the mode bits will exit the part from the mode in which it has been operating and place it in the newly requested mode immediately. The function of the mode bits is described in more detail below. 4 CLKDIS Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7734 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7734 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7734 digital interface can still be accessed using the SCLK pin. 3 DUMP DUMP Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communication register. The continuous read mode will always be dump mode reading of the channel status and data register, regardless of the dump bit value (see the Digital Interface Description section for more details). 2 Cont RD When this bit is set to 1, the AD7734 will operate in the continuous read mode (see the Digital Interface Description section for more details). 1 24/16 BIT The Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide. When set to 0, the channel data registers will be 16 bits wide. 0 CLAMP This bit determines the channel data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped either to all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the Analog Input’s Extended Voltage Range section). MD2 MD1 MD0 Mode Address Used for Mode Register Write Specifies: 0 0 0 Idle Mode 0 0 1 Continuous Conversion Mode The First Channel to Start Converting 0 1 0 Single Conversion Mode Channel to Convert 0 1 1 Power-Down (Standby) Mode 1 0 0 ADC Zero-Scale Self-Calibration Channel Conversion Time Used for the ADC Self-Calibration 1 0 1 For Future Use 1 1 0 Channel Zero-Scale System Calibration Channel to Calibrate 1 1 1 Channel Full-Scale System Calibration Channel to Calibrate Rev. 0 | Page 20 of 32 AD7734 MD2 MD1 MD0 Operating Mode 0 0 0 Idle Mode The default mode after power-on or reset. The AD7734 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 Continuous Conversion Mode The AD7734 performs a conversion on the specified channel. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7734 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time registers. 0 1 0 Single Conversion Mode The AD7734 performs a conversion on the specified channel. After the conversion is complete, the relevant channel RDY data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 Power-Down (Standby) Mode The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7734 digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not affected by the power-down (standby) mode. 1 0 0 ADC Zero-Scale Self-Calibration Mode A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the RDY ADC status register are set, the pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. 1 0 1 For Future Use. 1 1 0 Channel Zero-Scale System Calibration Mode A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be provided at the AD7734 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. 1 1 1 Channel Full-Scale System Calibration Mode A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7734 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all RDY RDY bits in the ADC status register are set, the pin goes low, the MD2–MD0 bits are reset, and the AD7734 returns to idle mode. Rev. 0 | Page 21 of 32 AD7734 DIGITAL INTERFACE DESCRIPTION The RESET pin can be used to reset the AD7734. When not Hardware used, connect this pin to DVDD. The AD7734 serial interface can be connected to the host device The AD7734 interface can be reduced to just two wires via the serial interface in several different ways. connecting the DIN and DOUT pins to a single bidirectional The CS pin can be used to select the AD7734 as one of several data line. The second signal in this 2-wire configuration is the circuits connected to the host serial interface. When is high, CS SCLK signal. The host system should change the data line direction with reference to the AD7734 timing specification the AD7734 ignores the SCLK and DIN signals and the DOUT (see the Bus Relinquish Time in Table 2). The AD7734 cannot pin goes to the high impedance state. When the CS signal is not operate in the continuous read mode in 2-wire serial interface used, connect the pin to DGND. CS configuration. The RDY pin can be polled for high-to-low transition or can All the digital interface inputs are Schmitt-Triggered; therefore, drive the host device interrupt input to indicate that the the AD7734 interface features higher noise immunity and can AD7734 has finished the selected operation and/or new data be easily isolated from the host system via optocouplers. from the AD7734 is available. The host system can also wait a Figure 13, Figure 14, and Figure 15 outline some of the possible designated time after a given command is written to the device host device interfaces: SPI without using the CS signal before reading. Alternatively, the AD7734 status can be polled. (Figure 13), a DSP interface (Figure 14), and a 2-wire When the RDY pin is not used in the system, it should be left as configuration (Figure 15). an open circuit. (Note that the pin is always an active RDY digital output, i.e., it never goes into a high impedance state.) DV DV DV DD DD DD AD7734 68HC11 AD7734 8xC51 RESET SS RESET SCLK SCK SCLK P3.1/TXD MISO P3.0/RXD DOUT DOUT MOSI DIN DIN INT RDY CS CS DGND DGND Figure 13. AD7734 to Host Device Interface, SPI Figure 15. AD7734 to Host Device Interface, 2-Wire Configuration DV DD AD7734 ADSP-2105 RESET SCLK SCLK DR DOUT DIN DT INT RDY CS TFS RFS Figure 14. AD7734 to Host Device Interface, DSP Rev. 0 | Page 22 of 32 AD7734 Reset CS The AD7734 can be reset by the RESET pin or by writing a reset SCLK sequence to the AD7734 serial interface. DIN The reset sequence is N × 0 + 32 × 1, which could be the data DOUT sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented WRITE READ interface. The AD7734 also features a power-on reset with a COMMUNICATIONS ADC STATUS trip point of 2 V and goes to the defined default state after REGISTER REGISTER power-on. Figure 16. Serial Interface Signals—Registers Access It is the system designer’s responsibility to prevent an unwanted Single Conversion and Reading Data write operation to the AD7734. The unwanted write operation could happen when a spurious clock appears on the SCLK while When the mode register is being written, the ADC status byte is the CS pin is low. It should be noted that on system power-on, if cleared and the pin goes high, regardless of its previous RDY the AD7734 interface signals are floating or undefined, the part state. When the single conversion command is written to the can be inadvertently configured into an unknown state. This mode register, the ADC starts the conversion on the channel could be easily overcome by initiating either a hardware reset selected by the address of the mode register. After the event or a 32 ones reset sequence as the first step in the system conversion is completed, the data register is updated, the mode configuration. register is changed to idle mode, the relevant RDY bit is set, and the pin goes low. The RDY bit is reset and the pin RDY RDY Access the AD7734 Registers returns high when the relevant channel data register is being read. All communications to the part start with a write operation to the communications register followed by either reading or Figure 17 shows the digital interface signals executing a single writing the addressed register. conversion on Channel 0, waiting for the pin to go low, RDY In a simultaneous read-write interface (such as SPI), write 0 to and reading the Channel 0 data register. the AD7734 while reading data. Figure 16 shows the AD7734 interface read sequence for the ADC status register. CS SCLK DIN 38h 40h 48h (00h) (00h) DOUT DATA DATA RDY WRITE WRITE CONVERSION TIME WRITE READ DATA REGISTER COMMUNICATIONS MODE COMMUNICATIONS REGISTER REGISTER REGISTER Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bits Data Reading Rev. 0 | Page 23 of 32 AD7734 Dump Mode The RDY bit is reset when the relevant channel data register is being read. The behavior of the pin depends on the RDY When the DUMP bit in the mode register is set to 1, the channel RDYFN bit in the I/O port register. When the RDYFN bit is 0, status register will be read immediately by a read of the channel the RDY pin goes low when any channel has unread data. When data register, regardless of whether the status or the data register the RDYFN bit is set to 1, the pin will only go low if all RDY has been addressed through the communications register. The enabled channels have unread data. DIN pin should not be high while reading 24-bit data in dump mode; otherwise, the AD7734 will be reset. If an ADC conversion result has not been read before a new ADC conversion is completed, the new result will overwrite the Figure 18 shows the digital interface signals executing a single previous one. The relevant RDY bit goes low and the pin RDY conversion on Channel 0, waiting for the RDY pin to go low, goes high for at least 163 MCLK cycles (~26.5 µs), indicating and reading the Channel 0 status register and data register in when the data register is updated, and the previous conversion the dump mode. data is lost. Continuous Conversion Mode If the data register is being read as an ADC conversion completes, the data register will not be updated with the new When the mode register is being written, the ADC status byte is result (to avoid data corruption) and the new conversion cleared and the RDY pin goes high, regardless of its previous data is lost. state. When the continuous conversion command is written to the mode register, the ADC starts conversion on the channel Figure 19 shows the digital interface signal’s sequence for the selected by the address of the mode register. continuous conversion mode with Channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the data After the conversion is complete, the relevant channel data register is read after each conversion. Figure 20 shows a similar register and channel status register are updated, the relevant sequence but with the RDYFN bit set to 1. The pin goes RDY RDY bit in the ADC status register is set, and the AD7734 continues converting on the next enabled channel. The part will low and all data registers are read after all conversions are cycle through all enabled channels until put into another mode completed. Figure 21 shows the pin when no data are read RDY or reset. The cycle period will be the sum of all enabled from the AD7734. channels’ conversion times, set by the corresponding channel conversion time registers. CS SCLK DIN 38h 48h 48h (00h) (00h) (00h) DOUT STATUS DATA DATA RDY WRITE WRITE CONVERSION TIME WRITE READ READ DATA COMMUNICATIONS MODE COMMUNICATIONS CHANNEL REGISTER REGISTER REGISTER REGISTER STATUS Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bits Data Reading, Dump Mode START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0 Rev. 0 | Page 24 of 32 AD7734 START READ READ READ READ CONTINUOUS DATA DATA DATA DATA CONVERSION CH0 CH1 CH0 CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 21. Continuous Conversion, CH0 and CH1, No Data Read CS SCLK DIN 38h 48h 48h 00h 00h 00h 00h 00h 00h DOUT STATUS DATA DATA STATUS DATA DATA RDY WRITE WRITE WRITE CONVERSION READ READ CONVERSION READ READ COMM. MODE COMM. ON CH0 CH0 CH0 ON CH1 CH1 CH1 REGISTER REGISTER REGISTER COMPLETE STATUS DATA COMPLETE STATUS DATA Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read Continuous Read (Continuous Conversion) Mode When the Cont RD bit in the mode register is set, the first write Note that the last completed conversion result is being read. of 48h to the communications register starts the continuous Therefore the RDYFN bit in the I/O port register should be 0, read mode. As shown in Figure 22, subsequent accesses to the and reading the result should always start before the next conversion is completed. part sequentially read the channel status and data registers of the last completed conversion without any further configuration The AD7734 will stay in continuous read mode as long as the of the communications register being required. DIN pin is low while the CS pin is low; therefore, write 0 to the Note that the continuous conversion bit in the mode register AD7734 while reading in continuous read mode. To exit should be set when entering the continuous read mode. continuous read mode, take the DIN pin high for at least 100 ns after a read is complete. (Write 80h to the AD7734 to exit Note that the continuous read mode is a dump mode reading of continuous reading.) the channel status and data registers regardless of the dump bit value. Use the channel bits in the channel status register to Taking the DIN pin high does not change the Cont RD bit in check/recognize which channel data is actually being the mode register. Therefore, the next write of 48h starts the shifted out. continuous read mode again. To completely stop the continuous read mode, write to the mode register to clear the Cont RD bit. Rev. 0 | Page 25 of 32 AD7734 CIRCUIT DESCRIPTION The AD7734 is a sigma-delta ADC that is intended for the If the BIAS pins are in normal configuration, the AIN pin measurement of wide dynamic range, low frequency signals in absolute voltage up to ±16.5 V does not degrade the adjacent industrial process control, instrumentation, and PLC systems. channel’s performance. An AIN absolute voltage over ±16.5 V results in current flowing through the internal protection It contains thin film resistor dividers, a multiplexer, an input diodes located behind the thin film resistors and the adjacent buffer, a sigma-delta (or charge balancing) ADC, a digital filter, channel can be affected. a clock oscillator, a digital I/O port, and a serial communications interface. The AIN pins are “overvoltage tolerant.” However, the absolute maximum AIN voltage of ±50 V must never be exceeded. Analog Front End Note that the OVR bit in the channel status register is generated The AD7734 features four single-ended analog inputs. The on- digitally from the conversion result and indicates the sigma- chip thin film resistor dividers allow ±10 V, ±5 V, 0 V to +10 V, delta modulator (nominal) overrange. The OVR bit DOES NOT and 0 V to +5 V input signals to be connected directly to the indicate exceeding the AIN pin absolute voltage limits. analog input pins. Figure 23 shows the AD7734 analog input internal structure. The resistor divider input stage is followed by the multiplexer and then by a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed PROTECTION AV DD DIODES AIN sigma-delta modulator. ±10V 7R BUFFER 108.5kΩ In normal circuit configuration, the BIAS0 to BIAS3 and MUX BIASHI pins are connected to the 2.5 V (reference) voltage 1R source and the BIASLO pin is connected to 0 V. This ensures 15.5kΩ BIAS that the differential signal seen by the internal input buffer is 2.5V 2.1875V ± 1.25V within its absolute/common-mode range of AGND + 200 mV to AVDD – 300 mV. AGND The AD7734 AIN voltage should be within the specified Figure 23. Simplified Analog Input Internal Structure nominal (up to ±10 V) input range, otherwise the performance on channel might degrade (see the Analog Input’s Extended Voltage Range section). Rev. 0 | Page 26 of 32 AD7734 Analog Input’s Extended Voltage Range Table 17. Extended Input Voltage Range, Nominal The AD7734 output data code span corresponds to the nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The Input (V) Data (hex) SIGN OVR sigma-delta modulator was designed to fully cover a ±11.6 V 11.60006 28F5 0 1 analog input voltage; outside this range, the performance might 10.00031 0001 0 1 degrade more rapidly. The adjacent channels are not affected by 10.00015 0000 0 1 up to ±16.5 V analog input voltage (Figure 8). 10.00000 FFFF 0 0 0.00015 0001 0 0 When the CLAMP bit in the mode register is set to 1, the 0.00000 0000 0 0 channel data register will be digitally clamped to either all 0s or –0.00015 0000 1 1 all 1s when the analog input voltage goes outside the nominal input voltage range. As shown in Table 16 and Table 17, when CLAMP = 0, the data Chopping reflects the analog input voltage outside the nominal voltage With chopping enabled, the multiplexer repeatedly reverses the range. In this case, the SIGN and OVR bits in the channel status register should be considered along with the data register value ADC inputs. Every output data result is then calculated as an to decode the actual conversion result. average of two conversions, the first with the positive and the second with the negative offset term included. This effectively Note that the OVR bit in the channel status register is generated removes any offset error of the input buffer and sigma-delta digitally from the conversion result and indicates the sigma- modulator. delta modulator (nominal) overrange. The OVR bit DOES NOT However, chopping is applied only behind the input resistor indicate exceeding the AIN pin’s absolute voltage limits divider stage; therefore, chopping does not eliminate the offset Table 16. Extended Input Voltage Range, Nominal error and drifts caused by the resistors. Figure 24 shows the Voltage Range ±10 V, 16 Bits, CLAMP = 0 channel signal chain with chopping enabled. Input (V) Data (hex) SIGN OVR 11.60039 147B 0 1 10.00061 0001 0 1 10.00031 0000 0 1 10.00000 FFFF 0 0 0.00031 8001 0 0 0.00000 8000 0 0 –0.00031 7FFF 1 0 –10.00000 0000 1 0 –10.00031 FFFF 1 1 –10.00061 FFFE 1 1 –11.60040 EB85 1 1 AIN MULTIPLEXER BUFFER BIAS + SCALING OUTPUT DATA Σ−∆ DIGITAL DIGITAL ARITHMETIC AT THE SELECTED MODULATOR FILTER INTERFACE - (CALIBRATIONS) DATA RATE BIASHI CHOP f /2 f /2 CHOP MCLK MCLK BIASLO Figure 24. Channel Signal Chain Diagram with Chopping Enabled Rev. 0 | Page 27 of 32 AD7734 Multiplexer, Conversion, and Data Output Timing The specified conversion time includes one or two settling and The RDY pin goes high during the scaling time, regardless of its sampling periods and a scaling time. previous state. The relevant RDY bit is set in the ADC status register and in the channel status register, and the RDY pin goes With chopping enabled (Figure 25), a conversion cycle starts low when the channel data register is updated and the channel with a settling time of 43 MCLK cycles or 44 MCLK cycles conversion cycle is finished. If in continuous conversion mode, (~7 µs with a 6.144 MHz MCLK) to allow the circuits following the part will automatically continue with a conversion cycle on the multiplexer to settle. The sigma-delta modulator then the next enabled channel. samples the analog signals and the digital filter processes the digital data stream. The sampling time depends on FW, i.e., on Note that every channel can be configured independently for the channel conversion time register contents. After another conversion time and chopping mode. The overall cycle and settling of 42 MCLK cycles (~6.8 µs), the sampling time is effective per channel data rates depend on all enabled repeated with a reversed (chopped) analog input signal. Then, channel settings. during the scaling time of 163 MCLK cycles (~26.5 µs), the two results from the digital filter are averaged, scaled using the Sigma-Delta ADC calibration registers, and written into the channel data register. The AD7734 core consists of a charge balancing sigma-delta With chopping disabled (Figure 26), there is only one sampling modulator and a digital filter. The architecture is optimized for time preceded by a settling time of 43 MCLK cycles or fast, fully settled conversion. This allows for fast channel-to- 44 MCLK cycles and followed by a scaling time of channel switching while maintaining inherently excellent 163 MCLK cycles. linearity, high resolution, and low noise. MULTIPLEXER – CHANNEL 0 + CHANNEL 1 – CHANNEL 1 RDY SETTLING SAMPLING SETTLING SAMPLING SCALING TIME TIME TIME TIME TIME CONVERSION TIME Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled MULTIPLEXER CHANNEL 0 CHANNEL 1 RDY SETTLING SAMPLING SCALING TIME TIME TIME CONVERSION TIME Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled Rev. 0 | Page 28 of 32 AD7734 Frequency Response Voltage Reference Inputs The sigma-delta modulator runs at ½ the MCLK frequency, The AD7734 has a differential reference input, REF IN(+) and which is effectively the sampling frequency. Therefore, the REF IN(–). The common-mode range for these inputs is from Nyquist frequency is ¼ the MCLK frequency. The digital filter, AGND to AV . The nominal differential reference voltage for DD in association with the modulator, features the frequency specified operation is 2.5 V. Both reference inputs feature response of a first order low-pass filter. The –3 dB point is close dynamic load. Therefore, the reference inputs should be to the frequency of 1/channel conversion time. The roll-off is connected to a low impedance reference voltage source. –20 dB/dec up to the Nyquist frequency. If chopping is enabled, External resistance/capacitance combinations may result in gain the input signal is resampled by chopping. Therefore, the overall errors on the part. frequency response features notches close to the frequency of 1/channel conversion time. The top envelope is again the ADC The output noise performance outlined in Table 4 through response of –20 dB/dec. Table 9 is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as The typical frequency response plots are given in Figure 27 shown in the noise tables over the full input range requires a and Figure 28. The plots are normalized to 1/channel low noise reference source for the AD7734. If the reference conversion time. noise in the bandwidth of interest is excessive, it will degrade 0 the performance of the AD7734. Recommended reference voltage sources for the AD7734 –10 include the AD780, ADR421, REF43, and REF192. Note that in a CHOP = 1 typical connection, the voltage reference must be capable of –20 sinking current flowing out of the BIAS pins through the internal resistors if a positive voltage is applied to the analog –30 input. The AD780 meets this requirement. If the voltage reference used in an application is not capable of sinking –40 current, an external resistor (5 kΩ) should be connected in parallel to the REFIN pins. –50 Reference Detect –60 0.1 1.0 10.0 NORMALIZED INPUT FREQUENCY The AD7734 includes on-chip circuitry to detect if the part has (INPUT FREQUENCY × CONVERSION TIME) a valid reference for conversions. If the voltage between the Figure 27. Typical ADC Frequency Response, Chopping Enabled REFIN(+) and REFIN(–) pins goes below the NOREF trigger voltage (0.5 V typ.) and the AD7734 is performing a conversion, 0 the NOREF bit in the channel status register is set. –10 CHOP = 1 –20 –30 –40 –50 –60 0.1 1.0 10.0 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY × CONVERSION TIME) Figure 28. Typical ADC Frequency Response, Chopping Disabled Rev. 0 | Page 29 of 32 GAIN – dB GAIN – dB AD7734 I/O Port duration is the same as the conversion time configured on the The AD7734 P0 pin can be used as a general-purpose digital selected channel. A longer conversion time gives less noise and I/O pin. The P1 pin ( /P1) can be used as a general- SYNC yields a more exact calibration; therefore, use at least the default purpose digital I/O pin or to synchronize the AD7734 with conversion time to initiate any calibration. other devices in the system. When the SYNC bit in the I/O port register is set and the SYNC pin is low, the AD7734 does not ADC Zero-Scale Self-Calibration process any conversion. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the The ADC zero-scale self-calibration can reduce the offset error AD7734 waits until the SYNC pin goes high and then starts in the chopping disabled mode. If repeated after a temperature operation. This allows conversion to start from a known point change, it can also reduce the offset drift error in the chopping in time, i.e., the rising edge of the pin. disabled mode. SYNC The zero-scale self-calibration is performed on internally The digital P0 and P1 voltage is referenced to the analog shorted ADC inputs. The negative analog input terminal on the supplies. When configured as inputs, the pins should be tied selected channel is used to set the ADC zero-scale calibration high or low. common mode. Therefore, either the negative terminal of the selected differential pair or the AINCOM on the single-ended Calibration channel configuration should be driven to a proper common- The AD7734 provides zero-scale self-calibration, and zero- and mode voltage. full-scale system calibration capability that can effectively It is strongly recommended that the ADC zero-scale calibration reduce the offset error and gain error to the order of the noise. register should only be updated as part of a zero-scale self- After each conversion, the ADC conversion result is scaled calibration. using the ADC calibration registers and the relevant channel calibration registers before being written to the data register. Per Channel System Calibration For unipolar ranges: If the per channel system calibrations are used, these should be Data = ((ADC result – ADC ZS Cal. reg.) initiated in the following order: a channel zero-scale system × ADC FS Reg./200000h – Ch. ZS Cal. reg.) calibration, followed by a channel full-scale system calibration. × Ch. FS Cal. reg./200000h The system calibration is affected by the ADC zero-scale and For bipolar ranges: full-scale calibration registers. Therefore, if both self-calibration and system calibration are used in the system, an ADC full-scale Data = ((ADC result – ADC ZS Cal. reg.) self-calibration should be performed first, followed by a system × ADC FS Reg./400000h + 800000h – Ch. ZS Cal. reg.) calibration cycle. × Ch. FS Cal. reg./200000h While executing a system calibration, the fully settled system Where the ADC result is in the range of 0 to FFFFFFh. zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs. Note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. The per channel calibration registers can be read, stored, or modified and written back to the AD7734. Note that when It is strongly recommended that the user not change the ADC writing the calibration registers the AD7734 must be in idle full-scale register. mode. Note that outside the specified calibration range, calibration is possible but the performance may degrade (see To start any calibration, write the relevant mode bits to the the System Calibration section in Table 1). AD7734 mode register. After the calibration is complete, the contents of the corresponding calibration registers are updated, all RDY bits in the ADC status register are set, the SYNC pin goes low, and the AD7734 reverts to idle mode. The calibration Rev. 0 | Page 30 of 32 AD7734 AV DV DD DD + + 10µF 0.1µF 0.1µF 10µF ANALOG AV DV DD DD INPUTS 7R AIN0(+) 6.144MHz 4 TO 20mA MCLKIN R=15.5kΩ BIAS0(+) 500R CLOCK GENERATOR MCLKOUT 7R AIN1 33pF 33pF 0V TO 10V R BIAS1 7R AIN2 –10V TO +10V R BIAS2 24-BIT MUX Σ-∆ ADC 7R AIN3 0V TO 5V DV R BUFFER DD BIAS3 RESET R BIASHI SCLK 7R BIASLO AD7734 SERIAL DIN INTERFACE HOST AND DOUT AV SYSTEM DD CONTROL +VIN VOUT +2.5V REFIN(+) RDY LOGIC AD780 REFIN(–) CS TEMP + + AGND DGND 10µF 0.01µF 10µF Figure 29. Typical Connections for the AD7734 Application Rev. 0 | Page 31 of 32 AD7734 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BS C 1 14 PIN 1 0.65 1.20 BSC MAX 0.15 0.10 88 0.75 0.30 0.20 08 0.60 COPLANARITY SEATING 0.19 0.09 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 30. 28-Lead This Shrink Small Outline Package [TSSOP] (RU-28)—Dimensions shown in millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 18. Ordering Guide AD7734 Products Temperature Package Package Description Package Outline AD7734BRU –40°C to +105°C TSSOP-28 RU-28 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C03071-0-2/03(0) Rev. 0 | Page 32 of 32