ANALOG DEVICES AD7731

Low Noise, High Throughput a 24-Bit Sigma-Delta ADC AD7731 FEATURES GENERAL DESCRIPTION 24-Bit Sigma-Delta ADC The AD7731 is a complete analog front-end for process control 16 Bits p-p Resolution at 800 Hz Output Rate applications. The device has a proprietary programmable gain Programmable Output Rates up to 6.4 kHz front end that allows it to accept a range of input signal ranges, Programmable Gain Front End including low level signals, directly from a transducer. The sigma- 60.0015% Nonlinearity delta architecture of the part consists of an analog modulator Buffered Differential Inputs and a low pass programmable digital filter, allowing adjustment Programmable Filter Cutoffs of filter cutoff, output rate and settling time. FASTStep™* Mode for Channel Sequencing The part features three buffered differential programmable gain Single Supply Operation analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part oper- APPLICATIONS ates from a single +5 V supply and accepts seven unipolar ana- Process Control log input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV, PLCs/DCS +320 mV, +640 mV and +1.28 V, and seven bipolar ranges: Industrial Instrumentation ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a perfor- mance level of 13 bits of peak-to-peak resolution. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM REF IN(–) AV DV REF IN(+) DD DD AD7731 NC AV DD STANDBY AIN1 SIGMA-DELTA A/D CONVERTER 100nA BUFFER AIN2 SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL AIN3 MODULATOR FILTER PGA MUX AIN4 100nA AIN5 CLOCK MCLK IN GENERATION AGND SERIAL INTERFACE AIN6 MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN DOUT AGND DGND POL RDY RESET *FASTStep is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1997 (AV = +5 V, DV = +3 V or +5 V; REF IN(+) = +2.5 V; REF IN(–) = AGND; AGND = DD DD DGND = 0 V; f = 4.9152 MHz. All specifications T to T unless otherwise noted.) AD7731–SPECIFICATIONS CLK IN MIN MAX 1 Parameter B Version Units Conditions/Comments STATIC PERFORMANCE (CHP = 0) 2 3 No Missing Codes 24 Bits min SKIP = 0 2 Output Noise and Update Rates See Tables I and II Integral Nonlinearity 15 ppm of FSR max 2 Offset Error See Note 4 Offset Error and Offset Drift Refer to Both 2 Offset Drift vs. Temperature 0.5 μV/°C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV 1/2/5 μV/°C typ Input Range = 320 mV/640 mV/1.28 V 5 Offset Drift vs. Time 2.5 μV/1000 Hr 2, 6 Positive Full-Scale Error See Note 4 2, 7, 8 Positive Full-Scale Drift vs. Temp 0.6 μV/°C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV 1.5/3/6 μV/°C typ Input Range = 320 mV/640 mV/1.28 V 5 Positive Full-Scale Drift vs. Time 3 μV/1000 Hr 2, 9 Gain Error See Note 4 2, 7, 10 Gain Drift vs. Temperature 2 ppm/°C typ 5 Gain Drift vs. Time 10 ppm/1000 Hr 2 Bipolar Negative Full-Scale Error See Note 4 2, 7 Negative Full-Scale Drift vs. Temp 1 μV/°C typ 11 Power Supply Rejection 90 dB typ Input Range = 20 mV 11 Power Supply Rejection 60 dB typ Input Range = 1.28 V 11 Common-Mode Rejection (CMR) On AIN 95 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V On REF IN 120 dB typ 2 Analog Input DC Bias Current 60 nA max 2 Analog Input DC Bias Current Drift 150 pA/°C typ 2 Analog Input DC Offset Current 30 nA max 2 Analog Input DC Offset Current Drift 100 pA/°C typ 2 STATIC PERFORMANCE (CHP = 1) No Missing Codes 24 Bits min Output Noise and Update Rates See Tables III and IV Integral Nonlinearity 15 ppm of FSR max Offset Error See Note 4 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature 5 nV/°C typ Unipolar Offset and Bipolar Zero Errors 5 Offset Drift vs. Time 25 nV/1000 Hr typ 6 Positive Full-Scale Error See Note 4 7, 8 Positive Full-Scale Drift vs. Temp 2 ppm of FS/°C max 5 Positive Full-Scale Drift vs. Time 10 ppm of FS/1000 Hr 9 Gain Error See Note 4 7, 10 Gain Drift vs. Temperature 2 ppm/°C max 5 Gain Drift vs. Time 10 ppm/1000 Hr Bipolar Negative Full-Scale Error See Note 4 Negative Full-Scale Drift vs. Temp 2 ppm of FS/°C max 11 Power Supply Rejection 110 dB typ Input Range = 20 mV 11 Power Supply Rejection 85 dB typ Input Range = 1.28 V 11 Common-Mode Rejection (CMR) On AIN 110 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V On REF IN 120 dB typ Analog Input DC Bias Current 50 nA max Analog Input DC Bias Current Drift 100 pA/°C typ Analog Input DC Offset Current 10 nA max Analog Input DC Offset Current Drift 50 pA/°C typ ANALOG INPUTS/REFERENCE INPUTS 2 Normal Mode 50 Hz/60 Hz Rejection 88 dB min 50 Hz/60 Hz ±1 Hz. SKIP = 0 2 Common-Mode 50 Hz/60 Hz Rejection 120 dB min 50 Hz/60 Hz ±1 Hz. SKIP = 0 Analog Inputs 12 Differential Input Voltage Ranges Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately 0 to +20 or ±20 mV nom RN2, RN1, RN0 of Mode Register = 0, 0, 1 0 to +40 or ±40 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 0 0 to +80 or ±80 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 1 0 to +160 or ±160 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 0 0 to +320 or ±320 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 1 0 to +640 or ±640 mV nom RN2, RN1, RN0 of Mode Register = 1, 1, 0 0 to +1.28 or ±1.28 V nom RN2, RN1, RN0 of Mode Register = 1, 1, 1 –2– REV. 0 AD7731 1 Parameter B Version Units Conditions/Comments 13 Absolute/Common-Mode Voltage AGND + 1.2 V V min AV – 0.95 V V max DD Reference Input REF IN(+) – REF IN (–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0 REF IN(+) – REF IN (–) Voltage +5 V nom HIREF Bit of Mode Register = 1 Reference DC Input Current 5.5 μA max HIREF Bit of Mode Register = 0 Reference DC Input Current 10 μA max HIREF Bit of Mode Register = 1 14 Absolute/Common-Mode Voltage AGND – 30 mV V min AV + 30 mV V max DD NO REF Trigger Voltage 0.3 V min NO REF Bit Active If VREF Below This Voltage 0.65 V max NO REF Bit Inactive If VREF Above This Voltage LOGIC INPUTS Input Current ±10 μA max All Inputs Except SCLK and MCLK IN V , Input Low Voltage 0.8 V max DV = +5 V INL DD V , Input Low Voltage 0.4 V max DV = +3 V INL DD V , Input High Voltage 2.0 V min INH SCLK Only (Schmitt Triggered Input) V 1.4/3 V min/V max DV = +5 V T+ DD V 0.95/2.5 V min/V max DV = +3 V T+ DD V 0.8/1.4 V min/V max DV = +5 V T– DD V 0.4/1.1 V min/V max DV = +3 V T– DD V – V 0.4/0.85 V min/V max DV = +5 V T+ T– DD V – V 0.4/0.8 V min/V max DV = +3 V T+ T– DD MCLK IN Only V , Input Low Voltage 0.8 V max DV = +5 V INL DD V , Input Low Voltage 0.4 V max DV = +3 V INL DD V , Input High Voltage 3.5 V min DV = +5 V INH DD V , Input High Voltage 2.5 V min DV = +3 V INH DD LOGIC OUTPUTS (Including MCLK OUT) 15 V , Output Low Voltage 0.4 V max I = 800 μA Except for MCLK OUT . OL SINK 16 V = +5 V DD 15 V , Output Low Voltage 0.4 V max I = 100 μA Except for MCLK OUT . OL SINK 16 V = +3 V DD 15 V , Output High Voltage 4.0 V min I = 200 μA Except for MCLK OUT . OH SOURCE 16 V = +5 V DD 15 V , Output High Voltage DV – 0.6 V V min I = 100 μA Except for MCLK OUT . OH DD SOURCE 16 V = +3 V DD Floating State Leakage Current ±10 μA max 3 Floating State Output Capacitance 6 pF typ 17 TRANSDUCER BURNOUT AIN1(+) Current –100 nA nom AIN1(–) Current 100 nA nom Initial Tolerance @ 25°C ±10 % typ Drift 0.1 %/°C typ SYSTEM CALIBRATION 18 Positive Full-Scale Calibration Limit 1.05 × FS V max FS Is the Nominal Full-Scale Voltage (20 mV, 40 mV, 80 mV, 160 mV, 320 mV, 640 mV, 1.28 V) 18 Negative Full-Scale Calibration Limit –1.05 × FS V max 19 Offset Calibration Limit –1.05 × FS V min 19 Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS Power Supply Voltages AV – AGND Voltage +5 V nom DD DV Voltage +2.7 to +5.25 V min to V max With AGND = 0 V DD Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV DD AV Current (Normal Mode) 10.3 mA max DD DV Current (Normal Mode) 1.7 mA max DV of 2.7 V to 3.3 V DD DD DV Current (Normal Mode) 3.2 mA max DV of 4.75 V to 5.25 V DD DD AV + DV Current (Standby Mode) 25 μA max Typically 10 μA. External MCLK IN = 0 V or DV DD DD DD Power Dissipation AV = DV = +5 V. Digital I/Ps = 0 V or DV DD DD DD Normal Mode 67.5 mW max Standby Mode 125 μW max Typically 50 μW. External MCLK IN = 0 V or DV DD REV. 0 –3– AD7731 NOTES 1 Temperature Range: –40°C to +85°C. 2 Sample tested during initial release. 3 No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits. 4 The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 μV typical. Offset numbers with CHP = 1 are typically 3 μV precalibration. Internal zero-scale calibration reduces this by about 1 μV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40 mV range, an internal full-scale calibration should be performed on the 80 mV input range with a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can be calculated from the offset and gain errors. 5 These numbers are generated during life testing of the part. 6 Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 7 Recalibration at any temperature will remove these errors. 8 Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 9 Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are positive full-scale and negative full-scale. See Terminology. 10 Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 11 Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs) between these values for the other input ranges. 12 The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input. 13 The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 14 The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed. 15 These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 16 V refers to DV for all logic outputs expect D0 and D1 where it refers to AV . In other words, the output logic high for these two outputs is determined by AV . DD DD DD DD 17 See Burnout Current section. 18 After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s. 19 These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice. (AV = +4.75 V to +5.25 V; DV = +2.7 V to +5.25 V; AGND = DGND = 0 V; DD DD 1, 2 f = 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted) TIMING CHARACTERISTICS CLK IN DD Limit at T , T MIN MAX Parameter (B Version) Units Conditions/Comments Master Clock Range 1 MHz min For Specified Performance 5 MHz max t 50 ns min SYNC Pulse Width 1 t 50 ns min RESET Pulse Width 2 Read Operation t 0 ns min RDY to CS Setup Time 3 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 4 4 3 t 0 ns min SCLK Active Edge to Data Valid Delay 5 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.7 V to +3.3 V DD 4, 5 3 t 0 ns min CS Falling Edge to Data Valid Delay 5A 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.7 V to +3.3 V DD t 100 ns min SCLK High Pulse Width 6 t 100 ns min SCLK Low Pulse Width 7 3 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 8 6 3 t 10 ns min Bus Relinquish Time after SCLK Inactive Edge 9 80 ns max 3, 7 t 100 ns max SCLK Active Edge to RDY High 10 Write Operation 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 t 100 ns min SCLK High Pulse Width 14 t 100 ns min SCLK Low Pulse Width 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 2 See Figures 15 and 16. 3 SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5 This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. –4– REV. 0 AD7731   ABSOLUTE MAXIMUM RATINGS* Plastic DIP Package, Power Dissipation ........................ 450 mW (TA = +25°C unless otherwise noted) θJA Thermal Impedance ............................................... 105°C/W AVDD to AGND .................................................. –0.3 V to +7 V Lead Temperature (Soldering, 10 sec) ............................ +260°C AVDD to DGND .................................................. –0.3 V to +7 V TSSOP Package, Power Dissipation .............................. 450 mW DVDD to AGND .................................................. –0.3 V to +7 V θJA Thermal Impedance ............................................... 128°C/W DVDD to DGND .................................................. –0.3 V to +7 V Lead Temperature, Soldering AGND to DGND ................................................ –5 V to +0.3 V Vapor Phase (60 sec) ...................................................... +215°C AVDD to DVDD ....................................................... –2 V to +5 V Infrared (15 sec) ............................................................. +220°C Analog Input Voltage to AGND ........... –0.3 V to AVDD + 0.3 V SOIC Package, Power Dissipation ................................ 450 mW Reference Input Voltage to AGND ....... –0.3 V to AVDD + 0.3 V θJA Thermal Impedance ................................................. 75°C/W AIN/REF IN Current (Indefinite) .................................... 30 mA Lead Temperature, Soldering Digital Input Voltage to DGND ............ –0.3 V to DVDD + 0.3 V Vapor Phase (60 sec) ...................................................... +215°C Digital Output Voltage to DGND ......... –0.3 V to DVDD + 0.3 V Infrared (15 sec) ............................................................ +220°C Output Voltage (D0, D1) to DGND ...... –0.3 V to AVDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause Operating Temperature Range permanent damage to the device. This is a stress rating only; functional Industrial (B Version) ....................................... –40°C to +85°C operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute Storage Temperature Range ............................ –65°C to +150°C maximum rating conditions for extended periods may affect device reliability. Junction Temperature ..................................................... +150°C ORDERING GUIDE Model (Z = RoHS) Temperature Range Package Description Package Option RoHS Compliant AD7731BN −40°C to +85°C 24-Lead PDIP N-24-1 No AD7731BNZ −40°C to +85°C 24-Lead PDIP N-24-1 Yes AD7731BR −40°C to +85°C 24-Lead SOIC_W RW-24 No AD7731BR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 No AD7731BR-REEL7 −40°C to +85°C 24-Lead SOIC_W RW-24 No AD7731BRZ −40°C to +85°C 24-Lead SOIC_W RW-24 Yes AD7731BRZ-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 Yes AD7731BRZ-REEL7 −40°C to +85°C 24-Lead SOIC_W RW-24 Yes AD7731BRU −40°C to +85°C 24-Lead TSSOP RU-24 No AD7731BRU-REEL −40°C to +85°C 24-Lead TSSOP RU-24 No AD7731BRU-REEL7 −40°C to +85°C 24-Lead TSSOP RU-24 No AD7731BRUZ −40°C to +85°C 24-Lead TSSOP RU-24 Yes AD7731BRUZ-REEL −40°C to +85°C 24-Lead TSSOP RU-24 Yes AD7731BRUZ-REEL7 −40°C to +85°C 24-Lead TSSOP RU-24 Yes EVAL-AD7731EBZ Evaluation Board Yes I (800µA AT DV = +5V SINK DD 100µA AT DV = +3V) DD TO OUTPUT +1.6V PIN 50pF I (200µA AT DV = +5V SOURCE DD 100µA AT DV = +3V) DD Figure 1. Load Circuit for Access Time and Bus Relinquish Time   ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy   electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.   REV. A       ‐5‐ AD7731 PROGRAMMABLE DIFFERENTIAL PROGRAMMABLE GAIN DIGITAL FILTER REFERENCE AMPLIFIER SIGMA-DELTA ADC BUFFER AMPLIFIER TWO STAGE FILTER THAT THE REFERENCE INPUT TO THE THE PROGRAMMABLE ALLOWS PROGRAMMING OF PART IS DIFFERENTIAL AND THE SIGMA-DELTA THE BUFFER AMPLIFIER GAIN AMPLIFIER ALLOWS OUTPUT UPDATE RATE AND PRESENTS A HIGH SEVEN UNIPOLAR AND FACILITATES RATIOMETRIC ARCHITECTURE ENSURES SETTLING TIME AND THAT IMPEDANCE INPUT STAGE OPERATION. THE REFERENCE 24 BITS NO MISSING TM SEVEN BIPOLAR INPUT HAS A FASTSTEP MODE VOLTAGE CAN BE SELECTED TO CODES. THE ENTIRE BURNOUT CURRENTS FOR THE ANALOG INPUTS RANGES FROM +20mV TO (SEE FIGURE 3) ALLOWING SIGNIFICANT +1.28V BE NOMINALLY +2.5V OR +5V. SIGMA-DELTA ADC CAN BE EXTERNAL SOURCE REFERENCE DETECT CIRCUITRY CHOPPED TO REMOVE TWO 100nA BURNOUT SEE PAGE 24 TESTS FOR OPEN OR SHORTED DRIFT ERRORS IMPEDANCES SEE PAGE 23 CURRENTS ALLOW THE REFERENCES USER TO EASILY DETECT SEE PAGE 24 SEE PAGE 23 IF A TRANSDUCER HAS SEE PAGE 24 BURNT OUT OR GONE STANDBY MODE OPEN-CIRCUIT AV DV REF IN(–) REF IN(+) DD DD THE STANDBY MODE SEE PAGE 23 REDUCES POWER CONSUMPTION TO 50mW AV DD SEE PAGE 32 STANDBY AIN1 SIGMA-DELTA A/D CONVERTER AIN2 SIGMA- PROGRAMMABLE SYNC CLOCK OSCILLATOR DELTA DIGITAL CIRCUIT AIN3/D1 MODULATOR FILTER MUX PGA AIN4/D0 THE CLOCK SOURCE FOR THE PART CAN BE PROVIDED BY BUFFER AIN5 AN EXTERNALLY-APPLIED MCLK IN CLOCK CLOCK OR BY CONNECTING A GENERATION SERIAL INTERFACE MCLK OUT CRYSTAL OR CERAMIC AIN6 AGND RESONATOR ACROSS THE AND CONTROL LOGIC CLOCK PINS REGISTER BANK SCLK SEE PAGE 31 CS CALIBRATION MICROCONTROLLER DIN SERIAL INTERFACE DOUT AD7731 SPI*-COMPATIBLE OR DSP- COMPATIBLE SERIAL INTERFACE THAT CAN BE OPERATED FROM JUST THREE AGND DGND POL WIRES. ALL FUNCTIONS ON THE RDY RESET PART (APART FROM MASTER ANALOG MULTIPLEXER RESET) CAN BE ACCESSED VIA THE SERIAL INTERFACE OUTPUT DRIVERS A DIFFERENTIAL MULTIPLEXER REGISTER BANK CALIBRATION ALLOWS SELECTION OF THREE SEE PAGE 33 MICROCONTROLLER FULLY DIFFERENTIAL PAIRS OR THE AIN3 AND AIN4 INPUT TWELVE REGISTERS CONTROL FIVE PSEUDO-DIFFERENTIAL INPUT CHANNELS CAN BE ALL FUNCTIONS ON THE PART THE AD7731 OFFERS A PAIRS TO BE SWITCHED TO THE RECONFIGURED TO BECOME AND PROVIDE STATUS NUMBER OF DIFFERENT BUFFER AMPLIFIER. THE TWO OUTPUT DIGITAL PORT INFORMATION AND CALIBRATION OPTIONS MULTIPLEXER IS CONTROLLED LINES THAT CAN BE CONVERSION RESULTS INCLUDING SELF AND VIA THE SERIAL INTERFACE PROGRAMMED OVER THE SYSTEM CALIBRATION SERIAL INTERFACE SEE PAGE 20 SEE PAGE 23 SEE PAGE 28 SEE PAGE 32 *SPI IS A TRADEMARK OF MOTOROLA, INC. Figure 2. Detailed Functional Block Diagram –6– REV. 0 AD7731 3 INPUT CHOPPING SINC FILTER SKIP MODE 22-TAP FIR FILTER THE ANALOG INPUT TO THE PART THE FIRST STAGE OF THE DIGITAL IN SKIP MODE, THERE IS NO WITH SKIP DISABLED, THE NORMAL SECOND STAGE OF FILTERING ON OPERATING MODE OF THE SECOND STAGE CAN BE CHOPPED. IN CHOPPING MODE, FILTERING ON THE PART IS THE 3 OF THE DIGITAL FILTERING ON THE PART IS 3 THE PART. THE SINC FILTER IS THE INPUT IS CHOPPEDAND THE OUTPUT OF SINC FILTER. THE OUTPUT UPDATE THE ONLY FILTERING PERFORMED A FIXED 22-TAP FIR FILTER. IN SKIP MODE, THE FIRST STAGE FILTER IS CHOPPED RATE AND BANDWIDTH OF THIS ON THE PART. THIS IS THE THIS FIR FILTER IS BYPASSED. WHEN REMOVING ERRORS IN THAT PATH. FILTER CAN BE PROGRAMMED. IN FASTSTEP™ MODE IS ENABLED AND A SECOND STAGE FILTER 3 THE DEFAULT CONDITION IS SKIP MODE, THE SINC FILTER IS STEP INPUT IS DETECTED, THE SECOND CHOPPING DISABLED THE ONLY FILTERING PERFORMED SEE PAGE 25 STAGE FILTERING IS PERFORMED BY THE ON THE P3T. SEE PAGE 25 FAST STEP FILTER UNTIL THE OUTPUT OF THIS FILTER HAS FULLY SETTLED SEE PAGE 25 SEE PAGE 26 22-TAP FIR FILTER PGA & 3 SKIP SINC OUTPUT ANALOG DIGITAL CHOP SIGMA-DELTA CHOP BUFFER FILTER SCALING INPUT OUTPUT MODULATOR FASTSTEP™ FILTER FASTSTEP™ FILTER BUFFER PGA & SIGMA-DELTA OUTPUT CHOPPING OUTPUT SCALING YY MODULATOR THE INPUT SIGNAL IS BUFFERED THE OUTPUT OF THE FIRST STAGE THE OUTPUT WORD FROM THE ON-CHIP BEFORE BEING APPLIED OF FILTERING ON THE PART CAN WHEN FASTSTEP™ MODE IS DIGITAL FILTER IS SCALED BY THE THE PROGRAMMABLE GAIN ENABLED AND A STEP CHANGE ON CALIBRATION COEFFICIENTS TO THE SAMPLING CAPACITOR OF BE CHOPPED. THE DEFAULT CAPABILITY OF THE PART IS THE INPUT HAS BEEN DETECTED, THE SIGMA DELTA MODULATOR. CONDITION IS CHOPPING BEFORE BEING PROVIDED AS THE INCORPORATED AROUND THE THIS ISOLATES THE SAMPLING THE SECOND STAGE FILTERING IS SIGMA DELTA MODULATOR.THE DISABLED CONVERSION RESULT CAPACITOR CHARGING CURRENTS PERFORMED BY THE FASTSTEP™ MODULATOR PROVIDES A HIGH- SEE PAGE 29 SEE PAGE 25 FILTER UNTIL THE FIR FILTER HAS FROM THE ANALOG INPUT PINS FREQUENCY 1-BIT DATA STREAM FULLY SETTLED. TO THE DIGITAL FILTER. SEE PAGE 23 SEE PAGE 28 SEE PAGE 24 Figure 3. Signal Processing Chain PIN CONFIGURATION SCLK 1 24 DGND MCLK IN 2 23 DV DD MCLK OUT 3 22 DIN POL 4 21 DOUT SYNC 5 20 RDY AD7731 6 19 RESET CS TOP VIEW NC 7 18 STANDBY (Not to Scale) 817 AIN6 AGND AV916 AIN5 DD 10 15 REF IN(–) AIN1 AIN2 11 14 REF IN(+) AIN3/D1 12 13 AIN4/D0 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin Pin No. Mnemonic Function 1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the AD7731 in smaller batches of data. 2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with a clock input frequency of 4.9152 MHz. REV. 0 –7– AD7731 PIN FUNCTION DESCRIPTIONS (Continued) Pin Pin No. Mnemonic Function 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving one CMOS load. 4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces- sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle low between data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a high-to-low transition of SCLK and clocks in data from the DATA IN line in a write operation on a low-to- high transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle high between data transfers. 5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number of AD7731s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up for a subsequent operation that will commence when the SYNC pin is deasserted. 6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock oscillator is reset when the RESET pin is exercised. 7 NC No Connect. The user is advised not to connect anything to this pin. 8 AGND Ground reference point for analog circuitry. 9AV Analog Positive Supply Voltage. The AV to AGND differential is 5 V nominal. DD DD 10 AIN1 Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential pair when used with AIN2. 11 AIN2 Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential pair when used with AIN1. 12 AIN3/D1 Analog Input Channel 3 or Digital Output 1. This pin can be used as either an analog input or a digital output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain analog input, it can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential pair when used with AIN4. When selected as a digital output, this output can be programmed over the serial interface using bit D1 of the Mode Register. 13 AIN4/D0 Analog Input Channel 4 or Digital Output 0. This pin can be used as either an analog input or a digital output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain analog input, it can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential pair when used with AIN3. When selected as a digital output, this output can be programmed over the serial interface using bit D0 of the Mode Register. 14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7731. REF IN(+) can lie anywhere between AV and AGND. The nominal reference voltage (i.e., the differential voltage between DD REF IN(+) and REF IN(–)) should be +2.5 V when the HIREF bit of the Mode Register is 0 and is +5 V when the HIREF bit of the Mode Register is 1. 15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7731. The REF IN(–) can lie anywhere between AV and AGND. DD 16 AIN5 Analog Input Channel 5. Programmable-gain analog input which can be used is the positive input of a differ- ential pair when used with AIN6. 17 AIN6 Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the negative input of a differential input pair when used with AIN5. 18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 10 μA range. The on-chip registers retain all their values when the part is in standby mode. 19 CS Chip Select. Active low Logic Input used to select the AD7731. With this input hardwired low, the AD7731 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7731. –8– REV. 0 AD7731 PIN FUNCTION DESCRIPTIONS (Continued) Pin Pin No. Mnemonic Function 20 RDY Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7731 data register. The RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again. This gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY goes high when calibration is initiated and returns low to indicate that calibration is complete. A number of different events on the AD7731 set the RDY high and these are outlined in Table XVII. 21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the calibration registers, mode register, status register, filter register or data register depending on the register selection bits of the Communications Register. 22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the calibration registers, mode register, communications register or filter regis- ter depending on the register selection bits of the Communications Register. 23 DV Digital Supply Voltage, +3 V or +5 V nominal. DD 24 DGND Ground reference point for digital circuitry. POSITIVE FULL-SCALE OVERRANGE TERMINOLOGY Positive Full-Scale Overrange is the amount of overhead avail- INTEGRAL NONLINEARITY able to handle input voltages on AIN(+) input greater than This is the maximum deviation of any code from a straight line AIN(–) + V /GAIN (for example, noise peaks or excess volt- passing through the endpoints of the transfer function. The end- REF ages due to system gain errors in system calibration routines) points of the transfer function are zero scale (not to be confused without introducing errors due to overloading the analog modu- with bipolar zero), a point 0.5 LSB below the first code transi- lator or overflowing the digital filter. tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The NEGATIVE FULL-SCALE OVERRANGE error is expressed as a percentage of full scale. This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) – V /GAIN without overloading the POSITIVE FULL-SCALE ERROR REF analog modulator or overflowing the digital filter. Positive Full-Scale Error is the deviation of the last code transi- tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage OFFSET CALIBRATION RANGE (AIN(–) + V /GAIN – 3/2 LSBs). It applies to both unipolar REF In the system calibration modes, the AD7731 calibrates its and bipolar analog input ranges. offset with respect to the analog input. The Offset Calibration Range specification defines the range of voltages the AD7731 UNIPOLAR OFFSET ERROR can accept and still accurately calibrate offset. Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- FULL-SCALE CALIBRATION RANGE ating in the unipolar mode. This is the range of voltages that the AD7731 can accept in the system calibration mode and still accurately calibrate full scale. BIPOLAR ZERO ERROR This is the deviation of the midscale transition (0111...111 INPUT SPAN to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – In system calibration schemes, two voltages applied in sequence 0.5 LSB) when operating in the bipolar mode. to the AD7731’s analog input define the analog input range. The input span specification defines the minimum and maxi- GAIN ERROR mum input voltages from zero to full scale that the AD7731 can This is a measure of the span error of the ADC. It is a measure accept and still accurately calibrate gain. of the difference between the measured and the ideal span be- tween any two points in the transfer function. The two points used to calculate the gain error are positive full scale and nega- tive full scale. BIPOLAR NEGATIVE FULL-SCALE ERROR This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – V /GAIN + 0.5 LSB) when operat- REF ing in the bipolar mode. Negative full-scale error is a summation of zero error and gain error. REV. 0 –9– AD7731 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7731 has a number of different modes of operation of the on-chip filter and chopping features. These options are discussed in more detail in later sections. The part can be programmed either to optimize the throughput rate and settling time or to optimize noise and drift performance. Noise tables for two of the primary modes of operation of the part are outlined below for a selection of output rates and settling times. The first mode, where the AD7731 is configured with CHP = 0 and SKIP mode enabled, provides fast settling time while still maintaining high resolution. The second mode, where CHP = 1 and the full second filter is included, provides very low noise numbers with lower output rates. Settling time refers to the time taken to get an output that is 100% settled to the new value after a channel change or exercising SYNC. Output Noise (CHP = 0, SKIP = 1) Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in nonchop mode (CHP of Filter Register = 0) and with the second filter bypassed (SKIP of Filter Register = 1). The table is generated with a master clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to- peak resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges. To calculate the numbers for Table II for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits. Table I. Output Noise vs. Input Range and Update Rate (CHP = 0, SKIP = 1) Typical Output RMS Noise in mV Output –3 dB SF Settling Input Range Data Rate Frequency Word Time 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV 150 Hz 39.3 Hz 2048 20 ms 2.6 1.45 0.87 0.6 0.43 0.28 0.2 200 Hz 52.4 Hz 1536 15 ms 3.0 1.66 1.02 0.69 0.48 0.32 0.22 300 Hz 78.6 Hz 1024 10 ms 3.7 2 1.26 0.84 0.58 0.41 0.28 400 Hz 104.8 Hz 768 7.5 ms 4.2 2.3 1.46 1.0 0.69 0.46 0.32 600 Hz 157 Hz 512 5 ms 5.2 2.9 1.78 1.2 0.85 0.58 0.41 800 Hz 209.6 Hz 384 3.75 ms 6 3.3 2.1 1.4 0.98 0.66 0.47 1200 Hz 314 Hz 256 2.5 ms 7.8 4.3 2.6 1.8 1.27 0.82 0.57 1600 Hz 419.2 Hz 192 1.87 ms 10.9 5.4 3.5 2.18 1.51 0.94 0.64 2400 Hz 629 Hz 128 1.25 ms 27.1 13.9 7.3 3.5 2.22 1.24 0.83 3200 Hz 838.4 Hz 96 0.94 ms 47 24.4 11.4 5.3 3.1 1.9 1.0 4800 Hz 1260 Hz 64 0.625 ms 99 50.3 24.5 12.5 6.5 3.3 1.7 6400 Hz 1676 Hz 48 0.47 ms 193 97 48 24 11.8 6.6 3.0 Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0, SKIP = 1) Peak-to-Peak Resolution in Bits Output –3 dB SF Settling Input Range Data Rate Frequency Word Time 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV 150 Hz 39.3 Hz 2048 20 ms 17.5 17 17 16.5 16 15.5 15 200 Hz 52.4 Hz 1536 15 ms 17 17 16.5 16.5 16 15.5 15 300 Hz 78.6 Hz 1024 10 ms 17 16.5 16.5 16 15.5 15 14.5 400 Hz 104.8 Hz 768 7.5 ms 16.5 16.5 16 15.5 15.5 15 14.5 600 Hz 157 Hz 512 5 ms 16.5 16 16 15.5 15 14.5 14 800 Hz 209.6 Hz 384 3.75 ms 16 16 15.5 15 14.5 14.5 14 1200 Hz 314 Hz 256 2.5 ms 15.5 15.5 15.5 15 14.5 14 13.5 1600 Hz 419.2 Hz 192 1.87 ms 15 15.5 15 14.5 14 14 13.5 2400 Hz 629 Hz 128 1.25 ms 14 14 14 14 13.5 13.5 13 3200 Hz 838.4 Hz 96 0.94 ms 13 13 13 13 13 13 12.5 4800 Hz 1260 Hz 64 0.625 ms 12 12 12 12 12 11.5 12 6400 Hz 1676 Hz 48 0.47 ms 11 11 11 11 11 11 11 –10– REV. 0 AD7731 Output Noise (CHP = 1, SKIP = 0) Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a mas- ter clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The out- put update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges. To calcu- late the number for Table IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits. Table III. Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0) Typical Output RMS Noise in nV Output –3 dB SF Settling Time Input Range Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV 50 Hz 1.97 Hz 2048 440 ms 40 ms 700 425 265 170 120 85 55 100 Hz 3.95 Hz 1024 220 ms 20 ms 980 550 330 230 190 115 90 150 Hz 5.92 Hz 683 147 ms 13.3 ms 1230 700 445 270 210 140 100 200 Hz 7.9 Hz 512 110 ms 10 ms 1260 840 500 340 245 170 105 400 Hz 15.8 Hz 256 55 ms 5 ms 2000 1230 690 430 335 215 160 800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 3800 2100 1400 760 590 345 220 Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0) Peak-to-Peak Resolution in Bits Output –3 dB SF Settling Time Input Range Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV 50 Hz 1.97 Hz 2048 440 ms 40 ms 19 19 18.5 18.5 18 17.5 17 100 Hz 3.95 Hz 1024 230 ms 30 ms 19 18.5 18.5 18 17 17 16 150 Hz 5.92 Hz 683 147 ms 13.3 ms 18.5 18 18 17.5 17 16.5 16 200 Hz 7.9 Hz 512 110 ms 10 ms 18.5 18 17.5 17.5 17 16.5 16 400 Hz 15.8 Hz 256 55 ms 5 ms 17.5 17.5 17 17 16.5 16 15.5 800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 17 16.5 16 16 15.5 15 15 COMMUNICATIONS REGISTER DIN DIN RS2 RS1 RS0 ON-CHIP REGISTERS The AD7731 contains 12 on-chip registers that can be accessed DOUT DOUT via the serial port of the part. These registers are summarized in STATUS REGISTER Figure 4 and in Table V, and described in detail in the following DOUT REGISTER sections. DATA REGISTER SELECT DECODER DIN DOUT MODE REGISTER DIN DOUT FILTER REGISTER DIN DOUT OFFSET REGISTER (x3) DIN DOUT GAIN REGISTER (x3) DIN DOUT TEST REGISTER Figure 4. Register Overview REV. 0 –11– AD7731 Table V. Summary of On-Chip Registers Power-On/Reset Register Name Type Size Default Value Function Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through Register the Communications Register. This controls whether subsequent operations are read or write operations WEN Z1 EROR0WRO WZ2 ERR1S R0 S RS and also selects the register for that subsequent opera- tion. Most subsequent operations return control to the Communications Register except for the continu- ous read mode of operation. Status Register Read Only 8 Bits CX Hex Provides status information on conversions, calibra- tions, settling to step inputs, standby operation and RY DYSTDSF TBYN3OREM2S M1 S M0 S MS the validity of the reference voltage. Data Register Read Only 16 Bits or 24 Bits 000000 Hex Provides the most up-to-date conversion result from the part. Register length can be programmed to be 16 bit or 24 bit. Mode Register Read/Write 16 Bits 0174 Hex Controls functions such as mode of operation, uni- polar/bipolar operation, controlling the function of B/U M1 D2M0 DMD D1EN D0DLW AIN3/D1 and AIN4/D0, burnout current and Data H2 IREFR1N R0 N RON B2C1 HC0 HCH Register word length. It also contains the reference selection bit, the range selection bits and the channel selection bits. Filter Register Read/Write 16 Bits 2002 Hex Controls the amount of averaging in the first stage filter, selects the fast step and skip modes and con- S0F11S9 F1S8 F S7 F S6 F S5 F S4 F SF trols the chopping modes on the part. S2F3S1 F S0 FSO F ZPERCP HST KIFAS Offset Register Read/Write 24 Bits Contains a 24-bit word which is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are three Offset Regis- ters on the part and these are associated with input channel pairs as outlined in Table XIII. Gain Register Read/Write 24 Bits Contains a 24-bit word which is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are three Gain Registers on the part and these are associated with input chan- nel pairs as outlined in Table XIII. Test Register Read/Write 24 Bits 000000 Hex Controls the test modes of the part which are used when testing the part. The user is advised not to change the contents of this register. –12– REV. 0 AD7731 Communications Register (RS2-RS0 = 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation and to which register this operation takes place. For single-shot read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op- eration to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7731 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. Table VI. Communications Register CR7 C5 R6 C4 R C3 R C2 R C1 R C0 R CR WENZ1 EROR0W RO WZ2 ER R1S R0 S RS Bit Bit Location Mnemonic Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communica- tions Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communica- tions Register. CR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. CR5, CR4 RW1, RW0 Read Write Mode Bits. These two bits determine the nature of the subsequent read/write operation. Table VII outlines the four options. Table VII. Read/Write Mode RW1 RW0 Read/Write Mode 0 0 Single Write to Specified Register 0 1 Single Read of Specified Register 1 0 Start Continuous Read of Specified Register 1 1 Stop Continuous Read Mode With 0, 0 written to these two bits, the next operation is a write operation to the register specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified regis- ter has been completed, the part returns to where it is expecting a write operation to the Communications Register. With 0, 1 written to these two bits, the next operation is a read operation of the register specified by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been completed, the part returns to where it is expecting a write operation to the Communications Register. Writing 1, 0 to these bits, sets the part into a mode of continuous reads from the register specified by bits RS2, RS1, RS0. The most likely registers which the user will want to use this function with are the Data Register and the Status Register. Subsequent operations to the part will consist of read operations to the specified register without any intermediate writes to the Communications Register. This means that once the next read operation to the specified register has taken place, the part will be in a mode where it is expecting another read from that specified register. The part will remain in this continuous read mode until 30 Hex has been written to bits RW1 and RW0. When 1, 1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous read mode is stopped and the part returns to where it is expecting a write operation to the Communications Register. Note, the part continues to look at the DIN line on each SCLK edge during the continuous read mode so that it can determine when to stop the continuous read mode. Therefore, the user must be careful not to inadvertently exit the continuous read mode or reset the part by writing a series of 1s to the part. The easiest way to avoid this is to place a logic 0 on the DIN line while the part is in continuous read mode. REV. 0 –13– AD7731 Bit Bit Location Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. CR2-CR0 RS2-RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which one of eight on-chip registers the next read or write operation takes place as shown in Table VIII. Table VIII. Register Selection RS2 RS1 RS0 Register 0 0 0 Communications Register (Write Operation) 0 0 0 Status Register (Read Operation) 0 0 1 Data Register 0 1 0 Mode Register 0 1 1 Filter Register 1 0 0 No Register Access 1 0 1 Offset Register 1 1 0 Gain Register 1 1 1 Test Register Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig- nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de- notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets indicates the power-on/reset default status of that bit. Table IX. Status Register S6 R7 S5 R S4 R S3 R S2 R S1 R S0 R SR RDY(1)STDY(1)S) TBY(0)N)OREF(0M)S3(XM) S2(XM) S1(XMS0(X Bit Bit Location Mnemonic Description SR7 RDY Ready Bit. This bit provides the status of the RDY flag from the part. The status and func- tion of this bit is the same as the RDY output pin. A number of events set the RDY bit high as indicated in Table XVII. SR6 STDY Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter is in FASTStep™ mode (see Filter Register section), and responding to a step input, the STDY bit remains high as the initial conversion results become available. The RDY output and bit are set low on these initial conversions to indicate that a result is available. However, if the STDY is high, it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coin- cident with RDY. If the part is never placed into its FASTStep™ mode, the STDY bit will go low at the first Data Register read and it is not cleared by subsequent Data Register reads. A number of events set the STDY bit high as indicated in Table XVII. STDY is set high along with RDY by all events in the table except a Data Register read. SR5 STBY Standby Bit. This bit indicates whether the AD7731 is in its Standby Mode or normal mode of operation. The part can be placed in its standby mode using the STANDBY input pin or by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit is 0 assuming the STANDBY pin is high. SR4 NOREF No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion of a calibration, updating of the calibration registers is inhibited. SR3-SR0 MS3-MS0 These bits are for factory use. The power-on/reset status of these bits varies depending on the factory-assigned number. –14– REV. 0 AD7731 Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex The Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5 shows a flowchart for reading from the registers on the AD7731. The register can be programmed to be either 16 or 24 bits wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16 or 24 bits) have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit will go high for at least 158.5 × t indicating when a read from the Data Register should not be initiated to avoid a transfer from the CLK IN Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low. If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter- face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7731. Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex The Mode Register is a 16-bit register from which data can either be read or to which data can be written. This register configures the operating modes of the AD7731, the input range selection, the channel selection and the word length of the Data Register. Table X outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. Table X. Mode Register M4 R15M3 R1M2 R1M1 R1M0 R1 M9R1 M8R MR B/U(0) M) D2(0)M) D1(0MD0(0 D)EN(0)D)1(0D) 0(0WL(1 M6R7 M5 R M4 R M3 R M2 R M1 R M0 R MR H) IREF(0)R)N2(1R) N1(1R)N0(1B) O(0C) H2(1C) H1(0CH0(0 Bit Bit Location Mnemonic Description MR15–MR13 MD2–MD0 Mode Bits. These three bits determine the mode of operation of the AD7731 as outlined in Table XI. The modes are independent, such that writing new mode bits to the Mode Regis- ter will exit the part from the mode in which it is operating and place it in the new requested mode immediately after the Mode Register write. The function of the mode bits is described in more detail below. Table XI. Operating Modes MD2 MD1 MD0 Mode of Operation 0 0 0 Sync (Idle) Mode Power-On/Reset Default 0 0 1 Continuous Conversion Mode 0 1 0 Single Conversion Mode 0 1 1 Power-Down (Standby) Mode 1 0 0 Internal Zero-Scale Calibration 1 0 1 Internal Full-Scale Calibration 1 1 0 System Zero-Scale Calibration 1 1 1 System Full-Scale Calibration REV. 0 –15– AD7731 MD2 MD1 MD0 Operating Mode 0 0 0 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC does not actually force these mode bits to 0, 0, 0. The part re- turns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the default condition of these bits after Power-On/Reset. 0 0 1 Continuous Conversion Mode. In this mode, the AD7731 is continuously processing data and providing conversion results to the Data Register at the programmed output update rate (as determined by the Filter Register). For most applications, this would be the normal operating mode of the AD7731. 0 1 0 Single Conversion Mode. In this mode, the AD7731 performs a single conversion, updates the Data Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion on the AD7731 in this mode will not be provided until the full settling-time of the filter has elapsed. 0 1 1 Power-Down (Standby) Mode. In this mode, the AD7731 goes into its power-down or standby state. Placing the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting STANDBY does not actually force these mode bits to 0, 1, 1. 1 0 0 Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by the CH2, CH1 and CH0 bits of the Mode Register. This zero-scale self-calibration is performed at the se- lected gain on internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 0 1 Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by the CH2, CH1 and CH0 bits of the Mode Register. This full-scale self-calibration is performed at the se- lected gain on an internally-generated full-scale signal. When this full-scale self-calibration is complete, the part updates the contents of the Gain Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 1 0 Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected by the CH2, CH1 and CH0 bits of the Mode Register. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. When this zero-scale system calibration is complete, the part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 1 1 Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input channel. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibra- tion. When this full-scale system calibration is complete, the part updates the contents of the Gain Cali- bration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this full-scale calibration is com- plete to indicate that the part is back in Sync Mode and ready for further operations. –16– REV. 0 AD7731 Bit Bit Location Mnemonic Description MR12 B/U Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00...000 for negative full-scale input, 10...000 for zero input and 11...111 for positive full- scale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for zero input and 11...111 for positive full-scale input. MR11 DEN Digital Output Enable Bit. With this bit at 1, the AIN3/D1 and AIN4/D0 pins assume their digital output functions and the output drivers connected to these pins are enabled. In this mode, the user effectively has two port bits which can be programmed over the serial interface. MR10–MR9 D1–D0 Digital Output Bits. These bits determine the digital outputs on the AIN3/D1 and AIN4/D0 pins respectively when the DEN bit is a 1. For example, a 1 written to the D1 bit of the Mode Register (with the DEN bit also a 1) will put a logic 1 on the AIN3/D1 pin. This logic 1 will remain on this pin until a 0 is written to the D1 bit (in which case, the AIN3/D1 pin goes to a logic 0) or the digital output function is disabled by writing a 0 to the DEN bit. MR8 WL Data Word Length Bit. This bit determines the word length of the Data Register. A 0 in this bit selects 16-bit word length when reading from the data register (i.e., RDY returns high after 16 serial clock cycles in the read operation). A 1 in this bit selects 24-bit word length for the Data Register. MR7 HIREF High Reference Bit. This bit should be set in accordance with the reference voltage which is being used on the part. If the reference voltage is 2.5 V, the HIREF bit should be set to 0. If the reference voltage is 5 V, the HIREF bit should be set to a 1. With the HIREF bit set correctly for the appropriate applied reference voltage, the input ranges are 0 mV to +20 mV, +40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V for unipolar operation and ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V for bipolar operation. It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the part is operating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the input ranges on the part become 0 mV to +10 mV through 0 mV to +640 mV for unipolar operation and ±10 mV through ±640 mV for bipolar operation. However, the output noise from the part (in nV) will remain unchanged so the resolution of the part (in LSBs) will re- duce by 1. MR6–MR4 RN2–RN0 Input Range Bits. These bits determine the analog input range for the selected analog input. The different input ranges are outlined in Table XII. The table is valid for a reference voltage of 2.5 V with the HIREF bit at 0 or for a reference voltage of 5 V with the HIREF bit at a logic 1. Table XII. Input Range Selection Input Range RN2 RN1 RN0 B/U Bit = 0 B/U Bit = 1 0 0 0 –20 mV to +20 mV 0 mV to +20 mV 0 0 1 –20 mV to +20 mV 0 mV to +20 mV 0 1 0 –40 mV to +40 mV 0 mV to +40 mV 0 1 1 –80 mV to +80 mV 0 mV to +80 mV 1 0 0 –160 mV to +160 mV 0 mV to +160 mV 1 0 1 –320 mV to +320 mV 0 mV to +320 mV 1 1 0 –640 mV to +640 mV 0 mV to +640 mV 1 1 1 –1.28 V to +1.28 V 0 mV to +1.28 V Power-On/Reset Default REV. 0 –17– AD7731 Bit Bit Location Mnemonic Description MR3 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents. MR2–MR0 CH2–CH0 Channel Select. These three bits select a channel either for conversion or for access to cali- bration coefficients as outlined in Table XIII. There are three pairs of calibration registers on the part. In fully differential mode, the part has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input channels with some of the input channel combinations sharing calibration registers. With CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no ex- ternal noise sources. In this mode, the AIN6 input should be connected to an external volt- age within the allowable common-mode range for the part. The power-on/default status of these bits is 1, 0, 0. Table XIII. Channel Selection CH2 CH1 CH0 AIN(+) AIN(–) Type Calibration Register Pair 0 0 0 AIN1 AIN6 Pseudo Differential Register Pair 0 0 0 1 AIN2 AIN6 Pseudo Differential Register Pair 1 0 1 0 AIN3 AIN6 Pseudo Differential Register Pair 2 0 1 1 AIN4 AIN6 Pseudo Differential Register Pair 2 1 0 0 AIN1 AIN2 Fully Differential Register Pair 0 1 0 1 AIN3 AIN4 Fully Differential Register Pair 1 1 1 0 AIN5 AIN6 Fully Differential Register Pair 2 1 1 1 AIN6 AIN6 Test Mode Register Pair 2 Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex The Filter Register is a 16-bit register from which data can either be read or to which data can be written. This register determines the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. Table XIV outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. Table XIV. Filter Register F4 R15F3 R1 F2 R1 F1 R1 F0 R1 F9R1 F8R FR S) F11(0)S)F10(0S)F9(1S) F8(0S) F7(0S) F6(0S) F5(0SF4(0 F6R7 F5 R F4 R F3 R F2 R F1 R F0 R FR S) F3(0)S) F2(0S) F1(0S) F0(0Z) ERO(0C)HP(0S) KIP(1FAST(0 Bit Bit Location Mnemonic Description 3 3 FR15–FR4 SF11–SF0 Sinc Filter Selection Bits. The AD7731 contains two filters, a Sinc filter and an FIR filter. 3 The 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre- quency and output update rate from the part (see Filter Architecture section). The allowable range for SF words depends on whether the part is operated with CHP on or off and SKIP on or off. Table XV outlines the SF ranges for different setups. –18– REV. 0 AD7731 Table XV. SF Ranges CHOP SKIP SF Range Output Update Rate Range (Assuming 4.9152 MHz Clock) 0 0 2048 to 150 150 Hz to 2.048 kHz 1 0 2048 to 75 50 Hz to 1.365 kHz 0 1 2048 to 40 150 Hz to 7.6 kHz 1 1 2048 to 20 50 Hz to 5.12 kHz Bit Bit Location Mnemonic Description FR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. FR2 CHP Chop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this bit location enables chopping on the part. When the chop mode is enabled, the part is effec- tively chopped at its input and output to remove all offset and offset drift errors on the part. If offset performance with time and temperature are important parameters in the design, it is recommended that the user enable chopping on the part. FR1 SKIP FIR Filter Skip Bit. With a 0 in this bit, the AD7731 performs two stages of filtering before 3 shipping a result out of the filter. The first is a Sinc filter followed by a 22-tap FIR filter. 3 With a 1 in this bit, the FIR filter on the part is bypassed and the output of the Sinc is fed directly as the output result of the AD7731’s filter (see Filter Architecture for more details on the filter implementation). FR0 FAST FASTStep™ Mode Enable Bit. A 1 in this bit enables the FASTStep™ mode on the AD7731. In this mode, if a step change on the input is detected, the FIR calculation portion of the filter is 3 suspended and replaced by a simple moving average on the output of the Sinc filter. Ini- 3 tially, two outputs from the sinc filter are used to calculate an AD7731 output. The number 3 of sinc outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until the STDY bit goes low. When the FIR filter has fully settled after a step, the STDY bit will become active and the FIR filter is switched back into the processing loop (see Filter Architecture section for more details on the FASTStep™ mode). Offset Calibration Register (RS2–RS0 = 1, 0, 1) The AD7731 contains three 24-bit Offset Calibration Registers, labeled Offset Calibration Register 0 to Offset Calibration Register 2, to which data can be written and from which data can be read. The three registers are totally independent of each other such that in fully-differential mode there is an offset register for each of the input channels. This register is used in conjunction with the associ- ated Gain Calibration Register to form a register pair. The calibration register pair used to scale the output of the filter is as outlined in Table XIII. To access the appropriate Offset Calibration Register the user should write first to the Mode Register setting up the appropriate address in the CH2 to CH0 bits. The Offset Calibration Register is updated after an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. Gain Calibration Register (RS2–RS0 = 1, 1, 0) The AD7731 contains three 24-bit Gain Calibration Registers to which data can be written and from which data can be read. The three registers are totally independent of each other such that in fully-differential mode there is a gain register for each of the input channels. This register is used in conjunction with the associated Offset Calibration Register to form a register pair which scale the output of the filter before it is loaded to the Data Register. These register pairs are associated with input channel pairs as outlined in Table XIII. To access the appropriate Gain Calibration Register the user should write first to the Mode Register setting up the ap- propriate address in the CH2 to CH0 bits. The Gain Calibration Register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent conversions, the contents of this register are used to scale the number which has already been offset corrected with the Offset Calibration Register contents. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. Test Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 000000Hex The AD7731 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the part from the mode and return all register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to read back the contents of the Test Register depending on the test mode which the part has been placed. REV. 0 –19– AD7731 READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7731 contains a total of twelve on-chip registers. These registers are all accessed over a three-wire interface. As a result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words to be written to the AD7731. START CONTINUOUS YES READS OF REGISTER REQUIRED? Byte W Byte Y Byte Z Register (Hex) (Hex) (Hex) NO Status Register 10 20 30 WRITE BYTE W TO Data Register 11 21 30 COMMUNICATIONS REGISTER (SEE ACCOMPANYING TABLE) Mode Register 12 22 30 WRITE BYTE Y TO Filter Register 13 N/A* N/A* COMMUNICATIONS REGISTER Offset Register 15 N/A* N/A* (SEE ACCOMPANYING TABLE) READ REGISTER Gain Register 16 N/A* N/A* *N/A = Not Applicable. Continuous reads of these registers does not make sense as the register contents would remain the same since they are only changed by a write operation. READ REGISTER STOP NO CONTINUOUS READ OPERATION? YES WRITE BYTE Z TO COMMUNICATIONS REGISTER (SEE ACCOMPANYING TABLE) Figure 5. Flowchart for Reading from the AD7731 Registers START Register Byte Y (Hex) Communications Register 00 WRITE BYTE Y TO COMMUNICATIONS REGISTER Data Register Read Only Register. (SEE ACCOMPANYING TABLE) Mode Register 02 Filter Register 03 WRITE TO REGISTER Offset Register 05 Gain Register 06 Test Register User is advised not to change contents of END Test Register Figure 6. Flowchart for Writing to the AD7731 Registers –20– REV. 0 AD7731 CALIBRATION OPERATION SUMMARY The AD7731 contains a number of calibration options as outlined previously. Table XVI summarizes the calibration types, the op- erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra- tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full details. Table XVI. Calibration Operations MD2, MD1, Duration to RDY Duration to RDY Calibration Type MD0 Low (CHP = 1) Low (CHP = 0) Calibration Sequence Internal Zero-Scale 1, 0, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set for selected input range. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. For full self-cali- bration, this calibration should be preceded by an Internal Full-Scale calibration. For applications which require an Internal Zero-Scale and System Full Scale calibration, this Internal Zero-Scale calibration should be performed first. Internal Full-Scale 1, 0, 1 44 × 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale with PGA set for selected input range. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. It is recommended that internal full-scale calibrations are performed on the operating input range except for the 20 mV and 40 mV input ranges where opti- mum results are achieved by calibrating on the 80 mV range. This calibration should be followed by either an Internal Zero-Scale or System Zero- Scale calibration. This calibration should be fol- lowed by either an Internal Zero-Scale or System Zero-Scale calibration. This zero-scale calibration should be performed at the operating input range. System Zero-Scale 1, 1, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with PGA set for selected input range. The input applied is assumed to be the zero-scale of the system. For full system calibration, this System Zero-Scale calibration should be performed first. For applica- tions which require a System Zero-Scale and Inter- nal Full Scale calibration, this calibration should be preceded by the Internal Full-Scale calibration. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. System Full-Scale 1, 1, 1 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with PGA set for selected input range. The input applied is assumed to be the full-scale of the system. This calibration should be preceded by a System Zero- Scale or Internal Zero-Scale calibration. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. REV. 0 –21– AD7731 CIRCUIT DESCRIPTION sigma-delta modulator converts the sampled input signal into a The AD7731 is a sigma-delta A/D converter with on-chip digital digital pulse train whose duty cycle contains the digital informa- filtering, intended for the measurement of wide dynamic range, tion. A digital low-pass filter processes the output of the sigma- low-frequency signals such as those in strain-gage, pressure delta modulator and updates the data register at a rate that can transducer, temperature measurement, industrial control or pro- be programmed over the serial interface. The output data from cess control applications. It contains a sigma-delta (or charge- the part is accessed over this serial interface. The cutoff fre- balancing) ADC, a calibration microcontroller with on-chip quency and output rate of this filter can be programmed via on- static RAM, a clock oscillator, a digital filter and a bidirectional chip registers. The output noise performance and peak-to-peak serial communications port. The part consumes 13.5 mA of resolution of the part varies with gain and with the output rate power supply current with a standby mode which consumes as shown in Tables I to IV. only 20 μA. The part operates from a single +5 V supply. The The analog inputs are buffered on-chip, allowing the part to clock source for the part can be provided via an external clock handle significant source impedances on the analog input. This or by connecting a crystal oscillator or ceramic resonator across means that external R, C filtering (for noise rejection or RFI the MCLK IN or MCLK OUT pins. interference reduction) can be placed on the analog inputs if The part contains three programmable-gain fully differential required. The common-mode voltage range for the analog in- analog input channels which can be reconfigured as five pseudo- puts comes within 1.2 V of AGND and 0.95 V of AV . The DD differential inputs. The part handles a total of seven different reference input is also differential and the common-mode range input ranges on all channels which are programmed via the on- here is from AGND to AV . DD chip registers. The differential unipolar ranges are: 0 mV to The AD7731 contains a number of hardware and software +20 mV through 0 V to +1.28 V and the differential bipolar events that set or reset status flags and bits in registers. Table ranges are: ±20 mV through ±1.28 V. XVII summarizes which blocks and flags are affected by the The AD7731 employs a sigma-delta conversion technique to different events. realize up to 24 bits of no missing codes performance. The Table XVII. Reset Events Set Registers Mode Filter Analog Reset Serial Set RDY Set STDY Event to Default Bits Reset Power-Down Interface Pin/Bit Bit Power-On Reset Yes 000 Yes Yes Yes Yes Yes RESET Pin Yes 000 Yes No Yes Yes Yes STANDBY Pin No As Is Yes Yes No Yes Yes Mode 011 Write No 011 Yes Yes No Yes Yes SYNC Pin No As Is Yes No No Yes Yes Mode 000 Write No 000 Yes No No Yes Yes Conversion or No New Initial No No Yes Yes Cal Mode Write Value Reset Clock 32 1s No As Is No No Yes Yes Yes Data Register Read No As Is No No No Yes No –22– REV. 0 AD7731 ANALOG INPUT 0 mV to +80 mV, 0 mV to +160 mV, 0 mV to +320 mV, 0 mV Analog Input Channels to +640 mV and 0 V to +1.28 V while the bipolar ranges are The AD7731 has six analog input pins (labelled AIN1 to AIN6) ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, which can be configured as either three fully differential input ±1.28 V. These are the nominal ranges which should appear at channels or five pseudo-differential input channels. Bits CH0, the input to the on-chip PGA. CH1 and CH2 of the Mode Register configure the input chan- Bipolar/Unipolar Inputs nel arrangement and the channel selection is as outlined The analog inputs on the AD7731 can accept either unipolar or previously in Table XIII. The input pairs (either differential bipolar input voltage ranges. Bipolar input ranges do not imply or pseudo-differential) provide programmable-gain, input chan- that the part can handle negative voltages with respect to system nels which can handle either unipolar or bipolar input signals. It ground on its analog inputs unless the AGND of the part is also should be noted that the bipolar input signals are referenced to biased below system ground. Unipolar and bipolar signals on the respective AIN(–) input of the input pair. The AIN3 and the AIN(+) input are referenced to the voltage on the respec- AIN4 pins can also be reconfigured as two digital output port tive AIN(–) input. For example, if AIN(–) is +2.5 V and the bits, also controlled by the Mode Register. AD7731 is configured for an analog input range of 0 mV to A differential multiplexer switches one of the two input channels +20 mV, the input voltage range on the AIN(+) input is +2.5 V to the on-chip buffer amplifier. When the analog input channel to +2.52 V. If AIN(–) is +2.5 V and the AD7731 is configured is switched, the RDY output goes high and the settling time of for an analog input range of ±1.28 V, the analog input range on the part must elapse before a valid word from the new channel is the AIN(+) input is +1.22 V to +3.78 V (i.e., 2.5 V ± 1.28 V). available in the Data Register (indicated by RDY going low). Bipolar or unipolar options are chosen by programming the B/U Buffered Inputs bit of the Mode Register. This programs the selected channel The output of the multiplexer feeds into a high impedance input for either unipolar or bipolar operation. Programming the chan- stage of the buffer amplifier. As a result, the analog inputs can nel for either unipolar or bipolar operation does not change any handle significant source impedances. This buffer amplifier has of the input signal conditioning; it simply changes the data an input bias current of 50 nA (CHP = 1) and 60 nA (CHP = 0). output coding and the points on the transfer function where This current flows in each leg of the analog input pair. The calibrations occur. When the AD7731 is configured for unipolar offset current on the part is the difference between the input operation, the output coding is natural (straight) binary with a bias on the legs of the input pair. This offset current is less than zero differential voltage resulting in a code of 000...000, a mid- 10 nA (CHP = 1) and 25 nA (CHP = 0). Large source resis- scale voltage resulting in a code of 100...000 and a full-scale tances result in a dc offset voltage developed across the source input voltage resulting in a code of 111...111. When the AD7731 is resistance on each leg but matched impedances on the analog configured for bipolar operation, the coding is offset binary with input legs will reduce the offset voltage to that generated by the a negative full-scale voltage resulting in a code of 000...000, a input offset current. zero differential voltage resulting in a code of 100...000 and a positive full-scale voltage resulting in a code of 111...111. Analog Input Ranges The absolute input voltage range is restricted to between Burnout Currents AGND + 1.2 V to AV – 0.95 V which also places restrictions The AD7731 contains two 100 nA constant current generators, DD on the common-mode range. Care must be taken in setting up one source current from AV to AIN(+) and one sink from DD the common-mode voltage and input voltage range so that these AIN1(–) to AGND. The currents are switched to the selected limits are not exceeded, otherwise there will be a degradation in analog input pair. Both currents are either on or off depending linearity performance. on the BO bit of the Mode Register. These currents can be used in checking that a transducer is still operational before attempt- In some applications, the analog input range may be biased ing to take measurements on that channel. If the currents are either around system ground or slightly below system ground. In turned on, allowed flow in the transducer, a measurement of the such cases, the AGND of the AD7731 must be biased negative input voltage on the analog input taken and the voltage mea- with respect to system ground such that the analog input voltage sured is full scale then it indicates that the transducer has gone does not go within 1.2 V of AGND. Care should taken to en- open-circuit. If the voltage measured is 0 V, it indicates that the sure that the differential between either AV or DV and this DD DD transducer has gone open-circuit. For normal operation, these biased AGND does not exceed 5.5 V. This is discussed in more burnout currents are turned off by writing a 0 to the BO bit. detail in the Applications section. The current sources work over the normal absolute input volt- Programmable Gain Amplifier age range specifications. The output from the buffer amplifier is applied to the input of the on-chip programmable gain amplifier (PGA). The PGA can handle seven different unipolar input ranges and seven bipolar ranges. With the HIREF bit of the Mode Register at 0 and a +2.5 V reference (or the HIREF bit at 1 and a +5 V reference), the unipolar ranges are 0 mV to +20 mV, 0 mV to +40 mV, REV. 0 –23– AD7731 REFERENCE INPUT SIGMA-DELTA MODULATOR The AD7731’s reference inputs, REF IN(+) and REF IN(–), A sigma-delta ADC generally consists of two main blocks, an provide a differential reference input capability. The common- analog modulator and a digital filter. In the case of the AD7731, mode range for these differential inputs is from AGND to AV . the analog modulator consists of a difference amplifier, an inte- DD The nominal reference voltage, V (REF IN(+) – REF IN(–)), grator block, a comparator and a feedback DAC as illustrated in REF for specified operation is +2.5 V with the HIREF bit at 0 and Figure 7. In operation, the analog signal sample is fed to the +5 V with the HIREF bit at 1. The part is also functional with difference amplifier along with the output of the feedback DAC. V of +2.5 V with the HIREF bit at 1. This results in a halv- The difference between these two signals is integrated and fed to REF ing of all input ranges. The resolution in nV will be unaltered, the comparator. The output of the comparator provides the but will be reduced by 1 bit in terms of peak-to-peak resolution. input to the feedback DAC so the system functions as a negative feedback loop that tries to minimize the difference signal. The Both reference inputs provide a high impedance, dynamic load. digital data that represents the analog input voltage is contained The typical average dc input leakage current is over temperature in the duty cycle of the pulse train appearing at the output of the is 4.5 μA with HIREF = 0 and 8 μA with HIREF = 1. Because comparator. This duty cycle data can be recovered as a data the input impedance on each reference input is dynamic, exter- word using the digital filter. The sampling frequency of the nal resistance/capacitance combinations may result in gain er- modulator loop is many times higher than the bandwidth of the rors on the part. input signal. The integrator in the modulator shapes the quanti- The output noise performance outlined in Tables I through IV zation noise (which results from the analog to digital conversion) so is for an analog input of 0 V and is unaffected by noise on the that the noise is pushed towards one half of the modulator fre- reference. To obtain the same noise performance as shown in quency. The digital filter then bandlimits the response to a fre- the noise tables over the full input range requires a low noise quency significantly lower than one half of the modulator reference source for the AD7731. If the reference noise in the frequency. In this manner, the 1-bit output of the comparator bandwidth of interest is excessive, it will degrade the perfor- is translated into a bandlimited, low noise output from the mance of the AD7731. In applications where the excitation AD7731. voltage for the transducer on the analog input also drives the ANALOG DIFFERENCE reference voltage for the part, the effect of the low-frequency INPUT AMP COMPARATOR noise in the excitation voltage will be removed as the application DIGITAL is ratiometric. In this case, the reference voltage for the AD7731 INTEGRATOR FILTER and the excitation voltage for the transducer are the same. The HIREF bit of the Mode Register should be set to 1. DIGITAL DATA DAC If the AD7731 is not used in a ratiometric application, a low noise reference should be used. Recommended reference voltage sources for the AD7731 include the AD780, REF43 and REF192. Figure 7. Sigma-Delta Modulator Block Diagram If any of these references are used as the reference source for the AD7731, the HIREF bit should be set to 0. It is generally rec- DIGITAL FILTERING ommended to decouple the output of these references to further Filter Architecture reduce the noise level. The output of the modulator feeds directly into the digital filter. This digital filter consists of two portions, a first stage filter and Reference Detect a second stage filter. The cutoff frequency and output rate of The AD7731 includes on-chip circuitry to detect if the part has the filter are programmable. The first stage filter is a low-pass, a valid reference for conversions or calibrations. If the voltage 3 3 sinc or (sinx/x) filter whose primary function is to remove the between the REF IN(+) and REF IN(–) pins goes below 0.3 V quantization noise introduced at the modulator. The second or either the REF IN(+) or REF IN(–) inputs is open circuit, stage filter has three distinct modes of operation. The first op- the AD7731 detects that it no longer has a valid reference. In tion is where it is bypassed completely such that the only filter- this case, the NOREF bit of the Status Register is set to a 1. 3 ing provided on the AD7731 is performed by the first stage sinc If the AD7731 is performing normal conversions and the NOREF filter. The second is where it provides a low-pass 22-tap FIR bit becomes active, the part places all 1s in the Data Register. filter which processes the output of the first stage filter. The Therefore, it is not necessary to continuously monitor the status third option is to enable FASTStep™ mode. In this mode, when of the NOREF bit when performing conversions. It is only nec- a step change is detected on the analog input or the analog input essary to verify its status if the conversion result read from the channel switched, the second stage filter enters a mode where it Data Register is all 1s. performs a variable number of averages for some time after the step change and then the second stage filter switches back to the If the AD7731 is performing either an offset or gain calibration FIR filter. and the NOREF bit becomes active, the updating of the respec- tive calibration register is inhibited to avoid loading incorrect The AD7731 has two primary modes of operation, chop mode coefficients to this register. If the user is concerned about verify- (CHP = 1) and nonchop mode (CHP = 0). The AD7731 alter- ing that a valid reference is in place every time a calibration is natively reverses its inputs with CHP = 1, and alternate outputs performed, then the status of the NOREF bit should be checked from the first stage filter have a positive offset and negative at the end of the calibration cycle. offset term included. With CHP = 0, the input is never reversed and the output of the first stage filter includes an offset which is always of the same polarity. –24– REV. 0 AD7731 0 The operation mode can be changed to achieve optimum per- –10 formance in various applications. The CHP bit should generally –20 be set to 0 when using the AD7731 in applications where higher –30 throughput rates are a concern or in applications where the –40 reduced rejection at the chopping frequency in chop mode is an –50 issue. The part should be operated with CHP = 1 when drift, –60 noise rejection and optimum EMI rejection are important crite- ria in the application. –70 –80 The output update rate of the AD7731 is programmed using the –90 SF bits of the Filter Register. With CHP = 0, the output update –100 is determined by the relationship: –110 1 –120 Output Rate = f × CHP = 0 0 200 400 600 800 1000 1200 1400 1600 1800 () MOD SF FREQUENCY – Hz where SF is the decimal equivalent of the data loaded to the SF Figure 8. SKIP Mode Frequency Response (SKIP = 1, bits of the Filter Register and f is the modulator frequency MOD SF = 512) and is 1/16th of the master clock frequency. Chop Mode (SKIP = 1, CHP = 1) With CHP = 1, the output update is determined by the relation- With CHP = 1, the AD7731 alternatively reverses the ADC ship: inputs, producing an output which contains the channel offset when not reversed and the negative of the offset when reversed. 1 Output Rate = f × CHP = 1 MOD () As a result, when operating in SKIP mode, the user has to take 3 × SF two subsequent outputs from the AD7731 and average them to where SF is the decimal equivalent of the data loaded to the SF produce a valid output from the first stage filter. While operat- bits of the Filter Register and f is the modulator frequency MOD ing in this mode gives the benefits of chopping without the and is 1/16th of the master clock frequency. longer settling time associated with the 22-tap FIR filter, care should be taken with input signals near positive full-scale or Thus for a given SF word the output rate from the AD7731 is negative full-scale (zero-scale in unipolar mode). Since the three times faster with CHP = 0 than CHP = 1. calibration coefficients are generated for the averaged offset, and The various filter stages and options are discussed in the follow- not for the individual offsets represented in each sample, one of ing sections. the two samples in the pair may record an all 1s or all 0s read- First Stage Filter/SKIP Mode Enabled (SKIP = 1) ing. If this happens it will result in an error in the averaged With SKIP mode enabled, the only filtering on the part is the reading. Time to first output for the part is 1/Output Rate in first stage filter. The frequency response for this first stage filter this mode. However, since the user really needs two outputs to is shown in Figure 8. The response of this first stage filter is derive a correct chopped result, the time to get two outputs for similar to that of an averaging filter but with a sharper roll-off. averaging is 2 × 1/Output Rate. Table XVIII summarizes the With CHP = 0, the output rate for the filter corresponds with settling time and subsequent throughput rate for the various the positioning of the first notch of the filter’s frequency re- different modes. If the user wants the benefits of chopping with- sponse. Thus, for the plot of Figure 8 where the output rate is out the longer settling time associated with the 22-tap FIR filter, 600 Hz (f = 4.9152 MHz and SF = 512), the first notch of it is recommended that the part be used in FASTStep™ mode. CLK IN the filter is at 600 Hz. With CHP = 1, the magnitude response Second Stage Filter is the same as in Figure 8 but in this case, the output rate is With SKIP mode disabled, the second stage filter is included in 1/3rd the output rate so for the example shown in Figure 8 the the signal processing. This second stage filter produces a differ- 3 output data rate is 200 Hz. The notches of this sinc filter fre- ent response depending on the CHP and FAST bits. quency response are repeated at multiples of the first notch. The Normal FIR Operation (SKIP = 0) filter provides attenuation of better than 100 dB around these The normal mode of operation of the second stage filter is as a notches. Programming a different cutoff frequency via SF0 – 22-tap low-pass FIR filter. This second stage filter processes the SF11 does not alter the profile of the filter response; it simply output of the first stage filter and the net frequency response of changes the location of the notches. The –3 dB frequency for both the filter is simply a product of the filter response of both filters. Chop and Nonchop modes is defined as: The overall filter response of the AD7731 is guaranteed to have no overshoot. 1 f = 0.262 × f × 3 dB MOD SF Nonchop Mode (SKIP = 1, CHP = 0) With CHP = 0, the input chopping on the AD7731 is disabled and any offset content in the samples to the first stage filter are all of the same polarity. When using the part in SKIP mode, the user can take the output from the AD7731 directly. Time to the first output for the part is 3 × 1/Output Rate in this mode. Table XVIII summarizes the settling time and subsequent throughput rate for the various different modes. REV. 0 –25– GAIN – dB AD7731 Chop Mode (SKIP = 0, CHP = 1) Figure 10 shows the frequency response for the same set of With CHOP mode enabled and SKIP mode disabled, the sec- conditions as for Figure 9 but in this case the response in shown ond stage filter is presented with alternating first stage filter out to 600 Hz. This response shows that the attenuation of outputs and processes data accordingly. It has two primary input frequencies close to 200 Hz and 400 Hz is significantly functions. One is to set the overall frequency response and the less than at other input frequencies. These “peaks” in the fre- second is to eliminate the modulated offset effect which appears quency response are a by-product of the chopping of the input. on the output of the first stage filter. Time to first output is The plot of Figure 10 is the amplitude for different input fre- 22 × 1/Output Rate in this mode. Table XVIII summarizes the quencies. Note that because the output rate is 200 Hz for the settling time and subsequent throughput rate for the various conditions under which Figure 10 is plotted, if something ex- different modes. isted in the input frequency domain at 200 Hz, it would be aliased and appear in the output frequency domain at dc. Figure 9 shows the full frequency response of the AD7731 when the second stage filter is set for normal FIR operation. This Because of this effect, care should be taken in choosing an out- response is for chop mode enabled with the decimal equivalent put rate which is close to the line frequency in the application. of the word in the SF bits set to 512 and a master clock fre- For example, if the line frequency is 50 Hz, an output update quency of 4.9152 MHz. The response will scale proportionately rate of 50 Hz should not be chosen as it will significantly reduce with master clock frequency. The response is shown from dc to the AD7731’s line frequency rejection (the 50 Hz will appear as 100 Hz. The rejection at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz is a dc component with only 6 dB attenuation). However, choos- better than 88 dB. ing 60 Hz as the output rate (SF = 1707) will give better than 90 dB attenuation of the aliased line frequency. In a similar The –3 dB frequency for the frequency response of the AD7731 fashion, if the line frequency is 60 Hz, it is recommended that with the second stage filter set for normal FIR operation and the user choose an output update rate of 50 Hz (SF = 2048). chop mode enabled is determined by the following relationship: 0 1 –10 f = 0.0395 × f × CHP = 1 () 3dB MOD 3 × SF –20 –30 In this case, f = 7.9 Hz and the stop-band, where the attenua- 3dB –40 tion is greater than 64.5 dB, is determined by: –50 1 –60 f = 0.14 × f × CHP = 1 () STOP MOD 3 × SF –70 –80 In this case, f = 28 Hz. STOP –90 0 –100 –10 –110 –20 –120 0 50 100 150 200 250 300 350 400 450 500 550 600 –30 FREQUENCY – Hz –40 –50 Figure 10. Expanded Full Frequency Response of AD7731 –60 (SKIP = 0, CHP = 1, SF = 512) –70 Similarly, multiples of the line frequency should be avoided as –80 the output rate because harmonics of the line frequency will not –90 be fully attenuated. The programmability of the AD7731’s –100 output rate should allow the user to readily choose an output –110 rate which overcomes this issue. An alternative is to use the part –120 in nonchop mode. 09 10 20 30 40 50 60 70 800 100 FREQUENCY – Hz Figure 9. Detailed Full Frequency Response of AD7731 (SKIP = 0, CHP = 1, SF = 512) –26– REV. 0 GAIN – dB GAIN – dB AD7731 Nonchop Mode (SKIP = 0, CHP = 0) Figure 12 shows the frequency response for the same set of With CHOP mode disabled and SKIP mode disabled, the only conditions as for Figure 11 but in this case the response in shown function of the second stage filter is to give the overall frequency out to 600 Hz. This plot is comparable to that of Figure 10. The response. Figure 11 shows the frequency response for the AD7731 most notable difference is absence of the peaks in the response with the second stage filter is set for normal FIR operation, chop at 200 Hz and 400 Hz. As a result, interference at these fre- mode disabled, the decimal equivalent of the word in the SF bits quencies will be effectively eliminated before being aliased back set to 1536 and a master clock frequency of 4.9152 MHz. The to dc. response is analogous to that of Figure 9 with the three-times Table XVIII summarizes the settling time and subsequent through- larger SF word producing the same 200 Hz output rate. Once put rate for the various different modes. again, the response will scale proportionally with master clock frequency. The response is shown from dc to 100 Hz. The re- 0 jection at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz is better than 88 dB. –10 –20 The –3 dB frequency for the frequency response of the AD7731 –30 with the second stage filter set for normal FIR operation and –40 chop mode enabled is determined by the following relationship: –50 1 –60 f = 0.039 × f × CHP = 0 3 dB MOD () SF –70 –80 In this case, f = 7.8 Hz and the stop-band, where the attenu- 3 dB –90 ation is greater than 64.5 dB, is determined by: –100 1 –110 f = 0.14 × f × CHP = 0 STOP MOD () –120 SF 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY – Hz In this case, f = 28 Hz. STOP Figure 12. Expanded Full Frequency Response of AD7731 0 –10 (SKIP = 0, CHP = 0, SF = 1536) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 09 10 20 30 40 50 60 70 800 100 FREQUENCY – Hz Figure 11. Detailed Full Frequency Response of AD7731 (SKIP = 0, CHP = 0, SF = 1536) REV. 0 –27– GAIN – dB GAIN – dB AD7731 FASTStep™ Mode (SKIP = 0, FAST = 1) In FASTStep™ mode, the part has settled to the new value The second mode of operation of the second stage filter is in much faster. For example, with CHP = 1, the FASTStep™ FASTStep™ mode which enables it to respond rapidly to step mode settles to its value in two outputs while the normal mode inputs even when the second stage filter is in the loop. The settling takes 23 outputs. Between the second and 23rd output, FASTStep™ mode is not relevant with SKIP mode enabled. the FASTStep™ mode produces a settled result but with addi- The FASTStep™ mode is enabled by placing a 1 in the FAST tional noise compared to the specified noise level for its operat- bit of the Filter Register. If the FAST bit is 0, the part continues ing conditions. This noise level starts at approximately 3 times to process step inputs with the normal FIR filter as the second the final noise converging to FIR mode performance. The com- stage filter. With FASTStep™ mode enabled, the second stage plete settling time to where the part is back within the specified filter will continue to process steady state inputs with the filter noise number, is the same for FASTStep™ mode and for normal in its normal FIR mode of operation. However, the part is con- mode. When switching channels, the profile of Figure 13 will tinuously monitoring the output of the first stage filter and com- not be seen. Since the part is synchronized when a channel paring it with the second-previous output. If the difference change takes place, it will not produce an output until the filter between these two outputs is greater than a predetermined (either FASTStep™ or FIR) is settled. Table XVIII gives an threshold (1% of full scale), the second stage filter switches to a indication of the faster settling time benefits of FASTStep™ simple moving average computation. This also happens when a mode. change in channels takes place regardless of how close the volt- As can be seen from Table XVIII, the FASTStep™ mode gives ages on the two channels are. When the change is detected, the a much earlier indication of where the output channel is going STDY bit of the Status Register goes to 1. and what its new value is. This feature is very useful in scanning The initial number of averages in the moving average computa- multiple channels where the user does not have to wait for the tion is either 2 (chop enabled) or 1 (chop disabled). The num- FIR settling time to see if a channel has changed value. In this ber of averages will be held at this value as long as the threshold case, the part can be set up with CHP = 1, SKIP = 0 and FAST is exceeded. Once the threshold is no longer exceeded (the step = 1. This takes advantage of the low drift, better noise immunity on the analog input has settled), the number of outputs used to benefits of the CHOP mode. When a change in channels takes compute the moving average output is increased. The first and place, the part enters FASTStep™ mode and provides an output second outputs from the first stage filter where the threshold is result in 2 × 1/Output Rate. no longer exceeded is computed as an average by 2, then 4 Note, if the FAST bit is set and the part operated in single con- outputs with an average of 4, 8 outputs with an average of 8 and version mode, the AD7731 will continue to output results until 6 outputs with an average of 16. At this time, the second stage the STDY bit goes to 0. filter reverts back to its normal FIR mode of operation. When the second stage filter reverts back to the normal FIR, the STDY Table XVIII. Time to First and Subsequent Outputs Follow- bit of the Status Register goes to 0. ing Channel Change Figure 13 gives an indication of the different responses to a step Time Time to input with FASTStep™ mode enabled and disabled. The verti- 1 SKIP CHP FAST to First O/P Subsequent O/Ps cal axis indicates the settling of the output to the input step change while the horizontal axis shows how many outputs it 0 0 0 24 × SF/f SF/f MOD MOD takes for that settling to occur. The positive input step change 0 1 0 66 × SF/f 3 × SF/f MOD MOD 2 occurs at a time coincident with the fifth output. 10 X 3 × SF/f SF/f MOD MOD 11 X 3 × SF/f 3 × SF/f MOD MOD 20000000 00 1 3 × SF/f SF/f MOD MOD 01 1 6 × SF/f 3 × SF/f MOD MOD 1 This O/P is fully settled. 15000000 2 X = Don’t Care. 10000000 5000000 0 025 10 15 205 NUMBER OF OUTPUTS Figure 13. Step Response for FASTStep™ and Normal Operation –28– REV. 0 CODE AD7731 CALIBRATION conversion on the input voltage provided, the accuracy of the The AD7731 provides a number of calibration options that can calibration can only be as good as the noise level which the part be programmed via the MD2, MD1 and MD0 bits of the Mode provides in normal mode. To optimize the calibration accuracy, Register. The different calibration options are outlined in the it is recommended to calibrate the part at its lowest output rate Mode Register and Calibration Operations sections. A calibra- where the noise level is lowest. The coefficients generated at any tion cycle may be initiated at any time by writing to these bits of output update rate will be valid for all selected output update the Mode Register. Calibration on the AD7731 removes offset rates. This scheme of calibrating at the lowest output update and gain errors from the device. rate does mean that the duration of calibration is longer. The AD7731 gives the user access to the on-chip calibration Internal Zero-Scale Calibration registers allowing the microprocessor to read the device’s cali- An internal zero-scale calibration is initiated on the AD7731 by bration coefficients and also to write its own calibration coeffi- writing the appropriate values (1, 0, 0) to the MD2, MD1 and 2 cients to the part from prestored values in E PROM. This gives MD0 bits of the Mode Register. In this calibration mode with a the microprocessor much greater control over the AD7731’s unipolar input range, the zero-scale point used in determining calibration procedure. It also means that by comparing the the calibration coefficients is with the inputs of the differential 2 coefficients after calibration with prestored values in E PROM, pair internally shorted on the part (i.e., AIN[+] = AIN[–] = the user can verify that the device has correctly performed its Externally-Applied AIN[–] voltage). The PGA is set for the calibration. The values in these calibration registers are 24 bits selected gain (as per the RN2, RN1, RN0 bits in the Mode wide. In addition, the span and offset for the part can be ad- Register) for this internal zero-scale calibration conversion. justed by the user. The duration time of the calibration depends upon the CHP bit Internally in the AD7731, the coefficients are normalized before of the Filter Register. With CHP = 1, the duration is 22 × 1/ being used to scale the words coming out of the digital filter. Output Rate; with CHP = 0, the duration is 24 × 1/Output The offset calibration register contains a value which, when Rate. At this time the MD2, MD1 and MD0 bits in the Mode normalized, is subtracted from all conversion results. The gain Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731). calibration register contains a value which, when normalized, is The RDY line goes high when calibration is initiated and re- multiplied by all conversion results. The offset calibration coeffi- turns low when calibration is complete. Note, the part has not cient is subtracted from the result prior to the multiplication by performed a conversion at this time; it has simply performed a the gain coefficient. zero-scale calibration and updated the Offset Calibration Register for the selected channel. The user must write either The AD7731 offers self-calibration or system calibration facili- 0, 0, 1 or 0, 1 ,0 to the MD2, MD1, MD0 bits of the Mode ties. For full calibration to occur on the selected channel, the Register to initiate a conversion. If RDY is low before (or goes on-chip microcontroller must record the modulator output for low during) the calibration command write to the Mode Regis- two different input conditions. These are “zero-scale” and “full- ter, it may take up to one modulator cycle (MCLK IN/16) be- scale” points. These points are derived by performing a conver- fore RDY goes high to indicate that calibration is in progress. sion on the different input voltages provided to the input of the Therefore, RDY should be ignored for up to one modulator modulator during calibration. The result of the “zero-scale” cycle after the last bit of the calibration command is written to calibration conversion is stored in the Offset Calibration Regis- the Mode Register. ter for the appropriate channel. The result of the “full-scale” calibration conversion is stored in the Gain Calibration Register For bipolar input ranges in the internal zero-scale calibrating for the appropriate channel. With these readings, the micro- mode, the sequence is very similar to that just outlined. In this controller can calculate the offset and the gain slope for the case, the zero-scale point is exactly the same as above but since input-to-output transfer function of the converter. Internally, the part is configured for bipolar operation, the output code for the part works with 33 bits of resolution to determine its conver- zero differential input is 800000 Hex in 24-bit mode. sion result of either 16 bits or 24 bits. The internal zero-scale calibration needs to be performed as one The sequence in which the zero-scale and full-scale calibration part of a two-step full calibration. However, once a full cali- occurs depends upon the type of full-scale calibration being bration has been performed, additional internal zero-scale performed. The internal full-scale calibration is a two-step cali- calibrations can be performed by themselves to adjust the bration that alters the value of the Offset Calibration Register. part’s zero-scale point only. When performing a two-step full Thus, the user must perform a zero-scale calibration (either calibration, care should be taken as to the sequence in which the internal or system) after an internal full-scale calibration to two steps are performed. If the internal zero-scale calibration is correct the Offset Calibration Register contents. When using one part of a full self-calibration, then it should take place after system full-scale calibration, it is recommended that the zero- an internal full-scale calibration. If it takes place in association scale calibration (either internal or system) is performed first. with a system full-scale calibration, then this internal zero-scale calibration should be performed first. Calibration time is the same regardless of whether the SKIP mode is enabled or not. This is because the SKIP bit is ignored and the second stage filter is included in the calibration cycle. This is done to derive more accurate calibration coefficients. If the subsequent operating mode is with CHP = 0, the calibration should be performed with CHP = 0 so the offset calibration coefficient and the subsequent conversion offsets are consistent. Since the calibration coefficients are derived by performing a REV. 0 –29– AD7731 Internal Full-Scale Calibration The duration time of the calibration depends upon the CHP bit An internal full-scale calibration is initiated on the AD7731 by of the Filter Register. With CHP = 1, the duration is 22 × 1/ writing the appropriate values (1, 0, 1) to the MD2, MD1 and Output Rate; with CHP = 0, the duration is 24 × 1/Output MD0 bits of the Mode Register. In this calibration mode, the Rate. At this time the MD2, MD1 and MD0 bits in the Mode full-scale point used in determining the calibration coefficients is Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731). with an internally-generated full-scale voltage. This full-scale The RDY line goes high when calibration is initiated and re- voltage is derived from the reference voltage for the AD7731 turns low when calibration is complete. Note, the part has not and the PGA is set for the selected gain (as per the RN2, RN1, performed a conversion at this time; it has simply performed a RN0 bits in the Mode Register) for this internal full-scale cali- zero-scale calibration and updated the Offset Calibration Regis- bration conversion. ter for the selected channel. The user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode Register to Normally, the internal full-scale calibration is performed at the initiate a conversion. If RDY is low before (or goes low during) required operating output range. When operating with a 20 mV the calibration command write to the Mode Register, it may or 40 mV input range, it is recommended that internal full-scale take up to one modulator cycle (MCLK IN/16) before RDY calibrations are performed on the 80 mV input range. goes high to indicate that calibration is in progress. Therefore, The internal full-scale calibration is a two-step sequence which RDY should be ignored for up to one modulator cycle after the runs when an internal full-scale calibration command is written last bit of the calibration command is written to the Mode Register. to the AD7731. One part of the calibration is a zero-scale cali- For bipolar input ranges in the system zero-scale calibrating bration and as a result, the contents of the Offset Calibration mode, the sequence is very similar to that just outlined. In this Register are altered during this Internal Full-Scale Calibration. case, the zero-scale point is the mid-point of the AD7731’s The user must, therefore, perform a zero-scale calibration transfer function. (either internal or system) AFTER the internal full-scale cali- bration. This means that internal full-scale calibrations cannot The system zero-scale calibration needs to be performed as one be performed in isolation. part of a two part full calibration. However, once a full cali- bration has been performed, additional system zero-scale The duration time of the calibration depends upon the CHP bit calibrations can be performed by themselves to adjust the of the Filter Register. With CHP = 1, the duration is 44 × 1/ part’s zero-scale point only. When performing a two-step full Output Rate; with CHP = 0, the duration is 48 × 1/Output calibration, care should be taken as to the sequence in which the Rate. At this time the MD2, MD1 and MD0 bits in the Mode two steps are performed. If the system zero-scale calibration is Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731). one part of a full system calibration, it should take place before a The RDY line goes high when calibration is initiated and re- system full-scale calibration. If it takes place in association with turns low when calibration is complete. Note, the part has not an internal full-scale calibration, this system zero-scale calibra- performed a conversion at this time. The user must write either tion should be performed after the full-scale calibration. 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode Register to initiate a conversion. If RDY is low before (or goes System Full-Scale Calibration low during) the calibration command write to the Mode Regis- A system full-scale calibration is initiated on the AD7731 by ter, it may take up to one modulator cycle (MCLK IN/16) be- writing the appropriate values (1, 1, 1) to the MD2, MD1 and fore RDY goes high to indicate that calibration is in progress. MD0 bits of the Mode Register. System full-scale calibration is Therefore, RDY should be ignored for up to one modulator performed using the system’s positive full-scale voltage. This cycle after the last bit of the calibration command is written to full-scale voltage must be set up before the calibration is initi- the Mode Register. ated, and it must remain stable throughout the calibration step. The system full-scale calibration is performed at the selected System Zero-Scale Calibration gain (as per the RN2, RN1, RN0 bits in the Mode Register). System calibration allows the AD7731 to compensate for system gain and offset errors as well as its own internal errors. System The duration time of the calibration depends upon the CHP bit calibration performs the same slope factor calculations as self- of the Filter Register. With CHP = 1, the duration is 22 × 1/ calibration but uses voltage values presented by the system to Output Rate; with CHP = 0, the duration is 24 × 1/Output Rate. the AIN inputs for the zero- and full-scale points. At this time the MD2, MD1 and MD0 bits in the Mode Regis- ter return to 0, 0, 0 (Sync or Idle Mode for the AD7731). The A system zero-scale calibration is initiated on the AD7731 by RDY line goes high when calibration is initiated and returns low writing the appropriate values (1, 1, 0) to the MD2, MD1 and when calibration is complete. Note, the part has not performed MD0 bits of the Mode Register. In this calibration mode with a a conversion at this time; it has simply performed a full-scale unipolar input range, the zero-scale point used in determining calibration and updated the Gain Calibration Register for the the calibration coefficients is the bottom end of the transfer selected channel. The user must write either 0, 0, 1 or 0, 1, 0 to function. The system’s zero-scale point is applied to the AD7731’s the MD2, MD1, MD0 bits of the Mode Register to initiate a AIN input before the calibration step and this voltage must conversion. If RDY is low before (or goes low during) the cali- remain stable for the duration of the system zero-scale calibra- bration command write to the Mode Register, it may take up to tion. The PGA is set for the selected gain (as per the RN2, one modulator cycle (MCLK IN/16) before RDY goes high to RN1, RN0 bits in the Mode Register) for this system zero-scale indicate that calibration is in progress. Therefore, RDY should calibration conversion. The allowable range for the system zero- be ignored for up to one modulator cycle after the last bit of the scale voltage is discussed in the Span and Offsets Section. calibration command is written to the Mode Register. –30– REV. 0 AD7731 1.05 FS. The system full-scale calibration needs to be performed as one UPPER LIMIT. AD7731’s INPUT VOLTAGE CANNOT EXCEED THIS part of a two part full calibration. However, once a full calibra- tion has been performed, additional system full-scale calibra- GAIN CALIBRATIONS EXPAND OR CONTRACT THE AD7731’s INPUT tions can be performed by themselves to adjust the part’s gain AD7731 RANGE calibration point only. When performing a two-step full calibra- INPUT RANGE (0.8 FS TO tion, care should be taken as to the sequence in which the two 2.1 FS) 0V DIFFERENTIAL steps are performed. A system full-scale calibration should not NOMINAL ZERO-SCALE POINT be carried out unless the part contains valid zero-scale coeffi- cients. Therefore, an internal zero-scale calibration or a system zero-scale calibration must be performed before the system full- ZERO-SCALE CALIBRATIONS MOVE INPUT RANGE UP OR DOWN scale calibration when a full two-step calibration operation is LOWER LIMIT. AD7731’s INPUT –1.05 FS. being performed. VOLTAGE CANNOT EXCEED THIS Span and Offset Limits Figure 14. Span and Offset Limits Whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The overriding requirement in determining the amount of offset and Power-Up and Calibration gain that can be accommodated by the part is the requirement On power-up, the AD7731 performs an internal reset that sets that the positive full-scale calibration limit is ≤ 1.05 × FS, where the contents of the internal registers to a known state. There are FS is 20 mV through 1.28 V depending on the RN2, RN1, RN0 default values loaded to all registers after a power-on or reset. bits in the Mode Register. This allows the input range to go 5% The default values contain nominal calibration coefficients for above the nominal range. The built-in headroom in the AD7731’s the calibration registers. However, to ensure correct calibration analog modulator ensures that the part will still operate correctly for the device, a calibration routine should be performed after with a positive full-scale voltage that is 5% beyond the nominal. power-up. The range of input span in both the unipolar and bipolar modes The power dissipation and temperature drift of the AD7731 are has a minimum value of 0.8 × FS and a maximum value of low and no warm-up time is required before the initial calibra- 2.1 × FS. However, the span (which is the difference between tion is performed. However, if an external reference is being the bottom of the AD7731’s input range and the top of its input used, this reference must have stabilized before calibration is range) has to take into account the limitation on the positive initiated. Similarly, if the clock source for the part is generated full-scale voltage. The amount of offset which can be accommo- from a crystal or resonator across the MCLK pins, the start-up dated depends on whether the unipolar or bipolar mode is being time for the oscillator circuit should elapse before a calibration used. Once again, the offset has to take into account the limita- is initiated on the part (see below). tion on the positive full-scale voltage. In unipolar mode, there is Drift Considerations considerable flexibility in handling negative (with respect to The AD7731 uses chopper stabilization techniques to minimize AIN[–]) offsets. In both unipolar and bipolar modes, the range input offset drift. Charge injection in the analog multiplexer and of positive offsets that can be handled by the part depends on dc leakage currents at the analog input are the primary sources the selected span. Therefore, in determining the limits for sys- of offset voltage drift in the part. The dc input leakage current is tem zero-scale and full-scale calibrations, the user has to ensure essentially independent of the selected gain. Gain drift within that the offset range plus the span range does not exceed the converter depends primarily upon the temperature tracking 1.05 × FS. This is best illustrated by looking at a few examples. of the internal capacitors. It is not affected by leakage currents. If the part is used in unipolar mode with a required span of When operating the part in CHOP mode (CHP = 1), the signal 0.8 × FS, the offset range the system calibration can handle is chain including the first-stage filter is chopped. This chopping from –1.05 × FS to +0.25 × FS. If the part is used in unipolar reduces the overall offset drift to 5 nV/°C. When operating in mode with a required span of FS, the offset range the system CHOP mode, it is recommended to calibrate the AD7731 only calibration can handle is from –1.05 × FS to +0.05 × FS. Simi- after power-up or reset to achieve the optimum drift perfor- larly, if the part is used in unipolar mode and required to remove mance from the part. Integral and differential linearity errors are an offset of 0.2 × FS, the span range the system calibration can not significantly affected by temperature changes. handle is 0.85 × FS. Care must also be taken with external drift effects in order to If the part is used in bipolar mode with a required span of achieve optimum drift performance. The user has to be espe- ±0.4 × FS, the offset range the system calibration can handle is cially careful to avoid, as much as possible, thermocouple effects from –0.65 × FS to +0.65 × FS. If the part is used in bipolar from junctions of different materials. Devices should not be mode with a required span of ±FS, the offset range the system placed in sockets when evaluating temperature drift, there should calibration can handle is from –0.05 × FS to +0.05 × FS. Simi- be no links in series with the analog inputs and care must be larly, if the part is used in bipolar mode and required to remove taken as to how the input voltage is applied to the input pins. an offset of ±0.2 × FS, the span range the system calibration can The true offset drift of the AD7731 itself can be evaluated by handle is ±0.85 × FS. Figure 14 summarizes the span and offset performing temperature drift testing of the part with the ranges. AIN(–)/AIN(–) input channel arrangement (i.e., internal shorted input, test mode). REV. 0 –31– AD7731 USING THE AD7731 output updates will then be synchronized with the maximum Clocking and Oscillator Circuit possible difference between the output updates of the individual The AD7731 requires a master clock input, which may be an AD7731s being one MCLK IN cycle. external CMOS compatible clock signal applied to the MCLK IN Single-Shot Conversions pin with the MCLK OUT pin left unconnected. Alternatively, a The SYNC input can also be used as a start convert command crystal or ceramic resonator of the correct frequency can be allowing the AD7731 to be operated in a conventional converter connected between MCLK IN and MCLK OUT in which case fashion. In this mode, the rising edge of SYNC starts conversion the clock circuit will function as an oscillator, providing the and the falling edge of RDY indicates when conversion is com- clock source for the part. The input sampling frequency, the plete. The disadvantage of this scheme is that the settling time modulator sampling frequency, the –3 dB frequency, output of the filter has to be taken into account for every data register update rate and calibration time are all directly related to the update. master clock frequency, f . Reducing the master clock CLK IN Writing 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode regis- frequency by a factor of 2 will halve the above frequencies and ter has the same effect. This initiates a single conversion on the update rate and double the calibration time. AD7731 with the part returning to idle mode at the end of The crystal or ceramic resonator is connected across the MCLK conversion. Once again, the full settling time of the filter has to IN and MCLK OUT pins, as per Figure 15*. When using a elapse before the Data Register is updated. master clock frequency of 4.9152 MHz, C1 and C2 should both Note, if the FAST bit is set and the part operated in single con- have a value equal to 33 pF. version mode, the AD7731 will continue to output results until the STDY bit goes to 0. MCLK IN Reset Input CRYSTAL OR C1 CERAMIC AD7731 The RESET input on the AD7731 resets all the logic, the digital RESONATOR filter and the analog modulator while all on-chip registers are MCLK OUT reset to their default state. RDY is driven high and the AD7731 C2 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7731 starts to process data and RDY will return low after Figure 15. Crystal/Resonator Connections the filter has settled indicating a valid new word in the data The on-chip oscillator circuit also has a start-up time associated register. However, the AD7731 operates with its default setup with it before it has attained its correct frequency and correct conditions after a RESET and it is generally necessary to set up voltage levels. The typical start-up time for the circuit is 6 ms all registers and carry out a calibration after a RESET command. with a DV of +5 V and 8 ms with a DV of +3 V. DD DD The AD7731’s on-chip oscillator circuit continues to function The AD7731’s master clock appears on the MCLK OUT pin of even when the RESET input is low. The master clock signal the device. The maximum recommended load on this pin is one continues to be available on the MCLK OUT pin. Therefore, in CMOS load. When using a crystal or ceramic resonator to gen- applications where the system clock is provided by the AD7731’s erate the AD7731’s clock, it may be desirable to then use this clock, the AD7731 produces an uninterrupted master clock clock as the clock source for the system. In this case, it is recom- during RESET commands. mended that the MCLK OUT signal is buffered with a CMOS Standby Mode buffer before being applied to the rest of the circuit. The STANDBY input on the AD7731 allows the user to place System Synchronization the part in a power-down mode when it is not required to The SYNC input allows the user to reset the modulator and provide conversion results. The part can also be placed in its digital filter without affecting any of the setup conditions on the standby mode by writing 0, 1, 1 to the MD2, MD1, MD0 bits part. This allows the user to start gathering samples of the ana- of the Mode Register. The AD7731 retains the contents of all its log input from a known point in time, i.e., the rising edge of on-chip registers (including the Data Register) while in standby SYNC. mode. Data can still be read from the part in Standby Mode. The STBY bit of the Status Register indicates whether the part If multiple AD7731s are operated from a common master clock, is in standby or normal operating mode. When the STANDBY they can be synchronized to update their output registers simul- pin is taken high, the part returns to operating as it had been taneously. A falling edge on the SYNC input resets the digital prior to the STANDBY pin going low. filter and analog modulator and places the AD7731 into a con- sistent, known state. While the SYNC input is low, the AD7731 The STANDBY input (or 0, 1, 1 in the MD2, MD1, MD0 bits) will be maintained in this state. On the rising edge of SYNC, does not affect the digital interface. It does, however, set the the modulator and filter are taken out of this reset state and on RDY bit and pin high and also sets the STDY bit high. When the next clock edge the part again starts to gather input samples. STANDBY goes high again, RDY and STDY remain high until In a system using multiple AD7731s, a common signal to their set low by a conversion or calibration. SYNC inputs will synchronize their operation. This would nor- mally be done after each AD7731 has performed its own cali- bration or has had calibration coefficients loaded to it. The *The AD7731 has a capacitance of 5 pF on MCLK IN and 13 pF on MCLK OUT. –32– REV. 0 AD7731 Placing the part in standby mode reduces the total current to an AGND to DGND connection, the ground planes should be 10 μA typical when the part is operated from an external master connected at the AGND and DGND pins of the AD7731. If the clock, provided this master clock is stopped. If the external AD7731 is in a system where multiple devices require AGND to clock continues to run in standby mode, the standby current DGND connections, the connection should still be made at one increases to 400 μA typical. If a crystal or ceramic resonator is point only, a star ground point, which should be established as used as the clock source, then the total current in standby mode close as possible to the AD7731. is 400 μA typical. This is because the on-chip oscillator circuit Avoid running digital lines under the device as these will couple continues to run when the part is in its standby mode. This is noise onto the die. The analog ground plane should be allowed important in applications where the system clock is provided by to run under the AD7731 to avoid noise coupling. The power the AD7731’s clock, so that the AD7731 produces an uninter- supply lines to the AD7731 should use as large a trace as pos- rupted master clock even when it is in its standby mode. sible to provide low impedance paths and reduce the effects of Digital Outputs glitches on the power supply line. Fast switching signals like The AD7731 has two digital output pins, D0 and D1. When clocks should be shielded with digital ground to avoid radiating the DEN bit of the Mode Register is set to 1, these digital noise to other sections of the board and clock signals should outputs assume the logic status of bits D0 and D1 of the never be run near the analog inputs. Avoid crossover of digital Mode Register. It gives the user access to two digital port and analog signals. Traces on opposite sides of the board should pins which can be programmed over the normal serial inter- run at right angles to each other. This will reduce the effects of face of the AD7731. The two outputs obtain their supply feedthrough through the board. A microstrip technique is by far voltage from AV , thus the outputs operate to 5 V levels the best but is not always possible with a double-sided board. In DD even in cases where DV = +3 V. this technique, the component side of the board is dedicated to DD ground planes while signals are placed on the solder side. POWER SUPPLIES Good decoupling is important when using high resolution ADCs. There is no specific power sequence required for the AD7731, All analog supplies should be decoupled with 10 μF tantalum in either the AV or the DV supply can come up first. While DD DD parallel with 0.1 μF capacitors to AGND. To achieve the best the latch-up performance of the AD7731 is very good, it is from these decoupling components, they have to be placed as important that power is applied to the AD7731 before signals at close as possible to the device, ideally right up against the device. REF IN, AIN or the logic input pins in order to avoid latch-up All logic chips should be decoupled with 0.1 μF disc ceramic caused by excessive current. If this is not possible, then the capacitors to DGND. In systems where a common supply volt- current which flows in any of these pins should be limited to less age is used to drive both the AV and DV of the AD7731, it DD DD than 30 mA per pin and less than 100 mA cumulative. If sepa- is recommended that the system’s AV supply is used. This DD rate supplies are used for the AD7731 and the system digital supply should have the recommended analog supply decoupling circuitry, then the AD7731 should be powered up first. If it is capacitors between the AV pin of the AD7731 and AGND DD not possible to guarantee this, then current limiting resistors and the recommended digital supply decoupling capacitor should be placed in series with the logic inputs to again limit the between the DV pin of the AD7731 and DGND. DD current to less than 30 mA per pin and less than 100 mA total. Evaluating the AD7731 Performance Grounding and Layout A recommended layout for the AD7731 is outlined in the evalu- Since the analog inputs and reference input are differential, ation board for the AD7731. The evaluation board package most of the voltages in the analog modulator are common-mode includes a fully assembled and tested evaluation board, docu- voltages. The excellent Common-Mode Rejection of the part mentation, software for controlling the board over the printer will remove common-mode noise on these inputs. The analog port of a PC and software for analyzing the AD7731’s perfor- and digital supplies to the AD7731 are independent and sepa- mance on the PC. The evaluation board order number is rately pinned out to minimize coupling between the analog and EVAL-AD7731EB. digital sections of the device. The digital filter will provide rejec- Noise levels in the signals applied to the AD7731 may also tion of broadband noise on the power supplies, except at integer affect performance of the part. The AD7731 allows a technique multiples of the modulator sampling frequency. The digital filter for evaluating the true performance of the part, independent of also removes noise from the analog and reference inputs pro- the analog input signal. This scheme should be used after a vided those noise sources do not saturate the analog modulator. calibration has been performed on the part. As a result, the AD7731 is more immune to noise interference that a conventional high resolution converter. However, because The first method is to select the AIN6/AIN6 input channel the resolution of the AD7731 is so high and the noise levels arrangement. In this case, the differential inputs to the AD7731 from the AD7731 so low, care must be taken with regard to are internally shorted together to provide a zero differential grounding and layout. voltage for the analog modulator. External to the device, the AIN6 input should be connected to a voltage which is within the The printed circuit board that houses the AD7731 should be allowable common-mode range of the part. designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the The software in the evaluation board package allows the user to use of ground planes which can be separated easily. A minimum look at the noise performance in terms of bits and nV. Once the etch technique is generally best for ground planes as it gives the user has established that the noise performance of the part is best shielding. Digital and analog ground planes should only be satisfactory in this mode, then an external input voltage can be joined in one place. If the AD7731 is the only device requiring applied to the device incorporating more of the signal chain. REV. 0 –33– AD7731 SERIAL INTERFACE data from the input shift register takes place after eight serial The AD7731’s programmable functions are controlled via a set clock cycles for a DAC Register write while the transfer of data of on-chip registers. Access to these registers is via the part’s from the input shift register takes place after 24 serial clock serial interface. After power-on or RESET, the device expects a cycles when writing to the Filter Register. Figure 16 shows a write to its Communications Register. The data written to this timing diagram for a write operation to the input shift register of register determines whether the next operation to the part is a the AD7731. With the POL input at a logic high, the data is read or a write operation and also determines to which register latched into the input shift register on the rising edge of SCLK. this read or write operation occurs. Therefore, write access to With the POL input at a logic low, the data is latched into the one of the control registers on the part starts with a write opera- input shift register on the falling edge of SCLK. tion to the Communications Register followed by a write to the Figure 16 also shows the CS input being used to decode the selected register. Reading from the part’s on-chip registers can write operation to the AD7731. However, this CS input can be either take the form of a single read or continuous read. A single used in a number of different ways. It is possible to operate the read from a register consists of a write to the Communications part in three-wire mode where the CS input is permanently tied Register (with RW1 = 0 and RW0 = 1) followed by the read low. In this case, the SCLK line should idle high between data from the specified register. To perform continuous reads from a transfer when the POL input is high and should idle low be- register, write to the Communications Register (with RW1 = 1 tween data transfers when the POL input is low. For POL = 1, and RW0 = 0) to place the part in continuous read mode. The the first falling edge of SCLK clocks data from the microcontroller specified register can then be read from continuously until a onto the DIN line of the AD7731. It is then clocked into the write operation to the Communications Register (with RW1 = 1 input shift register on the next rising edge of SCLK. For POL = 0, and RW0 = 1) which takes the part out of continuous read the first clock edge which clocks data from the microcontroller mode. When operating in continuous read mode, the part is onto the DIN line of the AD7731 is a rising edge. It is then continuously monitoring its DIN line. Therefore, the DIN line clocked into the input shift register on the next falling edge of should be permanently low to allow the part to stay in continu- SCLK. ous read mode. Figure 5 and Figure 6, shown previously, indi- In other microcontroller applications, which require a decoding cate the correct flow diagrams when reading and writing from of the AD7731, CS can be generated from a port line. In this the AD7731’s registers. case, CS would go low well in advance of the first falling edge of The AD7731’s serial interface consists of five signals, CS, SCLK, SCLK (POL = 1) or the first rising edge of SCLK (POL = 0). DIN, DOUT and RDY. The DIN line is used for transferring Clocking of each bit of data is as just described. data into the on-chip registers while the DOUT line is used for In DSP applications, the SCLK is generally a continuous clock. accessing data from the on-chip registers. SCLK is the serial In these applications, the CS input for the AD7731 is generated clock input for the device and all data transfers (either on DIN from a frame synchronization signal from the DSP. For proces- or DOUT) take place with respect to this SCLK signal. sors with the rising edge of SCLK as the active edge, the POL Write Operation input should be tied high. For processors with the falling edge of The transfer of data into the part is to an input shift register. On SCLK as the active edge, the POL input should be tied low. In completion of a write operation, data is transferred to the speci- these applications, the first edge after CS goes low is the active fied register. This internal transfer will not take place until the edge. The MSB of the data to be shifted into the AD7731 must correct number of bits for the specified register have been be set up prior to this first active edge. loaded to the input shift register. For example, the transfer of CS t t 11 16 t 14 SCLK (POL = 1) t15 t 14 SCLK (POL = 0) t 15 t 12 t 13 MSB LSB DIN Figure 16. Write Cycle Timing Diagram –34– REV. 0 AD7731 be set up prior to this first active edge. Unlike microcontroller Read Operation applications, the DSP does not provide a clock edge to clock the The reading of data from the part is from an output shift regis- MSB from the AD7731. In this case, the CS of the AD7731 ter. On initiation of a read operation, data is transferred from places the MSB on the DOUT line. For processors with the the specified register to the output shift register. This is a paral- rising edge of SCLK as the active edge, the POL input should lel shift and is transparent to the user. Figure 16 shows a timing be tied high. In this case, the microcontroller takes data on the diagram for a read operation from the output shift register of the rising edge. If CS goes low while SCLK is low, the MSB is AD7731. With the POL input at a logic high, the data is clocked clocked out on the DOUT line from the CS. Subsequent data out of the output shift register on the falling edge of SCLK. bits are clocked from the falling edge of SCLK. For processors With the POL input at a logic low, the data is clocked out of the with the falling edge of SCLK as the active edge, the POL input output shift register on the rising edge of SCLK. should be tied low. In this case, the microcontroller takes data Figure 16 also shows the CS input being used to decode the on the falling edge. If CS goes low while SCLK is high, then the read operation to the AD7731. However, this CS input can be MSB is clocked out on the DOUT line from the CS. Subse- used in a number of different ways. It is possible to operate the quent data bits are clocked from the rising edge of SCLK. part in three-wire mode where the CS input is tied low perma- The RDY line is used as a status signal to indicate when data is nently. In this case, the SCLK line should idle high between ready to be read from the AD7731’s data register. RDY goes data transfer when the POL input is high and should idle low low when a new data word is available in the data register. It is between data transfers when the POL input is low. For POL = 1, reset high when a read operation from the data register is com- the first falling edge of SCLK clocks data from the output shift plete. It also goes high prior to the updating of the data register register onto the DOUT line of the AD7731. It is then clocked to indicate when a read from the data register should not be into the microcontroller on the next rising edge of SCLK. For initiated. This is to ensure that the transfer of data from the data POL = 0, the first clock edge which clocks data from the AD7731 register to the output shift register does not occur while the data onto the DOUT line is a rising edge. It is then clocked into the register is being updated. It is possible to read the same data microcontroller on the next falling edge of SCLK. twice from the output register even though the RDY line returns In other microcontroller applications, which require a decoding high after the first read operation. Care must be taken, however, of the AD7731, CS can be generated from a port line. In this to ensure that the read operations are not initiated as the next case, CS would go low well in advance of the first falling edge of output update is about to take place. SCLK (POL = 1) or the first rising edge of SCLK (POL = 0). For systems with a single data line, the DIN and DOUT lines Clocking of each bit of data is as just described. on the AD7731 can be connected together but care must be In DSP applications, the SCLK is generally a continuous clock. taken in this case not to place the part in continuous read mode In these applications, the CS input for the AD7731 is generated as the part monitors DIN while supplying data on DOUT and from a frame synchronization signal from the DSP. In these as a result, it may not be possible to take the part out of its applications, the first edge after CS goes low is the active edge. continuous read mode. The MSB of the data to be shifted into the microcontroller must RDY t t 10 3 CS t t 8 4 t 6 SCLK (POL = 1) t 7 t 6 SCLK (POL = 0) t 7 t 5 t t 9 5A DOUT MSB LSB Figure 17. Read Cycle Timing Diagram REV. 0 –35– AD7731 CONFIGURING THE AD7731 The AD7731 contains twelve on-chip registers which can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode and Filter Registers. The values given here are for example purposes only. Table XIX. Pseudo-Code for Initiating a Self-Calibration after Power-On/Reset 1 Write 03 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Filter Register*/ 1 Write 1332 Hex to Serial Port /* Writes to Filter Register Setting a 1 kHz Output Rate in nonCHOP Mode*/ Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write B174 Hex to Serial Port /* Writes to Mode Register Initiating Internal Full-Scale Calibration for 0 V to +1.28 V Input Range on Channel Pair AIN1/AIN2*/ Wait for RDY Low /* Wait for RDY pin to go low to indicate end of calibration cycle*/ Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write 9174 Hex to Serial Port /* Writes to Mode Register Initiating Internal Zero-Scale Calibration for 0 V to +1.28 V Input Range*/ Wait for RDY Low /* Wait for RDY pin to go low to indicate end of calibration cycle*/ /* The part has now completed self-calibration and is in idle mode*/ 1 This operation is not necessary if the default values of the Filter Register are the values used in the application. Table XX. Pseudo-Code for Looping AD7731 Through Three Fully-Differential Channels CHANNEL = 4 Hex /* Sets a Variable Called CHANNEL*/ CH_LOOP: MODE = 2177 Hex /* Sets a Variable Called MODE */ MODE = MODE AND CHANNEL /* Logical AND of Both Variables */ Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write MODE to Serial Port /* Writes to Mode Register Setting Continuous Conversion Mode for 0 V to +1.28 V Input Range on Channel Determined by CHANNEL Variable*/ Wait for RDY Low /* Wait for RDY pin to go low to Indicate Output Update*/ Write 11 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Read From Data Register*/ Read 24-Bit Data From Serial Port /* Read Conversion Result from AD7731’s Data Register*/ Increment CHANNEL /* Increments Channel Address*/ If CHANNEL = 7Hex Then Set CHANNEL = 4 Hex /* Resets Channel Address*/ Loop to CH_LOOP –36– REV. 0 AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING that the SCLK idle high, the CPOL bit of the 68HC11 should The AD7731’s flexible serial interface allows for easy interface be set to a logic 1 and the POL input of the AD7731 should be to most microcomputers and microprocessors. The pseudo-code hard-wired to a logic high. of Table XVIII and Table XIX outline typical sequences for The AD7731 is not capable of full duplex operation. If the interfacing a microcontroller or microprocessor to the AD7731. AD7731 is configured for a write operation, no data appears on Figures 18, 19 and 20 show some typical interface circuits. the DATA OUT lines even when the SCLK input is active. The serial interface on the AD7731 has the capability of operat- However, when the AD7731 is configured for continuous read ing from just three wires and is compatible with SPI interface operation, data presented to the part on the DATA IN line is protocols. The three-wire operation makes the part ideal for monitored to determine when to exit the continuous read mode. isolated systems where minimizing the number of interface lines minimizes the number of opto-isolators required in the system. DV DV DD DD Register lengths on the AD7731 vary from 8 to 16 to 24 bits. SS SYNC The 8-bit serial serial ports of most microcontrollers can handle communication with these registers as either one, two or three RESET 68HC11 8-bit transfers. DSP processors and microprocessors generally AD7731 SCLK transfer 16 bits of data in a serial data operation. Some of these SCK processors, such as the ADSP-2105, have the facility to program MISO DATA OUT the amount of cycles in a serial transfer. This allows the user to DATA IN MOSI tailor the number of bits in any transfer to match the register length of the required register in the AD7731. In any case, CS writing 32 bits of data to a 24-bit register is not an issue pro- POL vided the final 8 bits of the word are all 1s. This is because the part returns to the Communications Register following a write operation. Figure 18. AD7731 to 68HC11 Interface AD7731 to 68HC11 Interface AD7731 to 8051 Interface Figure 18 shows an interface between the AD7731 and the An interface circuit between the AD7731 and the 8XC51 micro- 68HC11 microcontroller. The diagram shows the minimum controller is shown in Figure 19. The diagram shows the mini- (three-wire) interface with CS on the AD7731 hard-wired low. mum number of interface connections with CS on the AD7731 In this scheme, the RDY bit of the Status Register is monitored hard-wired low. In the case of the 8XC51 interface the mini- to determine when the Data Register is updated. An alternative mum number of interconnects is just two. In this scheme, the scheme, which increases the number of interface lines to four, is RDY bit of the Status Register is monitored to determine when to monitor the RDY output line from the AD7731. The moni- the Data Register is updated. The alternative scheme, which toring of the RDY line can be done in two ways. First, RDY can increases the number of interface lines to three, is to monitor be connected to one of the 68HC11’s port bits (such as PC0) the RDY output line from the AD7731. The monitoring of the which is configured as an input. This port bit is then polled to RDY line can be done in two ways. First, RDY can be con- determine the status of RDY. The second scheme is to use an nected to one of the 8XC51’s port bits (such as P1.0) which is interrupt driven system in which case, the RDY output is con- configured as an input. This port bit is then polled to determine nected to the IRQ input of the 68HC11. For interfaces which the status of RDY. The second scheme is to use an interrupt require control of the CS input on the AD7731, one of the port driven system in which case, the RDY output is connected to bits of the 68HC11 (such as PC1), which is configured as an the INT1 input of the 8XC51. For interfaces which require output, can be used to drive the CS input. control of the CS input on the AD7731, one of the port bits of The 68HC11 is configured in the master mode with its CPOL the 8XC51 (such as P1.1), which is configured as an output, bit set to a logic zero and its CPHA bit set to a logic one. When can be used to drive the CS input. the 68HC11 is configured like this, its SCLK line idles low between data transfers. Therefore, the POL input of the AD7731 should be hard-wired low. For systems where it is preferable REV. 0 –37– AD7731 The 8XC51 is configured in its Mode 0 serial interface mode. AD7731 to ADSP-2103/ADSP-2105 Interface Its serial interface contains a single data line. As a result, the Figure 20 shows an interface between the AD7731 and the DATA OUT and DATA IN pins of the AD7731 should be ADSP-2105 DSP processor. In the interface shown, the RDY connected together. This means that the AD7731 must not be bit of the Status Register is again monitored to determine when configured for continuous read operation when interfacing to the Data Register is updated. The alternative scheme is to use the 8XC51. The serial clock on the 8XC51 idles high between an interrupt driven system, in which case the RDY output is data transfers and, therefore, the POL input of the AD7731 connected to the IRQ2 input of the ADSP-2105. The RFS and should be hard-wired to a logic high. The 8XC51 outputs the TFS pins of the ADSP-2105 are configured as active low out- LSB first in a write operation while the AD7731 expects the puts and the ADSP-2105 serial clock line, SCLK, is also config- MSB first so the data to be transmitted has to be rearranged ured as an output. The POL pin of the AD7731 is hard-wired before being written to the output serial register. Similarly, the low. Because the SCLK from the ADSP-2105 is a continuous AD7731 outputs the MSB first during a read operation while clock, the CS of the AD7731 must be used to gate off the clock the 8XC51 expects the LSB first. Therefore, the data read into once the transfer is complete. The CS for the AD7731 is active the serial buffer needs to be rearranged before the correct data when either the RFS or TFS outputs from the ADSP-2105 are word from the AD7731 is available in the accumulator. active. The serial clock rate on the ADSP-2105 should be lim- ited to 3 MHz to ensure correct operation with the AD7731. DV DV DD DD SYNC SYNC ADSP-2105 RESET RESET 8XC51 AD7731 AD7731 RFS POL CS TFS P3.0 DATA OUT DR DATA OUT DATA IN DT DATA IN SCLK P3.1 SCLK SCLK POL CS Figure 20. AD7731 to ADSP-2105 Interface Figure 19. AD7731 to 8XC51 Interface –38– REV. 0 AD7731 APPLICATIONS Data Acquisition The on-chip PGA allows the AD7731 to handle analog input The AD7731 with its three differential channels (or five pseudo- voltage ranges from 20 mV to 1.28 V. This makes the AD7731 differential channels) is suited to low bandwidth, high resolution suitable for a range of application areas from handling signals data acquisition systems. In addition, the three-wire digital directly from a transducer to processing fully-conditioned full- interface allows this data acquisition front end to be isolated scale inputs. Some of these applications are discussed in the with just three optoisolators. The entire system can be operated following sections. from a single +5 V supply provided that the input signals to the AD7731’s analog inputs are all of positive polarity. Figure 21 The AD7731 offers both unipolar and bipolar input ranges. In shows the AD7731 in an isolated three-channel data acquisition many cases, the application is single supply with the bipolar system. input voltages referenced to a biased-up differential voltage. Some applications will, however, require the flexibility of han- Programmable Logic Controllers dling true bipolar inputs. Figure 25 shows how to configure the The AD7731 is also suited to programmable logic controller AD7731 to handle this type of signal. applications. In such applications, the ADC is required to handle signals from a variety of different transducers. The It should be noted in multiplexed applications that an input AD7731’s programmable gain front end allows the part to either overvoltage (either >AVDD + 0.3 V or