ANALOG DEVICES AD7729

Dual Sigma-Delta ADC a with Auxiliary DAC AD7729 FEATURES GENERAL DESCRIPTION +3 V Supply Voltage This monolithic 3 V CMOS device is a low power, two-channel, Baseband Serial Port (BSPORT) input port with signal conditioning. The receive path is com- Differential IRx and QRx posed of two high performance sigma-delta ADCs with digital ADC Channels filtering. A common bandgap reference feeds the ADCs. Two 15-Bit Sigma-Delta A/D Converters A control DAC is included for such functions as AFC. The auxil- FIR Digital Filters iary functions can be accessed via the auxiliary port (ASPORT). 64 dB SNR Output Word Rate 270.83 kHz This device is available in a 28-lead TSSOP package or a Twos Complement Coding 28-lead SOIC package. On-Chip Offset Calibration Power-Down Mode Auxiliary D/A Converter Auxiliary Serial Port (ASPORT) On-Chip Voltage Reference Low Power 28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations Pagers FUNCTIONAL BLOCK DIAGRAM DVDD2 DVDD1 DGND AGND AVDD1 AVDD2 ASDI ASDIFS 10-BIT AUXDAC AUXDAC ASCLK AUXILIARY SERIAL ASDO INTERFACE ASDOFS ASE DECIMATION BSDI SD IRxP OFFSET FIR DIGITAL MODULATOR ADJUST IRxN BSDIFS FILTER BSCLK BASEBAND SERIAL DECIMATION QRxP OFFSET SD BSDO INTERFACE FIR DIGITAL MODULATOR ADJUST QRxN FILTER BSDOFS BSE DIVIDE BY 2 MCLK MUX RxON REFERENCE REFCAP RESETB REFOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 1 (AVDD1 = AVDD2 = +3 V 6 10%; DVDD1 = DVDD2 = +3 V 6 10%; DGND = AGND = AD7729–SPECIFICATIONS 0 V, f = 13 MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; T = T to T unless otherwise noted) CLK A MIN MAX Parameter AD7729A Units Test Conditions/Comments REFERENCE REFCAP Absolute Voltage, V 1.3 – 5% V min/max REFCAP REFCAP TC 50 ppm/°C typ 0.1mF Capacitor Required from REFCAP to AGND REFOUT Absolute Voltage, V 1.3 – 10% V min/max REFOUT REFOUT TC 50 ppm/°C typ 0.1mF Capacitor Required from REFOUT to AGND ADC CHANNEL SPECIFICATIONS RxON = 1 Resolution 15 Bits ADC Signal Range 2 V V p-p REFCAP V V /2 to (AVDD – V /2) Volts Differential BIAS REFCAP REFCAP V to (AVDD – V ) Volts Single-Ended REFCAP REFCAP Differential Signal Range V – V /2 V min/max For Both Positive and Negative Analog Inputs BIAS REFCAP Single-Ended Signal Range V – V V min/max For Positive Analog Inputs; Negative Analog Inputs = V BIAS REFCAP BIAS Input Sample Rate 13 MSPS Output Word Rate 270.83 kHz DC Accuracy Precalibration Offset Error–45 mV typ Post Calibration Offset Error–10 mV max Post Calibration Offset Error TC 50mV/°C typ TC = Temperature Coefficient Input Resistance (DC) 1.23 MW typ Input Capacitance 10 pF typ Dynamic Specifications Input Frequency = 67.7 kHz Dynamic Range 67 dB typ Signal to (Noise + Distortion) 64 dB min Gain Error–1 dB max Input Frequency = 67.7 kHz, wrt 1.3 V –0.5 dB max Input Frequency = 67.7 kHz, wrt V REFCAP Gain Match Between Channels–0.2 dB max Filter Settling Time 47ms typ Frequency Response Does Not Include Input Antialias RC Circuit 0 kHz–70 kHz–0.05 dB max/min 85 kHz –1 dB max 96 kHz –3.0 dB max 135 kHz –55 dB max >170 kHz –55 dB max Absolute Group Delay 23ms typ Group Delay Between Channels (0 kHz–96 kHz) 5 ns typ Coding Twos Complement 2 AUXILIARY CONVERTER Resolution 10 Bits Output Range Code 000 2/32 · V V REFCAP Offset Error–35 mV max Code 3FF 2 V V REFCAP Gain Error –60 mV min +100 mV max DC Accuracy Maximum Output for Specified Accuracy = AVDD – 0.2 V or 2.6 V, Whichever Is Lower Integral Nonlinearity–4 LSB max Differential Nonlinearity–2 LSB max Guaranteed Monotonic to 9 Bits Update Rate 540 kHz max Load Resistance 10 kW min See Figure 1 Load Capacitance 50 pF max See Figure 1 I 50mA typ SINK Full-Scale Settling Time 4ms typ LSB Settling Time 2ms typ Coding Binary –2– REV. 0 AD7729 Parameter AD7729A Units Test Conditions/Comments LOGIC INPUTS V , Input High Voltage V – 0.8 V min INH DD V , Input Low Voltage 0.8 V max INL I , Input Current 10mA max IH C , Input Capacitance 10 pF max IN LOGIC OUTPUTS V , Output High Voltage V – 0.4 V min |I | < 100 mA OH DD OUT V , Output Low Voltage 0.4 V max |I | < 100 mA OL OUT I , Low Level Output Three-State Leakage Current 10mA max OZL I , High Level Output Three-State Leakage Current 10mA max OZH POWER SUPPLIES AVDD1, AVDD2 2.7/3.3 V min/max DVDD1, DVDD2 2.7/3.3 V min/max I See Table I DD NOTES 1 Operating Temperature Range: –40°C to +105°C. Therefore, T = –40°C and T = +105°C. MIN MAX 2 During power-down, the AUXDAC has an output resistance of 30 kW approximately to AGND. Specifications subject to change without notice. R C L L 10kV 50pF Figure 1. AUXDAC Load Equivalent Circuit Table I. Current Summary (AVDD1 = AVDD2 = DVDD1 = DVDD2 = +3.3 V, RxPOWER1 = 0, RxPOWER0 = 1) Internal External Analog Digital Interface Total Current Current Current Current MCLK Conditions (typ) (typ) (typ) (max) BSE ASE ON Comments ADCs On Only 4.2 3.4 4 13.5 1 0 YES REFOUT Enabled, BSCLK = MCLK AUXDAC On Only 2 0.86 0.1 3.4 0 1 YES REFOUT Disabled, ASCLK = MCLK/48 REFCAP On Only 0.7 0.0001 0.002 1.1 0 0 NO REFOUT Disabled REFCAP and REFOUT On Only 1 0.0001 0.002 1.7 0 0 NO REFOUT Enabled All Sections Off 0.0001 0.04 0.015 0.1 0 0 YES MCLK Active Levels Equal to 0 V and DVDD All Sections Off 0.0001 0.0001 0.005 0.05 0 0 NO Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA. REV. 0 –3– AD7729 Table II. Receive Section Signal Ranges Table III. Auxiliary Section Signal Ranges Baseband Section Signal Range AUXDAC Signal Range V 1.3 V – 5% Output Code REFCAP V 1.3 V – 10% Code 000 2/32 · V REFOUT REFCAP Code 3FF 2 V REFCAP ADC ADC Signal Range 2 V REFCAP V BIAS Differential Input V /2 to (AVDD1 – V /2) REFCAP REFCAP Single-Ended Input V to (AVDD1 – V ) REFCAP REFCAP Signal Range Differential V – V /2 BIAS REFCAP Single-Ended V – V BIAS REFCAP (AVDD1 = AVDD2 = +3 V 6 10%; DVDD1 = DVDD2 = +3 V 6 10%; AGND = DGND = 0 V; TIMING CHARACTERISTICS T = T to T , unless otherwise noted) A MIN MAX Limit at Parameter T = –408C to +1058C Units Description A AUXILIARY FUNCTIONS Clock Signals See Figure 2. t 76 ns min MCLK Period 1 t 30.4 ns min MCLK Width Low 2 t 30.4 ns min MCLK Width High 3 t t ns min ASCLK Period. See Figures 4 and 6. 4 1 t 0.4 · t ns min ASCLK Width Low 5 1 t 0.4 · t ns min ASCLK Width High 6 1 t 20 ns min ASDI/ASDIFS Setup Before ASCLK Low 10 t 10 ns min ASDI/ASDIFS Hold After ASCLK Low 11 t 15 ns max ASDOFS Delay from ASCLK High 12 t 0 ns min ASDOFS Hold After ASCLK High 13 t 0 ns min ASDO Hold After ASCLK High 14 t 15 ns max ASDO Delay from ASCLK High 15 t 10 ns min ASDIFS Low to ASDI LSB Read by ASPORT 16 t t + 15 ns min Interval Between Consecutive ASDIFS Pulses 17 4 Receive Section Clock Signals See Figures 5 and 7. t t ns min BSCLK Period 7 1 0.4 · t ns min BSCLK Width Low t 8 1 0.4 · t ns min BSCLK Width High t 9 1 20 ns min BSDI/BSDIFS Setup Before BSCLK Low t 18 10 ns min BSDI/BSDIFS HoldAfter BSCLK Low t 19 15 ns max BSDOFS Delay from BSCLK High t 20 0 ns min BSDOFS Hold After BSCLK High t 21 0 ns min BSDO Hold After BSCLK High t 22 15 ns max BSDO Delay from BSCLK High t 23 10 ns min BSDIFS Low to ASDI LSB Read by BSPORT t 24 t t + 15 ns min Interval Between Consecutive BSDIFS Pulses 25 7 ASCLK = MCLK/(2 · ASCLKRATE). ASCLKRATE can have a value from 0 . . . 1023. When ASCLKRATE = 0, ASCLK = 13 MHz. BSCLK = MCLK/(2 · BSCLKRATE). BSCLKRATE can have a value from 0 . . . 1023. When BSCLKRATE = 0, BSCLK = 13 MHz. Specifications subject to change without notice. –4– REV. 0 AD7729 TIMING DIAGRAMS t t t 1 3 2 t 1 MCLK t 3 t 5 *ASCLK t 6 t 4 t *ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY 2 (MCLK/4 SHOWN HERE). Figure 2. Clock Timing Figure 4. ASCLK 100mAI t t t OL 1 3 2 MCLK TO OUTPUT PIN +2.1V C L t 8 *BSCLK 15pF t 9 100mA I OH t 7 *BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). Figure 3. Load Circuit for Timing Specifications Figure 5. BSCLK ASE (I) THREE-STATE ASCLK (O) t 10 t 17 t 16 ASDIFS (I) t 11 t 11 t 10 D9 D8 D7 ASDI (I) A1 A0 D9 D8 t t 12 13 THREE-STATE ASDOFS (O) t 14 THREE-STATE A0 D9 D8 ASDO (O) D9 A2 A1 t 15 NOTE I = INPUT, O = OUTPUT Figure 6. Auxiliary Serial Port ASPORT BSE (I) THREE-STATE BSCLK (O) t 18 t 25 t 24 BSDIFS (I) t t 19 19 t 18 A1 A0 D9 D8 D7 D9 D8 BSDI (I) t t 20 21 THREE-STATE BSDOFS (O) t 22 THREE-STATE BSDO (O) A1 A0 D9 D8 D9 A2 t 23 NOTE I = INPUT, O = OUTPUT Figure 7. Baseband Serial Port BSPORT REV. 0 –5– AD7729 ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* (T = +25°C unless otherwise stated) A Temperature Package Package AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +7 V Model Range Descriptions Options AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AD7729AR –40°C to +105°C Small Outline IC R-28 Digital I/O Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V (SOIC) Analog I/O Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V AD7729ARU –40°C to +105°C Thin Shrink Small RU-28 Operating Temperature Range Outline (TSSOP) Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C TSSOP PIN CONFIGURATION qThermal Impedance . . . . . . . . . . . . . . . . . . . +122°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C IRxP 1 28 REFCAP Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C IRxN 2 27 REFOUT SOIC QRxP 3 26 AUXDAC qThermal Impedance . . . . . . . . . . . . . . . . . . . . +72°C/W JA 4 25 QRxN DVDD1 Lead Temperature, Soldering AVDD2 5 24 DVDD2 Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C AVDD1 6 23 DGND AD7729 Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C AGND 7 22 ASE TOP VIEW *Stresses above those listed under Absolute Maximum Ratings may cause perma- (Not to Scale) ASDIFS 8 21 ASDOFS nent damage to the device. This is a stress rating only; functional operation of the ASDI 9 20 ASDO device at these or any other conditions above those listed in the operational ASCLK 10 19 BSE sections of this specification is not implied. Exposure to absolute maximum rating BSDIFS 11 18 BSDOFS conditions for extended periods may affect device reliability. BSDI 12 17 BSDO RESETB 13 16 BSCLK RxON 14 15 MCLK CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. 0 AD7729 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function 15 MCLK Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are determined by the value of DVDD2. 13 RESETB Active Low Reset Signal. This input resets the entire AD7729 chip, resetting the control registers and clearing the digital filters. The logic input levels (V and V ) for RESETB INH INL are determined by the value of DVDD2. Power Supply 6 AVDD1 Analog Power Supply Connection for the Rx Section and the Bandgap Reference. 5 AVDD2 Analog Power Supply Connection for the Auxiliary Section. 7 AGND Analog Ground Connection. 25 DVDD1 Digital Power Supply Connection. 24 DVDD2 Digital Power Supply Connection for the Serial Interface Section. This power supply also sets the threshold voltages for RxON, RESETB and MCLK. 23 DGND Digital Ground Connection. Analog Signal and Reference 1, 2 IRxP, IRxN Differential Analog Input for I Receive Channel. 3, 4 QRxP, QRxN Differential Analog Input for Q Receive Channel. 26 AUXDAC Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for functions such as Automatic Gain Control (AGC). The DAC possesses a register that is accessible via the ASPORT or BSPORT. The DAC may be individually powered down. 28 REFCAP A bypass capacitor to AGND of 0.1 mF is required for the on-chip reference. The capacitor should be fixed to this pin. 27 REFOUT Buffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to AGND) of 0.1 mF is required on this pin. Auxiliary Serial Port (ASPORT) 10 ASCLK Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT). The frequency of ASCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number. 9 ASDI Serial Data Input of ASPORT. Both data and control information are input on this pin. 8 ASDIFS Input Framing Signal for ASDI Serial Transfers. 20 ASDO Serial Data Output of ASPORT. Both data and control information are output on this pin. ASDO is in three-state when no information is being transmitted, thereby allowing external control. 21 ASDOFS Output Framing Signal for ASDO Serial Transfers. 22 ASE ASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing external control of the serial bus. Baseband Serial Port (BSPORT) 16 BSCLK Output serial clock used to clock data or control bits to and from the baseband serial port (BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number. 12 BSDI Serial Data Input of BSPORT. Both data and control information are input on this pin. 11 BSDIFS Input Framing Signal for BSDI Serial Transfers. 17 BSDO Serial Data Output of BSPORT. Both data and control information are output on this pin. BSDO is in three-state when no information is being transmitted, thereby allowing external control. 18 BSDOFS Output Framing Signal for BSDO Serial Transfers. 19 BSE BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing external control of the serial bus. ADCs 14 RxON Receive Section Power-On Digital Input. The receive section is powered up by taking pin RxON high. The receive section can alternatively be powered up by programming bit RxON in baseband control register BCRA. When the powering up/down of the receive section is being controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/ down of the receive section is being controlled by bit RxON, pin RxON should be tied low. The logic input levels (V and V ) for RxON are determined by the value of DVDD2. INH INL REV. 0 –7– AD7729 Output Rate TERMINOLOGY This is the rate at which data words are made available Absolute Group Delay (270.833 kHz). Absolute group delay is the rate of change of phase versus fre- quency, dø/df. It is expressed in microseconds. Offset Error This is the amount of offset, wrt V in the auxiliary DAC and Differential Nonlinearity REF is expressed in mVs. This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or Output Signal Span ADC. This is the output signal range for the auxiliary DAC section. Dynamic Range Sampling Rate Dynamic Range is the ratio of the maximum output signal to the This is the rate at which the modulators on the receive channels smallest output signal the converter can produce (1 LSB), ex- sample the analog input. pressed logarithmically, in decibels (dB = 201og (ratio)). For 10 Settling Time an N-bit converter, the ratio is theoretically very nearly equal to N This is the digital filter settling time in the AD7729 receive 2 (in dB, 20Nlog10(2) = 6.02N). However, this theoretical section. On initial power-up or after returning from the power- value is degraded by converter noise and inaccuracies in the down mode, it is necessary to wait this amount of time to get LSB weight. useful data. Gain Error Signal Input Span This is a measure of the output error between an ideal DAC and The input signal range for the I and Q channels is biased about the actual device output with all 1s loaded after offset error has V . REF been adjusted out. In the AD7729, gain error is specified for the auxiliary section. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the Gain Matching Between Channels output of the receive channel. The signal is the rms amplitude of This is the gain matching between the IRx and QRx channel the fundamental. Noise is the rms sum of all nonfundamental and is expressed in dBs. signals up to half the sampling frequency (f /2), excluding dc. S Group Delay Between Channels The ratio is dependent upon the number of quantization levels This is the difference between the group delay of the I and Q in the digitization process; the more levels, the smaller the quan- channels and is a measure of the phase matching characteristics tization noise. The theoretical signal to (noise + distortion) ratio of the two. for a sine wave is given by: Integral Nonlinearity Signal to (Noise + Distortion) = (6.02N + 1.76) dB This is the maximum deviation from a straight line passing through the endpoints of the auxiliary DAC transfer function. –8– REV. 0 AD7729 FUNCTIONAL DESCRIPTION AD7729 BASEBAND CODEC Receive Section 4.7kV IRxP The receive section consists of I and Q receive channels, each I CHANNEL IRx comprising of a simple switched-capacitor filter followed by a IRxN 15-bit sigma-delta ADC. On-board digital filters, which form 4.7kV part of the sigma-delta ADCs, also perform critical system-level 100pF 100pF filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive sec- 4.7kV tion is also provided with a low power sleep mode to place the QRxP receive section on standby between receive bursts, drawing only Q CHANNEL QRx minimal current. QRxN 4.7kV Switched Capacitor Input 100pF 100pF The receive section analog front-end is sampled at 13 MHz by a switched-capacitor filter. The filter has a zero at 6.5 MHz as REFOUT shown in Figure 8a. The receive channel also contains a digital TO INPUT BIAS CIRCUITRY low-pass filter (further details are contained in the following section) which operates at a clock frequency of 6.5 MHz. Due 0.1mF VOLTAGE REFCAP to the sampling nature of the digital filter, the passband is re- REFERENCE 0.1mF peated about the operating clock frequency and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs Figure 9. Example Circuit for Differential Input (Figure 8c), further simplifying the external antialiasing require- Figure 10 shows the recommended single-ended analog input ments (see Figures 9 and 10). circuit. 0 dBs AD7729 FRONT-END ANALOG FILTER TRANSFER 4.7kV IRxP MHz FUNCTION IRx 6.5 13 19.5 I CHANNEL 100pF a) Switched-Cap Filter Frequency Response IRxN 0 dBs 4.7kV QRxP QRx Q CHANNEL DIGITAL FILTER 100pF TRANSFER MHz FUNCTION QRxN 6.5 13 19.5 b) Digital Filter Frequency Response V REFOUT BIAS HIGH SPEED 0 dBs BUFFER SYSTEM FILTER REFCAP 0.1mF VOLTAGE TRANSFER REFERENCE MHz FUNCTION 0.1mF 6.5 13 19.5 c) Overall System Response of the Receive Figure 10. Example Circuit for Single-Ended Input Channel Figure 8. The circuitry of Figure 9 implements first-order low-pass filters with a 3 dB point at 338 kHz; these are the only filters that must be implemented external to the baseband section to pre- vent aliasing of the sampled signal. REV. 0 –9– AD7729 The digital filter that follows the modulator removes the large V + V /2 out-of-band quantization noise (Figure 13c), while converting BIAS REF IRxN the digital pulse train into parallel 15-bit-wide binary data. The QRxN 15-bit I and Q data, which is in twos complement format, is made available via a serial port. V BIAS IRxP QRxP QUANTIZATION NOISE V – V /2 BIAS REF F /2 S BAND OF INTEREST 3.25MHz a) Effect of High Oversampling Ratio 10 ... 00 00 ... 00 01 ... 11 ADC CODE Figure 11. ADC Transfer Function for Differential Operation NOISE SHAPING V + V BIAS REF F /2 S BAND OF 3.25MHz INTEREST IRxN b) Use of Noise Shaping to Further Improve QRxN V SNR BIAS IRxP QRxP DIGITAL FILTER CUTOFF FREQUENCY = 100kHz V – V BIAS REF F /2 S BAND OF 3.25MHz INTEREST 10 ... 00 00 ... 00 01 ... 11 c) Use of Digital Filtering to Remove the Out- ADC CODE of-Band Quantization Noise Figure 12. ADC Transfer Function for Single-Ended Figure 13. Operation Digital Filter Sigma-Delta ADC The digital filters used in the AD7729 receive section carry out The AD7729 receive channels employ a sigma-delta conversion two important functions. Firstly, they remove the out-of-band technique, which provides a high-resolution 15-bit output for quantization noise which is shaped by the analog modulator. both I and Q channels with system filtering being implemented Secondly, they are also designed to perform system level filter- on-chip. ing, providing excellent rejection of the neighboring channels. The output of the switched-capacitor filter is continuously Digital filtering has certain advantages over analog filtering. sampled at 6.5 MHz (master clock/2), by a charge-balanced Firstly, since digital filtering occurs after the A/D conversion modulator, and is converted into a digital pulse train whose process, it can remove noise injected during the conversion duty cycle contains the digital information. Due to the high process. Analog filtering cannot do this. Secondly, the digital oversampling rate, which spreads the quantization noise from filter combines low passband ripple with a steep roll-off, while 0 MHz to 3.25 MHz (F /2), the noise energy contained in the S also maintaining a linear phase response. This is very difficult to band of interest is reduced (Figure 13a). To reduce the quanti- achieve with analog filters. zation noise still further, a high order modulator is employed to However, analog filtering can remove noise superimposed on shape the noise spectrum, so that most of the noise energy is the analog signal before it reaches the ADC. Digital filtering shifted out of the band of interest (Figure 13b). cannot do this and noise peaks riding on signals near full-scale have the potential to saturate the analog modulator, even though the average value of the signal is within limits. To allevi- ate this problem, the AD7729 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV. –10– REV. 0 VOLTAGE VOLTAGE AD7729 the RxON bit or the RxON pin high, 36 symbol periods are 10 allowed for the analog and digital circuitry to settle. An internal 0 timer then times out a time equal to RxDELAY1. –10 –20 When RxDELAY1 has expired, the AD7729 offset calibration –30 routine begins, assuming the RxAUTOCAL bit in control regis- –40 ter BCRA is equal to 1. If RxAUTOCAL equals zero, no cali- –50 bration occurs and T2 in Figure 16 equals zero. In internal –60 autocalibration mode, the AD7729 internally disconnects the –70 differential inputs from the input pins and shorts the inputs to –80 measure the resulting ADC offset. In external autocalibration –90 mode, the inputs remain connected to the pins, allowing system –100 offsets along with the AD7729 internal offsets to be evaluated. –110 This is then averaged 16 times to reduce noise and the averaged –120 result is then placed in the offset register. The input to the ADC 0 50 100 150 200 250 300 is then switched back for normal operation and the analog cir- FREQUENCY – kHz cuitry and digital filter are permitted to settle. This time period Figure 14. Digital Filter Frequency Response is included in T , which equals 40 · 48 MCLK cycles. CALIBRATE Filter Characteristics The digital filter is a 288-tap FIR filter, clocked at half the mas- RxON ter clock frequency. The 3 dB point is at 96 kHz. Due to the low-pass nature of the receive filters, a settling time T0 T1 T2 T3 is associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7729 T0 = T = 36 3 48 MCLKs SETTLE digital filters have a settling time of 44.7ms (288 · 2t ). 1 T1 = RxDELAY1 = 0...255 3 48 MCLKs FIRST VALID OUTPUT WORD HERE Receive Offset Calibration T2 = T = 40 3 48 MCLKs CALIBRATE T3 = RxDELAY2 = 0...255 3 48 MCLKs Included in the digital filter is a means by which receive offsets may be calibrated out. Each channel of the digital low-pass filter Figure 16. Data Rx Procedure section has an offset register. The offset register can be made to After calibration is complete, a second timer is started which contain a value representing the dc offset of the preceding ana- times out a time equal to RxDELAY2. The range of both log circuitry. In normal operation, the value stored in the offset RxDELAY1 and RxDELAY2 is 0 to 255 units where each unit register is subtracted from the filter output data before the data equals one bit time. Therefore, the maximum delay time is appears on the serial output pin. By so doing, dc offsets in the I 255 · 1/270 kHz = 941.55 ms. and Q channels are calibrated out. Autocalibration or user- calibration can be selected. Internal autocalibration will remove As soon as RxDELAY2 has expired, valid output words appear internal offsets only while user calibration allows the user to at the output. The Rx data will be 15 bits wide. write to the offset register in order to also remove external offsets. ASDOFS The offset registers have enough resolution to hold the value of BSDOFS any dc offset between –162.5 mV (1/8th of the input range). Offsets larger than –162.5 mV will cause a spurious result due to calibration overrange. However, the performance of the sigma- ASDO VALID I DATA I FLAG VALID Q DATA Q FLAG BSDO delta modulators will degrade if full-scale signals with more than 100 mV of offset are experienced. The 10-bit offset register represents a twos complement value. The LSB of the offset T2 T2 T1 T1 registers corresponds to Bit 3 of the Rx words while the MSB of I WORD Q WORD the offset registers corresponds to Bit 12 of the Rx words (see T1 = 16 MCLKs Figure 15). T2 = 8 MCLKs Figure 17. ASDO/BSDO in Rx Mode 11 RxDATA 15 14 13 12 10 9 8 7 6 54 3 2 1 0 Receive Offset Adjust: User Calibration When user calibration is selected, the receive offset register can 9 8 7 6 54 3 2 1 0 OFFSET REGISTER be written to, allowing offsets in the IF/RF demodulation cir- cuitry to be calibrated out also. However, the user is now re- Figure 15. Position of the 10-Bit Offset Word sponsible for calibrating out receive offsets belonging to the Receive Offset Adjust: Autocalibration AD7729. When the receive path enters the low power mode, the If receive autocalibration is selected, the AD7729 will initiate an registers remain valid. After powering up, the first IQ sample autocalibration routine each time the receive path is brought out pair is output once time has elapsed for both the analog circuitry of the low power sleep mode. After RxON is asserted, by taking to settle and also for the output of the digital filter to settle. REV. 0 –11– GAIN – dB AD7729 Figure 18 shows a flow diagram for calibration of the receive Voltage Reference section. The reference of the AD7729, REFCAP, is a bandgap reference which provides a low noise, temperature compensated reference to the IQ receive ADCs and the AUXDAC. The reference is also made available on the REFOUT pin. The reference has a value of 1.3 V nominal. When the AD7729 is powered down, the reference can also be 0 RxON powered down. Alternatively, by setting bit LP to 1, the refer- ence remains powered up. This is useful as the power-up time 1 for the receive section and auxiliary converter is reduced since the reference does not require time to power up and settle. 10 Baseband and Auxiliary Serial Ports (BSPORT and ASPORT) RxAUTOCAL Both the baseband and auxiliary SPORTs are DSP compatible serial ports which provide access to the 27 on-chip registers as T SETTLE illustrated in Table IV. 10 RxEXTCAL RxDELAY1 Since some registers are accessible over both the auxiliary and baseband SPORTs, the user can decide which registers will be RESETS TO ZERO CAN HAVE A VALUE CONNECT ADC INPUTS SHORT ADC INPUTS accessible over which SPORT, this feature providing maximum OF 0...255 3 48 MCLKs flexibility for the system designer. The user also has the ability to adjust the frequency of the SCLKs in each SPORT, which is COUNTER RESETS TO 36 useful for power dissipation minimization. Furthermore, it is (36 3 48 MCLKs) TO ALLOW FOR FILTER SETTLING TIME possible for the user to access all the ADC and AUXDAC con- trol registers over one SPORT, the other SPORT being disabled T SETTLE by tying its serial port enable (SE) low. This feature is useful when the user has only one SPORT available for communica- RxDELAY1 tion with the AD7729. T 40 348 MCLK CALIBRATE Resetting the AD7729 The pin RESETB resets all the control registers. All registers except ASCLKRATE and BSCLKRATE are reset to zero. On RxDELAY2 reset, ASCLKRATE and BSCLKRATE are set to 4 so that the RESETS TO ZERO. CAN HAVE A frequency of ASCLK and BSCLK is MCLK/8. As well as reset- VALUE OF 0...255 3 48 MCLKs RxREADY ting the control registers using the reset pin, these registers can be reset using the reset bits in the baseband and auxiliary regis- Figure 18. Receive Offset Adjust ters. All the auxiliary registers can be reset by taking the bit Auxiliary Control Functions ARESET in control register ACRB high. The baseband registers The AD7729 also contains an auxiliary DAC that may be used can be reset by taking bit BRESET in baseband control register for AGC. This 10-bit DAC consists of high impedance current BCRA high. This is illustrated in Table IV. After resetting, the sources, designed to operate at very low currents while main- bits ARESET and BRESET will reset to zero. A reset using taining its dc accuracy. The DAC is buffered by an output am- ARESET or BRESET requires 4 MCLK cycles. The registers plifier and allows a load of 10 kW. ARDADDR, BRDADDR, ASCLKRATE, and BSCLKRATE The DAC has a specified output range of 2 · V /32 to 2 ·REFCAP can only be reset using the reset pin RESETB—these registers V . The analog output is: REFCAP cannot be reset using the above mentioned bits. A system reset (using BRESET) requires eight MCLK cycles. 2 V /32 + (2 V – 2 V /32) · DAC/1023 REFCAP REFCAP REFCAP The functions of the control register bits are summarized in where DAC is the 10-bit digital word loaded into the DAC Table IV to Table X. register. To perform a conversion, the DAC is first powered up using the AUXDACON bit in control register ACRA. After power-up, 10ms are required for the AUXDAC circuitry to settle. The AUXDAC is loaded by writing to register AUXDAC. When the AUXDAC is in power-down mode, the AUXDAC register will retain its contents. When the AUXDAC is reset, the AUXDAC register will be set to all zeroes, leading to a voltage of 2·V /32 on the analog output. REFCAP –12– REV. 0 AD7729 Table IV. Baseband and Auxiliary Registers Table V. Baseband Control Register A (BCRA) Bit Name Function Name R/W Address Reset BCRA0 MCLKDIV MCLK Divider. When this bit is Reserved 000000 (0) set to 0, the internal MCLK has Reserved 000001 (1) the same value as the external Reserved 000010 (2) MCLK. When this bit equals 1, IRxOFFSET R/W 000011 (3) BRESET the external MCLK is divided by QRxOFFSET R/W 000100 (4) BRESET 2 within the AD7729 so that the Reserved 000101 (5) device operates at half the exter- Reserved 000110 (6) nal clock frequency. RxDELAY1 R/W 000111 (7) BRESET BCRA1 RxAUTOCAL Selects AutoCal when set to 1 RxDELAY2 R/W 001000 (8) BRESET and UserCal when set to 0. ARDADDR R/W 001001 (9) SRESET BCRA2 RxEXTCAL When set to 1, the Rx calibration BRDADDR R/W 001010 (10) SRESET operates in external mode i.e., Reserved 001011 (11) the I and Q analog inputs remain AUXDAC R/W 001100 (12) ARESET connected to the pins during the Reserved 001101 (13) Rx autocalibration routine. Reserved 001110 (14) BCRA3 RxPOWER0 This bit, in conjunction with Reserved 001111 (15) RxPOWER1, is used to reduce Reserved 010000 (16) the analog current consumption Reserved 010001 (17) of the ADCs. ACRA R/W 010010 (18) ARESET BCRA4 RxPOWER1 This bit, in conjunction with ACRB R/W 010011 (19) ARESET RxPOWER0, is used to reduce BCRA R/W 010100 (20) BRESET the analog current consumption BCRB R/W 010101 (21) BRESET of the ADCs. Reserved 010110 (22) BCRA5 Reserved Reserved 010111 (23) BCRA6 RxON Power-on for the receive section Reserved 011000 (24) of the AD7729. ASCLKRATE R/W 011001 (25) SRESET BCRA7 BRESET Baseband Reset. BSCLKRATE R/W 011010 (26) SRESET BCRA8 Reserved BCRA9 Reserved BRESET: can be reset using pin RESETB or bit BRESET. ARESET: can be reset using pin RESETB or bit ARESET. SRESET: only the pin RESETB can reset these registers. Table VI. Power Modes for the ADCs RxPOWER1 RxPOWER0 AIDD1 Reduction 0 0 Reserved 0 1 1/3 (Power Mode 1) 1 0 2/5 (Power Mode 2) 1 1 Reserved Bits RxPOWER0 and RxPOWER1 are used to reduce the ana- log current consumption of the ADCs. The part is specified in Power Mode 1. In Power Mode 2, the MCLK needs to be less than 10 MHz. The performance of the part will then be compa- rable to the performance in Power Mode 1 except that the ADC current will now be less than 9.5 mA. Table VII. Receive Section Activation RxON Pin RxON Bit Receive Section 0 0 OFF 01 ON 10 ON 11 ON REV. 0 –13– AD7729 Table VIII. Baseband Control Register B (BCRB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Function DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A5 A4 A3 A2 A1 A0 BCRB0 Reserved Figure 19. Write Operation Frame Format BCRB1 Reserved BCRB2 RU REFOUT Use. Reading Over the Baseband (or Auxiliary) SPORT BCRB3 LP Reference Low Power. To read the contents of a register, the address of the appropriate BCRB4 RxSPORTSEL Selects the SPORT register is written to the read address register, ARDADDR or that will provide BRDADDR. The time interval between writing to the read RxDATA when RxON is address register and the frame synchronization signal becoming asserted. When set to 0, active equals 4 MCLK cycles. The read address register is the BSPORT is selected 6 bits wide and Bits D11 to D6 of the input frame are used to and, when set to 1, the write to this register, Bits D12 to D15 being don’t cares, as ASPORT is selected. shown in Figure 20. The frame format for reading is identical to BCRB5 Reserved that for writing i.e., 10 bits of data followed by 6 address bits BCRB6 Reserved corresponding to the source address of the data (with the excep- BCRB7 Reserved tion of the Rx data). BCRB8 Reserved BCRB9 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X RA5 RA4 RA3 RA2 RA1 RA0 0 0 1 0 1 0 Table IX. Auxiliary Control Register A (ACRA) Bit Name Function Figure 20. Writing to the Read Address Register (BRDADDR Shown Here) ACRA0 Reserved Receiving RxDATA ACRA1 Reserved The Rx ADC is activated by taking either the RxON bit or the ACRA2 AUXDACON Power On for Auxiliary DAC RxON pin high. In this mode, Rx data is automatically output ACRA3 Reserved on the SDO pin of the SPORT at a word rate of 270 kHz for ACRA4 Reserved each of I and Q, after a delay of T1 + T2 + T3 (see Figure 16). ACRA5 Reserved The data format is I followed by Q. The AD7729 will output ACRA6 Reserved 16 bits of data, the 15-bit I or Q word, which is in twos comple- ACRA7 Reserved ment format, and a flag bit. This flag bit (LSB) distinguishes ACRA8 Reserved between the I and Q words, the bit being at 0 when the word ACRA9 Reserved being output is an I word while this bit is at 1 when the output is a Q word. Table X. Auxiliary Control Register B (ACRB) When RxON is taken high, the serial clock will have a frequency Bit Name Function of 13 MHz, irrespective of the value in the clock rate register. When the AD7729 is ready to output Rx data, an output frame ACRB0 ARESET Resets the Auxiliary Converter synchronization signal is generated and the Rx data is automati- ACRB1 Reserved cally output on the SDO pin, an I and Q word being output ACRB2 Reserved every 48 MCLK cycles (see Figure 17). Data can be output on ACRB3 Reserved the ASPORT or the BSPORT, bit RxSPORTSEL in control ACRB4 Reserved register BCRB being used to select the SPORT. Rx data can be ACRB5 Reserved received on one SPORT only, the user cannot interchange from ACRB6 Reserved one SPORT to the other. ACRB7 Reserved ACRB8 Reserved MICROPROCESSOR INTERFACING ACRB9 Reserved The AD7729 has a standard serial interface which allows the user to interface the part to several DSPs. In all cases, the Writing Over the Baseband (or Auxiliary) SPORT AD7729 operates as the master with the DSP acting as the Writing to and reading from registers via the SPORT involves slave. The AD7729 provides its own serial clock to clock the the transfer of 16 bit words, 10 bits of data and 6 bits of address serial data/control information to/from the DSP. (with the exception of the Rx data). The frame format is as AD7721-to-ADSP-21xx Interface shown in Figure 19, Bit 15 being the first input bit of the frame. Figure 21 shows the AD7729 interface to the ADSP-21xx. For The destination of the 10-bit data is determined by the 6-bit the ADSP-21xx, the bits in the serial port control register destination address as indicated in Figure 19. Note that some should be set up as TFSR = RFSR = 1 (a frame sync is needed registers are read only and, hence, cannot be written to. for each transfer), SLEN = 15 (16-bit word length), TFSW = RFSW = 0 (normal framing), INVTFS = INVRFS = 0 (active high frame sync signals), IRFS = 0 (external RFS), ITFS = 1 (internal TFS) and ISCLK = 0 (external serial clock). –14– REV. 0 AD7729 Grounding and Layout ADSP-21xx Since the analog inputs to the AD7729 are differential, most of AD7729 the voltages in the analog modulator are common-mode volt- DR SDO ages. The excellent Common-Mode Rejection of the part will remove common-mode noise on these inputs. The analog and RFS SDOFS digital supplies of the AD7729 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filters following the ADCs will SCLK SCLK provide rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. TFS SDIFS The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modula- tor. However, because the resolution of the AD7729 ADCs is DT SDI high and the noise levels from the AD7729 are so low, care must be taken with regard to grounding and layout. Figure 21. AD7729 to ADSP-21xx Interface The printed circuit board that houses the AD7729 should be AD7729-to-TMS320C5x Interface designed so that the analog and digital sections are separated Figure 22 shows the interface between the AD7729 and the and confined to certain sections of the board. This facilitates the TMS320C5x DSP. The TMS320C5x is configured as follows: use of ground planes that can be easily separated. A minimum MCM = 0 (CLKX is an input), TXM = 1 (the transmit frame etch technique is generally best for ground planes as it gives the sync signal is generated by the DSP), FSM = 1 (a frame sync is best shielding. Digital and analog ground planes should only be required for each transfer), FO = 0 (16-bit word length). joined in one place. If the AD7729 is the only device requiring an AGND-to-DGND connection, the ground planes should be connected at the AGND-and-DGND pins of the AD7729. If TMS320C5x AD7729 the AD7729 is in a system where multiple devices require AGND- DR SDO to-DGND connections, the connection should still be made at one point only, a star ground point that should be established as FSR SDOFS close as possible to the AD7729. Avoid running digital lines under the device as these will couple CLKR noise onto the die. The analog ground plane should be allowed SCLK CLKX to run under the AD7729 to avoid noise coupling. The power supply lines to the AD7729 should use as large a trace as pos- FSX SDIFS sible to provide low impedance paths and reduce the effects of glitches on the power supply lines. Fast switching signals like clocks should be shielded with digital ground to avoid radiating SDI DX noise to other sections of the board and clock signals should never be run near the analog inputs. Traces on opposite sides of Figure 22. AD7729 to TMS320C5x Interface the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip Power-Down technique is by far the best but is not always possible with a Each section of the AD7729 can be powered down. The Rx double-sided board. In this technique, the component side of ADCs and the auxiliary DAC can be powered down individually the board is dedicated to ground planes while signals are placed by setting the appropriate bits in the control registers. When on the other side. each section is powered up, time must be allowed so that the analog and digital circuitry can settle and, also, time is needed Good decoupling is important when using high speed devices. for the reference REFCAP to power up. To reduce this power- All analog and digital supplies should be decoupled to AGND up time, Bit LP can be set to 1 so that when the ADCs and and DGND respectively with 0.1mF ceramic capacitors in paral- DAC are powered down, the reference REFCAP remains pow- lel with 10mF tantalum capacitors. To achieve the best from ered up by setting Bit LP to 1. Therefore, because the reference these decoupling capacitors, they should be placed as close as is powered up, the time needed for circuitry to settle when a possible to the device, ideally right up against the device. In section is powered up is reduced considerably since the refer- systems where a common supply voltage is used to drive both ence does not require time to power up and settle. the AVDD and DVDD of the AD7729, it is recommended that the system’s AVDD supply be used. This supply should have When all sections of the AD7729 are powered down, including the recommended analog supply decoupling between the AVDD the reference, the MCLK is stopped after 64 clock periods fol- pins of the AD7729 and AGND and the recommended digital lowing the detection of the low power state. The MCLK reacti- supply decoupling capacitors between the DVDD pins and vates when the AD7729 is communicated with, i.e., the SPORTs DGND. are activated, RxON is taken high, etc. REV. 0 –15– AD7729 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Small Outline (SOIC) (R-28) 0.7125 (18.10) 0.6969 (17.70) 28 15 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0118 (0.30) 0.0500 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0118 (0.30) 0° 0.0256 (0.65) 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) –16– REV. 0 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PRINTED IN U.S.A. C3319–8–11/98