ANALOG DEVICES AD7725

16-Bit 900 kSPS �-� ADC with a Programmable Postprocessor AD7725 FEATURES FUNCTIONAL BLOCK DIAGRAM Programmable Filtering: AV 2.5V REF2 Any Characteristic up to 108 Tap FIR and/or IIR DD AD7725 REFERENCE AGND REF1 th Polynomial Signal Conditioning up to 8 Order Programmable Decimation and Output Word Rate POST- DV PROCESSOR V (+) DD Flexible Programming Modes: IN PRESET MOD DGND V (–) FILTER IN Boot from DSP or External EPROM DEFAULT FILTER (ROM) Parallel/Serial Interface Internal Default Filter for Evaluation UNI 14.4 MHz Max Master Clock Frequency HALF PWR XTAL_OFF XTAL STBY XTAL 0 V to +4 V (Single-Ended) or �2 V (Differential) Input CLOCK SYNC CLKIN Range S/P SMODE1/DB15 Power Supplies: AV , DV : 5 V � 5% DD DD SMODE0/DB14 On-Chip 2.5 V Voltage Reference RD/WR SCR/DB13 SOE/CS CFGEND/DB12 44-Lead MQFP Package CONTROL CFMT/RS DB11 LOGIC DVAL/INT DB10 TYPICAL APPLICATIONS SDI/DB0 FSO/DB9 Radar Sonar Auxiliary Car Functions Medical Communications GENERAL DESCRIPTION The AD7725 is a complete 16-bit, �-� analog-to-digital con- Filter Wizard allows the user to design different filter types verter with on-chip, user-programmable signal conditioning. The and generates the appropriate configuration file to be down- output of the modulator is processed by three cascaded finite loaded to the postprocessor. The AD7725 also has an internal impulse response (FIR) filters, followed by a fully user-program- default filter for evaluation purposes. mable postprocessor. The postprocessor provides processing It provides 16-bit performance for input bandwidths up to power of up to 130 million accumulates (MAC) per second. The 350 kHz with an output word rate of 900 kHz maximum. The user has complete control over the filter response, the filter coeffi- input sample rate is set either by the crystal oscillator or an cients, and the decimation ratio. external clock. The postprocessor permits the signal conditioning characteris- This part has an accurate on-chip 2.5 V reference for the modu- tics to be programmed through a parallel or serial interface. It lator. A reference input/output function allows either the is programmed by loading a user-defined filter in the form of a internal reference or an external system reference to be used as configuration file. This filter can be loaded from a DSP or an the reference source for the modulator. external serial EPROM. It is generated using a digital filter The device is available in a 44-lead MQFP package and is speci- design package called Filter Wizard, which is available from the fied over a –40°C to +85°C temperature range. AD7725 section on the Analog Devices website. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. ERR/DB1 DB2 DB3 RESETCFG/DB4 INT/DB5 FSI/DB6 SCO/DB7 SDO/DB8 (AV = 5 V � 5%, AGND = AGND1 = AGND2 = DGND = 0 V, 1 DD 2 AD7725–SPECIFICATIONS f = 9.6 MHz, REF2 = 2.5 V, T = T to T , unless otherwise noted.) CLKIN A MIN MAX B Version Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC SPECIFICATIONS When tested with the FIR filter in Figure 1, HALF_PWR = Logic High Bipolar Mode 3 4 Signal-to-Noise Measurement Bandwidth = 0.5 � f O 2.5 V Reference 77 83 dB 3 V Reference 79 85 dB 3, 5 Total Harmonic Distortion –94 –86 dB 3, 5 Spurious Free Dynamic Range –98 –89 dB Unipolar Mode 3 4 Signal-to-Noise Measurement Bandwidth = 0.5 � f 83 dB O 3, 5 Total Harmonic Distortion –94 dB ANALOG INPUTS Full-Scale Input Span V (+) – V (–) IN IN Bipolar Mode Differential or Single-Ended Input ±4/5 � V V REF2 Unipolar Mode Single-Ended Input 0 8/5 � V V REF2 Absolute Input Voltage V (+) and/or V (–) AGND AV V IN IN DD Input Sampling Capacitance 2 pF 6 Input Sampling Rate, f 14.4 MHz CLKIN CLOCK CLKIN Duty Ratio 45 55 % REFERENCE REF1 Output Resistance 3.5 kΩ Reference Buffer Offset Voltage Offset between REF1 and REF2 ±3mV Using Internal Reference REF2 Output Voltage 2.39 2.54 2.69 V REF2 Output Voltage Drift 60 ppm/°C Using External Reference REF2 Input Impedance REF1 = AGND 8 kΩ 7 REF2 External Voltage Input 2.5 V STATIC PERFORMANCE Resolution 16 Bits 3 8 Differential Nonlinearity (DNL) Guaranteed Monotonic ±0.5 ±1 LSB 3 Integral Nonlinearity (INL) ±2 LSB DC CMRR 80 dB Offset Error ±20 mV 3, 9 Gain Error ±0.5 %FSR LOGIC INPUTS (Excluding CLKIN) V , Input High Voltage 2.0 V INH V , Input Low Voltage 0.8 V INL CLOCK INPUT (CLKIN) V , Input High Voltage 0.7 � DV V INH DD V , Input Low Voltage 0.3 � DV V INL DD –2– REV. A AD7725 B Version Parameter Test Conditions/Comments Min Typ Max Unit ALL LOGIC INPUTS I , Input Current V = 0 V to DV ±10 µA IN IN DD C , Input Capacitance 10 pF IN LOGIC OUTPUTS V , Output High Voltage |I | = 200 µA 4.0 V OH OUT V , Output Low Voltage |I | = 1.6 mA 0.4 V OL OUT 10 POWER SUPPLIES AV 4.75 5.25 V DD 11 12 AI HALF_PWR = Logic High 28 33 mA DD DV 4.75 5.25 V DD 13 DI With the Filter in Figure 1 84 90 mA DD 14 Power Consumption Standby Mode 30 mW NOTES 1 Operating temperature range is as follows: B Version: –40°C to +85°C. 2 f is the CLKIN frequency. CLKIN 3 See Terminology section. 4 F = output data rate. O 5 When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and AGND2. At frequencies below 10 kHz, THD degrades to –80 dB and SFDR degrades to –83 dB. 6 See Figures 23 and 24 for information regarding the number of filter taps allowed and the current consumption as the CLKIN frequency is varied. 7 The AD7725 can operate with an external reference input in the range of 1.2 V to 3.15 V. 8 Guaranteed by the design. 9 Gain Error excludes reference error. 10 All I tests are done with the digital inputs equal to 0 V or DV . DD DD 11 Analog current does not vary as the CLKIN frequency and the number of filter taps used in the postprocessor is varied. 12 If HALF_PWR is logic low, AI will typically double. DD 13 Digital current varies as the CLKIN frequency and the number of filter taps used in the postprocessor is varied. See Figures 23 and 24. 14 Digital inputs static and equal to 0 V or DV . DD Specifications subject to change without notice. 0 CUTOFF FREQUENCY = 50kHz STOP-BAND FREQUENCY = 116kHz –20 NUMBER OF FILTER TAPS USED IN THE POSTPROCESSOR = 108 OUPUT DATA RATE = CLKIN/16 –40 –60 –80 –100 –120 –140 0 50 100 116 150 200 250 300 FREQUENCY – kHz Figure 1. Digital Filter Characteristics Used for Specifications REV. A –3– ATTENUATION – dB AD7725 1, 2 Preset Filter, Default Filter, and Postprocessor Characteristics Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL FILTER RESPONSE PRESET FIR Data Output Rate f /8 Hz CLKIN Stop-Band Attenuation 70 dB Low-Pass Corner Frequency f /16 Hz CLKIN 3 Group Delay 133/(2 � f)s CLKIN 3 Settling Time 133/f s CLKIN DEFAULT FILTER Internal FIR Filter Stored in ROM Number of Taps 106 Frequency Response 0 kHz to f /546.08 ±0.001 dB CLKIN f /195.04 –3 dB CLKIN f /184.08 –6 dB CLKIN f /133.2 to f /2 –120 dB CLKIN CLKIN 3 Group Delay 2141/(2 � f)s CLKIN 3 Settling Time 2141/f s CLKIN Output Data Rate, f f /32 Hz O CLKIN POSTPROCESSOR CHARACTERISTICS Input Data Rate f /8 Hz CLKIN 4 Coefficient Precision 24 Bits Arithmetic Precision 30 Bits Number of Taps Permitted 108 Decimation Factor 2 256 Number of Decimation Stages 1 5 Output Data Rate f /4096 f /16 Hz CLKIN CLKIN NOTES 1 These characteristics are fixed by the design. 2 f is the CLKIN frequency. CLKIN 3 See Terminology section. 4 See the Configuration File Format section for more information. –4– REV. A 1, 2 (AVDD = 5 V � 5%; DV = 5 V � 5%; AGND = DGND = 0 V, REF2 = 2.5 V, DD TIMING SPECIFICATIONS AD7725 unless otherwise noted.) Parameter Symbol Min Typ Max Unit CLKIN Frequency f 114.4 MHz CLKIN CLKIN Period (t = 1/f)t 0.07 1 µs CLK CLKIN 1 CLKIN Low Pulse Width t 0.45 � t 0.55 � t 2 1 1 CLKIN High Pulse Width t 0.45 � t 0.55 � t 3 1 1 CLKIN Rise Time t5ns 4 CLKIN Fall Time t5ns 5 CLKIN to SCO Delay t 35 50 ns 6 SCO Period: SCR = 0 t 1t 7 CLK SCR = 1 t 2t 7 CLK SERIAL INTERFACE (DSP MODE ONLY) FSI Setup Time before SCO Transition t 30 ns 8 FSI Hold Time after SCO Transition t0ns 9 SDI Setup Time t 30 ns 10 SDI Hold Time t0ns 11 SERIAL INTERFACE (DSP AND BFR MODES) SCO Transition to FSO High Delay t 20 ns 12 SCO Transition to FSO Low Delay t 20 ns 13 SDO Setup before SCO Transition t 10 ns 14 SDO Hold after SCO Transition t0ns 15 SERIAL INTERFACE (EPROM MODE) SCO High Time t 8t 16 CLK SCO Low Time t 8t 17 CLK SOE Low to First SCO Rising Edge t 20 t 18 CLK Data Setup before SCO Rising Edge t 22 ns 19 PARALLEL INTERFACE DATA WRITE RS Low to CS Low t 15 ns 20 WR Setup before CS Low t 15 ns 21 RS Hold after CS Rising Edge t0ns 22 CS Pulse Width t 50 ns 23 WR Hold after CS Rising Edge t0ns 24 Data Setup Time t 10 ns 25 Data Hold Time t5ns 26 DATA READ RS Low to CS Low t 15 ns 27 RD Setup before CS Low t 15 ns 28 RS Hold after CS Rising Edge t0ns 29 RD Hold after CS Rising Edge t0ns 30 3 Data Valid after CS Falling Edge t 30 ns 31 Data Hold after CS Rising Edge t 10 ns 32 STATUS READ/INSTRUCTION WRITE CS Duty Cycle t1t 33 CLK Interrupt Clear after CS Low t 15 ns 34 RD Setup to CS Low t 15 ns 35 RD Hold after CS Rising Edge t 0ns 36 3 Read Data Access Time t 30 ns 37 Read Data Hold after CS Rising Edge t 10 ns 38 Write Data Setup before CS Rising Edge t 10 ns 39 Write Data Hold after CS Rising Edge t5ns 40 NOTES 1 Guaranteed by design. 2 Guaranteed by characterization. All input signals are specified with tr � tf � 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V and 2.4 V. REV. A –5– AD7725 I OL 1.6mA TO OUTPUT 1.6V C PIN L 25pF I OH 200�A Figure 2. Load Circuit for Digital Output Timing Specifications t t 5 4 t 2 2.3V CLKIN 0.8V t 3 t 1 SCO SCR = 0 t 6 t 7 t 6 SCO SCR = 1 t 7 Figure 3. CLKIN to SCO Relationship SCO CFMT = 0 t 8 t 9 FSI t 11 t 10 SDI D15 D4 D3 D2 D1 D0 D15 D4 D3 D2 D1 t 13 t 12 FSO t 14 t 15 SDO D15 D14 D13 D12 D1 D0 D15 D14 Figure 4. Serial Mode (DSP Mode and Boot from ROM (BFR) Mode). In BFR Mode, FSI and SDI are not used. –6– REV. A AD7725 t 16 SCO t 17 t 18 SCO t19 SDI Figure 5. Serial Mode (EPROM Mode) INT RD/WR t 24 t 21 RS t 20 t 22 CS t 23 t t 25 26 THREE-STATE THREE-STATE DB0– DB15 VALID DATA Figure 6. Parallel Mode (Writing Data to the AD7725) INT t 28 t RD/WR 30 RS t 27 t 29 CS t t 32 23 t 31 THREE-STATE THREE-STATE DB0– DB15 VALID DATA Figure 7. Parallel Mode (Reading Data from the AD7725) REV. A –7– AD7725 t 34 INT t 35 t 36 RD/WR RS CS t 23 t 33 t 40 t t 37 38 t 39 DB0 DB15 – INSTRUCTION STATUS THREE-STATE THREE-STATE THREE-STATE Figure 8. Parallel Mode (Reading the Status Register and Writing Instructions) 1 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE (T = 25°C, unless otherwise noted.) A Temperature Package Package DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V 1 DD Model Range Description Option AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD AV , AV to DV . . . . . . . . . . . . . . . . . . . . –1 V to +1 V AD7725BS –40°C to +85°CMetric Quad S-44-2 DD DD1 DD AGND, AGND1 to DGND . . . . . . . . . . . . . –0.3 V to +0.3 V Flatpack Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV + 0.3 V DD AD7725BS-REEL –40°C to +85°CMetric Quad S-44-2 Digital Outputs to DGND . . . . . . . . . –0.3 V to DV + 0.3 V DD Flatpack V (+), V (–) to AGND . . . . . . . . . . . –0.3 V to AV + 0.3 V IN IN DD REF1 to AGND . . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD EVAL- Evaluation 2 REF2 to AGND . . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD AD7725CB Board REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD EVAL- Controller DGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V 2 CONTROL Board Input Current to Any Pin except Supplies . . . . . . . . . ±10 mA 3 BRD2 I (AI + DI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA DD DD DD Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C NOTES Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C 1 S = Metric Quad Flat Package (MQFP). 2 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C This board can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. It is accom- � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W JA panied by software and technical documentation. � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 20°C/W JC 3 Evaluation Board Controller. This board is a complete unit allowing a PC to Lead Temperature, Soldering control and communicate with all Analog Devices boards ending in the CB Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C designator. To obtain the complete evaluation kit, the following needs to be Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ordered: EVAL-AD7725CB, EVAL-CONTROL BRD2, and a 12 V ac transformer. The Filter Wizard software can be downloaded from the Analog Devices website. ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7725 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –8– REV. A AD7725 PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 EFMT/DB2 1 33 SCR/DB13 PIN 1 IDENTIFIER 2 ERR/DB1 32 SMODE0/DB14 SDI/DB0 3 31 SMODE1/DB15 CFMT/RS 4 30 SOE/CS SYNC 5 29 DVAL/INT AD7725 DGND 6 TOP VIEW 28 DGND (Not to Scale) RD/WR 7 27 STBY 8 AV S/P 26 DD AGND1 9 25 AGND 10 24 UNI AGND1 11 AV 23 REF2 DD1 12 13 14 15 16 17 18 19 20 21 22 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic S/P Description 1 EFMT/DB2 Serial Mode. EFMT–Serial Clock Format, Logic Input. This clock format pin selects the clock edge to be used during configuration. When EFMT is low, Serial Data In is valid on the rising edge of SCO; when EFMT is high, Serial Data In is valid on the falling edge of SCO. During normal operation, this pin is ignored. Parallel Mode. DB2–Data Input/Output Bit. 2 ERR/DB1 Serial Mode. ERR–Configuration Error Flag, Logic Output. If an error occurs during configuration, this output goes low and is reset high by a pulse on the RESETCFG pin. Parallel Mode. DB1–Data Input/Output Bit. 3 SDI/DB0 Serial Mode. SDI–Serial Data Input. Serial data is shifted in to the AD7725 MSB first, in twos complement format, synchronous with SCO. Parallel Mode. DB0–Data Input/Output Bit (LSB). 4 CFMT/RS Serial Mode. CFMT–Serial Clock Format, Logic Input. This clock format pin selects the clock edge to be used during normal operation. When CFMT is low, Serial Data Out is valid on the rising edge of SCO; when CFMT is high, Serial Data Out is valid on the falling edge of SCO. During configuration, this pin is ignored. Parallel Mode. RS–Register Select. RS selects between the data register, used to read conversion data or write configuration data, and the instruction register. When RS is high, the status register can be read or an instruction can be written to the AD7725. When RS is low, data such as the configuration file can be written to the ADC while data such as the device ID or a conversion result can be read from the AD7725 (see Table I). REV. A –9– CLKIN DGND/DB3 XTAL RESETCFG/DB4 XTALOFF INIT/DB5 HALF_PWR FSI/DB6 AGND SCO/DB7 AV DV DD DD AGND SDO/DB8 V (–) FSO/DB9 IN V (+) IN DGND/DB10 REF1 DGND/DB11 AGND2 CFGEND/DB12 AD7725 Pin No. Mnemonic S/P Description 5 DVAL/INT Serial Mode. DVAL–Data Valid Logic Output. This output is low when there are no overflows in the postprocessor and goes high when an overflow occurs in the postprocessor. Parallel Mode. INT–Interrupt Logic Output. INT idles low. A logic high on this output pin indicates that user intervention is required. There are several cases when this may occur: • An instruction is completed. Writing an instruction or reading the status register clears the interrupt. • Write data is requested. Writing data clears the interrupt. • Read data is ready. Reading data clears the interrupt. • An error occurs – ID or CRC error in the configuration file format, or an overflow in the postprocessor. Reading the status register clears the interrupt. • The device completes power-on reset. Reading the status register clears the interrupt. 6 DGND Ground Reference for Digital Circuitry. 7 RD/WR Serial Mode. This input is not used in serial mode and should be tied to DGND. Parallel Mode. Read/Write Logic Input. This input is used in conjunction with the CS input to read data from or write data to the device. A read cycle is initiated when RD/WR is high. A write cycle is initiated when RD/WR is low. To read or write data, CS should be low. 8S/P Serial/Parallel Interface Select. When S/P is tied low, parallel mode is selected. Serial mode is selected when S/P is tied high. To change the mode, a full power cycle needs to be performed. 9, 10 AGND1 Digital Logic Power Supply Ground for the Analog Modulator. 11 AV Digital Logic Power Supply for the Analog Modulator. DD1 12 CLKIN Clock Input. An external clock source can be applied directly to this pin with XTALOFF tied high. Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 M� resistor, can be connected between the XTAL pin and the CLKIN pin with XTALOFF tied low. External capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal manufacturer’s recommendation for the load capacitors. In both cases, once power is applied to the AD7725, the clock input has to be continual. 13 XTAL Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1. 14 XTALOFF Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow the use of an external clock source. Set low to enable the crystal oscillator amplifier when using an external crystal between the CLKIN and XTAL pins. 15 HALF_PWR Logic Input. When this input is low, the typical analog current is 50 mA and a maximum CLKIN frequency of 14.4 MHz applies. When this input is high, the analog current typically halves and a maximum CLKIN frequency of 9.6 MHz applies. 16, 18 AGND Power Supply Ground for the Analog Modulator. 17 AV Power Supply Voltage for the Analog Modulator. DD 19 V (–) Negative Terminal of the Differential Analog Input. IN 20 V (+) Positive Terminal of the Differential Analog Input. IN 21 REF1 Reference Output. REF1 is connected to the output of the internal 2.5 V reference through a 3 k� resistor and to a reference buffer amplifier that drives the �-� modulator. When the internal reference is used, a 1 µF capacitor is required between REF1 and AGND to decouple the band gap noise and REF2 should be decoupled to AGND with a 220 nF and a 10 nF capacitor in parallel. 22 AGND2 Power Supply Ground for the Reference Circuitry, REF2, of the Analog Modulator. 23 REF2 Reference Input. REF2 connects to the output of an external buffer amplifier used to drive the �-� modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the internal buffer amplifier. 24 UNI Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar (differential or single-ended input) or unipolar (single-ended input) operation. A logic high input selects unipolar operation and a logic low input selects bipolar operation. 25 AGND Power Supply Ground for the Analog Modulator. 26 AV Power Supply Voltage for the Analog Modulator. DD –10– REV. A AD7725 Pin No. Mnemonic S/P Description 27 STBY Standby, Logic Input. When STBY is taken high, the device will enter a low power mode. If the device was fully configured before entering this mode, it will not lose its configuration data. When STBY is brought low, the device exits the low power mode. If the device was partially configured before entering the low power mode, it will restart the configuration process in the case of boot from ROM (BFR) mode, DSP mode, and EPROM mode or, in parallel mode, a new configure instruction must be issued to configure the device. If the device was fully configured before entering the low power mode, it will continue to output conversion results in all serial modes; in parallel mode, the device will wait for an instruction to begin converting. In STBY mode, the clock input must be continual. 28 DGND Ground Reference for Digital Circuitry. 29 SYNC Synchronization Logic Input. When using more than one AD7725 operated from a common master clock, SYNC allows each ADC to simultaneously sample its analog input and update its output register. When SYNC is high, the digital filter sequencer counter is reset to zero and the postprocessor core is reset. Because the digital filter and sequencer are completely reset during this action, SYNC pulses cannot be applied continuously. When SYNC is taken low, normal conversions continue, with valid data resulting after the filter setting time. 30 SOE/CS Serial Mode. SOE–Serial Output Enable. In EPROM mode, SOE going low enables the external EPROM and is used to reset the EPROM’s address counter. In DSP mode, SOE is an active high interrupt. It goes high after a power-on reset and after a pulse on the RESETCFG pin, indicating the device is ready to be configured. It also goes high following a successful configuration, indicating that the device was configured correctly. SOE is reset low when FSI is detected high by CLKIN. In BFR mode, SOE pulses high for eight CLKIN cycles at the end of a successful configuration. Parallel Mode. CS–Chip Select Logic Input. This is an active low logic input used in conjunction with the RD/WR input to read data from or write data to the device. For a read operation, the falling edge of CS takes the bus out of three-state and either the conversion data or the status register data (depending on the state of the RS input), is placed onto the data bus, after the time t . For a write operation, the rising edge of CS 31 is used to latch either the configuration data or the instruction (depending on the state of the RS input) into the AD7725. In this case, the data should be set up for a time t before 25 the CS rising edge. 31 SMODE1/DB15 Serial Mode. SMODE1–Serial Mode Select, Logic Input. This pin selects the serial mode to be used (see Table IV) and thus informs the device where to download configuration data from automatically on power up. To change the value on this pin, a full power cycle needs to be performed. Parallel Mode. DB15–Data Input/Output Bit (MSB). 32 SMODE0/DB14 Serial Mode. SMODE0–Serial Mode Select, Logic Input. This pin selects the serial mode to be used (see Table IV) and thus informs the device where to download configuration data from automatically on power-up. To change the value on this pin, a full power cycle needs to be performed. Parallel Mode. DB14–Data Input/Output Bit. 33 SCR/DB13 Serial Mode. SCR–Serial Clock Rate Select, Logic Input. With SCR set to logic low, the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high sets the frequency of SCO to one half the CLKIN frequency. Parallel Mode. DB13–Data Input/Output Bit. 34 CFGEND/DB12 Serial Mode. CFGEND–Configuration End, Logic Output. A logic high on CFGEND indicates that device programming is complete and no programming errors occurred. Parallel Mode. DB12–Data Input/Output Bit. 35 DGND/DB11 Serial Mode. DGND–Digital Ground. Parallel Mode. DB11–Data Input/Output Bit. 36 DGND/DB10 Serial Mode. DGND–Digital Ground. Parallel Mode. DB10–Data Input/Output Bit. 37 FSO/DB9 Serial Mode. FSO–Frame Synchronization Output. FSO indicates the beginning of a word transmission on the SDO pin. The FSO signal is a positive pulse approximately one SCO period wide. Parallel Mode. DB9–Data Input/Output Bit. REV. A –11– AD7725 Pin No. Mnemonic S/P Description 38 SDO/DB8 Serial Mode. SDO–Serial Data Output. The serial data is shifted out of the AD7725 MSB first, in twos complement format, synchronous with SCO. Parallel Mode. DB8–Data Input/Output Bit. 39 DV Digital Power Supply Voltage. DD 40 SCO/DB7 Serial Mode. SCO–Serial Clock Output. The frequency of SCO is a function of the CLKIN frequency and is set by the SCR pin. When configuration data is being loaded into the AD7725, SCO = f /16. CLKIN Parallel Mode. DB7–Data Input/Output Bit. 41 FSI/DB6 Serial Mode. FSI–Frame Synchronization Input. FSI indicates the beginning of a word transmission on the SDI pin. Parallel Mode. DB6–Data Input/Output Bit. 42 INIT/DB5 Serial Mode. INIT–Logic Input. When the device is correctly configured, a logic low on this pin will prevent the device from converting. When this pin is taken high, the device will start converting. When daisy-chaining multiple devices, this pin ensures that all devices sample their analog inputs simultaneously without needing to activate the SYNC pin. Parallel Mode. DB5–Data Input/Output Bit. 43 RESETCFG/DB4 Serial Mode. RESETCFG–Logic Input. RESETCFG is used to reset the part when a configuration error occurs. A low pulse on this pin will reset the part, and the configuration file will be downloaded again. The SOE pin will go high following a pulse on the RESETCFG pin and then again following a successful configuration. Parallel Mode. DB4–Data Input/Output Bit. 44 DGND/DB3 Serial Mode. DGND–Digital Ground. Parallel Mode. DB3–Data Input/Output Bit. –12– REV. A AD7725 TERMINOLOGY Total Harmonic Distortion (THD) Integral Nonlinearity (INL) THD is the ratio of the rms sum of the harmonics to the rms This is the maximum deviation of any code from a straight line value of the fundamental. THD is defined as passing through the endpoints of the transfer function. The  2 2 2 2 2  VV + +++ VVV endpoints of the transfer function are zero scale (not to be 2 3 4 5 6 THD = 20log   confused with bipolar zero), a point 0.5 LSB below the first  V  1   code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a where V is the rms amplitude of the fundamental and V , V , 1 2 3 point 0.5 LSB above the last code transition (011...10 to V , V , and V are the rms amplitudes of the second through 4 5 6 011 . . . 11 in bipolar mode, 111 . . . 10 to 111...11 in sixth harmonics. unipolar mode). The error is expressed in LSBs. Spurious Free Dynamic Range (SFDR) Differential Nonlinearity (DNL) Defined as the difference, in dB, between the peak spurious or This is the difference between the measured and the ideal harmonic component in the ADC output spectrum (up to 1LSB change between two adjacent codes in the ADC. f /2 and excluding dc) and the rms value of the fundamental. O Normally, the value of this specification will be determined by Unipolar Offset Error the largest harmonic in the output spectrum of the FFT. For Unipolar offset error is the deviation of the first code transition input signals whose second harmonics occur in the stop band from the ideal V (+) voltage, which is (V (–) + 0.5 LSB) when IN IN region of the digital filter, the spur in the noise floor limits operating in the unipolar mode. the SFDR. Bipolar Offset Error Settling Time and Group Delay This is the deviation of the midscale transition code The settling time of a digital filter is dependent on the amount (111 . . . 11 to 000 . . . 00) from the ideal V (+) voltage, IN of decimation employed and the number of filter taps used in which is (V (–) – 0.5 LSB) when operating in the bipolar mode. IN the filter design and is calculated as follows: Gain Error   The first code transition should occur at an analog value 1 settling time =   × number of taps 0.5 LSB above negative full scale. The last code transition data input rate   should occur for an analog value 1.5 LSB below the nominal The settling time for each filter stage should be calculated full scale. Gain error is the deviation of the actual difference separately and then added to get the total filter settling time. between first and last code transitions and the ideal difference Group delay is half the settling time. between first and last code transitions. Signal-to-Noise Ratio (SNR) SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all of the nonfundamental signals up to half the output data rate (f /2), excluding dc. The ADC is O evaluated by applying a low noise, low distortion sine wave signal to the input pins. By generating a Fast Fourier Trans- form (FFT) plot, the SNR data can then be obtained from the output spectrum. REV. A –13– AD7725–Typical Performance Characteristics PERFORMANCE PLOTS The following typical plots are generated using the digital filter shown in Figure 1. (AV = DV , T = 25�C, CLKIN = 9.6 MHz, External Reference = 2.5 V, unless otherwise noted.) DD DD A 110 5000 8192 SAMPLES TAKEN INPUT FREQUENCY = 10kHz V (+) = V (–) IN IN 100 MAXIMUM OUTPUT DATA RATE 4000 90 80 3000 SFDR THD SNR 70 2000 60 50 1000 40 30 0 –50 –40 –30 –20 –10 0 32717 32718 32719 32720 32721 32722 32723 32724 32725 32726 ANALOG INPUT LEVEL – dB CODE TPC 1. SNR, THD, and SFDR vs. Analog Input TPC 4. Histogram of Output Codes for a DC Input Level Relative to Full Scale 120 0 INPUT FREQUENCY = 10kHz SNR = 84dB –20 THD = –93.85dB 110 SFDR = –98.47dB THD AIN = 10kHz –40 MEASURED BW = 300kHz SFDR 100 –60 90 –80 SNR –100 80 –120 70 –140 60 –160 0 2.4 4.8 7.2 9.6 12 14.4 250 0 50 100 150 200 300 CLKIN FREQUENCY – MHz FREQUENCY – kHz TPC 2. SNR, THD, and SFDR vs. Sampling Frequency TPC 5. 16k Point FFT 0 110 SNR = 80.48dB INPUT FREQUENCY = 10kHz –20 THD = –90.62dB 105 SFDR = –98dB AIN = 10kHz –40 100 MEASURED BW = 450kHz THD 95 –60 SFDR –80 90 –100 85 SNR –120 80 –140 75 –160 70 75 0 50 100 150 200 250 300 350 400 450 –50 –25 0 25 50 100 FREQUENCY – kHz TEMPERATURE – C TPC 3. SNR, THD, and SFDR vs. Temperature TPC 6. 16k Point FFT for a 108 Tap Low-Pass FIR Filter Operating with a CLKIN Frequency of 14.4 MHz –14– REV. A dB dB dB FREQUENCY OF OCCURRENCE POWER LEVEL RELATIVE TO FULL SCALE – dB POWER LEVEL RELATIVE TO FULL SCALE – dB AD7725 CIRCUIT DESCRIPTION APPLYING THE AD7725 The AD7725 employs a �-� conversion technique to convert Analog Input Range the analog input into an equivalent digital word. The modulator The AD7725 has differential inputs to provide common-mode samples the input waveform and outputs an equivalent digital noise rejection. In unipolar mode, the analog input is single- word at the input clock frequency, f . ended and its range is 0 V to (8/5 � V ). In bipolar mode, CLKIN REF2 the analog input is single-ended or differential, and its input Due to the high oversampling rate, which spreads the quantiza- range is ±(4/5 � V ). The output code is twos complement REF2 tion noise from 0 to f /2, the noise energy contained in the CLKIN in both modes with 1 LSB = 61 µV. band of interest is reduced (Figure 9a). To further reduce the quantization noise, a high order modulator is employed to shape The ideal input/output transfer characteristics for the two the noise spectrum so that most of the noise energy is shifted modes are shown in Figure 10. In both modes, the absolute out of the band of interest (Figure 9b). voltage on each input must remain within the supply range AGND to AV . Bipolar mode allows either single-ended or DD The digital filtering that follows the modulator removes the differential input signals while unipolar mode allows single- large out-of-band quantization noise (Figure 9c) while also ended signals. reducing the data rate from f at the input of the filter to CLKIN f /16 or less at the output of the filter, depending on the CLKIN filter type used. 011...111 011...110 Digital filtering has certain advantages over analog filtering. Because digital filtering occurs after the A/D conversion, it can 000...010 remove noise injected during the conversion process. Analog filtering cannot do this. The digital filter also has a linear 000...001 phase response. 000...000 111...111 111...110 QUANTIZATION NOISE 100...001 f /2 CLKIN BAND OF INTEREST 100...000 a. –4/5 � V 0V REF2 4/5 � V – 1LSB BIPOLAR REF2 (4/5 � V ) (0V) REF2 (8/5 � V – 1LSB) UNIPOLAR REF2 DIFFERENTIAL INPUT VOLTAGE, V (+) – V (–) NOISE SHAPING IN IN Figure 10. Bipolar/(Unipolar) Mode Transfer Function f /2 CLKIN BAND OF INTEREST The AD7725 will accept full-scale inband signals; however, b. large scale out-of-band signals can overload the modulator inputs. A minimal single-pole RC antialias filter set to f /24 will allow CLKIN full-scale input signals over the entire frequency spectrum. DIGITAL FILTER CUTOFF FREQUENCY Analog Input The analog input of the AD7725 uses a switched capacitor f /2 CLKIN BAND OF INTEREST c. technique to sample the input signal. For the purpose of driving the AD7725, an equivalent circuit of the analog inputs is shown Figure 9. �-� ADC in Figure 11. For each half-clock cycle, two highly linear sam- The AD7725 employs three fixed finite impulse response (FIR) pling capacitors are switched to both inputs, converting the filters in series. Each individual filter’s output data rate is half input signal into an equivalent sampled charge. A signal source that of its input data rate. The fourth stage is programmable; driving the analog inputs must be able to source this charge, the user can select a range of different filter responses at this while also settling to the required accuracy by the end of each stage. Both the filter response and the decimation are user pro- half-clock phase. grammable. See the Filtering section for more details. REV. A –15– OUTPUT CODE AD7725 With the unipolar input mode selected, just one op amp is AD7725 required to buffer the single-ended input signal to the V (+) IN �A input, and a dc input is applied to the V (–) pin to provide an IN 500� V (+) offset. However, driving the AD7725 with differential signals IN 2pF �B (i.e., the bipolar input range is selected) has some distinct advantages: even-order harmonics in both the drive circuits and 2pF �A the AD7725 front end are attenuated, and the peak-to-peak 500� input signal range on both inputs is halved. Halving the input V (–) IN �B signal range allows some op amps to be powered from the same AC GROUND supplies as the AD7725. An example of providing differential drive to the AD7725 is to use a dual op amp. �A �B �A �B CLKIN Dual Op Amp Although this differential drive circuit will require two op amps per ADC, it may avoid the need to generate additional supplies just for these op amps. Figure 11. Analog Input Equivalent Circuit Figures 13 and 14 show two circuits for driving the AD7725. Driving the Analog Inputs Figure 13 is intended for use when the input signal is biased To interface the signal source to the AD7725, at least one op about 2.5 V, while Figure 14 is used when the input signal is amp will generally be required. The choice of op amp will be biased about ground. While both circuits convert the input critical to achieving the full performance of the AD7725. The signal into a differential signal, the circuit in Figure 14 also level op amp not only has to recover from the transient loads that the shifts the signal so that both outputs are biased about 2.5 V. ADC imposes on it, but it must also have good distortion char- acteristics and very low input noise. Resistors in the signal path Suitable op amps include the AD8047, the AD8041 and its dual will also add to the overall thermal noise floor, necessitating the equivalent the AD8042, or the AD8022. The AD8047 has choice of low value resistors. lower input noise than the AD8041/AD8042 but has to be supplied from a +7.5 V/–2.5 V supply. The AD8041/AD8042 Placing an RC filter between the drive source and the ADC will typically degrade the SNR from 83 dB to 81 dB but can be inputs, as shown in Figure 12, has a number of beneficial powered from the same single 5 V supply as the AD7725. effects: transients on the op amp outputs are significantly reduced since the external capacitor now supplies the instanta- R FB neous charge required when the sampling capacitors are switched 220� R to the ADC input pins, and input circuit noise at the sample IN AIN = 2V V+ 50� 390� AD7725 images is now significantly attenuated, resulting in improved BIASED R 27� SOURCE ABOUT +2.5V overall SNR. The external resistor serves to isolate the external V (+) IN capacitor from the ADC output, thus improving op amp stabil- V– ity while also isolating the op amp output from any remaining 220� transients on the capacitor. By experimenting with different 220pF 220� filter values, the optimum performance can be achieved for each application. As a guideline, the RC time constant (R � C) should V+ be less than a quarter of the clock period to avoid nonlinear 27� V (–) IN currents from the ADC inputs being stored on the external capacitor and degrading distortion. This restriction means that REF2 V– this filter cannot form the main antialias filter for the ADC. 220nF 10nF R REF1 V (+) IN 1�F 10k� C AD7725 R V (–) IN Figure 13. Single-Ended-to-Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased about 2.5 V) Figure 12. Input RC Network –16– REV. A AD7725 R FB Where the output common-mode range of the amplifier driving 220� the inputs is restricted, the full-scale input signal span can be R IN AIN = 2V 50� 390� reduced by applying a lower than 2.5 V reference. For example, BIASED 27� R a 1.25 V reference would make the bipolar (differential) input SOURCE ABOUT V (+) IN GROUND range ±1 V but would degrade SNR. In all cases, since the REF2 voltage connects to the analog 220� modulator, a 220 nF and 10 nF capacitor must connect directly 220� AD7725 220pF from REF2 to AGND. The external capacitors provide the charge required for the dynamic load presented at the REF2 pin 220� (see Figure 16). 27� V (–) IN 10k� AD7725 � A REF2 20k� � 220nF 10nF B 4pF REF2 REF1 220nF 10nF 4pF � A 1�F � B SWITCHED-CAPACITOR DAC REFERENCE Figure 14. Single-Ended-to-Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased about Ground) Applying the Reference �A �B �A �B CLKIN The AD7725 can operate with either an external reference or with its on-chip 2.5 V reference. A block diagram of the internal Figure 16. REF2 Equivalent Input Circuit reference circuit is shown in Figure 15. The internal reference The AD780 is ideal to use as an external reference with the circuitry includes an on-chip 2.5 V band gap reference and a AD7725. Figure 17 shows a suggested connection diagram. reference buffer circuit. The internal 2.5 V reference voltage is Grounding Pin 8 on the AD780 selects the 3 V output mode. connected to the REF1 pin through a 3 kΩ resistor. It is buffered to drive the analog modulator’s switched capacitor DAC (REF2) AD780 as shown in Figure 15. When using the internal reference, a 1 µF 5V O/P 1 8 NC capacitor is required between REF1 and AGND to decouple the 2.5V SELECT REF2 2 +V NC 7 band gap noise. If the internal reference is required to bias IN external circuits, an external precision op amp should be used to 1�F 3 6 TEMP V AD7725 220nF 10nF OUT 22nF buffer REF1. 4 GND 5 22�F TRIM REF1 NC = NO CONNECT COMPARATOR 1V AD7725 Figure 17. External Reference Circuit Connection REFERENCE Clock Generation BUFFER SWITCHED-CAPACITOR REF1 The AD7725 has an on-chip oscillator circuit to allow a crystal DAC REFERENCE or an external clock signal to generate the master clock for 1�F the ADC. In both cases, the clock input has to be continual; 2.5 once power is applied to the AD7725, it has to be continually REFERENCE 3k� clocked. The connection diagram for use with a crystal is shown REF2 in Figure 18. Consult the manufacturer’s recommendation for 220nF 10nF the load capacitors. To enable the oscillator circuit on the AD7725, XTAL_OFF should be tied low. Figure 15. Reference Circuit Block Diagram Where gain error or gain drift requires the use of an external reference, this can be applied directly to the REF2 pin. In this case, the reference buffer in Figure 15 can be turned off by grounding the REF1 pin. The AD7725 will accept an external reference voltage between 1.2 V and 3.15 V. REV. A –17– AD7725 FILTERING The Preset Filter XTAL MCLK The preset filter is the digital filter directly following the modu- lator. This is a fixed filter whose main function is to remove the 1M� large out-of-band quantization noise shaped by the modulator. This filter is made up of three cascaded half-band FIR filters, and each filter decimates by two. The word rate into the preset filter is CLKIN, and due to the decimation in the three subse- Figure 18. Crystal Oscillator Connection quent filter stages, the output word rate of the preset filter, and When an external clock source is being used, the internal oscil- thus the input word rate to the postprocessor, is CLKIN/8. See lator circuit can be disabled by tying XTAL_OFF high. A low Figure 19. phase noise clock should be used to generate the ADC sam- pling clock because sampling clock jitter effectively modulates MODULATOR the input signal and raises the noise floor. The sampling clock INPUT WORD RATE = CLKIN generator should be isolated from noisy digital circuits, grounded, and heavily decoupled to the analog ground plane. FIR 1 DEC � 2 The sampling clock generator should be referenced to the analog FIR 2 PRESET ground in a split ground system; however, this is not always pos- DEC � 2 FILTER sible because of system constraints. In many applications, the FIR 3 sampling clock must be derived from a higher frequency multi- DEC � 2 purpose system clock that is generated on the digital ground OUTPUT WORD RATE = CLKIN/8 plane. If the clock signal is passed between its origin on a digital POST- ground plane to the AD7725 on the analog ground plane, the PROCESSOR ground noise between the two planes adds directly to the clock Figure 19. The Preset Filter and will produce excess jitter. The jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmon- The Postprocessor TM ics. This can be remedied somewhat by transmitting the sampling The AD7725 contains Systolix’s PulseDSP user-program- signal as a differential one, using either a small RF transformer mable postprocessor. The postprocessor directly follows the or a high speed differential driver and a receiver such as PECL. preset filter. The postprocessor core is a systolic array of simple In either case, the original master system clock should be gener- high performance processors. These processors are grouped into ated from a low phase noise crystal oscillator. 36 multiply accumulate (MAC) blocks, with each block consist- ing of three multipliers and one adder. Each block can process SYSTEM SYNCHRONIZATION three filter taps, thus the postprocessor allows up to 36 � 3 = 108 The SYNC input provides a synchronization function for use in filter taps. In a systolic array, numerical data is pumped around parallel or serial mode. SYNC allows the user to begin gathering processors. Each of these processors is allocated to a dedicated samples of the analog input from a known point in time. This function and only performs that single function. The data is allows a system using multiple AD7725s, operated from a passed between processors and, in this manner, complex opera- common master clock, to be synchronized so that each ADC tions are performed on the input signal. In the AD7725, data simultaneously updates its output register. In a system using transfers between processors are fully synchronous. As a result, multiple AD7725s, a common signal to their SYNC inputs the user does not have to consider timing issues. will synchronize their operation. When SYNC is high, the digi- The postprocessor core is optimized for signal conditioning tal filter sequencer is reset to zero. A SYNC pulse, one CLKIN applications. In this type of application, generally the most cycle long, can be applied. This way, SYNC is sensed low on common function is filtering. The core can support any filter the next rising edge of CLKIN. When SYNC is sensed low, structure, whether FIR, IIR, recursive, or nonrecursive. The normal conversion continues. Following a SYNC, the modula- core also supports polynomial functions, commonly used in tor and filter need time to settle before data can be read from linearization algorithms. the AD7725. Also, when INIT is taken high, it activates SYNC, Data can be transparently decimated or interpolated when which ensures that multiple devices cascaded in serial mode will passed between processors. This simplifies the design of multirate sample their analog inputs simultaneously. filtering and gives great flexibility when specifying the final output word rate. The AD7725 postprocessor supports decima- tion/interpolation by factors up to 256. –18– REV. A AD7725 Figure 20 shows an example of a filtering function implemented frequency, transition width, attenuation) before generating the on the postprocessor. Figure 20a shows the data path representa- coefficients. Once the filter characteristics have been decided, tion of an FIR filter, while Figure 20b shows how this algorithm the configuration file is generated and will be ready for loading would be implemented on the AD7725. Because the postprocessor into the postprocessor. can implement three filter taps per MAC block, 1.3 MAC Filter Configuration File Format blocks are required to implement a 4-tap FIR filter. This is a The configuration file that is generated by the Filter Wizard is useful guideline when calculating the design requirements for a made up of 8272 bits of data. The first word in the file is called new application. the ID word, and the device will accept the configuration file only if this is 0x7725. The rest of the configuration data is split into 12 SIGNAL –1 –1 –1 –1 Z Z Z Z IN blocks of 672 bits. The AD7725 postprocessor therefore accepts 672 bits at a time (42, 16-bit words). Each block of 672 bits is C C C C 0 1 2 3 followed by a cyclic redundancy check (CRC) word. The ID word and the CRC words are used by the device to check for SIGNAL errors in the configuration file and are not actually written to the OUT postprocessor. The postprocessor therefore holds 8064 bits of a) FIR Data Path Representation data (672 � 12). See the Serial Mode and Parallel Mode sections for further information on how configuration errors are detected 1 MAC BLOCK and handled. The filter coefficients in the configuration file that are loaded into the postprocessor have 24-bit precision and have SIGNAL –1 –1 –1 a value in the range –8 ≤ coefficient < +8. The coefficients are Z Z Z IN made up of 1 sign bit, 3 magnitude bits left of the decimal point, and 20 right of the decimal point. C C C C 0 1 2 3 Using the Internal Default Filter The AD7725 has a default filter stored in internal ROM that SIGNAL OUT can be loaded into the postprocessor. This functionality allows –1 Z the user to evaluate the device without having to download a –1 Z configuration file. The default filter is a two-stage, low-pass, FIR filter whose specifications are directly related to the CLKIN b) FIR Postprocessor Implementation frequency. With a CLKIN frequency of 9.6 MHz, the default filter has a cutoff frequency of 49 kHz and a stop-band frequency Figure 20. AD7725 Postprocessor Mapping of 72.7 kHz. This filter has a total decimation by 4, which occurs in the first stage, resulting in the output data being available to the PROGRAMMING THE POSTPROCESSOR interface at a frequency of CLKIN/32. For more detailed specifica- The postprocessor is programmed by loading a user-defined tions on this filter see the Preset Filter, Default Filter, and filter in the form of a configuration file into the device. Postprocessor Characteristics section. When powered up in Generating a Configuration File to Load into the Postprocessor boot-from-ROM mode, the AD7725 will automatically load the A user-defined configuration file can be generated to load into default filter characteristic into the postprocessor. Figure 21 the postprocessor on the AD7725 to program the multipliers shows the default filter response, when operating with a 9.6 MHz and accumulators to perform user-specific filtering require- CLKIN frequency. ments. The configuration file can be generated using a digital filter design package called Filter Wizard, which is available 0 from the Analog Devices website. –20 Filter Wizard –40 This digital filter design package allows the user to design differ- ent filter types and then generates the appropriate configuration –60 file to be loaded into the postprocessor. This application includes the ability to specify a range of different filter options including –80 single or multistage; normalized or user-specified output –100 frequency; FIR or IIR; low-pass, band-pass; Window type; pass-band frequency and ripple; stop-band frequency, attenua- –120 tion and ripple; daisy-chaining and interlacing. It also informs the user of the power dissipation of the AD7725 associated –140 with the particular filter designed. This is to avoid filters being –160 designed that result in the device exceeding its maximum power 0 50 100 150 specifications. The magnitude, phase, and impulse responses FREQUENCY – kHz can be plotted so that the user knows the filter response (cutoff Figure 21. Default Filter Response for CLKIN = 9.6 MHz REV. A –19– ATTENUATION – dB AD7725 Filter Design and a stop-band frequency of 150 kHz if the data stream is The bit stream of data from the modulator and preset filter is decimated by 2 prior to the filtering stage. For IIR filters, available to the postprocessor at a frequency of CLKIN/8. Due decimation has no effect on the transition width. to the nature of the design of the postprocessor, there is an When decimation is performed, the amount of filter coefficients unavoidable minimum decimate by 2 resulting in the maximum required to achieve certain filter specifications is reduced, result- output data rate of any filter being CLKIN/16. ing in a reduction in the power dissipation of the device to A filter can be either FIR or IIR in design. FIR filters are inherently realize the filter. Therefore, if a one-stage filter meets the roll-off stable and have linear phase. However, they are computationally and stop-band attenuation requirements of the application but inefficient and require more coefficients for a given roll-off com- is dissipating more power than is acceptable, then decimation pared to IIR filters. IIR filters have the disadvantage of being will provide a solution here. Prior to decimating, a suggestion is potentially unstable and having nonlinear phase. The maximum to use a half-band filter as these require a low number of taps to number of taps that the postprocessor can hold is 108. Therefore, accomplish simple low-pass filtering. A half-band filter has its a single filter with 108 taps can be generated, or a multistage filter midpoint of the transition region centered on half the Nyquist can be designed whereby the total number of taps adds up to 108. frequency (or f /4). By decimating though, because the input to S subsequent stages is reduced, so is the bandwidth. Design Factors Stop-Band Attenuation and Transition Width Figure 22 shows that for a given transition width, as the In filter design, it is desirable to have a large stop-band attenu- decimation factor prior to the filter is increased the current ation and a narrow filter transition width. To achieve both of consumption is reduced, resulting in reduced power dissipation. these, a large number of filter taps is required. Therefore some 120 compromises have to be made during the design to be able to optimize the amount of taps used. There is usually a trade-off of stop-band attenuation for transition width, or vice versa. For example, a filter with a cutoff frequency of 100 kHz that rolls off 100 between 100 kHz and 200 kHz uses fewer taps than a filter with a cutoff frequency of 100 kHz that rolls off between 100 kHz and 150 kHz. To reduce the number of taps used to achieve a 80 certain specification, a multistage filter can be designed that performs decimation between stages. The first filter stage can be used to perform decimation and as a prefilter to remove out-of- 60 band noise, then the subsequent stages can have more stringent specifications. Decimation 40 Decimation reduces the output data rate of the filter, resulting in 08 2 46 DECIMATION FACTOR lower input data rates for subsequent filter stages. When decimation is used in a multistage filter, the noise is wrapped around f /2 each S Figure 22. I vs. Decimation for a Filter with a DD time the bit stream is decimated by 2. It is therefore important to Transition Width of 66 kHz as Shown in Figure 1 appropriately filter out the quantization noise that will wrap into Power Consumption vs. Filter Taps vs. CLKIN Frequency the band of interest when decimation occurs, prior to decimation. When designing filters for the AD7725, an important factor to With appropriate filtering, the noise floor will increase by 3 dB each take into account is the power consumption. There is a direct time the data stream is decimated by 2; however the noise floor is relationship between DI , the number of filter taps used in DD down at 120 dB prior to decimation. Therefore, with suitable deci- the postprocessor, and the CLKIN frequency. The maximum mation, the SNR will be 83 dB typically at the AD7725 output. I (combined AI and DI ) allowed by the AD7725 pack- DD DD DD Decimating the data rate allows an improvement in the filter age is 150 mA. The more filter taps used, the higher the DI . DD transition width equal to the inverse of the decimation factor. Also, the higher the CLKIN frequency, the higher the DI . DD For FIR filters, if a filter is designed for an input data rate of Therefore, a trade-off sometimes needs to be made between half the maximum data rate, i.e., the previous filter stage had CLKIN frequency and filter taps to stay within the power decimation by 2, the filter can obtain half the transition width of budget of the part. a filter designed for the maximum input data rate for a given These power constraints are built into the filter design package, number of taps. For example, the number of taps required to Filter Wizard. As the filter is being designed, the power con- generate a filter with a cutoff frequency of 100 kHz and a sumption is shown and is highlighted once the power budget stop-band frequency of 200 kHz will equal the number of taps has been exceeded. required to generate a filter with a cutoff frequency of 100 kHz –20– REV. A I – mA DD AD7725 Figures 23 and 24 show plots of filter taps and CLKIN PARALLEL MODE frequency versus I . The parallel mode is selected by tying S/P to DGND. Pro- DD gramming the postprocessor and operation of the AD7725 in 180 MAXIMUM I DD parallel mode requires the use of an instruction set. The user 108 T APS 160 also has access to an on-chip status register that provides infor- 90 T APS mation about the operation of the device. The parallel interface 140 is a standard interface that interfaces to digital signal processors 72 T APS 120 and microprocessors. Figure 25 shows the interface between the 54 T APS 100 AD7725 and a DSP/microprocessor, and Figures 6, 7, and 8 36 T APS show the timing of the parallel interface. 80 60 AD7725 DSP/�P ADDR RS ADDR 40 DECODER 20 SYNC CS 0 0 2.4 4.8 7.2 9.6 12.0 14.4 HALF_PWR ENABLED HALF_PWR DISABLED WR CLKIN – MHz RD RD/WR Figure 23. Typical I vs. CLKIN for Various DD S/P DATA[15:0] Numbers of Filter Taps DATA[15:0] To get a more accurate number of taps for a given CLKIN DVAL/INT INTERRUPT frequency, see Figure 24. 180 Figure 25. AD7725 Parallel Interface to Microprocessor MAXIMUM I DD 160 Operating the AD7725 in Parallel Mode 14.4MHz The AD7725 uses an instruction set, its interrupt pin output 140 12MHz (the INT pin), and an on-chip status register to communicate 120 with the DSP/microprocessor. An interrupt is issued by the AD7725 whenever user intervention is required. The interrupt 100 9.6MHz can be cleared by either writing an instruction or reading the 80 7.2MHz status register. At the completion of power-on reset, the AD7725 will issue an interrupt to indicate that user intervention 60 4.8MHz 2.4MHz is required for it to begin communicating with the DSP/micro- 40 processor. An instruction should then be issued to load the 1MHz configuration data to program the postprocessor. Once the 20 configuration file has been loaded, another interrupt is issued by 0 0 10 20 30 40 50 60 70 80 90 100 110 the device. The status register can then be read to check if any FIL TER T APS errors occurred during configuration. If no errors occur during the configuration process, an instruction can be issued to inform Figure 24. Typical I vs. Filter Taps for Various DD the device to begin converting. CLKIN Frequencies Pins RD/WR, CS, and RS are used along with the data pins D0 Figures 23 and 24 were created for a one-stage low-pass FIR to D15 to write instructions/configuration data and read the filter, which will give the worst case I figures. DD status register/conversion data. The I will decrease as the amount of decimation employed in DD During a read cycle, the RS pin informs the AD7725 whether the filter is increased. the status register or a conversion result is being read. When RS is high, the status register is read while the data register, such as MODES OF OPERATION the device ID or a conversion result, is read when RS is low. The AD7725 can operate with either a serial or a parallel interface. Similarly, during a WR cycle, an instruction is written when RS These modes are chosen by setting the logic state of the S/P pin. is high and data (such as configuration data) is written when RS is low (see Table I). Table I. Reading and Writing RD/WR (Pin 7) RS (Pin 4) Operation 00 Write Data 01 Write Instruction 10 Read Data 11 Read Status Register REV. A –21– I – mA DD I – mA DD AD7725 Status Register Table III. Instruction Set for Parallel Mode The status register is a 16-bit register that provides the user with Instruction Hex Code Description information about the status of the device. The information avail- RdID 0x8802 Read Device ID able to the user includes whether a configuration file was loaded successfully, what errors if any, occurred the last instruction RdCONV 0x8D21 Read Converter Data. When written, and other information that may be useful to the user this instruction is issued to the when operating the device. To read the status register, RS is AD7725, the device continues to taken high and RD/WR is taken high. When CS is taken low, the output conversion data until the contents of the status register will be output. The status register is ABORT instruction is issued. shown in Table II and the instruction set in Table III. WrConfig 0x1800 Write Configuration Data Table II. Status Register WrConfigEM 0x1A00 Write Configuration Data, Bit Name Function Mask Errors 15 InstrBUSY This bit is set to 1 when an ABORT 0x0000 Abort. This instruction is a instruction is performed. soft reset, that is, it breaks the conversion process and leaves 14 Data Ready This bit is set to 1 when data is the device in a clean state, ready to be read from the device still configured, ready for the (a read data cycle is required). next instruction. 13 Data Request This bit is set to 1 when the device. BFR 0x2000 Boot from Internal ROM requires data to be written to it (a write data cycle is required). Configuring the Device 12 ID Error This bit is set to 1 if the programming Following power-up, the AD7725 is configured by loading a user- data has an incorrect ID value. defined filter from an external source via the parallel interface. Three instructions are provided for configuring the AD7725 (see 11 CRC Error This bit is set to 1 if corrupt Table III). data is loaded into the device. • WrConfig (Write Configuration) 10 Data Error This bit is set to 1 if an overflow occurs When this instruction is issued, the device generates an to indicate that the conversion result is interrupt every time a new word of the configuration data is invalid. required. The interrupt is cleared on the falling edge of CS 9 InstrReg[15] Instruction Register Bit 15 during the data write cycle. This continues until the com- 8 InstrReg[13] Instruction Register Bit 13 plete file is written. Immediately after the last word of the configuration data is written, a final interrupt is asserted to 7 InstrReg[12] Instruction Register Bit 12 indicate “Instruction Done.” 6 InstrReg[11] Instruction Register Bit 11 However, if an error occurred during the configuration 5 InstrReg[6] Instruction Register Bit 6 process, for example, if the configuration data is corrupt or 4 InstrReg[5] Instruction Register Bit 5 in the wrong format, an interrupt will be asserted. 3 InstrReg[4] Instruction Register Bit 4 It is advised that when using this instruction, the status regis- ter be read after each interrupt to ensure no errors occurred 2 InstrReg[1] Instruction Register Bit 1 and that the correct response is made. If configuration data is 1 InstrReg[0] Instruction Register Bit 0 corrupt, it will not be internally written to the postprocessor. 0 CFGEND Configuration End Flag. This is set to 1 • WrConfigEM (Write Configuration with Error Mask) when the device has been configured When this instruction is issued, no interrupts to signal errors correctly and is ready to start converting. will ever be asserted during the download of the configura- tion file. This saves reading the status register in response to every interrupt as with the previous instruction. The configuration process will always run through the 504 (42 writes � 12 blocks) data write cycles in the configura- tion file and once this is complete, the “Instruction Done” interrupt is issued. In this case, the status register should be checked at the end of the configuration to verify whether any errors occurred. If configuration data is corrupt, it will not be internally written to the postprocessor. For evaluation purposes, the user can load the default filter stored in internal ROM into the postprocessor. In this case the following instruction should be issued: • BFR (Boot from ROM) This instruction informs the device to load the configuration data for the default filter stored in internal ROM. –22– REV. A AD7725 Converting the CFGEND is tied to INIT, thus it will drive INIT high, and the To begin conversions, the RdCONV (Read Converter Data) part will begin converting. However, if an error does occur during instruction is issued (see Table III). INT is asserted as soon as the configuration, the ERR bit will go low, and CFGEND will not the conversion data is ready to be read (Bit 14 of the status go high. The INIT pin will therefore not start conversions. The register will be set). INT remains high until the digital word is part will not do anything until RESETCFG is pulsed low. When read from the device. It will then go low and return high when this occurs, the part is reset, SOE goes high, and the configuration the next conversion is complete. The device continues to con- file is reloaded. vert until the ABORT instruction is issued. The AD7725 will read the entire configuration file, and, if an error does occur during configuration, the user will be notified SERIAL MODE only once the whole file has been read. In this case, the data will The serial mode is selected by tying S/P to DV . Figure 4 DD not be loaded into the postprocessor. After data has been down- shows the serial interface of the AD7725. The AD7725 operates loaded, the serial clock frequency (SCO) is selected by the value solely as a master providing two serial data input pins for the on SCR and can be CLKIN (SCR = 0) or CLKIN/2 (SCR = 1). transfer of configuration data into the device (FSI and SDI), SCO must have a frequency equal to CLKIN if the AD7725 two serial data output pins for transfer of conversion data out of outputs data at CLKIN/16. For lower output word rates, either the device (FSO and SDO), and a serial clock output (SCO). clock frequency can be used. To load configuration data into Data is shifted in or out of the device synchronous with SCO. the AD7725, an FSI pulse one CLKIN cycle wide informs the The FSI and FSO signals are used to indicate to either the AD7725 that data is being transferred into the device. The data device or the processor, the beginning of a word transmission is loaded using the next 16 SCLK cycles following the detection into or out of the device. The AD7725 provides the clock for of the FSI pulse. Figure 26 shows the connection diagram for conversion and data transfers. The CFMT pin selects the active the AD7725 when loading configuration data from a DSP, and edge of SCO during conversions and the EFMT pin selects the Figure 27 shows a flow chart of the power-up and configura- active edge of SCO during configuration. tion sequence. Programming the postprocessor and operating the AD7725 in DV serial mode is purely pin-driven. Serial mode has three different DD SMODE0 submodes that determine the way in which the postprocessor is to S/P AD7725 be configured following power-up. These modes are selected by ADSP-21xx ERR SCO SCLK0 setting the logic values on the SMODE0 and SMODE1 pins (see CFGEND FSO RFS0 Table IV). These modes are INIT SDO DR0 SOE SDI DT0 • DSP: The filter can be user defined and can be loaded from DV DD DVAL TFS0 FSI INT a DSP. RESETCFG SMODE1 • EPROM: The filter can be user defined and can be loaded SYNC from an external EPROM. • Boot from ROM (BFR): The default filter (stored in inter- nal ROM) can be loaded into the postprocessor, which Figure 26. Connection Diagram for Loading the allows the user to evaluate the device without having to load Filter Configuration Data from a DSP configuration data. In serial mode, several AD7725s can be daisy-chained together SMODE0 = 1 POWER-ON RESET SMODE1 = 0 so they can all be configured from one EPROM or DSP and SOE GOES HIGH conversion data from all devices can be read back by one DSP. DSP Mode–Loading Configuration Data from a DSP IMMEDIATE BOOT In this mode, a user-defined filter can be developed and the FROM A DSP resulting configuration file loaded into the postprocessor from a DSP. The DSP therefore loads data into the AD7725 and reads PULSE USER-DEFINED FILTER back the conversion results. This mode of operation is selected by DATA LOADED INTO RESETCFG THE POSTPROCESSOR LOW tying SMODE0 to DV and SMODE1 to DGND. The values DD FROM A DSP on these pins inform the AD7725 that user-defined filter data is to be loaded into the postprocessor from the DSP automatically DATA following power-up. The data is loaded using FSI and SDI and NO LOADED the transfer of data is controlled by SCO. During the download CORRECTLY? ERR = 0 of configuration data, SCO = f /16. Following power-on YES CLKIN CFGEND = 1 reset, the SOE pin goes high to inform the DSP that configura- INIT = 1 tion of the postprocessor can begin. If no errors occur during the DEVICE STARTS configuration, the CFGEND output will go high. In Figure 26, CONVERTING Figure 27. Flow Chart of DSP Mode REV. A –23– AD7725 Table IV. Programming Modes S/P SMODE[1, 0] Configuration Mode Description 0xx PARALLEL Parallel Interface. The 16-bit bidirectional microprocessor. Interface is used for read/write operations. 100 BFR Serial Interface. Boot from the default filter (internal ROM) at power-on reset (POR). 101 DSP Serial Interface. Bidirectional serial synchronous interface suitable for interfacing to a DSP. 110 EPROM Serial Interface. Boot from external serial EPROM at POR. 111 EPROM Serial Interface. Boot from external serial EPROM at POR. EPROM Mode—Loading Configuration Data from an SMODE0 = 0 POWER-ON RESET SMODE1 = 1 External EPROM In this mode, a user-defined filter can be developed off-chip, and the resulting configuration file is loaded into the postprocessor in IMMEDIATE BOOT the AD7725 from an External EPROM. The AD7725 therefore FROM AN EPROM receives filter data from an EPROM before outputting conversion SOE GOES LOW results via the serial interface to a DSP. This mode of operation is USER-DEFINED FILTER PULSE selected by tying SMODE0 to DGND and SMODE1 to DV . DD DATA LOADED INTO RESETCFG The values on these pins inform the AD7725 that user-defined THE POSTPROCESSOR LOW FROM EPROM filter data is to be loaded from an external EPROM automatically on power-up. Following power-up, the AD7725 will drive the SOE pin low, which will enable the EPROM and reset its address DATA NO LOADED counter. The transfer of the configuration data will then com- CORRECTLY? ERR = 0 mence with the data being latched into the AD7725 on the SCO YES SOE GOES HIGH rising edge. During the download of data, SCO has a frequency of CFGEND = 1 INIT = 1 CLKIN/16. FSI is not used in the data transfer, so it should be tied low. Once configuration is complete and no error occurred, SOE DEVICE STARTS CONVERTING will go high, disabling the EPROM; SCO will return to either CLKIN or CLKIN/2, depending on SCR; CFGEND will go high Figure 29. Flow Chart of EPROM Mode driving the INIT pin high, and the device will start converting. Boot from ROM Mode (BFR)—Using the Internal However, if an error does occur during the configuration, the ERR Default Filter bit will go low and CFGEND will not go high. The part will not This mode of operation allows the user to evaluate the AD7725 do anything until RESETCFG is pulsed low. When this occurs, without having to load configuration data. It is selected by tying the part is reset, SOE goes low again to enable the EPROM, SMODE0 and SMODE1 to DGND. The values on these pins and the part is reconfigured. Figure 28 shows the connection inform the AD7725 that the postprocessor is to be configured diagram for the AD7725 when loading configuration data from with the default filter stored in internal ROM. The default filter an EPROM, and Figure 29 shows a flow chart of the power-up data will be loaded into the postprocessor automatically following and configuration sequence. power-up. Once the configuration is complete, the CFGEND pin will go high. In Figure 30, CFGEND is tied to INIT, thus it will SERIAL EPROM drive the INIT pin high, and the AD7725 will begin converting. FSI and SDI are not used in this mode, so they should be tied to DGND. In this mode of operation, the AD7725 operates as a normal �-� ADC with a fixed filter response. DV DD SOE SDI During configuration, SCO will have a frequency of CLKIN/16. SMODE1 S/P AD7725 ADSP-21xx Once configuration is complete, the frequency of SCO is selected ERR SCLK0 SCO by SCR and will be either CLKIN or CLKIN/2. Additionally, CFGEND RFS0 FSO the SCO edge on which the data is output from the device can INIT DR0 SDO DV DD FSI be selected using CFMT. With SCR = 0, SCO equals CLKIN. DVAL With SCR = 1, SCO equals CLKIN/2. With CFMT = 0, data is RESETCFG output on the SCO rising edge, while data is output on the SMODE0 falling edge when CFMT = 1. Figure 30 shows the connection SYNC diagram for the AD7725 when using the internal default filter, and Figure 31 shows a flow chart of the power-up and configu- Figure 28. Connection Diagram for Loading the ration sequence. Filter Configuration Data from an External EPROM –24– REV. A CE OE CEO DATA CLK AD7725 DV It then generates a separate configuration file for each device. DD AD7725 The configuration files for all the devices can be combined S/P RESETCFG into one configuration file in order, starting with the file for ADSP-21xx ERR SCLK0 SCO the first device, (for example, with a text editor) so that the CFGEND RFS0 FSO user only has to load one file into the EPROM or DSP. This INIT DR0 SDO DVAL configuration file is loaded into the devices using the FSI/SDI SDI DT0 TFS0 SOE FSI and the FSO/SDO of each device. Once the devices have been SMODE0 configured in a daisy chain, each device can be run indepen- SMODE1 dently, and conversion data is read back using the FSO and SYNC SDO from each device separately. Daisy-Chaining—Configuration and Conversion Data Figure 30. Connection Diagram for Loading the Several AD7725s can be daisy-chained so that they are con- Default Filter in BFR Mode figured from a common external serial EPROM or DSP (as discussed earlier in Daisy-Chaining during Configuration), SMODE0 = 0 POWER-ON RESET SMODE1 = 0 and all conversion data from each individual device can be read back by a single DSP on one serial data stream. To do this, an interlacer is required following each filter on each IMMEDIATE BOOT device. This design can be implemented using Filter Wizard. FROM ROM The function of the interlacer is to sequentially combine the conversion data outputs of each device into one serial data DEFAULT FILTER stream. The interlacer combines the data using interpolation LOADED INTO and summing. Interpolation pads the data with zeros; then the POSTPROCESSOR FROM INTERNAL ROM interlacer takes the output data from the previous device, delays CFGEND = 1 it by one clock cycle and sums it with the interpolated output INIT = 1 from the current device. This occurs on each device in the chain, and the output data from the last device consists of the conver- sion data from all devices in one continuous data stream. When DEVICE STARTS CONVERTING designing filters with interlacing, the decimation rate of the filter on each device should be twice the number of devices in the Figure 31. Flow Chart of BFR Mode chain, or a multiple of this value, to ensure there is no interfer- ence between the conversion data of different devices. Due to DAISY-CHAINING DEVICES the interpolation and decimation, the effective output data rate Several AD7725s can be daisy-chained/cascaded together. of each device (out of the last device) is CLKIN/(16 � number This feature of the AD7725 reduces system demands as it of devices) and the actual output data rate of the final device is allows several devices to be configured using one serial data CLKIN/16. Once the daisy-chaining and interlacing design is stream. It also allows conversion data from several devices to complete, one configuration file is generated to be loaded into be read back by a single DSP as one serial data stream. When the devices. Figure 32 shows an example of daisy-chaining three devices are daisy-chained, configuration/conversion data flows devices, using interlacing. from device to device using the SDO/FSO and SDI/FSI pins of Loading Configuration Data each device. A specific daisy-chaining configuration file needs When loading the configuration file from a common EPROM or to be developed using the filter design package Filter Wizard. DSP, the configuration data is loaded into the first device in the The following sections describe the daisy-chaining options the chain. Once this device is configured, the data will be loaded user can choose. into the second device in the chain via FSO/SDO of Device 1 Daisy-Chaining during Configuration and FSI/SDI of Device 2. When this device is configured, Several AD7725s can be daisy-chained together so that they can the data is loaded into the next device in the chain until all all be configured from a common external serial EPROM or a devices are configured. The CFGEND pin of the last device is DSP. Filter Wizard allows the user to specify the number of connected to the INIT pin of all the devices so that when the devices in the chain and to design a specific filter for each device. last device is successfully configured, conversions are initiated. CLKIN 9.6MHz DIGITAL DIGITAL INPUT INPUT DEVICE2 DEVICE3 DEVICE1 DATA OUTPUT RATE = CLKIN/16 FILTER1 FILTER2 FILTER3 INTERLACER INTERLACER DEC � 6 DEC � 6 DEC � 6 INTERLACER ANALOG ANALOG ANALOG INPUT DATA OUTPUT FORMAT: INPUT INPUT DEVICE3, DEVICE2, DEVICE1; DEVICE3, ... EFFECTIVE DATA OUTPUT RATE FROM EACH DEVICE: = CLKIN/(16 � 3) = 200kSPS Figure 32. Daisy-Chaining Example REV. A –25– AD7725 Converting SERIAL INTERFACE TO A DSP When the ADCs are converting, the conversion result of the In serial mode, the AD7725 can be directly interfaced to several first device in the chain is sent to the second device and is com- industry-standard digital signal processors. In all cases, the bined with the conversion data of the second device by the AD7725 operates as the master with the DSP operating as a slave. interlacer. This data is then combined with the data from the The AD7725 provides its own serial clock (SCO) to transmit the next device in the chain, and so on. The output from the last digital words on the SDO pin to the DSP. The AD7725 also gen- device will be a continuous serial data stream consisting of the erates the frame synchronization signal that synchronizes the conversion results of all the devices in the chain. A single DSP transfer of the 16-bit word from the AD7725 to a DSP. SCO will can read back all the conversion data in the sequence: have a frequency equal to CLKIN or CLKIN/2 depending on the state of the SCR pin. Device N; ... Device 2; Device 1; Device N; ... Device 2; Device 1; and so on. AD7725 to ADSP-21xx Interface Figure 35 shows the interface between the ADSP-21xx and the Figure 33 shows a connection diagram for daisy-chaining multiple AD7725. For the ADSP-21xx, the bits in the serial port control devices with a common DSP, and Figure 34 shows a connection register should be set up as RFSR and TFSR = 1 (a frame sync diagram for daisy-chaining multiple devices with a common DSP is required for each data transfer), SLEN = 15 (16-bit word and a shared EPROM. lengths), RFSW and TFSW = 0 (normal framing mode for receive and transmit operations), INVRFS and INVTFS = 0 (active high RFS and TFS), IRFS = 0 (external RFS), ITFS = 1 (internal TFS), and ISCLK = 0 (external serial clock). AD7725 AD7725 ADSP-21xx INIT CFGEND INIT CFGEND SCO SCLK RFS0 RFS FSO DR0 SCLK0 SCO SCO AD7725* DR ADSP-21xx* SDO SDO DT0 SDI SDI SDO FSI TFS TFS0 FSI FSO FSI FSO SDI DT SOE IRQ1 SOE DSP MODE DSP MODE *ADDITIONAL PINS OMITTED FOR CLARITY Figure 33. Daisy-Chaining Devices with a Common DSP Figure 35. AD7725 to ADSP-21xx Interface GROUNDING AND LAYOUT The analog and digital power supplies to the AD7725 are inde- AD7725 AD7725 pendent and separately pinned out to minimize coupling between ADSP-21xx analog and digital sections within the device. All the AD7725 XC1700D INIT INIT CFGEND CFGEND AGND and DGND pins should be soldered directly to a ground CEO SPORT0 plane to minimize series inductance. In addition, the ac path CLK SCO SCLK0 DAT SCO from any supply pin or reference pin (REF1 and REF2) through SDI its decoupling capacitors to its associated ground must be made FSI SDO SDI DR0 SDO as short as possible (Figure 36). To achieve the best decoupling, FSI RFS0 OE SOE FSO FSO place surface-mount capacitors as close as possible to the device, CE SOE ideally right up against the device pins. EPROM MODE DSP MODE To avoid capacitive coupling, ground planes must not over- lap. The AD7725’s digital and analog ground planes must be Figure 34. Daisy-Chaining Devices with a Common DSP connected at one place by a low inductance path, preferably and a Shared EPROM right under the device. Typically, this connection will either Cascading Filters across Multiple Devices be a trace on the printed circuit board of 0.5 cm wide when If the design of a filter is too large for one AD7725 device to the ground planes are on the same layer, or plated through handle, the filter can be cascaded across multiple devices. holes with an equivalent resistance of a 0.5 cm track when For example, if you have a 3-stage filter in your design that the ground planes are on different layers. Any external logic requires over 108 taps to be implemented, this filter can be connected to the AD7725 should use a ground plane separate shared between two or three devices. To do this, a configura- from the AD7725’s digital ground plane. These two digital tion file needs to be developed in Filter Wizard. Filter Wizard ground planes should also be connected at just one place. allows the user to split the filter stages up and implement Separate power supplies for AV and DV are also highly DD DD them on different devices with the output of the final device desirable. The digital supply pin DV should be powered from DD being the filtered input of the first device. a separate analog supply, but, if necessary, DV may share its DD power connection to AV . DD –26– REV. A SPORT0 AD7725 A minimum etch technique is generally best for ground planes OPTIMIZING HEAT REMOVAL BY PCB as it gives the best shielding. Noise can be minimized by paying CONSTRUCTION AND DEVICE MOUNTING attention to the system layout and preventing different signals For normal still air conditions, the primary heat dissipation path from interfering with each other. High level analog signals should from the chip to the ambient is via the component leads into the be separated from low level analog signals, and both should be PCB. The thermal resistance of the board is then a significant kept away from digital signals. In waveform sampling and recon- variable. This can be lowered by maximizing the use of ground struction systems, the sampling clock (CLKIN) is as vulnerable planes as heat sinks and also by optimizing the way in which the to noise as any analog signal. CLKIN should be isolated from the heat can be dissipated, for example conduction into the board analog and digital systems. Fast switching signals like clocks mounting chassis. The greater the percentage of copper in the should be shielded with their associated ground to avoid radiating board, especially in the region of the device, the lower the ther- noise to other sections of the board, and clock signals should mal resistance. The use of wide tracks and thermal vias to the never be routed near the analog inputs. ground plane will have a significant effect. Placing critical com- ponents close to where the edge of the board is attached to the Avoid running digital lines under the device, as these will couple chassis can provide additional cooling without the use of heat noise onto the die. The analog ground plane should be allowed sinks or forced air. Avoid close spacing of high power devices in to run under the AD7725 to shield it from noise coupling. The order to ensure that the heat is dissipated over the maximum power supply lines to the AD7725 should use as large a trace as possible area. possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. EVALUATING THE AD7725 PERFORMANCE Avoid crossover of digital and analog signals. Traces on oppo- There is an AD7725 evaluation package available that includes site sides of the board should run at right angles to each other. a fully assembled and tested evaluation board, documentation, This will reduce the effects of feedthrough through the board. and software for controlling the board from a PC via the Evalu- ation Board Controller. The Evaluation Board Controller can 5V be used in conjunction with the AD7725 Evaluation Board (as 39 DV DD 10nF + 0.1�F 10nF 10�F well as with many other Analog Devices evaluation boards ending DGND DIGITAL GROUND in the CB designator) to demonstrate/evaluate the performance of DGND DGND PLANE the AD7725. The software allows the user to perform ac (Fast AV 1 DD ANALOG 10nF Fourier Transform) and dc (Histogram of Codes) tests on the GROUND AGND1 PLANE AD7725. By downloading the filter design package, Filter AGND1 Wizard, user-defined filter files can be loaded into the AD7725 5V to program the postprocessor via the Evaluation Board Controller. AV DD 10�F 0.1�F 0.1�F 10nF See the ADI website for more information. AGND AV AGND DD 10nF AGND AGND REF2 220nF 10nF AGND2 1�F REF1 Figure 36. Reference and Supply Decoupling REV. A –27– AD7725 OUTLINE DIMENSIONS 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters 1.03 13.90 BSC SQ 0.88 2.45 MAX 0.73 33 23 8� 0.8� 34 22 SEATING PLANE 10.00 TOP VIEW BSC SQ (PINS DOWN) 7� VIEW A 2.10 0� PIN 1 2.00 44 12 1.95 0.25 MIN 1 11 COPLANARITY 0.10 0.45 0.80 VIEW A 0.30 BSC ROTATED 90� CCW COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Revision History Location Page 2/04—Data Sheet changed from REV. 0 to REV. A Changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Changes to Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Changes to DSP Mode—Loading Configuration Data from a DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Changes to EPROM Mode—Loading Configuration Data from an External EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Changes to Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Changes to GROUNDING AND LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Changes to Figure 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 –28– REV. A C01552–0–2/04(A)