ANALOG DEVICES AD7724

a Dual CMOS �-� Modulators AD7724 FEATURES FUNCTIONAL BLOCK DIAGRAM 13 MHz Master Clock Frequency 0 V to +2.5 V or �1.25 V Input Range REF1 REF2A REF2B Single Bit Output Stream 2.5V 90 dB Dynamic Range REFERENCE Power Supplies AD7724 AVDD, DVDD: 5 V� 5% DVDD1: 3 V � 5% AVIN(+) �-� ADATA MODULATOR A Logic Outputs 3 V/5 V Compatible AVIN(–) On-Chip 2.5 V Voltage Reference SCLK 48-Lead LQFP BVIN(+) �-� BDATA MODULATOR B BVIN(–) XTAL OFF XTAL1 CLOCK CIRCUITRY MZERO XTAL2/MCLK GC CONTROL BIP DVAL LOGIC STBY RESET DVDD DVDD1 DGND AVDD AGND GENERAL DESCRIPTION This device consists of two seventh order sigma-delta modula- tors. Each modulator converts its analog input signal into a high speed 1-bit data stream. The part operates from a 5 V power supply and accepts a differential input range of 0 V to +2.5 V or ±1.25 V centered about a common-mode bias. The analog inputs are continuously sampled by the analog modulators, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones. The original information can be digitally reconstructed with an appropriate digital filter. The part provides an accurate on-chip 2.5 V reference for each modulator. A reference input/output function is provided to allow either the internal reference or an external system refer- ence to be used as the reference source for the modulator. The device is offered in a 48-lead LQFP package and designed to operate from –40°C to +85°C. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002 1 (AVDD = 5 V � 5%; DVDD = 5 V � 5%, DVDD1 = 3 V � 5%; AGND = DGND = 0 V, AD7724–SPECIFICATIONS f = 13 MHz ac-coupled sine wave, REF2A = REF2B = 2.5 V; T = T to T , unless otherwise noted.) MCLK A MIN MAX Parameter A Version Unit Test Conditions/Comments STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1 Integral Nonlinearity ±0.003 % FSR typ Offset Error ±0.24 % FSR typ 2 Gain Error ±0.6 % FSR typ Offset Error Drift ±37.69 µV/°C typ Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode ±37.69 µV/°C typ Bipolar Mode ±18.85 µV/°C typ ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) Bipolar Mode ±V /2 V max BIP = V REF2 IH Unipolar Mode 0 to V V max BIP = V REF2 IL Maximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 f MHz MCLK 9 Differential Input Impedance 10 /(8 f )kΩ typ MCLK REFERENCE INPUTS REF1 Output Voltage 2.32 to 2.68 V min/max REF1 Output Voltage Drift 60 ppm/°C typ REF1 Output Impedance 4 kΩ typ Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2 Using Internal Reference REF2 Output Voltage 2.32 to 2.68 V min/max REF2 Output Voltage Drift 60 ppm/°C typ Using External Reference REF1 = AGND 9 /(16 f )kΩ typ REF2 Input Impedance 10 MCLK External Reference Voltage Range 2.32 to 2.68 V min/max Applied to REF1 or REF2 3 DYNAMIC SPECIFICATIONS When Tested with Ideal FIR Filter as in Figure 1 Bipolar Mode BIP = V , V = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p IH CM or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V Signal-to-(Noise + Distortion) 90 dB typ Input BW = 0 kHz–94.25 kHz 86 dB min Total Harmonic Distortion –90 dB max Input BW = 0 kHz–94.25 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–94.25 kHz Unipolar Mode BIP = V , VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V IL Signal-to-(Noise + Distortion) 88 dB typ Input BW = 0 kHz–94.25 kHz Total Harmonic Distortion –90 dB typ Input BW = 0 kHz–101.556 kHz Spurious Free Dynamic Range –90 dB typ Input BW = 0 kHz–101.556 kHz Intermodulation Distortion –93 dB typ AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, V = 1.25 V to CM 3.75 V, 20 kHz CLOCK 4 Square Wave MCLK Duty Ratio 45 to 55 % max For Specified Operation V , MCLK High Voltage 4 V min MCLK Uses CMOS Logic MCLKH V , MCLK Low Voltage 0.4 V max MCLKL Sine Wave XTAL1 Voltage Swing 0.4 V p-p min XTAL_OFF Tied Low 4 V p-p max LOGIC INPUTS V , Input High Voltage 2.4 V min IH V , Input Low Voltage 0.8 V max IL I , Input Current 10 µA max INH C , Input Capacitance 10 pF max IN –2– REV. B AD7724 Parameter A Version Unit Test Conditions/Comments LOGIC OUTPUTS V , Output High Voltage DVDD1 – 0.2 V min |I | ≤ 200 µA OH OUT V , Output Low Voltage 0.4 V max |I | ≤ 1.6 mA OL OUT POWER SUPPLIES AVDD/DVDD 4.75/5.25 V min/V max DVDD1 2.85/5.25 V min/V max I (Total for AVDD, DVDD) Digital Inputs Equal to 0 V or DVDD DD Active Mode 60 mA max Standby Mode 20 µA max NOTES 1 Operating temperature range is as follows: A Version: –40°C to +85°C. 2 Gain Error excludes reference error. The modulator gain is calibrated wrt the voltage on the REF2 pin. 3 Measurement Bandwidth = 0.5 × f ; Input Level = –0.05 dB. MCLK 4 When a square wave clock is used, the dynamic specifications will degrade by 1 dB typically. Specifications subject to change without notice. 94.25kHz 94.25kHz BIT STREAM DECIMATE DECIMATE 16-BIT BY 32 BY 2 OUTPUT 120dB 90dB FILTER 1 304.687kHz FILTER 2 108.874kHz BANDWIDTH = 94.25kHz BANDWIDTH = 94.25kHz TRANSITION = 304.687kHz TRANSITION = 108.874kHz ATTENUATION = 120dB ATTENUATION = 90dB COEFFICIENTS = 384 COEFFICIENTS = 151 Figure 1. Digital Filter (Consists of Two FIR Filters). This Filter is Implemented on the AD7722. REV. B –3– AD7724 (AVDD = 5 V � 5%; DVDD = 5 V � 5%; DVDD1 = 3 V � 5%; AGND = DGND = 0 V, REF2A = 1, 2 TIMING CHARACTERISTICS REF2B = 2.5 V, unless otherwise noted.) Limit at T , T MIN MAX Parameter (A Version) Unit Conditions/Comments f 100 kHz min Master Clock Frequency MCLK 15 MHz max 13 MHz for Specified Performance 14 ns max MCLK to SCLK Delay t DELAY t 67 ns min Master Clock Period 1 t 0.45 × t ns min Master Clock Input High Time 2 MCLK t 0.45 × t ns min Master Clock Input Low Time 3 MCLK t 15 ns min Data Hold Time After SCLK Rising Edge 4 t 10 ns min RESET Pulsewidth 5 t 10 ns min RESET Low Time Before MCLK Rising 6 t 20 × t ns max DVAL High Delay After RESET Low 7 MCLK t 3 ns max Data Access Time After SCLK Falling Edge 8 t t –t ns max Data Valid Time Before SCLK Rising Edge 9 3 8 NOTES 1 Sample tested at 25°C to ensure compliance. 2 Guaranteed by design. I OL 1.6mA TO OUTPUT 1.6V PIN C L 50pF I OH 200�A Figure 2. Load Circuit for Access Time and Bus Relinquish Time t 1 t 2 SCLK (O) t 3 t 9 t 8 t 4 DATA (O) NOTE: O SIGNIFIES AN OUTPUT Figure 3. Data Timing MCLK (I) t 6 t RESET (I) 5 t 7 DVAL (O) NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT Figure 4. RESET Timing –4– REV. B AD7724 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (T = 25°C unless otherwise noted) A DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V 48 47 46 45 44 43 42 41 40 39 38 37 AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V 1 AVDD 36 AVDD PIN 1 Digital Inputs to DGND . . . . . . . . –0.3 V to DVDD + 0.3 V 2 AGND IDENTIFIER 35 AGND 3 AVIN(–) 34 Digital Outputs to DGND . . . . . . . –0.3 V to DVDD + 0.3 V BVIN(–) 4 NC 33 NC VIN(+), VIN(–) to AGND . . . . . . . –0.3 V to AVDD + 0.3 V 5 AVIN(+) 32 BVIN(+) REF1 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V AD7724 AGND 6 31 AGND TOP VIEW REF2 to AGND . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V AVDD 7 30 AVDD (Not to Scale) 8 REFIN to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V NC 29 NC 9 STBY 28 GC Operating Temperature Range . . . . . . . . . . . –40°C to +85°C 10 MZERO 27 BIP Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 11 RESET 26 XTAL_OFF Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C 12 NC 25 NC θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA 13 14 15 16 17 18 19 20 21 22 23 24 Lead Temperature, Soldering NC = NO CONNECT Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option AD7724AST –40°C to +85°C 48-Lead Plastic Thin Quad Flatpack (LQFP) ST-48 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7724 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– NC NC XTAL1 NC XTAL1/MCLK AGND DVDD REF2A DGND AGND DGND REF1 ADATA AVDD BDATA NC SCLK REF2B DVDD1 AGND DVAL NC NC NC AD7724 PIN FUNCTION DESCRIPTIONS Mnemonic Description AVDD Analog Positive Supply Voltage, 5 V ± 5%. AGND Ground reference point for analog circuitry. AVIN(–), AVIN(+) Analog Input to Modulator A. In unipolar operation, the analog input range on AVIN(+) is AVIN(–) to (AVIN(–) + VREF); for bipolar operation, the analog input range on AVIN(+) is (AVIN(–) ± VREF/2). The absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and pro- cessed by the analog modulator. STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode. When STBY is low, the device is powered up. MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded i.e. tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip offsets to be calibrated out. MZERO is low for normal operation. RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL goes low for 20 MCLK cycles while the modulator is being reset. XTAL1 Input to Crystal Oscillator Amplifier. This pin can also be used to gain up a small input square or sine wave with XTAL_OFF tied low (see Figure 32 on page 12). When a clock source is applied to XTAL1, SCLK will be inverted and the XTAL1_CLK to SCLK delay will be typically 14 ns longer than t . DELAY XTAL2/MCLK Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. In this case, XTAL1 should be tied to AGND. Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor, can be connected between XTAL1 and XTAL2 with XTAL_OFF tied low. Exter- nal capacitors are then required from the XTAL1 and XTAL2 pins to ground. Consult the crystal manufacturer's recommendation for the load capacitors. A sine wave can also be used to provide the clock. A sine wave with a voltage swing between 0.4 V p-p and 4 V p-p is needed. XTAL_OFF is tied low and a 1 MΩ resistor is needed between XTAL1 and XTAL2. A 22 pF capacitor is connected in parallel with this resistor. The sine wave is ac coupled to XTAL1 using a 120 pF capacitor. The use of a sine wave to generate the clock eliminates the need for a square wave clock source which introduces noise. DVDD Digital Supply Voltage, 5 V ± 5%. DGND Ground reference for the digital circuitry. ADATA Modulator A Bit Stream. The digital bit stream from the sigma-delta modulator is output at ADATA. BDATA Modulator B Bit Stream. The digital bit stream from the sigma-delta modulator is output at BDATA. SCLK Serial Clock, Logic Output. The bit stream from modulator A and modulator B is valid on the rising edge of ASCLK. DVDD1 Digital Supply Voltage for the digital outputs. DVDD1 can have a value of 5 V ± 5% or 3 V ± 5% so that the logic outputs can be 3 V or 5 V compatible. DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7724 is an accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is overranged. XTAL_OFF Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock source. XTAL_OFF is set to a logic low when an external crystal is used between XTAL1 and XTAL2. BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects bipolar mode. GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated. BVIN(–), BVIN(+) Analog Input to Modulator B. In unipolar operation, the analog input range on BVIN(+) is BVIN(–) to (BVIN(–) + VREF); for bipolar operation, the analog input range on BVIN(+) is (BVIN(–) ± VREF/2). The absolute analog input range must lie between 0 and AVDD. The input range is continuously sampled and pro- cessed by the analog modulator. REF2B Reference Input/Output to Sigma-Delta Modulator B. REF2B connects to the output of an external buffer amplifier used to drive sigma-delta modulator B. When REF2B is used as an input, REF1 must be connected to AGND. REF1 Reference Input/Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to the input of two buffer amplifiers that drive Σ-∆ modulator A and Σ-∆ modulator B. The pin can be overdriven with an external 2.5 V reference. REF2A Reference Input/Output to Sigma-Delta Modulator A. REF2A connects to the output of an external buffer amplifier used to drive sigma-delta modulator A. When REF2A is used as an input, REF1 must be connected to AGND. –6– REV. B AD7724 TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7724 rms sum of all of the nonfundamental signals and harmonics up [FIGURE 1]) to half the Output Data Rate (f /2), excluding dc. Signal-to- O Integral Nonlinearity (Noise + Distortion) is dependent on the number of quantiza- This is the maximum deviation of any code from a straight line tion levels used in the digitization process; the more levels, the passing through the endpoints of the transfer function. The smaller the quantization noise. The theoretical Signal-to-(Noise endpoints of the transfer function are zero scale (not to be con- + Distortion) ratio for a sine wave input is given by fused with bipolar zero), a point 0.5 LSB below the first code Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB transition (100...00 to 100...01 in bipolar mode and where N is the number of bits. 000...00 to 000...01 in unipolar mode) and full scale, a point 0.5 LSB above the last code transition (011...10 to Total Harmonic Distortion 011...11 in bipolar mode and 111...10 to 111...11 in THD is the ratio of the rms sum of harmonics to the rms value unipolar mode). The error is expressed in LSBs. of the fundamental. THD is defined as Common-Mode Rejection Ratio 2 2 2 2 2 (V +V +V +V +V ) The ability of a device to reject the effect of a voltage applied to 2 3 4 5 6 THD = 20 log both input terminals simultaneously—often through variation of V 1 a ground level—is specified as a common–mode rejection ratio. where V is the rms amplitude of the fundamental and V , V , 1 2 3 CMRR is the ratio of gain for the differential signal to the gain , V and V are the rms amplitudes of the second through the V 4 5 6 for the common-mode signal. sixth harmonic. Unipolar Offset Error Spurious Free Dynamic Range Unipolar offset error is the deviation of the first code transition Spurious free dynamic range is the difference, in dB, between from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB) the peak spurious or harmonic component in the ADC output when operating in the unipolar mode. spectrum (up to f /2 and excluding dc) and the rms value of the O Bipolar Offset Error fundamental. Normally, the value of this specification will be This is the deviation of the midscale transition (111...11 determined by the largest harmonic in the output spectrum of to 000... 00) from the ideal VIN(+) voltage which is (VIN(–) the FFT. For input signals whose second harmonics occur in –0.5 LSB) when operating in the bipolar mode. the stop band region of the digital filter, a spur in the noise floor Gain Error limits the SFDR. The first code transition should occur at an analog value 1/2 LSB Intermodulation Distortion above minus full scale. The last code transition should occur for With inputs consisting of sine waves at two frequencies, fa and an analog value 1 1/2 LSB below the nominal full-scale. Gain fb, any active device with nonlinearities will create distortion error is the deviation of the actual difference between first and products at sum and difference frequencies of mfa ± nfb where last code transitions and the ideal difference between first and m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are last code transitions. those for which neither m nor n are equal to zero. For example, Signal-to-(Noise + Distortion) the second order terms include (fa + fb) and (fa – fb), while the Signal-to-(Noise + Distortion) is the measured signal-to-noise third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and plus distortion ratio at the output of the ADC. The signal is the (fa – 2fb). rms magnitude of the fundamental. Noise plus distortion is the REV. B –7– AD7724–Typical Performance Characteristics (AVDD = DVDD = 5.0 V, T = 25�C; CLKIN = 13 MHz ac-coupled sine wave, AIN = 20 kHz, Bipolar Mode; V (+) = 0 V to 2.5 V, V (–) = 1.25 V A IN IN unless otherwise noted) 110 84 –85 85 100 –90 AIN = 1/5 � BW SNR 86 90 –95 87 SFDR 80 88 –100 S/ (N+D) 89 70 –105 SFDR 90 60 –110 91 THD 50 92 –115 –40 –30 –20 –10 0 0 20 40 60 80 100 0 50 100 150 200 250 300 INPUT LEVEL – dB OUTPUT DATA RATE – kSPS INPUT FREQUENCY – kHz TPC 1. S/(N+D) and SFDR vs. TPC 2. S/(N+D) vs. Output Sample TPC 3. SNR, THD, and SFDR vs. Analog Input Level Rate Input Frequency 92.0 –85 84 85 91.5 –90 AIN = 1/5 � BW SNR V (+) = V (–) = 1.25V p-p IN IN 86 91.0 V (+) = V (–) = 1.25V p-p IN IN V = 2.5V CM –95 V = 2.5V CM 90.5 87 THD –100 88 90.0 89 89.5 –105 90 89.0 SFDR –110 88.5 91 –115 92 88.0 0 20 40 60 80 100 0 50 100 150 200 250 300 –50 0 50 100 INPUT FREQUENCY – kHz OUTPUT DATA RATE – kSPS TEMPERATURE – °C TPC 4. SNR, THD, and SFDR vs. TPC 5. S/(N+D) vs. Output Sample TPC 6. SNR vs. Temperature Input Frequency Rate –94 5000 1.0 –96 0.8 4500 THD V (+) = V (–) –98 IN IN 4000 0.6 CLKIN = 13MHz –100 3500 8k SAMPLES 0.4 –102 0.2 3000 3RD –104 2500 0 –106 4TH –0.2 2000 –108 1500 –0.4 –110 –0.6 1000 –112 500 –0.8 –114 2ND –116 –1.0 0 –50 –25 025 50 75 100 0 20000 40000 65535 n–3n–2 n–1 n n+1 n+2 n+3 TEMPERATURE – °C CODE CODES TPC 7. THD vs. Temperature TPC 9. Differential Nonlinearity TPC 8. Histogram of Output Codes with DC Input –8– REV. B dB dB dB FREQUENCY OF OCCURENCE dB dB DNL ERROR – LSB dB dB AD7724 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 20000 40000 65535 CODE TPC 10. Integral Nonlinearity Error 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 6.5 0 409.0268 FREQUENCY – MHz FREQUENCY – kHz TPC 11. Modulator Output (0 Hz to MCLK/2) TPC 14. Modulator Output (0 to 409.0268 kHz) 0 0 AIN = 90kHz CLKIN = 13MHz –20 –20 CLKIN = 13MHz SNR = 90.1dB SNR = 89.6dB –40 S/(N+D) = 89.2dB –40 S/(N+D) = 89.6dB SFDR = –99.5dB SFDR = –108.0dB –60 THD = –96.6dB –60 2ND = –100.9dB –80 –80 3RD = –106.0dB 4TH = –99.5dB –100 –100 –120 –120 –140 –140 –154 –154 98E+3 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3 TPC 12. 16K Point FFT TPC 15. 16K Point FFT 0 0 XTAL = 12.288MHz AIN = 90kHz –20 –20 SNR = 89.0dB XTAL = 12.288MHz S/(N+D) = 87.8dB SNR = 88.1dB –40 –40 SFDR = –94.3dB S/(N+D) = 88.1dB SFDR = –103.7dB THD = –93.8dB –60 –60 2ND = –94.3dB –80 3RD = –108.5dB –80 4TH = –105.7dB –100 –100 –120 –120 –140 –140 –154 –154 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3 TPC 13. 16K Point FFT TPC 16. 16K Point FFT REV. B –9– dB dB dB INL ERROR – LSB dB dB dB AD7724 CIRCUIT DESCRIPTION � A The AD7724 employs a sigma-delta conversion technique to 500� VIN(+) 2pF � convert the analog input into a digital pulse train. The analog B input is continuously sampled by a switched capacitor modulator 2pF � A at twice the rate of the clock input frequency (2 f ). The MCLK 500� VIN(–) digital data that represents the analog input is in the ones’ den- � AC B GROUND sity of the bit stream at the output of the sigma-delta modulator. � � � � The modulator outputs the bit stream at a data rate equal to f . MCLK A B A B MCLK Due to the high oversampling rate, which spreads the quantiza- tion noise from 0 to f /2, the noise energy contained in the MCLK Figure 6. Analog Input Equivalent Circuit band of interest is reduced (Figure 5a). To reduce the quantiza- Since the AD7724 samples the differential voltage across its tion noise further, a high order modulator is employed to shape analog inputs, low noise performance is attained with an input the noise spectrum, so that most of the noise energy is shifted circuit that provides low differential mode noise at each input. out of the band of interest (Figure 5b). The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7724. When a capacitive load is switched onto the output of an op QUANTIZATION NOISE amp, the amplitude will momentarily drop. The op amp will try to correct the situation and, in the process, hits its slew rate f /2 MCLK BAND OF INTEREST limit. This nonlinear response, which can cause excessive ring- a. ing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7724 as shown in Figure 7. The external capacitor at NOISE SHAPING each input aids in supplying the current spikes created during the sampling process. The resistor in the diagram, as well as f /2 MCLK creating a pole for the antialiasing, isolates the op amp from the BAND OF INTEREST transient nature of the load. b. Figure 5. Sigma-Delta ADC R VIN(+) USING THE AD7724 C ADC Differential Inputs ANALOG INPUT The AD7724 uses differential inputs to provide common-mode R VIN(–) noise rejection (i.e., the converted result will correspond to the C differential voltage between the two inputs). The absolute volt- age on both inputs must lie between AGND and AVDD. In the unipolar mode, the full scale-input range (VIN(+) – Figure 7. Simple RC Antialiasing Circuit VIN(–)) is 0 V to V . In the bipolar mode configuration, the REF The differential input impedance of the AD7724 switched capaci- full-scale analog input range is ±V /2. The bipolar mode REF tor input varies as a function of the MCLK frequency, given by allows complementary input signals. Alternatively, VIN(–) can the equation: be connected to a dc bias voltage to allow a single-ended input 9 on VIN(+) equal to V ± V /2. BIAS REF Zf = 10 / 8 kΩ () IN MCLK Differential Inputs Even though the voltage on the input sampling capacitors may The analog input to the modulator is a switched capacitor design. not have enough time to settle to the accuracy indicated by the The analog input is converted into charge by highly linear sam- resolution of the AD7724, as long as the sampling capacitor charg- pling capacitors. A simplified equivalent circuit diagram of the ing follows the exponential curve of RC circuits, only the gain analog input is shown in Figure 6. A signal source driving the accuracy suffers if the input capacitor is switched away too early. analog input must be able to provide the charge onto the sam- pling capacitors every half MCLK cycle and settle to the required accuracy within the next half cycle. –10– REV. B AD7724 An alternative circuit configuration for driving the differential The AD7724 can operate with its internal reference, or an inputs to the AD7724 is shown in Figure 8. external reference can be applied in two ways. An external reference can be connected to REF1, overdriving the internal reference. However, an error will be introduced due to the C R 2.7nF offset of the internal buffer amplifier. For lowest system gain 100� VIN(+) errors when using an external reference, REF1 is grounded C (disabling the internal buffer) and the external reference is con- 2.7nF R nected to REF2. 100� VIN(–) In all cases, since the REF2 voltage connects to the analog modu- C 2.7nF lator, a 110 nF capacitor must connect directly from REF2 to AGND. The external capacitor provides the charge required for the dynamic load presented at the REF2 pin (Figure 10). Figure 8. Differential Input with Antialiasing A capacitor between the two input pins sources or sinks charge to allow most of the charge needed by one input to be effectively � A supplied by the other input. This minimizes undesirable charge � B 4pF transfer from the analog inputs to and from ground. The series REF2 resistor isolates the operational amplifier from the current spikes 110nF 4pF created during the sampling process and provides a pole for � A � B antialiasing. The 3 dB cutoff frequency of the antialias filter is given by Equation 1, and the attenuation of the filter is given by SWITCHED-CAP DAC REF Equation 2. � � � � fR =12 / πC (1) () MCLK A B A B 3 dB EXT EXT Figure 10. REF2 Equivalent Circuit  2 Attenuation=+ 20 log 1// 1 f f (2)  () 3 dB  The AD780 is ideal to use as an external reference with the   AD7724. Figure 11 shows a suggested connection diagram. The choice of the filter cutoff frequency will depend on the amount of roll-off that is acceptable in the passband of the digi- O/P 1 NC 8 5V SELECT tal filter and the required attenuation at the first image frequency. REF2 2 +V NC 7 IN 110nF The capacitors used for the input antialiasing circuit must have 1�F 3 TEMP V 6 OUT low dielectric absorption to avoid distortion. Film capacitors 22nF REF1 22�F GND 4 TRIM 5 such as polypropylene or polycarbonate are suitable. If ceramic capacitors are used, they must have NPO dielectric. AD780 NC = NO CONNECT Applying the Reference Figure 11. External Reference Circuit Connection The reference circuitry used in the AD7724 includes an on-chip 2.5 V bandgap reference and a reference buffer circuit. The block diagram of the reference circuit is shown in Figure 9. The internal reference voltage is connected to REF1 via a 3 kΩ resistor and is internally buffered to drive the analog modulator’s switched capacitor DAC (REF2). When using the internal refer- ence, connect 110 nF between REF1 and AGND. If the internal reference is required to bias external circuits, use an external precision op amp to buffer REF1. COMPARATOR 1V REFERENCE BUFFER REF1 SWITCHED-CAP DAC REF 110nF 4k� 2.5V REFERENCE REF2 Figure 9. Reference Circuit Block Diagram REV. B –11– AD7724 Input Circuits The 1 nF capacitors at each input store charge to aid the Figures 12 and 13 show two simple circuits for bipolar mode amplifier settling as the input is continuously switched. A operation. Both circuits accept a single-ended bipolar signal resistor in series with the drive amplifier output and the 1 nF source and create the necessary differential signals at the input input capacitor may also be used to create an antialias filter. to the ADC. Clock Generation The circuit in Figure 12 creates a 0 V to 2.5 V signal at the The AD7724 contains an oscillator circuit to allow a crystal or VIN(+) pins to form a differential signal around an initial bias an external clock signal to generate the master clock for the voltage of 1.25 V. For single-ended applications, best THD ADC. The connection diagram for use with the crystal is shown performance is obtained with VIN(–) set to 1.25 V rather than in Figure 14. Consult the crystal manufacturer’s recommenda- 2.5 V. The input to the AD7724 can also be driven differen- tion for the load capacitors. tially with a complementary input as shown in Figure 13. In this case, the input common-mode voltage is set to 2.5 V. The 2.5 V p-p full-scale differential input is obtained with a XTAL MCLK 1.25 V p-p signal at each input in antiphase. This configuration minimizes the required output swing from the amplifier circuit 1M� and is useful for single supply applications. 12pF 1k� 1k� AIN = Figure 14. Crystal Oscillator Connection 1.25V 12pF An external clock must be free of ringing and have a minimum – 1/2 DIFFERENTIAL rise time of 5 ns. Degradation in performance can result as high OP275 1k� INPUT = 2.5V p-p + edge rates increase coupling that can generate noise in the sam- 1k� VIN(–) BIAS VOLTAGE = 2.5V pling process. The connection diagram for an external clock – 1/2 VIN(+) source (Figure 15) shows a series damping resistor connected OP275 + 1nF between the clock output and the clock input to the AD7724. The optimum resistor will depend on the board layout and the VIN(–) impedance of the trace connecting to the clock input. 1nF + R 25–150� REF1 CLOCK MCLK CIRCUITRY 110nF OP07 – R REF2 Figure 15. External Clock Oscillator Connection 110nF A low phase clock should be used to generate the ADC sam- pling clock because sampling clock jitter effectively modulates Figure 12. Single-Ended Analog Input for Bipolar Mode the input signal and raises the noise floor. The sampling clock Operation generator should be isolated from noisy digital circuits, grounded and heavily decoupled to the analog ground plane. 12pF A sine wave can also be used to provide the clock (Figure 16.) A 1k� 1k� AIN = sine wave with a voltage swing between 0.4 V p-p and 4 V p-p is �0.625V needed. XTAL_OFF is tied low and a 1 MΩ resistor is needed 1/2 between XTAL1 and XTAL2. A 22 pF capacitor is connected VIN(–) OP275 1nF in parallel with this resistor. The sine wave is ac coupled to 12pF XTAL1 using a 120 pF capacitor. The use of a sine wave to DIFFERENTIAL 1k� INPUT = 2.5V p-p 1k� generate the clock eliminates the need for a square wave clock COMMON-MODE source which introduces noise. VOLTAGE = 2.5V 1/2 VIN(+) 120pF OP275 XTAL1 1nF SINEWAVE R 22pF 1M� INPUT XTAL2 REF1 R 110nF OP07 XTAL_OFF REF2 110nF Figure 16. Using a Sine Wave Input as a Clock Source Figure 13. Single-Ended-to-Differential Analog Input Circuit for Bipolar Mode Operation –12– REV. B AD7724 The sampling clock generator should be referenced to the ana- DVAL log ground plane in a split ground system. However, this is not The DVAL pin is used to indicate that an overrange input signal always possible because of system constraints. In many cases, has resulted in invalid data at the modulator output. As with all the sampling clock must be derived from a higher frequency single-bit DAC high-order sigma-delta modulators, large over- multipurpose system clock that is generated on the digital loads on the inputs can cause the modulator to go unstable. The ground plane. If the clock signal is passed between its origin on modulator is designed to be stable with signals within the input a digital plane to the AD7724 on the analog ground plane, the bandwidth that exceed full-scale by 100%. When instability is ground noise between the two planes adds directly to the clock detected by internal circuits, the modulator is reset to a stable and will produce excess jitter. The jitter can cause unwanted state and DVAL is held low for 20 clock cycles. degradation in the signal-to-noise ratio and also produce Grounding and Layout unwanted harmonics. Since the analog inputs are differential, most of the voltages in This can be somewhat remedied by transmitting the sampling the analog modulator are common-mode voltages. The excel- signal as a differential one, using either a small RF transformer lent common-mode rejection of the part will remove common- or a high-speed differential driver and receiver such as PECL. In mode noise on these inputs. The analog and digital supplies to either case, the original master system clock should be generated the AD7724 are independent and separately pinned out to mini- from a low phase noise crystal oscillator. mize coupling between analog and digital sections of the device. Offset and Gain Calibration The printed circuit board that houses the AD7724 should be The analog inputs of the AD7724 can be configured to measure designed so that the analog and digital sections are separated offset and gain errors. Pins MZERO and GC are used to config- and confined to certain areas of the board. This facilitates the ure the part. Before calibrating the device, the part should be use of ground planes that can be easily separated. A minimum reset so that the modulator is in a known state at calibration. etch technique is generally best for ground planes as it gives the When MZERO is taken high, the analog inputs are tied to AGND best shielding. Digital and analog ground planes should be in unipolar mode and VREF in bipolar mode. After taking joined in only one place. If the AD7724 is the only device MZERO high, 1000 MCLK cycles should be allowed for the requiring an AGND-to-DGND connection, the ground planes circuitry to settle before the bit stream is read from the device. should be connected at the AGND and DGND pins of the The ideal ones density is 50% when bipolar operation is selected AD7724. If the AD7724 is in a system where multiple devices and 37.5% when unipolar mode is selected. require AGND-to-DGND connections, the connection should still be made at one point only, a star ground point that should When GC is taken high, VIN(–) is tied to ground while VIN(+) be established as close as possible to the AD7724. is tied to VREF. Again, 1000 MCLK cycles should be allowed for the circuitry to settle before the bit stream is read. The ideal Avoid running digital lines under the device as these will couple ones density is 62.5%. noise onto the die. The analog ground plane should be allowed to run under the AD7724 to avoid noise coupling. The power The calibration results apply only for the particular analog input supply lines to the AD7724 should use as large a trace as pos- mode (unipolar/bipolar) selected when performing the calibra- sible to provide low impedance paths and reduce the effects of tion cycle. On changing to a different analog input mode, a new glitches on the power supply line. Fast switching signals such as calibration must be performed. clocks should be shielded with digital ground to avoid radiating Before calibrating, ensure that the supplies have settled and that noise to other sections of the board, and clock signals should the voltage on the analog input pins is between the supply voltages. run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far Standby the best, but is not always possible with a double-sided board. The part can be put into a low power standby mode by taking In this technique, the component side of the board is dedicated STBY high. During standby, the clock to the modulators is to ground planes while signals are placed on the other side. turned off and bias is removed from all analog circuits. Good decoupling is important when using high resolution Reset ADCs. All analog and digital supplies should be decoupled to The RESET pin is used to reset the modulators to a known AGND and DGND respectively, with 100 nF ceramic capaci- state. When RESET is taken high, the integrator capacitors of tors in parallel with 10 µF tantalum capacitors. To achieve the the modulator are shorted and DVAL goes low and remains low best from these decoupling capacitors, they should be placed as until 20 MCLK cycles after RESET is deasserted. However, an close as possible to the device, ideally right up against the additional 1000 MCLK cycles should be allowed before reading device. In systems where a common supply voltage is used to the modulator bit stream as the modulator circuitry needs to drive both the AVDD and DVDD of the AD7724, it is recom- settle after the reset. mended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD7724 and AGND and the recom- mended digital supply decoupling between the DVDD pins and DGND. REV. B –13– AD7724 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75) 37 48 0.018 (0.45) 36 1 SEATING 0.276 PLANE TOP VIEW (7.00) (PINS DOWN) BSC SQ 0.006 (0.15) 12 25 0� 0.002 (0.05) 13 24 MIN 0.011 (0.27) 0.007 (0.18) 0.019 (0.5) BSC 0.006 (0.17) 0.004 (0.09) 0.057 (1.45) 7� 0.053 (1.35) 0� –14– REV. B AD7724 Revision History Location Page Data Sheet changed from REV. A to REV. B. Additions to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 REV. B –15– –16– PRINTED IN U.S.A. C01187–0–3/02(B)