ANALOG DEVICES AD7723

16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC AD7723 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-bit Σ-∆ ADC 2.5V REF2 AV AD7723 1.2 MSPS output word rate DD REFERENCE REF1 AGND 32×/16× oversampling ratio VIN(+) FIR DV DD Low-pass and band-pass digital filter MODULATOR FILTER VIN(–) DGND Linear phase On-chip 2.5 V voltage reference XTAL_OFF UNI XTAL XTAL HALF_PWR Standby mode CLOCK CLKIN STBY Flexible parallel or serial interface MODE 1 DGND/DB15 MODE 2 Crystal oscillator DGND/DB14 SYNC SCR/DB13 Single 5 V supply DV /CS SLDR/DB12 DD CONTROL CFMT/RD SLP/DB11 LOGIC DGND/DRDY TSI/DB10 GENERAL DESCRIPTION DGND/DB0 FSO/DB9 The AD7723 is a complete 16-bit, sigma-delta ADC. The part DGND/ DGND/ DGND/ DOE/ SFMT/ FSI/ SCO/ SDO/ operates from a 5 V supply. The analog input is continuously DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 sampled, eliminating the need for an external sample-and-hold. Figure 1. The modulator output is processed by a finite impulse response (FIR) digital filter. The on-chip filtering combined with a high The part provides an on-chip 2.5 V reference. Alternatively, an oversampling ratio reduces the external antialias requirements external reference can be used. to first order in most cases. The digital filter frequency response can be programmed to be either low-pass or band-pass. A power-down mode reduces the idle power consumption to 200 µW. The AD7723 provides 16-bit performance for input bandwidths up to 460 kHz at an output word rate up to 1.2 MHz. The The AD7723 is available in a 44-lead MQFP package and is sample rate, filter corner frequencies, and output word rate are specified over the industrial temperature range from set by the crystal oscillator or external clock frequency. –40°C to +85°C. Data can be read from the device in either serial or parallel Two input modes are provided, allowing both unipolar and format. A stereo mode allows data from two devices to share a bipolar input ranges. single serial data line. All interface modes offer easy, high speed connections to modern digital signal processors. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 01186-001 AD7723 TABLE OF CONTENTS Specifications..................................................................................... 3 System Synchronization ................................................................ 23 Timing Specifications....................................................................... 6 Data Interfacing.............................................................................. 24 Absolute Maximum Ratings.......................................................... 10 Parallel Interface......................................................................... 24 ESD Caution................................................................................ 10 Serial Interface ................................................................................ 25 Pin Configuration And Function Descriptions.......................... 11 Two-Channel Multiplexed Operation ..................................... 25 Terminology .................................................................................... 14 Serial Interface to DSPs ................................................................. 27 Typical Performance Characteristics ........................................... 15 AD7723 to ADSP-21xx Interface ............................................. 27 Circuit Description......................................................................... 18 AD7723 to SHARC Interface.................................................... 27 Applying the AD7723 .................................................................... 20 AD7723 to DSP56002 Interface ............................................... 27 Analog Input Range ................................................................... 20 AD7723 to TMS320C5x Interface............................................ 27 Analog Input ............................................................................... 20 Grounding and Layout .................................................................. 28 Driving the Analog Inputs ........................................................ 20 Outline Dimensions ....................................................................... 29 Applying the Reference.............................................................. 21 Ordering Guide .......................................................................... 29 Clock Generation ....................................................................... 22 REVISION HISTORY 5/05—Rev. B to Rev. C 9/02—Data Sheet changed from Rev. 0 to Rev. A Changes to Format .............................................................Universal New TPCs 1 and 2 Added ............................................................. 13 Changes to Figure 6.......................................................................... 8 Edits to Figures 17 and 18 ............................................................. 18 Outline Dimensions Updated....................................................... 23 Changes to System Synchronization ............................................ 23 Updated Outline Dimensions ....................................................... 29 Changes to the Ordering Guide.................................................... 29 10/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 8 Outline Dimensions Updated ....................................................... 23 Rev. C | Page 2 of 32 AD7723 1 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = AGND2 = DGND = 0 V; fCLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. B Version Parameter Test Conditions/Comments Min Typ Max Unit 2, 3 DYNAMIC SPECIFICATIONS HALF_PWR = 0 to 1 fCLKIN = 10 MHz when HALF_PWR = 1 Decimate by 32 Bipolar Mode Signal to Noise Full Power 2.5 V reference 87 90 dB 3 V reference 88.5 91 dB Half Power 86.5 89 dB 4 Total Harmonic Distortion −96 −90 dB 4 Spurious-Free Dynamic Range 2.5 V reference −92 dB 3 V reference −90 dB Unipolar Mode Signal to Noise 87 dB 4 Total Harmonic Distortion −89 dB 4 Spurious-Free Dynamic Range −90 dB Band-Pass Filter Mode Bipolar Mode Signal to Noise 76 79 dB Decimate by 16 Bipolar Mode Signal to Noise Measurement bandwidth = 0.383 × F O 2.5 V reference 82 86 dB 3 V reference 83 87 dB Signal to Noise Measurement bandwidth = 0.5 × FO 78 81.5 dB 4 Total Harmonic Distortion 2.5 V reference −88 dB 4 Spurious-Free Dynamic Range 3 V reference −86 dB 2.5 V reference −90 dB 3 V reference −88 dB Unipolar Mode Signal to Noise Measurement bandwidth = 0.383 × FO 84 dB Signal to Noise Measurement bandwidth = 0.5 × F 81 dB O 4 Total Harmonic Distortion −89 dB DIGITAL FILTER RESPONSE Low-Pass Decimate by 32 0 kHz to f/83.5 ±0.001 dB CLKIN f/66.9 −3 dB CLKIN fCLKIN/64 −6 dB fCLKIN/51.9 to fCLKIN/2 −90 dB Group Delay 1293/2 fCLKIN Settling Time 1293/f CLKIN Rev. C | Page 3 of 32 AD7723 B Version Parameter Test Conditions/Comments Min Typ Max Unit Low-Pass Decimate by 16 0 kHz to f/41.75 ±0.001 dB CLKIN f/33.45 −3 dB CLKIN f/32 −6 dB CLKIN fCLKIN/25.95 to fCLKIN/2 −90 dB Group Delay 541/2 fCLKIN Settling Time 541/fCLKIN Band-Pass Decimate by 32 f /51.90 to f/41.75 ±0.001 dB CLKIN CLKIN fCLKIN/62.95, fCLKIN/33.34 −3 dB fCLKIN/64, fCLKIN/32 −6 dB 0 kHz to fCLKIN/83.5, fCLKIN/25.95 to fCLKIN/2 −90 dB Group Delay 1293/2 f CLKIN Settling Time 1293/f CLKIN Output Data Rate, F O Decimate by 32 fCLKIN/32 Decimate by 166 fCLKIN/16 ANALOG INPUTS Full-Scale Input Span VIN(+) − VIN(−) Bipolar Mode ±4/5 × VREF2 V Unipolar Mode 0 8/5 × VREF2 V Absolute Input Voltage VIN(+) − VIN(−) AGND AV V DD Input Sampling Capacitance 2 pF Input Sampling Rage, fCLKIN 19.2 MHz CLOCK CLKIN Duty Ratio 45 55 % REFERENCE REF1 Output Resistance 3 kΩ Using Internal Reference REF2 Output Voltage 2.39 2.54 2.69 V REF2 Output Voltage Drift 60 ppm/°C Using External Reference REF2 Input Impedance REF1 = AGND 4 kΩ REF2 External Voltage Range 1.2 2.5 3.15 V STATIC PERFORMANCE Resolution 16 Bits Differential Nonlinearity Guaranteed monotonic ±0.5 ±1 LSB Integral Nonlinearity ±2 LSB DC CMRR 80 dB Offset Error ±20 mV 5 Gain Error ±0.5 % FSR LOGIC INPUTS (EXCLUDING CLKIN) VINH, Input High Voltage 2.0 V V , Input High Voltage 0.8 V INL CLOCK INPUT (CLKIN) VINH, Input High Voltage 3.8 V V , Input High Voltage 0.4 V INL ALL LOGIC INPUTS IIN, Input Current VIN = 0 V to DVDD ±10 µA C , Input Capacitance 10 pF IN Rev. C | Page 4 of 32 AD7723 B Version Parameter Test Conditions/Comments Min Typ Max Unit LOGIC OUPUTS V , Output High Voltage |I | = 200 µA 4.0 V OH OUT V , Output Low Voltage |I | = 1.6 mA 0.4 V OL OUT POWER SUPPLIES AV 4.75 5.25 V DD I HALF_PWR = Logic Low 50 60 mA AVDD HALF_PWR = Logic High 25 33 mA DVDD 4.75 5.25 V IDVDD HALF_PWR = Logic Low 25 35 mA HALF_PWR = Logic High 15 20 mA 6 Power Consumption Standby Mode 200 µW 1 Operating temperature range is −40°C to +85°C (B: Version). 2 Typical values for SNR apply for parts soldered directly to the PCB ground plane. 3 Dynamic specifications apply for input signal frequencies from dc to 0.0240 × fCLKIN in decimate by 16 mode and from dc to 0.0120 × fCLKIN in decimate by 32 mode. 4 When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB. 5 Gain error excludes reference error. 6 CLKIN and digital inputs static and equal to 0 or DVDD. Rev. C | Page 5 of 32 AD7723 TIMING SPECIFICATIONS AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = logic low or high, CFMT = logic low or high; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Symbol Min Typ Max Unit CLKIN Frequency f 1 19.2 MHz CLK CLKIN Period (tCLK – 1/fCLK) t1 0.052 1 µs CLKIN Low Pulse Width t2 0.45 × t1 0.55 × t1 CLKIN High Pulse Width t3 0.45 × t1 0.55 × t1 CLKIN Rise Time t 5 ns 4 CLKIN Fall Time t 5 ns 5 FSI Setup Time t6 0 5 ns FSI Hold Time t 0 5 ns 7 1 FSI High Time t 1 t 8 CLK CLKIN to SCO Delay t 25 40 ns 9 2 SCO Period , SCR = 1 t10 2 tCLK 2 SCO Period , SCR = 0 t10 1 tCLK SCO Transition to FSO High Delay t 0 5 ns 11 SCO Transition to FSO Low Delay t 0 5 ns 12 SCO Transition to SDO Valid Delay t 5 12 ns 13 3 SCO Transition from FSI t14 60 tCLK + t2 SDO Enable Delay Time t15 5 20 ns SDO Disable Delay Time t16 5 20 ns 2 DRDY t17 2 tCLK High Time 2 Conversion Time (Refer to Table 3 and Table 4) t18 16/32 tCLK DRDY t19 35 50 ns CLKIN to Transition CLKIN to DATA Valid t 20 35 ns 20 t 0 ns CS/RD Setup Time to CLKIN 21 CS RD t22 20 ns / Hold Time to CLKIN Data Access Time t23 20 35 ns Bus Relinquish Time t24 20 35 ns SYNC Input Pulse Width t25 1 tCLK SYNC Low Time before CLKIN Rising t26 0 ns DRDY t27 25 35 ns High Delay after Rising SYNC DRDY t 2049 t Low Delay after SYNC Low 28 CLK 1 FSO pulses are gated by the release of FSI (going low). 2 Guaranteed by design. 3 Frame sync is initiated on the falling edge of CLKIN. I OL 1.6mA TO 1.6V OUTPUT PIN C L 50pF I OH 200µA Figure 2. Load Circuit for Timing Specifications Rev. C | Page 6 of 32 01186-002 AD7723 t 5 t 4 t 2 2.3V CLKIN 0.8V t 3 t 1 t 7 t 6 FSI t 8 t 9 SCO t 9 t 10 Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output 32 CLKIN CYCLES CLKIN t 8 FSI (SFMT = 1) t 14 SCO (CFMT = 0) t 11 FSO (SFMT = 0) t t 11 12 FSO (SFMT = 1) t 13 SDO D15 D14 D13 D2 D1 D0 D15 D14 Figure 4. Serial Mode 1: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) 32 CLKIN CYCLES CLKIN t 8 FSI t 14 SCO (CFMT = 0) t 11 t 12 FSO t 13 SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D3 D2 D1 D0 D15 D14 D4 Figure 5. Serial Mode 2: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Rev. C | Page 7 of 32 01186-005 01186-003 01186-004 AD7723 32 CLKIN CYCLES CLKIN t 8 FSI t 14 SCO (CFMT = 0) t 12 t 11 16 CLKIN CYCLES 16 CLKIN CYCLES FSO t 13 SDO D3 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D3 D2 D1 D0 D15 D3 Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Table 3. Serial Interface (MODE1 = 0, MODE2 = 0) Control Inputs Serial Mode Decimation Ratio (SLDR) Digital Filter Mode (SLP) SCO Frequency (SCR) Output Data Rate SLDR SLP SCR 1 32 Low Pass fCLKIN fCLKIN/32 1 1 0 1 32 Band Pass fCLKIN fCLKIN/32 1 0 0 2 32 Low Pass f/2 f/32 1 1 1 CLKIN CLKIN 2 32 Band Pass f/2 f/32 1 0 1 CLKIN CLKIN 3 16 Low Pass f f/16 0 1 0 CLKIN CLKIN Table 4. Parallel Interface Control Inputs Digital Filter Mode Decimation Ratio Output Data Rate MODE1 MODE2 Band Pass 32 fCLKIN/32 0 1 Low Pass 32 f/32 1 0 CLKIN Low Pass 16 f/16 1 1 CLKIN DOE t t 16 15 SDO Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output Rev. C | Page 8 of 32 01186-007 01186-006 AD7723 t 18 CLKIN t 19 t 19 t 17 DRDY t 20 DB0–DB15 WORD N WORD N – 1 WORD N + 1 Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low CLKIN t 18 t 19 DRDY t t 22 19 RD/CS t 21 t 22 t 21 t 24 DB0–DB15 VALID DATA t 23 Figure 9. Parallel Mode Read Timing, CS = RD t 28 CLKIN t 26 SYNC t 25 DRDY t 27 Figure 10. SYNC Timing Rev. C | Page 9 of 32 01186-009 01186-008 01186-010 AD7723 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress DV to DGND −0.3 V to +7 V DD rating only; functional operation of the device at these or any AV , AV to AGND −0.3 V to +7 V DD DD1 other conditions above those indicated in the operational AVDD, AVDD1 to DVDD −1 V to +1 V section of this specification is not implied. Exposure to absolute AGND, AGND1 to DGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect Digital Inputs to DGND −0.3 V to DV + 0.3 V DD device reliability. Digital Outputs to DGND −0.3 V to DV + 0.3 V DD VIN (+), VIN(−) to AGND −0.3 V to AVDD + 0.3 V REF1 to AGND −0.3 V to AV + 0.3 V DD REF2 to AGND −0.3 V to AV + 0.3 V DD Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 95°C/W θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 10 of 32 AD7723 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 1 33 DGND/DB2 SCR/DB13 PIN 1 DGND/DB1 2 IDENTIFIER 32 DGND/DB14 3 31 DGND/DB0 DGND/DB15 4 30 CFMT/RD DV /CS DD 5 DGND/DRDY 29 SYNC AD7723 DGND 6 TOP VIEW 28 DGND (Not to Scale) 7 MODE2 27 STBY 8 26 AV MODE1 DD 9 AGND1 25 AGND 10 24 UNI AGND1 11 AV 23 REF2 DD1 12 13 14 15 16 17 18 19 20 21 22 Figure 11. 44-Lead MQFP Table 6. Pin Function Descriptions Pin No. Mnemonic Description 6, 28 DGND Ground Reference for Digital Circuitry. 8, 7 MODE1/MODE2 Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface operation and select the operating mode for the digital filter in parallel mode. See Table 3 and Table 4. 9, 10 AGND1 Digital Logic Power Supply Ground for the Analog Modulator. 11 AVDD1 Digital Logic Power Supply Voltage for the Analog Modulator. 12 CLKIN Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 MΩ resistor, can be connected betweenthe XTAL pin and the CLKIN pin with XTAL_OFF tied low. External capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal manufacturer’s recommendation for the load capacitors. 13 XTAL Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1. 14 XTAL_OFF Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock source. Set low when using an external crystal between the CLKIN and XTAL pins. 15 HALF_PWR When set high, the power dissipation is reduced by approximately one-half, and a maximum CLKIN frequency of 10 MHz applies. 16, 18, 25 AGND Power Supply Ground for the Analog Modulator. 17, 26 AVDD Positive Power Supply Voltage for the Analog Modulator. 19 VIN(−) Negative Terminal of the Differential Analog Input. 20 VIN(+) Positive Terminal of the Differential Analog Input. 21 REF1 Reference Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to a buffer amplifier that drives the Σ-∆ modulator. 22 AGND2 Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator. 23 REF2 Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the Σ-∆ modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the internal buffer amplifier. 24 UNI Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipolar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation. 27 STBY Standby Logic Input. A logic high sets the AD7723 into the power-down state. Rev. C | Page 11 of 32 CLKIN DGND/DB3 XTAL DOE/DB4 XTAL_OFF SFMT/DB5 HALF_PWR FSI/DB6 AGND SCO/DB7 AV DV DD DD AGND SDO/DB8 VIN(–) FSO/DB9 VIN(+) TSI/DB10 REF1 SLP/DB11 AGND2 SLDR/DB12 01186-011 AD7723 Pin No. Mnemonic Description 29 SYNC Synchronization Logic Input. When using more than one AD7723 operated from a common master clock, SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising edge resets the AD7723 digital filter sequencer counter to 0. When the rising edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset during this action, SYNC pulses cannot be applied continuously. 39 DVDD Digital Power Supply Voltage; 5 V ± 5%. Table 7. Parallel Mode Pin Function Descriptions Pin No. Mnemonic Description 1 DGND/DB2 Data Output Bit. 2 DGND/DB1 Data Output Bit. 3 DGND/DB0 Data Output Bit (LSB). 4 CFMT/RD Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output data bits, DB15 to DB0, are high impedance. 5 DGND/DRDY Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data register. DRDY returns high upon completion of a read operation. If a read operation does not occur between output updates, DRDY pulses high for two CLKIN cycles before the next output update. DRDY also indicates when conversion results are available after a SYNC sequence. 30 DV /CS Chip Select Logic Input. DD 31 DGND/DB15 Data Output Bit (MSB). 32 DGND/DB14 Data Output Bit. 33 SCR/DB13 Data Output Bit. 34 SLDR/DB12 Data Output Bit. 35 SLP/DB11 Data Output Bit. 36 TSI/DB10 Data Output Bit. 37 FSO/DB9 Data Output Bit. 38 SDO/DB8 Data Output Bit. 40 SCO/DB7 Data Output Bit. 41 FSI/DB6 Data Output Bit. 42 SFMT/DB5 Data Output Bit. 43 DOE/DB4 Data Output Bit. 44 DGND/DB3 Data Output Bit. Rev. C | Page 12 of 32 AD7723 Table 8. Serial Mode Pin Function Descriptions Pin No. Mnemonic Description 1 DGND/DB2 Tie to DGND. 2 DGND/DB1 Tie to DGND. 3 DGND/DB0 Tie to DGND. 4 CFMT/RD Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of SCO. 5 DGND/DRDY Tie to DGND. 30 DV /CS Tie to DVDD. DD 31 DGND/DB15 Tie to DGND. 32 DGND/DB14 Tie to DGND. 33 SCR/DB13 Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency. 34 SLDR/DB12 Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate is selected. A logic low selects the high data rate. The high data rate corresponds to data at the output of the fourth decimation filter (decimate by 16). The low data rate corresponds to data at the output of the fifth decimation filter (decimate by 32). 35 SLP/DB11 Serial Mode Low-Pass/Band-Pass Filter Select Input. With SLP set logic high, the low-pass filter response is selected. A logic low selects band-pass. 36 TSI/DB10 Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE enables the SDO output buffer when it is a logic high and vice versa. TSI is used when two AD7723s are connected to the same serial data bus. When this function is not needed, TSI and DOE should be tied low. 37 FSO/DB9 Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse that is active low for the duration of the 16-data bit transmission. 38 SDO/DB8 Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles. 40 SCO/DB7 Serial Clock Output. 41 FSI/DB6 Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output data register to an external source and to allow more than one AD7723, operated from a common master clock, to simultaneously sample its analog input and update its output register. 42 SFMT/DB5 Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal for Serial Mode 1. A logic low makes the FSO output a pulse one SCO cycle wide at the beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT should be tied high. 43 DOE/DB4 Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin, the serial data output, SDO, is active. Otherwise, SDO is high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO. In normal operations, TSI and DOE should be tied low. 44 DGND/DB3 Tie to DGND. Rev. C | Page 13 of 32 AD7723 TERMINOLOGY Signal-to-Noise Ratio (SNR) Integral Nonlinearity SNR is the measured signal-to-noise ratio at the output of the This is the maximum deviation of any code from a straight line ADC. The signal is the rms magnitude of the fundamental. passing through the endpoints of the transfer function. The Noise is the rms sum of all of the nonfundamental signals up to endpoints of the transfer function are minus full scale, a point half the output data rate (F /2), excluding dc. The ADC is 0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01 O evaluated by applying a low noise, low distortion sine wave in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode), signal to the input pins. By generating a fast fourier transform and plus full scale, a point 0.5 LSB above the last code transition (FFT) plot, the SNR data can then be obtained from the output (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . spectrum. 11 in unipolar mode). The error is expressed in LSBs. Total Harmonic Distortion (THD) Differential Nonlinearity THD is the ratio of the rms sum of the harmonics to the rms This is the difference between the measured and the ideal 1 LSB value of the fundamental. THD is defined as change between two adjacent codes in the ADC. 2 2 2 2 2 Common-Mode Rejection Ratio V +V +V +V +V 2 3 4 5 6 THD= 20log The ability of a device to reject the effect of a voltage applied to V 1 both input terminals simultaneously—often through variation of a ground level—is specified as a common–mode rejection where V is the rms amplitude of the fundamental, and V , V , 1 2 3 ratio. CMRR is the ratio of gain for the differential signal to the V , V , and V are the rms amplitudes of the second through 4 5 6 gain for the common-mode signal. sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectrum. Unipolar Offset Error Unipolar offset error is the deviation of the first code transition Spurious-Free Dynamic Range (SFDR) (10 . . . 000 to 10 . . . 001) from the ideal differential voltage Defined as the difference, in dB, between the peak spurious or (VIN(+) – VIN(–)+ 0.5 LSB) when operating in the unipolar harmonic component in the ADC output spectrum (up to FO/2 mode. and excluding dc) and the rms value of the fundamental. Normally, the value of this specification is determined by the Bipolar Offset Error largest harmonic in the output spectrum of the FFT. For input This is the deviation of the midscale transition code (111 . . . 11 signals whose second harmonics occur in the stop-band region to 000 . . . 00) from the ideal differential voltage (VIN(+) – of the digital filter, the spur in the noise floor limits the SFDR. VIN(–) – 0.5 LSB) when operating in the bipolar mode. Pass-Band Ripple Gain Error The frequency response variation of the AD7723 in the defined The first code transition should occur at an analog value ½ LSB pass-band frequency range. above –full scale. The last transition should occur for an analog value 1 ½ LSB below the nominal full scale. Gain error is the Pass-Band Frequency deviation of the actual difference between first and last code The frequency up to which the frequency response variation is transitions and the ideal difference between first and last code within the pass-band ripple specification. transitions. Cutoff Frequency The frequency below which the AD7723’s frequency response will not have more than 3 dB of attenuation. Stop-Band Frequency The frequency above which the AD7723’s frequency response will be within its stop-band attenuation. Stop-Band Attenuation The AD7723’s frequency response will not have less than 90 dB of attenuation in the stated frequency band. Rev. C | Page 14 of 32 AD7723 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; TA = 25°C; CLKIN = 19.2 MHz; external 2.5 V reference, unless otherwise noted. 106 110 SIGNAL FREQUENCY = 98kHz SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz MEASUREMENT BANDWIDTH = 460kHz 104 100 3RD 102 90 100 THD 80 98 SFDR 96 70 2ND 94 SNR THD 60 92 SNR 50 90 88 40 –50 –25 0 25 50 75 100 –50 –40 –30 –20 –10 0 TEMPERATURE (°C) ANALOG INPUT LEVEL (dB) Figure 15. SNR and THD vs. Temperature (Output Data Rate = 600 kHz) Figure 12. SNR, THD, and SFDR vs. Analog Input Level Relative to Full Scale (Output Data Rate = 1.2 MHz) 110 106 SIGNAL FREQUENCY = 98kHz 104 MEASUREMENT BANDWIDTH = 300kHz SFDR 100 102 100 90 THD THD 98 80 96 SFDR INPUT SIGNAL = 10kHz 94 MEASUREMENT BANDWIDTH = 0.383× OWR 70 SNR 92 60 90 88 50 SNR 86 40 84 –50 –40 –30 –20 –10 0 100 500 1000 1500 2150 ANALOG INPUT LEVEL (dB) OUTPUT WORD RATE (kHz) Figure 13. SNR, THD, and SFDR vs. Analog Input Level Relative to Full Scale Figure 16. SNR, THD, and SFDR vs. Sampling Frequency (Decimate by 16) (Output Data Rate = 600 kHz) 102 115 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz INPUT SIGNAL = 10kHz 100 MEASUREMENT BANDWIDTH = 0.5× OWR 3RD 110 98 SFDR 96 2ND 105 94 THD 92 100 90 THD 88 95 SNR 86 SNR 84 90 –50 –25 0 25 50 75 100 50 150 300 450 600 750 900 TEMPERATURE (°C) OUTPUT WORD RATE (kHz) Figure 14. SNR and THD vs. Temperature (Output Data Rate = 1.2 MHz) Figure 17. SNR, THD, and SFDR vs. Sampling Frequency (Decimate by 32) Rev. C | Page 15 of 32 (dB) (dB) (dB) 01186-013 01186-012 01186-014 (dB) (dB) (dB) 01186-015 01186-017 01186-016 AD7723 R 2000 FB 220Ω V (+) = V (–) IN IN R SOURCE R 1800 IN 8192 SAMPLES TAKEN AIN =±2V 50Ω AD8047 390Ω BIASED 27Ω 1600 ABOUT 20 VIN(+) A1 GROUND 1400 R BALANCE2 R BALANCE1 1200 220Ω 220Ω 220pF R BALANCE2 1000 AD7723 220Ω 800 R REF1 27Ω 19 VIN(–) A2 10kΩ 600 AD8047 23 R REF2 REF2 220nF 10nF 20kΩ 400 21 REF1 200 GAIN = 2× R /(R + R ) FB IN SOURCE 1µF R = R × (R + R )/(2× R ) 0 BALANCE1 BALANCE2 IN SOURCE FB R = R × (R + R )/R 32700 32702 32704 32706 32708 32710 32712 32713 REF2 REF1 IN SOURCE FB CODE Figure 18. Histogram of Output Codes with DC Input Figure 21. Differential Nonlinearity (Output Data Rate = 600 kHz) (Output Data Rate = 1.2 MHz) 5000 1.0 V (+) = V (–) IN IN 67108864 SAMPLES TAKEN 4500 8192 SAMPLES TAKEN 0.8 DIFFERENTIAL MODE 4000 0.6 3500 0.4 3000 0.2 2500 0 2000 –0.2 1500 –0.4 –0.6 1000 500 –0.8 0 –1.0 32703 32704 32705 32706 32707 32708 32709 32710 0 16384 32768 49152 65535 CODE CODE Figure 19. Histogram of Output Codes with DC Input Figure 22. Integral Nonlinearity (Output Data Rate =1.2 MHz) (Output Data Rate = 600 kHz) 1.0 1.0 67108864 SAMPLES TAKEN 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0.8 0.8 DIFFERENTIAL MODE 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 16384 32768 49152 65535 0 16384 32768 49152 65535 CODE CODE Figure 20. Differential Nonlinearity (Output Data Rate = 1.2 MHz) Figure 23. Integral Nonlinearity (Output Data Rate = 600 kHz) Rev. C | Page 16 of 32 DNL ERROR (LSB) FREQUENCY OF OCCURRENCE FREQUENCY OF OCCURRENCE 01186-019 01186-018 01186-020 INL ERROR (LSB) INL ERROR (LSB) 01186-023 01186-022 01186-021 AD7723 225 0 SNR = –89.91dB 200 –20 SNR + D = –89.7dB AI (HALF_POWER = 0) THD = –101.16dB DD 175 SFDR = –102.1dB –40 2ND HARMONIC = –102.1dB 3RD HARMONIC = –110.3dB 150 A = 50kHz IN –60 MEASURED BW = 300kHz 125 –80 100 AI (HALF_POWER = 1) DD –100 75 DI DD –120 50 25 –140 0 –160 02 510 15 205 150k 200k 250k 300k 0 50k 100k CLOCK FREQUENCY (MHz) FREQUENCY (Hz) Figure 24. Power Consumption vs. CLKIN Frequency Figure 26. 16 K Point FFT (Output Data Rate = 600 kHz) 0 SNR = –86.19dB SNR + D = –85.9dB –25 THD = –96.42dB SFDR = –99.61dB 2ND HARMONIC = –100.98dB 3RD HARMONIC = –99.61dB –50 A = 100kHz IN MEASURED BW = 460kHz –75 –100 –125 –150 300k 400k 500k 600k 0 100k 200k FREQUENCY (Hz) Figure 25. 16 K Point FFT (Output Data Rate = 1.2 MHz) Rev. C | Page 17 of 32 POWER LEVEL RELATIVE TO FULL SCALE (dB) POWER (mW) 01186-024 01186-025 POWER LEVEL RELATIVE TO FULL SCALE (dB) 01186-026 AD7723 CIRCUIT DESCRIPTION the converter is 16. Data fed to the interface from the output of The AD7723 ADC employs a Σ-Δ conversion technique to the fifth filter results in an output data rate of fCLKIN/32 and a convert the analog input into an equivalent digital word. The corresponding OSR for the converter of 32. When an output modulator samples the input waveform and outputs an data rate (ODR) of fCLKIN/32 is selected, the digital filter equivalent digital word at the input clock frequency, fCLKIN. response can be set to either low-pass or band-pass. The band- Due to the high oversampling rate that spreads the quantization pass response is useful when the input signal is band limited noise from 0 to f /2, the noise energy contained in the band because the resulting output data rate is half that required to CLKIN of interest is reduced (Figure 27A). To further reduce the convert the band when the low-pass operating mode is used. To quantization noise, a high-order modulator is employed to illustrate the operation of this mode, consider a band-limited shape the noise spectrum so that most of the noise energy is signal, as shown in Figure 28A. This signal band can be shifted out of the band of interest (Figure 27B). correctly converted by selecting the (low-pass) ODR = fCLKIN/16 mode, as shown in Figure 28B. Note that the output data rate is a The digital filter that follows the modulator removes the large little over twice the maximum frequency in the frequency band. out-of-band quantization noise (Figure 27C) while also reducing the data rate from f at the input of the filter to Alternatively, the band-pass mode can be selected, as shown in CLKIN f /32 or f /16 at the output of the filter, depending on the Figure 28C. The band-pass filter removes unwanted signals CLKIN CLKIN state on the MODE1/MODE2 pins in parallel interface mode or from dc to just below fCLKIN/64. Rather than outputting data at the SLDR pin in serial interface mode. The AD7723 output data fCLKIN/16, the output of the band-pass filter is sampled at rate is a little over twice the signal bandwidth, which guarantees fCLKIN/32. This effectively translates the wanted band to a that there is no loss of data in the signal band. maximum frequency of a little less than fCLKIN/64, as shown in Figure 28D. Halving the output data rate reduces the workload Digital filtering has certain advantages over analog filtering. of any following signal processor and also allows a lower serial First, since digital filtering occurs after the A/D conversion, it clock rate to be used. can remove noise injected during the conversion process. BAND LIMITED SIGNAL Analog filtering cannot remove noise injected during 0dB conversion. Second, the digital filter combines low pass-band ripple with a steep roll-off while also maintaining a linear phase f /16 CLKIN response. A LOW-PASS FILTER RESPONSE ODR 0dB SAMPLE QUANTIZATION NOISE IMAGE f /2 CLKIN BAND OF INTEREST f /16 CLKIN A LOW-PASS FILTER. OUTPUT DATA RATE = f /16 CLKIN B BAND-PASS FILTER NOISE SHAPING RESPONSE SAMPLE 0dB IMAGE f /2 CLKIN BAND OF INTEREST B f /16 CLKIN BAND-PASS FILTER C DIGITAL FILTER CUTOFF FREQUENCY FREQUENCY SAMPLE TRANSLATED ODR 0dB IMAGE INPUT SIGNAL f /2 CLKIN BAND OF INTEREST C f /16 CLKIN LOW-PASS FILTER. OUTPUT DATA RATE = f /32 CLKIN Figure 27. Sigma-Delta ADC D The AD7723 employs four or five finite impulse response (FIR) Figure 28. Band-Pass Operation filters in series. Each individual filter’s output data rate is half that of the filter’s input data rate. When data is fed to the The frequency response of the three digital filter operating interface from the output of the fourth filter, the output data modes is shown in Figure 29, Figure 30, and Figure 31. rate is f /16 and the resulting oversampling ratio (OSR) of CLKIN Rev. C | Page 18 of 32 01186-027 01186-028 AD7723 Figure 32 shows the frequency response of the digital filter in both low-pass and band-pass modes. Due to the sampling nature of the converter, the pass-band response is repeated 0dB about the input sampling frequency, fCLKIN, and at integer multiples of fCLKIN. Out-of-band noise or signals coincident with any of the filter images are aliased down to the pass band. However, due to the AD7723’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most –100dB broadband noise is attenuated by at least 90 dB. In addition, as shown in Figure 33, with even a low-order filter, there is significant attenuation at the first image frequency. This contrasts with a normal Nyquist rate converter where a very high-order antialias filter is required to allow most of the 0 0.5 1.0 f CLKIN bandwidth to be used while ensuring sufficient attenuation at multiples of fCLKIN. Figure 29. Low-Pass Filter Decimate by 16 0dB 0dB 1f 2f 3f CLKIN CLKIN CLKIN Figure 32. Digital Filter Frequency Response –100dB OUTPUT DATA RATE ANTIALIAS FILTER RESPONSE REQUIRED 0dB ATTENUATION f /32 f CLKIN CLKIN Figure 33. Frequency Response of Antialias Filter 0 0.5 1.0 f CLKIN Figure 30. Low-Pass Filter Decimate by 32 0dB –100dB 0 0.5 1.0 f CLKIN Figure 31. Band-Pass Filter Decimate by 32 Rev. C | Page 19 of 32 01186-030 01186-031 01186-029 01186-032 01186-033 AD7723 APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT The AD7723 has differential inputs to provide common-mode The analog input of the AD7723 uses a switched capacitor noise rejection. In unipolar mode, the analog input range is 0 to technique to sample the input signal. For the purpose of driving 8/5 × V , while in bipolar mode, the analog input range is the AD7723, an equivalent circuit of the analog inputs is shown REF2 ±4/5 × VREF2. The output code is twos complement binary in in Figure 36. For each half clock cycle, two highly linear both modes with 1 LSB = 61 µV. The ideal input/output transfer sampling capacitors are switched to both inputs, converting the characteristics for the two modes are shown in Figure 34. In input signal into an equivalent sampled charge. A signal source both modes, the absolute voltage on each input must remain driving the analog inputs must be able to source this charge within the supply range AGND to AV . The bipolar mode while also settling to the required accuracy by the end of each DD allows either single-ended or complementary input signals. half-clock phase. 011…111 ΦA AD7723 011…110 500Ω VIN(+) 20 2pF ΦB 000…010 2pF 000…001 ΦA 500Ω 000…000 VIN(–) 19 AC 111…111 GROUND ΦB 111…110 Φ Φ Φ Φ CLKIN A A B B 100…001 100…000 Figure 36. Analog Input Equivalent Circuit –4/5×V 0V +4/5× V – 1LSB BIPOLAR REF2 REF2 (0V) DRIVING THE ANALOG INPUTS (+4/5× V ) (+8/5× V – 1LSB) UNIPOLAR REF2 REF2 To interface the signal source to the AD7723, at least one op Figure 34. Bipolar (Unipolar) Mode Transfer Function amp is generally required. Choice of op amp is critical to The AD7723 accepts full-scale, in-band signals. However, large achieving the full performance of the AD7723. The op amp not scale out-of-band signals can overload the modulator inputs. only has to recover from the transient loads that the ADC Figure 35 shows the maximum input signal level as a function imposes on it, but it must also have good distortion of frequency. A minimal single-pole, RC, antialias filter set to characteristics and very low input noise. Resistors in the signal fCLKIN/24 allows full-scale input signals over the entire frequency path can also add to the overall thermal noise floor, spectrum. necessitating the choice of low value resistors. 2.2 Placing an RC filter between the drive source and the ADC 2.1 inputs, as shown in Figure 37, has a number of beneficial effects. Transients on the op amp outputs are significantly 2.0 reduced because the external capacitor now supplies the 1.9 instantaneous charge required when the sampling capacitors are 1.8 switched to the ADC input pins and input circuit noise at the sample images is now significantly attenuated, resulting in 1.7 improved overall SNR. The external resistor serves to isolate the 1.6 external capacitor from the ADC output, thus improving op 1.5 amp stability while also isolating the op amp output from any V = 2.5V REF remaining transients on the capacitor. By experimenting with 1.4 different filter values, the optimum performance can be 1.3 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.5 achieved for each application. As a guideline, the RC time INPUT SIGNAL FREQUENCY RELATIVE TO f CLKIN constant (R × C) should be less than a quarter of the clock period to avoid nonlinear currents from the ADC inputs being Figure 35. Peak Input Signal Level vs. Signal Frequency stored on the external capacitor and degrading distortion. This restriction means that this filter cannot form the main antialias filter for the ADC. Rev. C | Page 20 of 32 PEAK INPUT (V p-p) 01186-034 01186-035 01186-036 AD7723 R FB 220Ω R R SOURCE R IN VIN(+) AIN =±2V AD8047 50Ω 390Ω BIASED 27Ω ABOUT 20 VIN(+) A1 C AD7723 GROUND R 220Ω R BALANCE1 VIN(–) R BALANCE2 220Ω 220pF R BALANCE2 AD7723 220Ω Figure 37. Input RC Network R REF1 27Ω 19 VIN(–) A2 10kΩ With the unipolar input mode selected, just one op amp is AD8047 23 R REF2 REF2 20kΩ 220nF 10nF required to buffer single-ended input signals. However, driving the AD7723 with complementary signals and with the bipolar 21 REF1 GAIN = 2× R /(R + R ) FB IN SOURCE 1µF input range selected has some distinct advantages: even-order R = R × (R + R )/(2× R ) BALANCE1 BALANCE2 IN SOURCE FB R = R × (R + R )/R REF2 REF1 IN SOURCE FB harmonics in both the drive circuits and the AD7723 front end are attenuated and the peak-to-peak input signal range on both Figure 39. Single-Ended-to-Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased About Ground) inputs is halved. Halving the input signal range allows some op amps to be powered from the same supplies as the AD7723. APPLYING THE REFERENCE Although a complementary driver requires the use of two op The reference circuitry used in the AD7723 includes an on-chip amps per ADC, it may avoid the need to generate additional 2.5 V band-gap reference and a reference buffer circuit. The supplies just for these op amps. block diagram of the reference circuit is shown in Figure 40. Figure 38 and Figure 39 show two such circuits for driving the The internal reference voltage is connected to REF1 through a AD7723. Figure 38 is intended for use when the input signal is 3 kΩ resistor and is internally buffered to drive the analog biased about 2.5 V, while Figure 39 is used when the input signal modulator’s switched cap DAC (REF2). When using the is biased about ground. While both circuits convert the input internal reference, a 1 µF capacitor is required between REF1 and AGND to decouple the band-gap noise. If the internal signal into a complementary signal, the circuit in Figure 39 also level shifts the signal so that both outputs are biased about 2.5 V. reference is required to bias external circuits, use an external Suitable op amps include the AD8047, AD8044, AD8041, and precision op amp to buffer REF1. its dual equivalent, the AD8042. The AD8047 has lower input noise than the AD8041/AD8042 but has to be supplied from a COMPARATOR 1V AD7723 +7.5 V/−2.5 V supply. The AD8041/AD8042 typically degrades REFERENCE SNR from 90 dB to 88 dB but can be powered from the same BUFFER REF1 SWITCHED-CAP 21 single 5 V supply as the AD7723. DAC REFERENCED 1µF R 3kΩ FB 2.5V 220Ω REFERENCE R SOURCE R IN AIN =±2V REF2 23 AD8047 50Ω 390Ω BIASED 27Ω ABOUT 2.5V 20 A1 VIN(+) Figure 40. Reference Circuit Block Diagram 220Ω Where gain error or gain error drift requires the use of an 220pF external reference, the reference buffer in Figure 40 can be AD7723 220Ω turned off by grounding the REF1 pin and the external 27Ω 19 VIN(–) A2 reference can be applied directly to REF2 pin. The AD7723 10kΩ AD8047 accepts an external reference voltage between 1.2 V to 3.15 V. 23 REF2 220nF 10nF By applying a 3 V rather than a 2.5 V reference, SNR is typically improved by about 1 dB. Where the output common-mode 21 REF1 1µF range of the amplifier driving the inputs is restricted, the full- GAIN = 2× R /(R + R ) FB SOURCE IN scale input signal span can be reduced by applying a lower than 2.5 V reference. For example, a 1.25 V reference would make Figure 38. Single-Ended-to-Differential Input Circuit for Bipolar Mode the bipolar input span ±1 V but would degrade SNR. Operation (Analog Input Biased About 2.5 V) Rev. C | Page 21 of 32 01186-037 01186-038 01186-040 01186-039 AD7723 In all cases, since the REF2 voltage connects to the analog AD7723 modulator, a 220 nF and 10 nF capacitor must connect directly XTAL CLKIN from REF2 to AGND. The external capacitor provides the 1MΩ charge required for the dynamic load presented at the REF2 pin (see Figure 41). Φ A Figure 43. Crystal Oscillator Connection Φ 4pF B When an external clock source is being used, the internal REF2 23 oscillator circuit can be disabled by tying XTAL_OFF high. A 10nF 220nF Φ 4pF Φ A low phase noise clock should be used to generate the ADC B SWITCHED-CAP sampling clock because sampling clock jitter effectively DAC REFERENCED modulates the input signal and raises the noise floor. The Φ Φ CLKIN ΦΦ A A sampling clock generator should be isolated from noisy digital B B circuits, grounded, and heavily decoupled to the analog ground Figure 41. REF2 Equivalent Input Circuit plane. The AD780 is ideal to use as an external reference with the The sampling clock generator should be referenced to the AD7723. Figure 42 shows a suggested connection diagram. analog ground in a split ground system. However, this is not Grounding Pin 8 on the AD780 selects the 3 V output mode. always possible because of system constraints. In many 2.5V applications, the sampling clock must be derived from a higher 5V O/P REF2 NC 1 8 SELECT frequency multipurpose system clock that is generated on the +V 2 7 IN NC 220nF AD7723 10nF 1µ F digital ground plane. If the clock signal is passed between its V 3 TEMP 6 OUT 22nF 4 5 22µF origin on a digital ground plane to the AD7723 on the analog GND TRIM REF1 AD780 ground plane, the ground noise between the two planes adds NC = NO CONNECT directly to the clock and produces excess jitter. The jitter can cause degradation in the signal-to-noise ratio and also produce Figure 42. External Reference Circuit Connection unwanted harmonics. This can be remedied somewhat by CLOCK GENERATION transmitting the sampling signal as a differential one, using The AD7723 contains an oscillator circuit to allow a crystal or either a small RF transformer or a high speed differential driver an external clock signal to generate the master clock for the and a receiver such as PECL. In either case, the original master ADC. The connection diagram for use with a crystal is shown system clock should be generated from a low phase noise crystal in Figure 43. Consult the manufacturer’s recommendation for oscillator. the load capacitors. To enable the oscillator circuit on board the AD7723, XTAL_OFF should be tied low. Rev. C | Page 22 of 32 01186-041 01186-042 01186-043 AD7723 SYSTEM SYNCHRONIZATION The SYNC input provides a synchronization function for use in Following a SYNC, the modulator and filter need time to settle parallel or serial mode. SYNC allows the user to begin gathering before data can be read from the AD7723. DRDY goes high samples of the analog input from a known point in time. following a synchronization and it remains high until valid data is available at the interface. This allows a system using multiple AD7723s, operated from a common master clock, to be synchronized so that each ADC When operating in any of the serial modes, either SYNC or simultaneously updates its output register. frame sync input (FSI) may be used to synchronize multiple AD7723 devices to a common master clock. The functionality In a system using multiple AD7723s, a common signal to their of FSI is detailed in the Serial Interface section. sync inputs synchronizes their operation. On the rising edge of SYNC, the digital filter sequencer is reset to 0. The filter is held in a reset state until a rising edge on CLKIN senses SYNC low. A SYNC pulse, one CLKIN cycle long, can be applied synchronous to the falling edge of CLKIN. This way, on the next rising edge of CLKIN, SYNC is sensed low, the filter is taken out of its reset state, and multiple parts begin to gather input samples. Rev. C | Page 23 of 32 AD7723 DATA INTERFACING is used to latch the conversion cycles, the rising edge of DRDY The AD7723 offers a choice of serial or parallel data interface data before a new conversion result is loaded into the output options to meet the requirements of a variety of system data register. The falling edge of then sends an DRDY configurations. In parallel mode, multiple AD7723s can easily appropriate interrupt signal for interface control. Alternatively, be configured to share a common data bus. Serial mode is ideal if buffers are used instead of latches, the falling edge of DRDY when it is required to minimize the number of data interface lines connected to a host processor. In either case, careful provides the necessary interrupt when a new output word is attention to the system configuration is required to realize the available from the AD7723. high dynamic range available with the AD7723. Consult the recommendations in the Grounding and Layout section. The AD7723 DSP following recommendations for parallel interfacing also apply 16 74XX16374 16 DB15 D15 for the system design when using the serial mode. ADDR ADDR PARALLEL INTERFACE DECODE DRDY When using the AD7723, place a buffer/latch adjacent to the OE converter to isolate the converter’s data lines from any noise RD CS that may be on the data bus. Even though the AD7723 has three RD INTERRUPT state outputs, use of an isolation latch represents good design practice. Figure 44. Parallel Interface Connection Figure 44 shows how the parallel interface of the AD7723 can be configured to interface with the system data bus of a microprocessor or a microcontroller, such as the MC68HC16 or 8XC251. With CS and RD tied permanently low, the data output bits are always active. When goes high for two clock DRDY Rev. C | Page 24 of 32 01186-044 AD7723 SERIAL INTERFACE The AD7723’s serial data interface can operate in three modes, In Serial Mode 1, the control input, SFMT, can be used to select depending on the application requirements. The timing the format for the serial data transmission (see Figure 4). FSO is diagrams in Figure 4, Figure 5, and Figure 6 show how the either a pulse, approximately one SCO cycle in duration, or a AD7723 may be used to transmit its conversion results. Table 3 square wave with a period of 32 SCO cycles. With a logic low shows the control inputs required to select each serial mode and level on SFMT, FSO pulses high for one SCO cycle at the the digital filter operating mode. The AD7723 operates solely in beginning of a data transmission frame. With a logic high level the master mode, providing three serial data output pins for on SFMT, FSO goes low at the beginning of a data transmission transfer of the conversion results. The serial data clock output, frame and returns high after 16 SCO cycles. SCO, serial data output, SDO, and frame sync output, FSO, are Note that in Serial Mode 1, FSI can be used to synchronize the all synchronous with CLKIN. FSO is continuously output at the AD7723 if SFMT is set to a logic high. If SFMT is set low, the conversion rate of the ADC. FSI input has no effect on synchronization. Serial data shifts out of the SDO pin synchronous with SCO. In Serial Mode 2 and Serial Mode 3, SFMT should be tied high. The FSO is used to frame the output data transmission to an TSI and DOE should be tied low in these modes. The FSO is a external device. An output data transmission is either 16 or 32 pulse, approximately one SCO cycle in duration, occurring at SCO cycles in duration (see Table 3). Serial data shifts out of the the beginning of the serial data transmission. SDO pin, MSB first, LSB last, for a duration of 16 SCO cycles. In Serial Mode 1, SDO outputs 0s for the last 16 SCO cycles of the TWO-CHANNEL MULTIPLEXED OPERATION 32-cycle data transmission frame. Two additional serial interface control pins, DOE and TSI, are provided to allow the serial data outputs of two AD7723s, to The clock format pin, CFMT, selects the active edge of SCO. easily share one serial data line when operating in Serial With CFMT tied logic low, the serial interface outputs FSO and SDO change state on the SCO rising edge and are valid on the Mode 1. Figure 45 shows the connection diagram. Since a serial falling edge of SCO. With CFMT set high, FSO and SDO data transmission frame lasts 32 SCO cycles, two ADCs can change state on the falling SCO edge and are valid on the SCO share a single data line by alternating transmission of their 16- rising edge. bit output data onto one SDO pin. DV AD7723 The frame sync input, FSI, can be used if the AD7723 DD MASTER conversion process must be synchronized to an external source. SFMT SDO TO HOST CFMT SCO FSI allows the conversion data presented to the serial interface PROCESSOR TSI FSO DGND to be a filtered and decimated result derived from a known FSI DOE point in time. A common frame sync signal can be applied to CLKIN two or more AD7723s to synchronize them to a common FROM CONTROL master clock. LOGIC AD7723 When FSI is applied for the first time, the digital filter SLAVE DOE sequencer counter is reset to 0, the AD7723 interrupts the FSI DV DD SDO CLKIN current data transmission, reloads the output shift register, SCO SFMT resets SCO, and transmits the conversion result. Synchro- TSI FSO nization starts immediately and the following conversions are CFMT DGND invalid while the digital filter settles. FSI can be applied once after power-up, or it can be a periodic signal, synchronous to Figure 45. Serial Mode 1 Connection for Two-Channel Multiplexed Operation CLKIN, occurring every 32 CLKIN cycles. Subsequent FSI The data output enable pin, DOE, controls the SDO output inputs applied every 32 CLKIN cycles do not alter the serial buffer. When the logic level on DOE matches the state of the data transmission and do not reset the digital filter sequencer TSI pin, the SDO output buffer drives the serial data line; counter. FSI is an optional signal; if synchronization is not otherwise, the output of the buffer goes high impedance. The required, FSI can be tied to a logic low and the AD7723 serial format pin, SFMT, is set high to choose the frame sync generates FSO outputs. output format. The clock format pin, CFMT, is set low so that serial data is made available on SDO after the rising edge of SCO and can be latched on the SCO falling edge. Rev. C | Page 25 of 32 01186-045 AD7723 The master device is selected by setting TSI to a logic low and Since FSO pulses are gated by the release of FSI (going low) and connecting its FSO to DOE. The slave device is selected with its the FSI of the slave device is held high during its data TSI pin tied high and both its FSI and DOE controlled from the transmission, the FSO from the master device must be used for master’s FSO. Since the FSO of the master controls the DOE connection to the host processor. input of both the master and slave, one ADC’s SDO is active while the other is high impedance (Figure 46). When the master transmits its conversion result during the first 16 SCO cycles of a data transmission frame, the low level on DOE sets the slave’s SDO high impedance. Once the master completes transmitting its conversion data, its FSO goes high and triggers the slave’s FSI to begin its data transmission frame. CLKIN FSI t 9 SCO t 11 t FSO (MASTER) 12 t 13 FSI (SLAVE) DOE (MASTER AND SLAVE) t t 15 16 SDO (MASTER) D15 D14 D1 D0 t t 16 15 SDO (SLAVE) D1 D0 D15 D14 Figure 46. Serial Mode 1 Timing for Two-Channel Multiplexed Operation Rev. C | Page 26 of 32 01186-046 AD7723 SERIAL INTERFACE TO DSPs (the DSP begins reading the 16-bit word after the DSP has In serial mode, the AD7723 can be directly interfaced to several identified the frame sync signal rather than the DSP reading the industry-standard digital signal processors. In all cases, the word at the same instant as the frame sync signal is identified), AD7723 operates as the master with the DSP operating as the and LRFS = 0 (RFS is active high). The AD7723 can be used in slave. The AD7723 provides its own serial clock (SCO) to Mode 1, Mode 2, or Mode 3 when interfaced to the ADSP- transmit the digital word on the SDO pin to the DSP. The 2106x SHARC DSP. AD7723 also generates the frame synchronization signal that synchronizes the transfer of the 16-bit word from the AD7723 AD7723 TO DSP56002 INTERFACE to the DSP. Depending on the serial mode used, SCO has a Figure 48 shows the AD7723 to DSP56002 interface. To frequency equal to CLKIN or equal to CLKIN/2. When SCO interface the AD7723 to the DSP56002, the ADC is operated in equals 19.2 MHz, the AD7723 can be interfaced to the Analog Mode 2 when the ADC is operated with a 19.2 MHz clock. The Devices ADSP-2106x SHARC DSP. With a 19.2 MHz master DSP56002 is configured as follows: SYN = 1 (synchronous clock and SCO equal to CLKIN/2, the AD7723 can be mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous interfaced with the ADSP-21xx family of DSPs, the DSP56002, serial clock is used), SCKD = 0 (the serial clock is external), and the TMS320C5x-57. When the AD7723 is used in the WL1 = l, WL0 = 0 (transfers is 16 bits wide), FSL1 = 0, and HALF_PWR Mode, that is, CLKIN is less than 10 MHz, then FSL0 = 1 (the frame sync is active at the beginning of each the AD7723 can be used with DSPs, such as the transfer). Alternatively, the DSP56002 can be operated in TMS320C20/TMS320C25 and the DSP56000/DSP56001. asynchronous mode (SYN = 0). AD7723 TO ADSP-21xx INTERFACE In this mode, the serial clock for the receive section is input to Figure 47 shows the interface between the ADSP-21xx and the the SCO pin. This is accomplished by setting Bit SCDO to 0 AD7723. The AD7723 is operated in Mode 2 so that SCO = (external Rx clock). CLKIN/2. For the ADSP-21xx, the bits in the serial port control register should be set up as RFSR = 1 (a frame sync is needed DSP56002 AD7723 for each transfer), SLEN = 15 (16-bit word lengths), RFSW = 0 SDR SDO (normal framing mode for receive operations), INVRFS = 0 SC1 FSO (active high RFS), IRFS = 0 (external RFS), and ISCLK = 0 SCK SCO (external serial clock). Figure 48. AD7723 to DSP56002 Interface ADSP-21xx AD7723 DR SDO AD7723 TO TMS320C5x INTERFACE RFS FSO Figure 49 shows the AD7723 to TMS320C5x interface. For the SCLK TMS320C5x, FSR and CLKR are automatically configured as SCO inputs. The serial port is configured as follows: FO = 0 (16-bit word transfers) and FSM = 1 (a frame sync occurs for each Figure 47. AD7723 to ADSP-21xx Interface transfer). AD7723 TO SHARC INTERFACE TMS320C5x The interface between the AD7723 and the ADSP-2106x AD7723 SHARC DSP is the same as shown in Figure 47, but the DSP is DR SDO configured as follows: SLEN = 15 (16-bit word transfers), FSR FSO SENDN = 0 (the MSB of the 16-bit word is received by the DSP CLKR SCO first), ICLK = 0 (an external serial clock is used), RFSR = 0 (a frame sync is required for every word transfer), IRFS = 0 (the Figure 49. AD7723 to TMS320C5x Interface receive frame sync signal is external), CKRE = 0 (the receive data is latched into the DSP on the falling clock edge), LAFS = 0 Rev. C | Page 27 of 32 01186-047 01186-049 01186-048 AD7723 GROUNDING AND LAYOUT The analog and digital power supplies to the AD7723 are Avoid running digital lines under the device as these couple independent and separately pinned out to minimize coupling noise onto the die. The analog ground plane should be allowed between the analog and digital sections within the device. The to run under the AD7723 to shield it from noise coupling. The AD7723 AGND and DGND pins should be soldered directly to power supply lines to the AD7723 should use as large a trace as a ground plane to minimize series inductance. In addition, the possible (preferably a plane) to provide a low impedance path ac path from any supply pin or reference pin (REF1 and REF2) and reduce the effects of glitches on the power supply line. through its decoupling capacitors to its associated ground must Avoid crossover of digital and analog signals. Traces on be made as short as possible (Figure 50). To achieve the best opposite sides of the board should run at right angles to each decoupling, place surface-mount capacitors as close as possible other. This reduces the effects of feedthrough through the to the device, ideally right up against the device pins. board. All ground planes must not overlap to avoid capacitive 23 REF2 coupling. The AD7723’s digital and analog ground planes must 220nF 10nF be connected at one place by a low inductance path, preferably 22 AGND2 right under the device. Typically, this connection is either a 1µ F 21 REF1 trace on the printed circuit board of 0.5 cm wide when the ground planes are on the same layer, or 0.5 cm wide minimum 11 AV 1 DD 10nF plated through holes when the ground planes are on different 10 AGND1 layers. Any external logic connected to the AD7723 should use 5V 9 AGND1 a ground plane separate from the AD7723’s digital ground 17 AV DD plane. These two digital ground planes should also be 10nF 10µ F 100nF 100nF 18 AGND connected at just one place. 26 AV DD 10nF Separate power supplies for AV and DV are also highly 25 DD DD AGND AD7723 ANALOG GROUND PLANE desirable. The digital supply pin DV should be powered from DD AD7723 DIGITAL a separate analog supply, but if necessary, DVDD may share its 39 DV DD GROUND PLANE 10nF 10µ F power connection to AVDD, as shown in the connection diagram 100nF 10nF 6 DGND in Figure 50. The ferrites are also recommended to filter high 28 DGND frequency signals from corrupting the analog power supply. A minimum etch technique is generally best for ground planes Figure 50. Reference and Power Supply Decoupling because it gives the best shielding. Noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. High level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. In waveform sampling and reconstruction systems, the sampling clock (CLKIN) is as vulnerable to noise as any analog signal. CLKIN should be isolated from the analog and digital systems. Fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs. Rev. C | Page 28 of 32 01186-050 AD7723 OUTLINE DIMENSIONS 1.03 13.90 2.45 MAX BSC SQ 0.88 0.73 33 23 34 22 SEATING PLANE 10.00 BSC SQ TOP VIEW (PINS DOWN) 10° 6° 2.10 2° 0.23 2.00 VIEW A 0.11 1.95 PIN 1 44 12 7° 0° 1 11 0.25 MIN 0.10 0.45 COPLANARITY 0.30 VIEW A 0.80 BSC LEAD WIDTH ROTATED 90° CCW LEAD PITCH COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Figure 51. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Package Package Description Package Outline AD7723BS –40°C to +85°C 44-Lead Metric Quad Flat Package (MQFP) S-44-2 AD7723BS-REEL –40°C to +85°C 44-Lead Metric Quad Flat Package (MQFP) S-44-2 1 AD7723BSZ –40°C to +85°C 44-Lead Metric Quad Flat Package (MQFP) S-44-2 1 AD7723BSZ-REEL –40°C to +85°C 44-Lead Metric Quad Flat Package (MQFP) S-44-2 EVAL-AD7723CB Evaluation Board 1 Z = Pb-free part. Rev. C | Page 29 of 32 AD7723 NOTES Rev. C | Page 30 of 32 AD7723 NOTES Rev. C | Page 31 of 32 AD7723 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01186–0–5/05(C) Rev. C | Page 32 of 32