ANALOG DEVICES AD7722

16-Bit, 195 kSPS CMOS, �-� ADC AD7722 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-Bit �-� ADC DGND DV AGND AV REF1 64� Oversampling Ratio DD DD Up to 220 kSPS Output Word Rate Low-Pass, Linear Phase Digital Filter AD7722 2.5V REF2 Inherently Monotonic REFERENCE On-Chip 2.5 V Voltage Reference 16-BIT A/D CONVERTER V (+) Single-Supply 5 V IN �-� FIR High Speed Parallel or Serial Interface V (–) MODULATOR FILTER IN CLOCK XTAL P/S CIRCUITRY CLKIN CAL UNI RESET SYNC DB15 CS DB14 DVAL/RD DB13 CFMT/DRDY DB12 DB0 CONTROL DB11 LOGIC DB1 DB10 DB2 DB9/FSO GENERAL DESCRIPTION DB3/ DB4/ DB5/ DB6/ DB7/ DB8/ The AD7722 is a complete low power, 16-bit, Σ-∆ ADC. The TSI DOE SFMT FSI SCO SDO part operates from a 5 V supply and accepts a differential input voltage range of 0 V to +2.5 V or ±1.25 V centered around a common-mode bias. The AD7722 provides 16-bit performance for input bandwidths up to 90.625 kHz. The part provides data Conversion data is provided at the output register through a flex- at an output word rate of 195.3 kHz. ible serial port or a parallel port. This offers 3-wire, high speed interfacing to digital signal processors. The serial interface operates The analog input is continuously sampled by an analog modula- in an internal clocking (master) mode, whereby an internal serial tor, eliminating the need for external sample-and-hold circuitry. data clock and framing pulse are device outputs. Additionally, The modulator output is processed by two finite impulse response two AD7722s can be configured with the serial data outputs (FIR) digital filters in series. The on-chip filtering reduces the connected together. Each converter alternately transmits its conver- external antialias requirements to first order, in most cases. The sion data on a shared serial data line. group delay for the filter is 215.5 µs, while the settling time for a step input is 431 µs. The sample rate, filter corner frequency, The part provides an accurate on-chip 2.5 V reference. A and output word rate are set by an external clock that is reference input/output function is provided to allow either the nominally 12.5 MHz. internal reference or an external system reference to be used as the reference source for the part. Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured on-chip The AD7722 is available in a 44-lead MQFP package and is by calibration. This calibration procedure minimizes the zero- specified over the industrial temperature range of –40°C to +85°C. scale and full-scale errors. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 1 AD7722–SPECIFICATIONS (AV = AV = 5 V � 5%; DV = 5 V � 5%; AGND = AGND1 = DGND = 0 V; DD DD1 DD UNI = Logic Low or High; f = 12.5 MHz; f = 195.3 kSPS; REF2 = 2.5 V; T = T to T , unless otherwise noted.) CLKIN S A MIN MAX A Version Parameter Test Conditions/Comments Min Typ Max Unit 2 DYNAMIC SPECIFICATIONS Bipolar Mode, UNI = V V = 2.5 V, V (+) = V (–) =1.25 V p-p, INH CM IN IN or V (–) = 1.25 V, V (+) = 0 V to 2.5 V IN IN 3 Signal-to-(Noise + Distortion) Input Bandwidth 0 kHz–90.625 kHz 86/84.5 90 dB Input Bandwidth 0 kHz–100 kHz, f = 14 MHz 84.5/83 dB CLKIN 3 Total Harmonic Distortion Input Bandwidth 0 kHz–90.625 kHz –90/–88 dB Input Bandwidth 0 kHz–100 kHz, f = 14 MHz –88/–86 dB CLKIN Spurious-Free Dynamic Range Input Bandwidth 0 kHz–90.625 kHz –90 dB Input Bandwidth 0 kHz–100 kHz, f = 14 MHz –88 dB CLKIN Unipolar Mode, UNI = V V (–) = 0 V, V (+) = 0 V to 2.5 V INL IN IN 3 Signal-to-(Noise + Distortion) Input Bandwidth 0 kHz–90.625 kHz 84.5/83 88 dB 3 Total Harmonic Distortion Input Bandwidth 0 kHz–97.65 kHz –89/–87 dB Spurious-Free Dynamic Range Input Bandwidth 0 kHz–97.65 kHz –90 dB Intermodulation Distortion –93 dB AC CMRR V (+) = V (–) = 2.5 V p-p IN IN V = 1.25 V to 3.75 V, 20 kHz 96 dB CM Digital Filter Response Pass-Band Ripple 0 kHz to 90.625 kHz ±0.005 dB Cutoff Frequency 96.92 kHz Stop-Band Attenuation 104.6875 kHz to 12.395 MHz 90 dB ANALOG INPUTS Full-Scale Input Span V (+) – V (–) IN IN Bipolar Mode UNI = V –V /2 +V /2 V INH REF2 REF2 Unipolar Mode UNI = V 0V V INL REF2 Absolute Input Voltage V (+) and V (–)0 AV V IN IN DD Input Sampling Capacitance 2pF Input Sampling Rate Guaranteed by Design 2 × f Hz CLKIN -9 Differential Input Impedance 1/(4 × 10 )f kΩ CLKIN CLOCK CLKIN Mark Space Ratio 45 55 % REFERENCE REF1 Output Voltage 2.32 2.47 2.62 V REF1 Output Voltage Drift 60 ppm/°C REF1 Output Impedance 3kΩ Reference Buffer Offset Voltage Offset between REF1 and REF2 ±12 mV Using Internal Reference REF2 Output Voltage 2.32 2.47 2.62 V REF2 Output Voltage Drift 60 ppm/°C Using External Reference −9 REF2 Input Impedance REF1 = AGND 1/(16 × 10 )f kΩ CLKIN External Reference Voltage Range Applied to REF1 or REF2 2.32 2.5 2.62 V STATIC PERFORMANCE Resolution 16 Bits Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1LSB Integral Nonlinearity ±2LSB After Calibration 4 Offset Error ±3mV 4, 5 Gain Error ±0.6 % FSR Without Calibration Offset Error ±6mV 5 Gain Error ±0.6 % FSR Offset Error Drift ±1 LSB/°C Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode ±1 LSB/°C Bipolar Mode ±0.5 LSB/°C –2– REV. B AD7722 A Version Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (Excluding CLKIN) V , Input High Voltage 2.0 V INH V , Input Low Voltage 0.8 V INL CLOCK INPUT (CLKIN) V , Input High Voltage 4.0 V INH V , Input Low Voltage 0.4 V INL ALL LOGIC INPUTS I , Input Current V = 0 V to DV ±10 µA IN IN DD C , Input Capacitance 10 pF IN LOGIC OUTPUTS V , Output High Voltage |I | = 200 µA 4.0 V OH OUT V , Output Low Voltage |I | = 1.6 mA 0.4 V OL OUT POWER SUPPLIES AV , AV 4.75 5.25 V DD DD1 DV 4.75 5.25 V DD I Total from AV and DV 75 mA DD DD DD Power Consumption 375 mW NOTES 1 Operating temperature range is –40°C to +85°C (A Version). 2 Measurement Bandwidth = 0.5 × f ; Input Level = –0.05 dB. S 3 T = 25°C to 85°C/T = T to T . A A MIN MAX 4 Applies after calibration at temperature of interest. 5 Gain error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin. Specifications subject to change without notice. REV. B –3– AD7722 1 ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE (T = 25°C, unless otherwise noted.) A Package Package DV to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V DD Model Temperature Description Option AV , AV to AGND . . . . . . . . . . . . . . . . . .–0.3 V to +7 V DD DD1 AV , AV to DVDD . . . . . . . . . . . . . . . . . . . –1 V to +1 V DD DD1 AD7722AS –40°C to +85°C 44-Lead MQFP S-44B AGND, AGND1 to DGND . . . . . . . . . . . . . –0.3 V to +0.3 V EVAL-AD7722CB Evaluation Board Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV + 0.3 V DD Digital Outputs to DGND . . . . . . . . . –0.3 V to DV + 0.3 V DD V (+), V (–) to AGND . . . . . . . . . . –0.3 V to AV + 0.3 V IN IN DD I REF1 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V OL DD 1.6mA REF2 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD TO DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . . . ±0.3 V 1.6V OUTPUT 2 Input current to any pin except the supplies . . . . . . . . ±10 mA PIN C L 50pF Operating Temperature Range . . . . . . . . . . . –40°C to +85°C I OH Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 200�A Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Figure 1. Load Circuit for Timing Specifications θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 72°C/W JA θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 20°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional opera - tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7722 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. B AD7722 (AV = 5 V � 5%, DV = 5 V � 5%, AGND = DGND = 0 V, C = 50 pF, T = T to T , DD DD L A MIN MAX f = 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High.) TIMING SPECIFICATIONS CLKIN Parameter Symbol Min Typ Max Unit CLKIN Frequency f 0.3 12.5 15 MHz CLK CLKIN Period (t = 1/f)t 0.067 0.08 3.33 µs CLK CLK 1 CLKIN Low Pulse Width t 0.45 × t 0.55 × t 2 1 1 CLKIN High Pulse Width t 0.45 × t 0.55 × t 3 1 1 CLKIN Rise Time t5ns 4 CLKIN Fall Time t5ns 5 FSI Low Time t2t 6 CLK FSI Setup Time t 20 ns 7 FSI Hold Time t 20 ns 8 CLKIN to SCO Delay t 40 ns 9 1 SCO Period t2t 10 CLK SCO Transition to FSO High Delay t 410 ns 11 SCO Transition to FSO Low Delay t 410 ns 12 SCO Transition to SDO Valid Delay t 38 ns 13 2 SCO Transition from FSI t 2.5 t 14 CLK SDO Enable Delay Time t 30 45 ns 15 SDO Disable Delay Time t 10 30 ns 16 DRDY High Time t2t 17 CLK 1 Conversion Time t 64 t 18 CLK DRDY to CS Setup Time t0ns 19 CS to RD Setup Time t0ns 20 RD Pulse Width t t + 20 ns 21 CLK 3 Data Access Time after RD Falling Edge t t + 40 ns 22 CLK Bus Relinquish Time after RD Rising Edge t t + 40 ns 23 CLK CS to RD Hold Time t0ns 24 RD to DRDY High Time t 1t 25 CLK SYNC/RESET Input Pulse Width t 10 ns 26 DVAL Low Delay from SYNC/RESET t 40 ns 27 SYNC/RESET Low Time after CLKIN Rising t 10 t – 10 ns 28 CLK DRDY High Delay after SYNC/RESET Low t 50 ns 29 1 DRDY Low Delay after SYNC/RESET Low t (8192 + 64) t 30 CLK 1 DVAL High Delay after SYNC/RESET Low t 8192 t 31 CLK CAL Setup Time t 10 ns 34 CAL Pulse Width t12 t 35 CLK Calibration Delay from CAL High t 64 t 36 CLK 1, 4 Unipolar Input Calibration Time, (UNI = 0) t (3 × 8192 + 2 × 512) t 37 CLK 1, 4 Bipolar Input Calibration Time, (UNI = 1) t (4 × 8192 + 3 × 512) t 37 CLK 1 Conversion Results Valid, (UNI = 0) t (3 × 8192 + 2 × 512 + 64) t 38 CLK 1 Conversion Results Valid, (UNI = 1) t (4 × 8192 + 3 × 512 + 64) t 38 CLK NOTES 1 Guaranteed by design. 2 Frame sync is initiated on falling edge of CLKIN. 3 With RD synchronous to CLKIN, t can be reduced up to 1 t . 22 CLK 4 See Figure 8. Specifications subject to change without notice. REV. B –5– AD7722 64 CKLIN CYCLES CLKIN SCO (CFMT = 0) 32 SCO CYCLES FSO (SFMT = 0) SCO VALID VALID DATA FOR 16 SCO CYCLES ZERO FOR LAST 16 SCO CYCLES Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) 64 CKLIN CYCLES CLKIN SCO (CFMT = 0) 32 SCO CYCLES FSO LOW FOR 16 SCO CYCLES HIGH FOR LAST 16 SCO CYCLES (SFMT = 1) SCO ZERO FOR LAST 16 SCO CYCLES VALID DATA FOR 16 SCO CYCLES VALID Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) t t 5 4 t 2 2.3V CLKIN 0.8V t 3 t t 1 8 t 6 FSI t t 7 9 SCO t 9 t 10 Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output CLKIN t 1 FSI t 10 SCO t t 11 12 SFMT = LOGIC FSO LOW(0) t 14 D15 D14 D13 D1 D0 SDO t 13 SCO t t 12 11 LOW FOR SFMT = LOGIC FSO D15–D0 HIGH(1) t 13 D15 D14 D13 D1 D0 SDO Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (CFMT = Logic Low, TSI = DOE) –6– REV. B AD7722 DOE t t 15 16 SDO Figure 5. Serial Mode Timing for Data Output Enable and Serial Data Output (TSI = Logic Low) t t 17 18 DRDY t 19 t 25 CS t t 20 24 t 21 RD t t 23 22 DB0–DB15 VALID DATA Figure 6. Parallel Mode Read Timing t 30 CLKIN t MIN 28 t MAX 28 t 31 SYNC, RESET t 26 t 27 DVAL t 29 DRDY Figure 7. SYNC and RESET Timing, Serial and Parallel Mode t 36 CLKIN t 34 SYNC, RESET t 35 t UNI = 1 37 t UNI = 0 37 8192 t 8192 t 8192 t 8192 t CLK CLK CLK CLK DVAL 512 t 512 t 512 t CLK CLK CLK t 38 DRDY Figure 8. Calibration Timing, Serial and Parallel Mode REV. B –7– AD7722 PIN FUNCTION DESCRIPTIONS Mnemonic Pin No. Description AV 14 Clock Logic Power Supply Voltage for the Analog Modulator, 5 V ± 5%. DD1 AGND1 10 Clock Logic Ground Reference for the Analog Modulator. AV 20, 23 Analog Power Supply Voltage, 5 V ± 5%. DD AGND 9, 13, 15, 19, Ground Reference for Analog Circuitry. 21, 25, 26 DV 39 Digital Power Supply Voltage, 5 V ± 5%. DD DGND 6, 28 Ground Reference for Digital Circuitry. REF1 22 Reference Input/Output. REF1 connects through 3 kΩ to the output of the internal 2.5 V reference and to the input of a buffer amplifier that drives the Σ-∆ modulator. This pin can also be overdriven with an external reference 2.5 V. REF2 24 Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to drive the Σ-∆ modulator. When REF2 is used as an input, REF1 must be connected to AGND. V (+) 18 Positive Terminal of the Differential Analog Input. IN V (–)16Negative Terminal of the Differential Analog Input. IN UNI 7Analog Input Range Select Input. UNI selects the analog input range for either bipolar or unipolar operation. A logic low input selects unipolar operation. A logic high input selects bipolar operation. CLKIN 11 Clock Input. Master clock signal for the device. The CLKIN pin interfaces the AD7722 internal oscillator circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency, microprocessor-grade crystal and a 1 MΩ resistor should be connected between the CLKIN and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the CLKIN pin can be driven with an external CMOS compatible clock. The AD7722 is specified with a clock input frequency of 12.5 MHz. XTAL 12 Oscillator Output. The XTAL pin connects the internal oscillator output to an external crystal. If an external clock is used, XTAL should be left unconnected. P/S 8 Parallel/Serial Interface Select Input. A logic high configures the output data interface for parallel mode operation. The serial mode operation is selected with the P/S set to a logic low. CAL 27 Calibration Logic Input. A logic high input for a duration of one CLKIN cycle initiates a calibration sequence for the device gain and offset error. RESET 17 Reset Logic Input. RESET is used to clear the offset and gain calibration registers. RESET is an asynchronous input. RESET allows the user to set the AD7722 to an uncalibrated state if the device had been previously calibrated. A rising edge also resets the AD7722 Σ-∆ modulator by shorting the integrator capacitors in the modulator. In addition, RESET functions identically to the SYNC pin described below. When operating with more than one AD7722, a RESET/SYNC should be issued following power up to ensure the devices are synchronized. Ensure that the supplies are settled before applying the RESET/SYNC pulse. CS 29 Chip select is a level sensitive logic input. CS enables the output data register for parallel mode read operation. The CS logic level is sensed on the rising edge of CLKIN. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on CS if RD is also low. When CS is sensed high, the output data bits DB15–DB0 will be high impedance. In serial mode, tie CS to a logic low. SYNC 30 Synchronization Logic Input. SYNC is an asynchronous input. When using more than one AD7722 operated from a common master clock, SYNC allows each ADC’s Σ-∆ modulator to simultaneously sample its analog input and update its output data register. A rising edge resets the AD7722 digital filter sequencer counter to zero. After a SYNC, conversion data is not valid until after the digital filter settles (see Figure 7). DVAL goes low in the serial mode. When the rising edge of CLKIN senses a logic low on SYNC (or RESET), the reset state is released; in parallel mode, DRDY goes high. After the reset state is released, DVAL returns high after 8192 CLKIN cycles (128 × 64/f ); in parallel mode, DRDY returns low after one additional convolution cycle CLKIN of the digital filter (64 CLKIN periods), when valid data is ready to be read from the output data register. When operating with more than one AD7722, a RESET/SYNC should be issued follow- ing power up to ensure the devices are synchronized. Ensure that the supplies are settled before applying the RESET/SYNC pulse. –8– REV. B AD7722 PIN CONFIGURATION 44-Lead MQFP (S-44B) 44 43 42 41 40 39 38 37 36 35 34 DGND/DB2 1 33 DGND/DB13 PIN 1 IDENTIFIER DGND/DB1 2 32 DGND/DB14 DGND/DB0 3 31 DGND/DB15 CFMT/DRDY 4 SYNC 30 CS DVAL/RD 5 29 AD7722 DGND 6 DGND TOP VIEW 28 (Not to Scale) UNI 7 27 CAL AGND P/S 8 26 AGND 9 25 AGND AGND1 10 24 REF2 AV CLKIN 11 23 DD 12 13 14 15 16 17 18 19 20 21 22 PARALLEL MODE PIN FUNCTION DESCRIPTIONS Mnemonic Pin No. Description DVAL/RD 5 Read input is a level sensitive logic input. The RD logic level is sensed on the rising edge of CLKIN. This digital input can be used in conjunction with CS to read data from the device. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output data bits DB15–DB0 will be high impedance. CFMT/DRDY4Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data register. DRDY will return high upon completion of a read operation. If a read operation does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next output update. DRDY also indicates when conversion results are available after a SYNC or RESET sequence and when completing a self-calibration. DGND/DB15 31 Data Output Bit (MSB). DGND/DB14 32 Data Output Bit. DGND/DB13 33 Data Output Bit. DGND/DB12 34 Data Output Bit. DGND/DB11 35 Data Output Bit. DGND/DB10 36 Data Output Bit. FSO/DB9 37 Data Output Bit. SDO/DB8 38 Data Output Bit. SCO/DB7 40 Data Output Bit. FSI/DB6 41 Data Output Bit. SFMT/DB5 42 Data Output Bit. DOE/DB4 43 Data Output Bit. TSI/DB3 44 Data Output Bit. DGND/DB2 1 Data Output Bit. DGND/DB1 2 Data Output Bit. DGND/DB0 3 Data Output Bit (LSB). REV. B –9– XTAL TSI/DB3 AGND DOE/DB4 AV SFMT/DB5 DD1 AGND FSI/DB6 V (–) IN SCO/DB7 RESET DV DD V (+) SDO/DB8 IN FSO/DB9 AGND AV DGND/DB10 DD DGND/DB11 AGND DGND/DB12 REF1 AD7722 SERIAL MODE PIN FUNCTION DESCRIPTIONS Mnemonic Pin No. Description DVAL/RD 5Data Valid Logic Output. A logic high on DVAL indicates that the conversion result in the output data register is an accurate digital representation of the analog voltage at the input to the �-� modu- lator. The DVAL pin is set low for 8,192 CLKIN cycles if the analog input is overranged and after initiating CAL, SYNC, or RESET. CFMT/DRDY 4 Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, SDO is valid on the falling edge of SCO if SFMT is low; SDO is valid on the rising edge of SCO if SFMT is high. When CFMT is logic high, SDO is valid on the rising edge of SCO if SFMT is low; SDO is valid on the falling edge of SCO if SFMT is high. TSI/DB3 44 Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is used when two AD7722s are connected to the same serial data bus. When using a single ADC, connect TSI to DGND. DOE/DB4 43 Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin, the serial data output, SDO, is active. Otherwise, SDO will be high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO. This input is useful when two AD7722s are connected to the same serial data bus. When using a single ADC, to ensure SDO is active, connect DOE to DGND so that it equals the logic level of TSI. SFMT/DB5 42 Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal. A logic low makes the FSO output a pulse one SCO cycle wide occurring every 32 SCO cycles. With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16 data bit transmission. FSI/DB6 41 Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7722 serial output data register to an external source. When the falling edge of CLKIN detects a low-to-high transition, the AD7722 interrupts the current data transmission, reloads the output serial shift register, resets SCO, and transmits the conversion result. Synchronization starts immediately, and the next 127 conversions are invalid. In serial mode, DVAL remains high. FSI inputs applied synchronous to the output data rate do not alter the serial data transmission. If FSI is tied to either a logic high or low, the AD7722 will generate FSO outputs controlled by the logic level on SFMT. SCO/DB7 40 Serial Data Clock Output. The serial clock output is synchronous to the CLKIN signal and has a frequency one-half the CLKIN frequency. A data transmission frame is 32 SCO cycles long. SDO/DB8 38 Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. A serial data transmission lasts 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles. FSO/DB9 37 Frame Sync Output. This output indicates the beginning of a word transmission on the SDO pin. Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse, which is active low for the duration of the 16 data bit trans- mission (see Figure 4). DGND/DB0 3 In serial mode, these pins should be tied to DGND. DGND/DB1 2 DGND/DB2 1 DGND/DB10 36 DGND/DB11 35 DGND/DB12 34 DGND/DB13 33 DGND/DB14 32 DGND/DB15 31 –10– REV. B AD7722 TERMINOLOGY Pass-Band Ripple Signal-to-Noise Plus Distortion Ratio (S/(N+D)) The frequency response variation of the AD7722 in the defined S/(N+D) is the measured signal-to-noise plus distortion ratio pass-band frequency range. at the output of the ADC. The signal is the rms magnitude of Pass-Band Frequency the fundamental. Noise plus distortion is the rms sum of all The frequency up to which the frequency response variation is nonfundamental signals and harmonics to half the sampling rate within the pass-band ripple specification. (f /128), excluding dc. The ADC is evaluated by applying a CLKIN Cutoff Frequency low noise, low distortion sine wave signal to the input pins. By The frequency below which the AD7722’s frequency response generating a fast Fourier transform (FFT) plot, the S/(N+D) data will not have more than 3 dB of attenuation. can then be obtained from the output spectrum. Stop-Band Frequency Total Harmonic Distortion (THD) The frequency above which the AD7722’s frequency response THD is the ratio of the rms sum of the harmonics to the rms will be within its stop-band attenuation. value of the fundamental. THD is defined as Stop-Band Attenuation 2 2 2 2 2   SQRT V +V +V +V +V 2 3 4 5 6 The AD7722’s frequency response will not have less than 90 dB ()   THD = 20 log of attenuation in the stated frequency band.   V 1     Integral Nonlinearity where V is the rms amplitude of the fundamental, and V , V , This is the maximum deviation of any code from a straight line 1 2 3 V , V , and V are the rms amplitudes of the second through passing through the endpoints of the transfer function. The 4 5 6 sixth harmonics. The THD is also derived from the FFT plot of endpoints of the transfer function are minus full scale, a point the ADC output spectrum. 0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) Spurious-Free Dynamic Range (SFDR) and plus full scale, a point 0.5 LSB above the last code transition Defined as the difference in dB between the peak spurious or har- (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to monic component in the ADC output spectrum (up to f /128 CLKIN 111 . . . 11 in unipolar mode). The error is expressed in LSB. and excluding dc) and the rms value of the fundamental. Normally, the value of this specification will be determined by the largest Differential Nonlinearity harmonic in the output spectrum of the FFT. For input signals This is the difference between the measured and the ideal 1 LSB whose second harmonics occur in the stop-band region of the change between two adjacent codes in the ADC. digital filter, a spur in the noise floor limits the SFDR. Common-Mode Rejection Ratio Intermodulation Distortion The ability of a device to reject the effect of a voltage applied to With inputs consisting of sine waves at two frequencies, fa and both input terminals simultaneously—often through variation of fb, any active device with nonlinearities will create distortion a ground level—is specified as a common-mode rejection ratio. products at sum and difference frequencies of mfa ± nfb, where CMRR is the ratio of gain for the differential signal to the gain m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are for the common-mode signal. those for which neither m nor n is equal to zero. For example, the Unipolar Offset Error second order terms include (fa + fb) and (fa – fb), while the third Unipolar offset error is the deviation of the first code transition order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). (00 . . . 000 to 00 . . . 001) from the ideal differential voltage Testing is performed using the CCIF standard, where two input (V (+) – V (–) + 0.5 LSB) when operating in the unipolar mode. IN IN frequencies near the top end of the input bandwidth are used. Bipolar Offset Error In this case, the second order terms are usually distanced in This is the deviation of the midscale transition code frequency from the original sine waves, while the third order (111 . . . 11 to 000 . . . 00) from the ideal differential voltage terms are usually at a frequency close to the input frequencies. (V (+) – V (–) – 0.5 LSB) when operating in the bipolar mode. IN IN As a result, the second and third order terms are specified Gain Error separately. The calculation of the intermodulation distortion is The first code transition should occur at an analog value 1/2 LSB as per the THD specification, where it is the ratio of the rms above – full scale. The last transition should occur for an analog sum of the individual distortion products to the rms amplitude value 1 1/2 LSB below the nominal full scale. Gain error is the of the sum of the fundamental, expressed in dB. deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. REV. B –11– AD7722–Typical Performance Characteristics (AV = DV = 5.0 V, T = 25�C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; V (+) = 0 V to 2.5 V, V (–) = 1.25 V, unless otherwise noted.) DD DD A IN IN 110 –85 84 85 100 –90 AIN = 1/5 � BW SNR 86 –95 90 87 SFDR 80 –100 88 S/(N+D) 89 70 –105 SFDR 90 60 –110 THD 91 50 –115 92 –40 –30 –20 –10 0 020 40 60 80 100 050 300 100 150 200 250 INPUT LEVEL (dB) INPUT FREQUENCY (kHz) OUTPUT DATA RATE (kSPS) TPC 1. S/(N+D) and SFDR vs. TPC 2. S/(N+D) vs. Output TPC 3. SNR, THD, and SFDR Analog Input Level Sample Rate vs. Input Frequency –85 84 92.0 85 91.5 –90 AIN = 1/5 � BW SNR 91.0 86 V (+) = V (–) = 1.25V p-p IN IN V (+) = V (–) = 1.25V p-p IN IN –95 V = 2.5V CM V = 2.5V CM 90.5 87 THD 90.0 –100 88 89 89.5 –105 90 89.0 SFDR –110 91 88.5 92 –115 88.0 020 40 60 80 100 050 100 150 200 250 300 –50 0 50 100 OUTPUT DATA RATE (kSPS) INPUT FREQUENCY (kHz) TEMPERATURE (�C) TPC 4. SNR, THD, and SFDR TPC 5. S/(N+D) vs. Output TPC 6. SNR vs. Temperature vs. Input Frequency Sample Rate 1.0 –94 5000 0.8 –96 4500 THD V (+) = V (–) IN IN –98 0.6 4000 CLKIN = 12.5MHz –100 0.4 3500 8k SAMPLES –102 0.2 3000 3RD –104 0 2500 –106 4TH –0.2 2000 –108 –0.4 1500 –110 –0.6 1000 –112 –0.8 500 –114 2ND –1.0 –116 0 0 20000 40000 65535 –50 –25 025 50 75 100 n–3 n–2 n–1 n n+1 n+2 n+3 CODE TEMPERATURE (�C) CODES TPC 7. THD vs. Temperature TPC 8. Histogram of Output TPC 9. Differential Nonlinearity Codes with DC Input –12– REV. B dB dB dB FREQUENCY OF OCCURRENCE dB dB DNL ERROR (LSB) dB dB AD7722 200 1.0 180 0.8 AI DD 160 0.6 140 0.4 120 0.2 DI DD 100 0 80 –0.2 60 –0.4 40 –0.6 20 –0.8 0 –1.0 0 2.5 5.0 7.5 10.0 12.5 15.0 0 20000 40000 65535 CODE CLKIN FREQUENCY (MHz) TPC 10. Integral Nonlinearity Error TPC 13. Power Consumption vs. CLKIN Frequency 0 0 AIN = 90kHz CLKIN = 12.5MHz –20 –20 XTAL = 12.288MHz SNR = 90.1dB SNR = 88.1dB S/(N+D) = 89.2dB –40 –40 S/(N+D) = 88.1dB SFDR = –99.5dB SFDR = –103.7dB THD = –96.6dB –60 –60 2ND = –100.9dB 3RD = –106.0dB –80 –80 4TH = –99.5dB –100 –100 –120 –120 –140 –140 –154 –154 98 010 20 30 40 50 60 70 80 020 40 60 80 96 FREQUENCY (kHz) FREQUENCY (kHz) TPC 11. 16K Point FFT TPC 14. 16K Point FFT 0 0 AIN = 90kHz XTAL = 12.288MHz –20 –20 CLKIN = 12.5 MHz SNR = 89.0dB SNR = 89.6dB S/(N+D) = 87.8dB –40 –40 S/(N+D) = 89.6dB SFDR = –94.3dB SFDR = –108.0dB THD = –93.8dB –60 –60 2ND = –94.3dB 3RD = –108.5dB –80 –80 4TH = –105.7dB –100 –100 –120 –120 –140 –140 –154 –154 020 40 6080 96 020 40 60 80 98 FREQUENCY (kHz) FREQUENCY (kHz) TPC 12. 16K Point FFT TPC 15. 16K Point FFT REV. B –13– dB dB INL ERROR (LSB) dB dB POWER (mW) AD7722 CIRCUIT DESCRIPTION The AD7722 employs two finite impulse response (FIR) filters in The AD7722 ADC employs a Σ-∆ conversion technique that series. The first filter is a 384-tap filter that samples the output of converts the analog input into a digital pulse train. The analog the modulator at f . The second filter is a 151-tap half-band CLKIN input is continuously sampled by a switched capacitor modulator filter that samples the output of the first filter at f /32 and CLKIN at twice the rate of the clock input frequency, 2 × f . The decimates by 2. The implementation of this filter architecture CLKIN digital data that represents the analog input is in the ones density results in a filter with a group delay of 42 conversions (84 conver- of the bit stream at the output of the Σ-∆ modulator. The modu- sions for settling to a full-scale step). lator outputs a bit stream at a data rate equal to f . CLKIN The digital filter provides 6 dB of attenuation at a frequency Due to the high oversampling rate, which spreads the quantization (f /128) one-half its output rate. With a clock frequency CLKIN noise from 0 to f /2, the noise energy contained in the band of 12.5 MHz, the digital filter has a pass-band frequency of CLKIN of interest is reduced (Figure 9a). To reduce the quantization 90.625 kHz, a cutoff frequency is 96.92 kHz, and a stop-band noise further, a high order modulator is employed to shape the frequency of 104.6875 kHz. noise spectrum so that most of the noise energy is shifted out of Due to the sampling nature of the digital filter, the filter does not the band of interest (Figure 9b). provide any rejection at integer multiples of its input sampling The digital filter that follows the modulator provides three main frequency. The filter response in Figure 10a shows the unattenu- functions. The filter performs sophisticated averaging on the ated frequency bands occurring at n × f where n = 1, 2, 3. . . . CLKIN 1-bit samples from the output of the modulator, while removing At these frequencies, there are frequency bands ± f wide 3 dB the large out of band quantization noise (Figure 9c). Lastly, the (f is the –3 dB bandwidth of the digital filter) on either side 3 dB digital filter reduces the data rate from f at the input of the of n × f where noise passes unattenuated to the output. CLKIN CLKIN filter to f /64 at the output of the filter. The AD7722 output Out-of-band signals coincident with any of the filter images are CLKIN data rate, f , is a little over twice the signal bandwidth, which aliased into the pass band. However, due to the AD7722’s high S guarantees that there is no loss of data in the signal band. oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is filtered. This means Digital filtering has certain advantages over analog filtering. First, that the antialias filtering requirements in front of the AD7722 since digital filtering occurs after the A/D conversion, it can are considerably reduced versus a conventional converter with no remove noise injected during the conversion process. Analog on-chip filtering. Figure 10b shows the frequency response of an filtering cannot remove noise injected during conversion. Second, antialias filter. With a –3 dB corner frequency set at f /64, CLKIN the digital filter combines low pass-band ripple with a steep roll-off a single-pole filter will provide 36 dB of attenuation at f . CLKIN while also maintaining a linear phase response. Depending on the application, however, it may be necessary to provide additional antialias filtering prior to the AD7722 to eliminate unwanted signals from the frequency bands the digital QUANTIZATION NOISE filter passes. It may also be necessary in some applications to f /2 provide analog filtering in front of the AD7722 to ensure that CLKIN BAND OF INTEREST a. differential noise signals outside the band of interest do not saturate the analog modulator. NOISE SHAPING 0dB f /2 CLKIN 1f 2f 3f BAND OF INTEREST CLKIN CLKIN CLKIN b. Figure 10a. Digital Filter Frequency Response OUTPUT DIGITAL FILTER CUTOFF FREQUENCY DATA RATE WHICH EQUALS 97.65kHz (12.5MHz) ANTIALIAS FILTER RESPONSE REQUIRED 0dB f /2 CLKIN ATTENUATION BAND OF INTEREST c. f /64 f CLKIN CLKIN Figure 9. Σ-∆ ADC Figure 10b. Frequency Response of Antialias Filter –14– REV. B AD7722 APPLYING THE AD7722 Differential Inputs Analog Input Range The analog input to the modulator is a switched capacitor design. The AD7722 uses differential inputs to provide common-mode The analog signal is converted into charge by highly linear noise rejection (i.e., the converted result will correspond to the sampling capacitors. A simplified equivalent circuit diagram of differential voltage between the two inputs). The absolute voltage the analog input is shown in Figure 13. A signal source driving on both inputs must lie between AGND and AV . the analog input must be able to provide the charge onto the DD sampling capacitors every half CLKIN cycle and settle to the In unipolar mode, the full-scale analog input range required accuracy within the next half cycle. (V (+) – V (–)) is 0 V to V . The output code is straight IN IN REF2 binary in the unipolar mode with 1 LSB = 38 µV. The ideal transfer function is shown in Figure 11. AD7722 Φ A In bipolar mode, the full-scale input range is ±V /2. The 500� REF2 V (+) 18 2pF IN Φ bipolar mode allows complementary input signals. As another B example, in bipolar mode, V (–) can be connected to a dc bias IN 2pF Φ A voltage to allow a single-ended input on V (+) equal to V IN BIAS 500� V (–) 16 ±V /2. In bipolar mode, the output code is twos complement IN REF2 Φ AC B GROUND with 1 LSB = 38 µV. The ideal transfer function is shown in Φ Φ Φ Φ Figure 12. CLKIN A B A B OUTPUT CODE Figure 13. Analog Input Equivalent Circuit 111...111 Since the AD7722 samples the differential voltage across its 111...110 analog inputs, low noise performance is attained with an input 111...101 circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role 111...100 in attaining the high performance available from the AD7722. When a capacitive load is switched onto the output of an op amp, the amplitude will momentarily drop. The op amp will try to 000...011 correct the situation and, in the process, will hit its slew rate limit. 000...010 This nonlinear response, which can cause excessive ringing, can 000...001 lead to distortion. To remedy the situation, a low-pass RC filter 000...000 can be connected between the amplifier and the input to the AD7722 as shown in Figure 14. The external capacitor at each V –1LSB 0V REF2 DIFFERENTIAL INPUT VOLTAGE V (+) – V (–) IN IN input aids in supplying the current spikes created during the sampling process. The resistor in this diagram, as well as creating Figure 11. Unipolar Mode Transfer Function the pole for the antialiasing, isolates the op amp from the transient nature of the load. OUTPUT CODE 011...111 R 011...110 V (+) IN C ANALOG AD7722 INPUT 000...010 R 000...001 V (–) IN –V REF2 000...000 C +V /2 – 1LSB REF2 111...111 111...110 Figure 14. Simple RC Antialiasing Circuit The differential input impedance of the AD7722 switched capacitor 100...001 input varies as a function of the CLKIN frequency, given by the 100...000 equation 0V DIFFERENTIAL INPUT VOLTAGE V (+) – V (–) 9 IN IN 10 Z = kΩ IN 4 × f CLKIN Figure 12. Bipolar Mode Transfer Function REV. B –15– AD7722 Even though the voltage on the input sampling capacitors may not required to bias external circuits, use an external precision op have enough time to settle to the accuracy indicated by the resolu- amp to buffer REF1. tion of the AD7722, as long as the sampling capacitor charging follows the exponential curve of RC circuits, only the gain COMPARATOR accuracy suffers if the input capacitor is switched away too early. 1V AD7722 An alternative circuit configuration for driving the differential REFERENCE BUFFER inputs to the AD7722 is shown in Figure 15. REF1 SWITCHED-CAP 22 DAC REF 100nF C R 3k� 2.7nF 100� 2.5V V (+) REFERENCE IN 24 REF2 C AD7722 2.7nF R 100� V (–) IN Figure 16. Reference Circuit Block Diagram C 2.7nF The AD7722 can operate with its internal reference, or an external reference can be applied in two ways. An external Figure 15. Differential Input with Antialiasing reference can be connected to REF1, overdriving the internal A capacitor between the two input pins sources or sinks charge reference. However, there will be an error introduced due to the to allow most of the charge that is needed by one input to be offset of the internal buffer amplifier. For the lowest system gain effectively supplied by the other input. This minimizes undesir- errors when using an external reference, REF1 is grounded able charge transfer from the analog inputs to and from ground. (disabling the internal buffer) and the external reference is The series resistor isolates the operational amplifier from the connected to REF2. current spikes created during the sampling process and provides In all cases, since the REF2 voltage connects to the analog a pole for antialiasing. The –3 dB cutoff frequency (f ) of the 3 dB modulator, a 100 nF capacitor must connect directly from antialias filter is given by Equation 1, and the attenuation of the REF2 to AGND. The external capacitor provides the charge filter is given by Equation 2. required for the dynamic load presented at the REF2 pin 1 (Figure 17). f = 3 dB (1) 6 � RC  2  AD7722 Φ   A f   Attenuation=+ 20 log 1/ 1 Φ   B (2)   f 4pF   3 dB REF2   24 100nF 4pF The choice of the filter cutoff frequency will depend on the Φ A Φ B amount of roll-off that is acceptable in the pass band of the digital filter and the required attenuation at the first image SWITCHED-CAP DAC REF frequency. For example, when operating the AD7722 with a 12.5 MHz clock, with the typical values of R and C of 100 Ω and CLKIN Φ Φ Φ Φ A B A B 2.7 nF shown in Figure 15, the –3 dB cutoff frequency (f ) 3 dB creates less than 1 dB of in-band (90.625 kHz) roll-off and Figure 17. REF2 Equivalent Input Circuit provides about 36 dB attenuation at the first image frequency. The AD780 is ideal to use as an external reference with the The capacitors used for the input antialiasing circuit must have AD7722. Figure 18 shows a suggested connection diagram. low dielectric absorption to avoid distortion. Film capacitors such as polypropylene, polystyrene, or polycarbonate are suitable. If O/P ceramic capacitors are used, they must have NP0 dielectric. 1 NC 8 5V SELECT 24 REF2 2 +V NC 7 IN Applying the Reference 100nF AD7722 1�F 3 TEMP V 6 The reference circuitry used in the AD7722 includes an on-chip OUT 22 REF1 22nF 22�F 4 GND TRIM 5 2.5 V band gap reference and a reference buffer circuit. The block diagram of the reference circuit is shown in Figure 16. The inter- AD780 nal reference voltage is connected to REF1 through a 3 kΩ resistor Figure 18. External Reference Circuit Connection and is internally buffered to drive the analog modulator’s switched cap DAC (REF2). When using the internal reference, connect 100 nF between REF1 and AGND. If the internal reference is –16– REV. B AD7722 Input Circuits The 1 nF capacitors at each ADC input store charge to aid the Figures 19 and 20 show two simple circuits for bipolar mode amplifier settling as the input is continuously sampled. A resistor operation. Both circuits accept a single-ended bipolar signal in series with the drive amplifier output and the 1 nF input source and create the necessary differential signals at the input capacitor may also be used to create an antialias filter. to the ADC. Clock Generation The circuit in Figure 19 creates a 0 V to 2.5 V signal at the The AD7722 contains an oscillator circuit to allow a crystal or V (+) pin to form a differential signal around an initial bias of an external clock signal to generate the master clock for the ADC. IN 1.25 V. For single-ended applications, best THD performance The connection diagram for use with the crystal is shown in is obtained with V (–) set to 1.25 V rather than 2.5 V. The Figure 21. Consult the crystal manufacturer’s recommendation IN input to the AD7722 can also be driven differentially with a for the load capacitors. complementary input, as shown in Figure 20. In this case, the input common-mode voltage is set to 2.5 V. AD7722 The 2.5 V p-p full-scale differential input is obtained with a XTAL CLKIN 1.25 V p-p signal at each input in antiphase. This configuration minimizes the required output swing from the amplifier circuit 1M� and is useful for single-supply applications. 12pF 1k� 1k� AIN = Figure 21. Crystal Oscillator Connection �1.25V An external clock must be free of ringing and have a minimum 1/2 18 V (+) rise time of 5 ns. Degradation in performance can result as high IN OP275 1nF edge rates increase coupling that can generate noise in the 1k� sampling process. The connection diagram for an external clock 16 V (–) IN source (Figure 22) shows a series damping resistor connected 1nF DIFFERENTIAL 12pF between the clock output and the clock input to the AD7722. INPUT = 2.5V p-p The optimum resistor will depend on the board layout and the V (–) BIAS 1k� IN VOLTAGE = 1.25V impedance of the trace connecting to the clock input. 22 REF1 1k� 100nF 1/2 374k� AD7722 OP275 25�–150� CLOCK AD7722 CLKIN CIRCUITRY 10nF 374k� 24 REF2 100nF Figure 22. External Clock Oscillator Connection A low phase noise clock should be used to generate the ADC Figure 19. Single-Ended Analog Input Circuit for sampling clock because sampling clock jitter effectively modulates Bipolar Mode Operation the input signal and raises the noise floor. The sampling clock generator should be isolated from noisy digital circuits, grounded, 12pF and heavily decoupled to the analog ground plane. 1k� 1k� AIN = The sampling clock generator should be referenced to the analog �0.625V ground plane in a split-ground system. However, this is not always possible because of system constraints. In many cases, 1/2 16 V (–) IN OP275 the sampling clock must be derived from a higher frequency 1nF 12pF multipurpose system clock that is generated on the digital ground DIFFERENTIAL 1k� plane. If the clock signal is passed between its origin on a digital INPUT = 2.5V p-p 1k� COMMON-MODE ground plane to the AD7722 on the analog ground plane, the VOLTAGE = 2.5V ground noise between the two planes adds directly to the clock 1/2 and will produce excess jitter. The jitter can cause degradation in the 18 V (+) IN OP275 signal-to-noise ratio and can also produce unwanted harmonics. 1nF AD7722 R This can be remedied somewhat by transmitting the sampling 22 REF1 clock signal as a differential one, using either a small RF trans- R 100nF OP07 former or a high speed differential driver and receiver, such as the PECL. In either case, the original master system clock 24 REF2 should be generated from a low phase noise crystal oscillator. 100nF Figure 20. Single-Ended-to-Differential Analog Input Circuit for Bipolar Mode Operation REV. B –17– AD7722 Varying the Master Clock DVAL Although the AD7722 is specified with a master clock of 12.5 MHz, The DVAL pin, when used in the serial mode, indicates if invalid the AD7722 operates with clock frequencies up to 15 MHz and data may be present at the ADC output. There are four events that as low as 300 kHz. The input sample rate, output word rate, and can cause DVAL to be deasserted, and they have different impli- frequency response of the digital filter are directly proportional cations for how long the results should be considered invalid. to the master clock frequency. For example, reducing the clock DVAL is set low if there is an overflow condition in the first stage frequency to 5 MHz leads to an analog input sample rate of of the digital filter. The overflow can result from an analog input 10 MHz, an output word rate of 78.125 kSPS, a pass-band signal nearly twice the allowable maximum input span. When an frequency of 36.25 kHz, a cutoff frequency of 38.77 kHz, and a overflow condition is detected, DVAL is set low for 64 CLKIN stop-band frequency of 41.875 kHz. cycles (one output period) and the output data is clipped to either positive or negative full scale depending on the sign of the SYSTEM SYNCHRONIZATION AND CONTROL overflow. After the next convolution is completed (64 CLKIN The AD7722 digital filter contains a sequencer block that cycles), if the overflow condition does not exist, DVAL goes controls the digital interface and all the control logic needed to high to indicate that a valid output is available. Otherwise, DVAL operate the digital filter. A 14-bit cycle counter keeps track of will remain low until the overflow condition is eliminated. where the filters are in their overall operating cycle and decodes The second stage digital filter can overflow as a result of overflow the digital interface signals to the AD7722. The cycle counter from the first stage. The overflow condition is detected when has a number of important transition points. In particular, the the second stage filter calculates a conversion result that exceeds bottom six bits control the convolution counter that decimates either plus or minus full scale (i.e., below –32,768 or above by 64 to the update rate of the output data register. The counter’s 32,767 in bipolar mode). When the overflow is detected, DVAL top bit is used to provide ample time (8192 CLKIN cycles) to is set low and the output register is updated with either positive allow the modulator and digital filter to settle as the AD7722 or negative full scale, depending on the sign of the overload. sequences through its autocalibration process. The counter After the next convolution is completed, DVAL returns high increments on the rising edge of the signal at the CLKIN pin and if the next conversion result is within the full-scale range. all of the digital I/O signals are synchronous with this clock. The upper bit of this counter also controls when DVAL or DRDY As with all high order Σ-∆ modulators, large overloads on the indicates that valid data is available in the output data register analog input can cause the modulator to go unstable. The after a SYNC, RESET, CAL, or initial FSI. During normal modulator is designed to be stable with input signals as high as operation, the delay of 128 conversions (8192 CLKIN cycles) twice full scale within the input bandwidth. Out-of-band signals should not be confused with the actual settling time (5376 as high as the full-scale range will not cause instability. When CLKIN cycles) and group delay (2688 CLKIN cycles) of the instability is detected by internal circuits, DVAL is set low and digital filter. the output is clipped to either positive or negative full scale depending on the polarity of the overload. The modulator is SYNC Input reset to a stable state, and the digital filter sequencer counter is The SYNC input provides a synchronization function for use in reset. DVAL is set low for a minimum of 8192 CLKIN cycles parallel or serial mode. SYNC allows the user to start gathering while the modulator settles out, and the digital filter accumu- samples of the analog input from a known point in time. This lates new samples. DVAL returns high to indicate that valid allows a system using multiple AD7722s, operated from a common data is available from the serial output register 8192 CLKIN master clock, to be synchronized so that each ADC updates its cycles after the overload condition is removed. output register simultaneously. The SYNC input resets the digital filter without affecting the contents of the calibration registers. Lastly, DVAL also indicates when valid data is available at the serial interface after initial power-up or upon completion of a In a system using multiple AD7722s, a common signal to their CAL, RESET, or SYNC sequence. sync input will synchronize their operation. On the rising edge of SYNC, the digital filter sequencer counter is reset to zero. Reset Input The filter is held in a reset state until a rising edge on CLKIN The AD7722 RESET input controls the digital filter the same senses SYNC low. A SYNC pulse, one CLKIN cycle long, can as the SYNC input described previously. Additionally, it resets be applied synchronous to the falling edge of CLKIN. This way, the modulator by shorting its integrator capacitors and clears on the next rising edge of CLKIN, SYNC is sensed low, the the on-chip calibration registers so that the conversion results filter is taken out of its reset state, and multiple parts start to are not corrected for offset or gain error. gather input samples. Power-On Reset In serial mode, DVAL remains low for 8192 CLKIN cycles to A power-on reset function is provided to reset the AD7722 allow the modulator and digital filter to settle. In parallel mode, internal logic after initial power-up. On power-up, the offset and DRDY remains high for an additional 64 CLKIN cycles when gain calibration registers are cleared. valid data is loaded into the output register. After a SYNC, conver- sion data is not valid until the digital filter settles (see Figure 7). –18– REV. B AD7722 Offset and Gain Calibration initiating a calibration routine, ensure that the supplies and A calibration of offset and gain errors can be performed in both reference input have settled, and that the voltage on the analog serial and parallel modes by initiating a calibration cycle. During input pins is between the supply voltages. this cycle, offset and gain registers in the filter are loaded with values representing the dc offset of the analog modulator and a DATA INTERFACING modulator gain correction factor. The correction factors are The AD7722 offers a choice of serial or parallel data interface determined by an on-chip microcontroller measuring the conver- options to meet the requirements of a variety of system configu- sion results for three different input conditions: minus full scale rations. In parallel mode, multiple AD7722s can be easily (–FS), plus full scale (+FS), and midscale. In normal operation, configured to share a common data bus. Serial mode is ideal the offset register is subtracted from the digital filter output and when it is required to minimize the number of data interface the result is multiplied by the gain correction factor to obtain an lines connected to a host processor. In either case, careful offset and gain corrected final result. attention to the system configuration is required to realize the high dynamic range available with the AD7722. Consult the The calibration cycle is controlled by internal logic, and the user recommendations in the Power Supply Grounding and Layout need only initiate the cycle. A calibration is initiated when the section. The following recommendations for parallel interfacing rising edge of CLKIN senses a high level on the CAL input. also apply for the system design in serial mode. There is an uncertainty of up to 64 CLKIN cycles before the calibration cycle actually begins because the current conversion Parallel Interface must complete before calibration commences. The calibration When using the AD7722, place a buffer/latch adjacent to the values loaded into the registers only apply for the particular converter to isolate the converter’s data lines from any noise analog input mode (bipolar/unipolar) selected when initiating that may be on the data bus. Even though the AD7722 has the calibration cycle. On changing to a different analog input three-state outputs, use of an isolation latch represents good mode, a new calibration must be performed. design practice. This arrangement will inject a small amount of digital noise on the AD7722 ground plane; these currents During the calibration cycle, in unipolar mode, the offset of the should be quite small and can be minimized by ensuring that analog modulator is evaluated; the differential inputs to the the converter input/output does not drive a large fanout (they modulator are shorted internally to AGND. Once calibration normally can’t by design). Minimizing the fanout on the begins, DVAL goes low and DRDY goes high, indicating there AD7722’s digital port will also keep the converter logic transi- is invalid data in the output register. After 8192 CLKIN cycles, tions relatively free from ringing and thereby minimize any when the modulator and digital filter settle, the average of eight potential coupling into the analog port of the converter. output results (512 CLKIN cycles) is calculated and stored in the offset register. In unipolar mode, this result also represents The simplified diagram (Figure 23) shows how the parallel minus full scale, required to calculate the gain correction factor. interface of the AD7722 can be configured to interface with the The gain correction factor can then be determined by internally system data bus of a microprocessor or a modern microcontroller, switching the inputs to +FS (V ). The positive input of the such as the MC68HC16 or 8xC251. REF2 modulator is switched to the reference voltage and the negative input to AGND. Again, when the modulator and digital filter AD7722 DSP/µC settle, the average of the eight output results is used to calculate 16 16 the gain correction factor. DVAL goes high whenever a calcula- DB0–DB15 D0–D15 tion is performed on the average of eight conversion results 74xx16374 OR (512 CLKIN cycles) and then returns low. See Figure 8. 74xx16244 DRDY In bipolar mode, an additional measurement is required since ADDR zero scale is not the same as –FS. Therefore, calibration in ADDR DECODE bipolar mode requires an additional (512 + 8192) CLKIN OE cycles. Zero scale is similarly determined by shorting both CS RD analog inputs to AGND. Then the inputs are internally RD reconfigured to apply +FS and –FS (+V /2 and –V /2) REF2 REF2 to determine the gain correction factor. INTERRUPT After the calibration registers have been loaded with new values, the inputs of the modulator are switched back to the input pins. Figure 23. Parallel Interface Connection However, correct data is available at the interface only after the modulator and filter have settled to the new input values. With CS and RD tied permanently low, the data output bits are always active. When the DRDY output goes high for two CLKIN Should the part see a rising edge on the SYNC or RESET pin cycles, the rising edge of DRDY is used to latch the conversion during a calibration cycle, the calibration cycle is discontinued, data before a new conversion result is loaded into the output and a synchronization operation or reset will be performed. data register. The falling edge of DRDY then sends an appro- The calibration registers are static. They need to be updated priate interrupt signal for interface control. Alternatively if buffers only if unacceptable drifts in analog offsets or gain are expected. are used instead of latches, the falling edge of DRDY provides After power-up, a RESET is not mandatory since power-on reset the necessary interrupt when a new output word is available circuitry clears the offset and gain registers. Care must be taken from the AD7722. to ensure that the CAL pin is held low during power-up. Before REV. B –19– AD7722 SERIAL INTERFACE AD7722 DV DD The AD7722’s serial data interface port allows easy interfacing MASTER CFMT SDO to industry-standard digital signal processors. The AD7722 SFMT SCO operates solely in the master mode, providing three serial data TSI DGND FSO output pins for transfer of the conversion results. The serial data FSI DOE clock output (SCO), serial data output (SDO), and frame sync CLKIN output (FSO) are all synchronous with CLKIN. SCO frequency FROM is always one-half the CLKIN frequency. FSO is continuously CONTROL output at the conversion rate of the ADC (f /64). The CLKIN LOGIC generalized timing diagrams in Figure 2 show how the AD7722 AD7722 may be used to transmit its conversion results. SLAVE FSI DOE Serial data shifts out of the SDO pin synchronous with SCO. The DV DD CLKIN SDO FSO is used to frame the output data transmission to an external TO HOST CFMT SCO PROCESSOR device. An output data transmission is 32 SCO cycles in duration. SFMT FSO The serial data shifts out of the SDO pin MSB first, LSB last TSI for a duration of 16 SCO cycles. For the next 16 SCO cycles, SDO outputs zeros. Figure 24. Connection for 2-Channel Multiplexed Two control inputs, SFMT and CFMT, select the format for the Operation serial data transmission. FSO is either a pulse (approximately The data output enable pin (DOE) controls SDO’s output buffer. one SCO cycle in duration) or a square wave with a period of When the logic level on DOE matches the state of the TSI pin, 32 SCO cycles, depending on the state of the SFMT. The logic the SDO output buffer drives the serial dataline; otherwise, the level applied to SFMT also determines if the serial data is valid output of the buffer goes high impedance. The serial format pin on the rising or falling edge of the SCO. The clock format pin, (SFMT) is set high to choose the frame sync output format. The CFMT, simply switches the phase of SCO for the selected clock format pin (CFMT) is set high so that serial data is made FSO format. available on SDO after the rising edge of SCO and can be With a logic low level on SFMT and CFMT set low (Figure 4), latched on the SCO falling edge. FSO pulses high for one SCO cycle at the beginning of a data The master device is selected by setting TSI to a logic low and transmission frame. When FSO goes low, the MSB is available connecting its FSO to DOE. The slave device is selected with its on the SDO pin after the rising edge of SCO and can be latched TSI pin tied high, and both its FSI and DOE are controlled on the SCO falling edge. from the master’s FSO. Since the FSO of the master controls With a logic high level on SFMT and CFMT set low (Figure 4), the DOE input of both the master and slave, one ADC’s SDO is the data on the SDO pin is available after the falling edge of active while the other is high impedance (Figure 25). When the SCO and can be latched on the SCO rising edge. FSO goes low master transmits its conversion result during the first 16 SCO at the beginning of a data transmission frame when the MSB is cycles of a data transmission frame, the low level on DOE sets available and returns high after 16 SCO cycles. the slave’s SDO high impedance. Once the master completes The frame sync input (FSI) can be used if the AD7722 conver- transmitting its conversion data, its FSO goes high and triggers sion process must be synchronized to an external source. FSI is the slave’s FSI to begin its data transmission frame. an optional signal; if FSI is grounded or tied high frame syncs Following power up of the two devices, once the supplies have are internally generated. Frame sync allows the conversion data settled, a synchronous RESET/SYNC pulse should be issued to presented to the serial interface to be a filtered and decimated both ADCs to ensure synchronization. After a RESET/SYNC result derived from a known point in time. FSI can be applied has been issued, FSI can be applied to the master ADC to once after power-up, or it can be a periodic signal, synchronous to allow continuous synchronization between the processor and CLKIN, occurring every 64 CLKIN cycles. When FSI is applied the ADCs. For continuous synchronization, FSI should not be for the first time, or if a low-to-high transition is detected that is not applied within four CLKIN cycles before an FSO (master) edge. synchronized to the output word rate, the next 127 conversions See Figure 25. should be considered invalid while the digital filter accumulates Serial Interfacing to DSPs new samples. Figure 4 shows how the frame sync signal resets In serial mode, the AD7722 can be interfaced directly to several the serial output interface and how the AD7722 will begin to industry-standard DSPs. In all cases, the AD7722 operates as output its serial data transmission frame. A common frame sync the master with the DSP operating as the slave. The AD7722 signal can be applied to two or more AD7722s to synchronize outputs its own serial clock (SCO) to transmit the digital word on them to a common master clock. the SDO pin to a DSP. The DSP’s serial interface is synchronized 2-Channel Multiplexed Operation to the data transmission provided by the FSO signal. Three additional serial interface control pins (DOE, TSI, and Since the serial data clock from the AD7722 is always one-half CFMT) are provided. The connection diagram in Figure 24 the CLKIN frequency, DSPs that can accept relatively high shows how they are used to allow the serial data outputs of two serial clock frequencies are required. The ADSP-21xx family of AD7722s to easily share one serial data line. Since a serial data DSPs can operate with a maximum serial clock of 13.824 MHz; transmission frame lasts 32 SCO cycles, two AD7722s can share the DSP56002 allows a maximum serial clock of 13.3 MHz; the a single data line by alternating transmission of their 16-bit output TMS320C5x-57 accepts a maximum serial clock of 10.989 MHz. data onto one SDO pin. –20– REV. B AD7722 CLKIN t 1 t RESET/SYNC 14 FSI NOTE 1 NOTE 1 SCO t t FSO (MASTER) 12 11 FSI (SLAVE) DOE (MASTER AND SLAVE) t t 16 15 SDO (MASTER) D15 D14 D1 D0 t t 16 15 SDO (SLAVE) D4 D3 D2 D1 D0 D15 NOTE 1: THE STATE OF FSI CANNOT BE CHANGED 4 CLKIN CYCLES BEFORE A FSO EDGE. Figure 25. Timing for 2-Channel Multiplexed Operation To interface the AD7722 to other DSPs, the master clock Grounding and Layout frequency of the AD7722 can be reduced so that the SCO The analog and digital power supplies to the AD7722 are indepen- frequency equals the maximum allowable frequency of the serial dent and separately pinned out to minimize coupling between clock input to the DSP. When the AD7722 is operated with a analog and digital sections within the device. The AD7722 should lower CLKIN frequency (< 10 MHz), DSPs, such as the be treated as an analog component and grounded and decoupled TMS320C20/C25 and DSP56000/1, can be used. to the analog ground plane. All the AD7722 ground pins should be soldered directly to a ground plane to minimize series induc- Figures 26 to 28 show the interfaces between the AD7722 and tance. All converter power pins should be decoupled to the analog several DSPs. In all cases, the interface control pins, TSI, DOE, ground plane. To achieve the best decoupling, place surface- SFMT, CFMT, SYNC, and FSI, can be permanently hardwired mount capacitors as close as possible to the device, ideally right together to either DGND or DV . Alternatively, SFMT or DD up against the device pins. CFMT can be tied either high or low to configure the serial data interface for the particular format required by the DSP. The The printed circuit board that houses the AD7722 should use frame synchronization signal, FSI, can be applied from the user’s separate ground planes for the analog and digital interface system control logic. circuitry. All converter power pins should be decoupled to the analog ground plane, and all interface logic circuit power pins should be decoupled to the digital ground plane. This facili- RFS FSO tates the use of ground planes, which can physically separate ADSP-21xx AD7722 sensitive analog components from the noisy digital system. SDO DR Digital and analog ground planes should only be joined in one SCO SCLK place and should not overlap to minimize capacitive coupling between them. Figure 26. AD7722 to ADSP-21xx Interface Separate power supplies for AV and DV are also highly DD DD desirable. The digital supply pin DV should be powered from DD a separate analog supply, but if necessary DV may share its DD FSO SC1 power connection to AV (see the connection diagram in DSP56001/2/3 DD AD7722 Figure 29). The 10 Ω resistor, in series with the DV pin, is DD SDO SRD required to dampen the effects of the fast switching currents into SCO SCK the digital section of the AD7722. The ferrite is also recommended to filter high frequency signals from corrupting the analog power supply. Figure 27. AD7722 to DSP56000 Interface A minimum etch technique is generally best for ground planes because it gives the best shielding. Noise can be minimized by FSO FSR TMS320Cxx AD7722 paying attention to the system layout and preventing different SDO DR signals from interfering with each other. High level analog signals should be separated from low level analog signals, and both should SCO CLKR be kept away from digital signals. In waveform sampling and reconstruction systems, the sampling clock (CLKIN) is as vulner- Figure 28. AD7722 to TMS320C20/TMS320C25/ able to noise as any analog signal. CLKIN should be isolated from TMS320C50 Interface REV. B –21– AD7722 the analog and digital systems. Fast switching signals like clocks AV 1 14 DD should be shielded with their associated ground to avoid radiating 100nF 10 AGND1 noise to other sections of the board, and clock signals should never be routed near the analog inputs. 5V Avoid running digital lines under the device as these will couple AV 20 DD 100nF noise onto the die. The analog ground plane should be allowed 10�F 100nF 19 AGND to run under the AD7722 to shield it from noise coupling. The AV 23 DD power supply lines to the AD7722 should use as large a trace as 100nF AGND 25 possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. 10� Avoid crossover of digital and analog signals. Traces on opposite 39 DV DD sides of the board should run at right angles to each other. This 1nF 100nF 10�F 100nF DGND 5 will reduce the effects of feedthrough through the board. 28 DGND Figure 29. Power Supply Decoupling –22– REV. B AD7722 OUTLINE DIMENSIONS 44-Lead Metric Quad Flat Package [MQFP] (S-44B) Dimensions shown in millimeters 14.15 1.03 13.90 SQ 0.88 2.45 13.65 MAX 0.73 33 23 8� 0.8� 34 22 SEATING PLANE 10.20 TOP VIEW COPLANARITY 10.00 SQ (PINS DOWN) 0.10 9.80 PIN 1 44 12 1 11 2.10 0.45 2.00 0.80 0.25 MAX 0.30 1.96 BSC COMPLIANT TO JEDEC STANDARDS MS-022-AA-1 REV. B –23– AD7722 Revision History Location Page 10/03—Data Sheet changed from REV. A to REV. B. Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Replaced Figures 7 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Text added to 2-Channel Multiplexed Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Replaced Figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Changes to text in 2-Channel Multiplexed Operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Changes to Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5/03—Data Sheet changed from REV. 0 to REV. A. Figures and TPCs Renumbered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to PARALLEL MODE PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to SERIAL MODE PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Differential Inputs sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 –24– REV. B C01185–0–10/03(B)