ANALOG DEVICES AD7720

a CMOS Sigma-Delta Modulator AD7720 FUNCTIONAL BLOCK DIAGRAM FEATURES 12.5 MHz Master Clock Frequency AVDD AGND DVDD DGND REF1 0 V to +2.5 V or 61.25 V Input Range Single Bit Output Stream 90 dB Dynamic Range AD7720 2.5V REF2 Power Supplies: AVDD, DVDD: +5 V 6 5% REFERENCE On-Chip 2.5 V Voltage Reference VIN(+) 28-Lead TSSOP DATA SIGMA-DELTA MODULATOR VIN(–) SCLK MZERO XTAL1/MCLK CLOCK GC CIRCUITRY XTAL2 DVAL CONTROL BIP LOGIC RESETO STBY RESET GENERAL DESCRIPTION This device is a 7th order sigma-delta modulator that converts the analog input signal into a high speed 1-bit data stream. The part operates from a +5 V supply and accepts a differential input range of 0 V to +2.5 V or ±1.25 V centered about a common- mode bias. The analog input is continuously sampled by the analog modulator, eliminating the need for external sample and hold circuitry. The input information is contained in the output stream as a density of ones. The original information can be reconstructed with an appropriate digital filter. The part provides an accurate on-chip 2.5 V reference. A refer- ence input/output function is provided to allow either the inter- nal reference or an external system reference to be used as the reference source for the part. The device is offered in a 28-lead TSSOP package and designed to operate from –40°C to +85°C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1997 (AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V, f = 12.5 MHz, MCLK 1 REF2 = +2.5 V; T = T to T , unless otherwise noted) AD7720–SPECIFICATIONS A MIN MIN Parameter B Version Units Test Conditions/Comments STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1 Resolution 16 Bits Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Integral Nonlinearity ±2 LSB typ Precalibration Offset Error ±6 mV typ 2 Precalibration Gain Error ±0.6 % FSR typ 3 Postcalibration Offset Error ±1.5 mV typ 2, 3 Postcalibration Gain Error ±0.3 % FSR typ Offset Error Drift ±1 LSB/°C typ Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode ±1 LSB/°C typ Bipolar Mode ±0.5 LSB/°C typ ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) Bipolar Mode ±V /2 V max BIP = V REF2 IH Unipolar Mode 0 to V V max BIP = V REF2 IL Maximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 f MHz MCLK 9 Differential Input Impedance 10 /(8 f )kΩ typ MCLK REFERENCE INPUTS REF1 Output Voltage 2.32 to 2.62 V min/max REF1 Output Voltage Drift 60 ppm/°C typ REF1 Output Impedance 3 kΩ typ Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2 Using Internal Reference REF2 Output Voltage 2.32 to 2.62 V min/max REF2 Output Voltage Drift 60 ppm/°C typ Using External Reference REF1 = AGND 9 REF2 Input Impedance 10 /(16 f )kΩ typ MCLK External Reference Voltage Range 2.32 to 2.62 V min/max Applied to REF1 or REF2 4 DYNAMIC SPECIFICATIONS When Tested with Ideal FIR Filter as in Figure 1 Bipolar Mode BIP = V , V = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p IH CM or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V 5 Signal to (Noise + Distortion) 90 dB typ Input BW = 0 kHz–90.625 kHz 86/84.5 dB min 5 Total Harmonic Distortion –90/–88 dB max Input BW = 0 kHz–90.625 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–90.625 kHz Unipolar Mode BIP = V , VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V IL 5 Signal to (Noise + Distortion) 88 dB typ Input BW = 0 kHz–90.625 kHz 84.5/83 dB min 5 Total Harmonic Distortion –89/–87 dB max Input BW = 0 kHz–97.65 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–97.65 kHz Intermodulation Distortion –93 dB typ AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, V = 1.25 V to CM 3.75 V, 20 kHz Overall Digital Filter Response See Figure 1 for Characteristics of FIR Filter 0 kHz–90.625 kHz ±0.005 dB max 96.92 kHz –3 dB min 104.6875 kHz to 12.395 MHz 90 dB typ CLOCK MCLK Duty Ratio 45 to 55 % max For Specified Operation V , MCLK High Voltage 4 V min MCLK Uses CMOS Logic MCLKH V , MCLK Low Voltage 0.4 V max MCLKL –2– REV. 0 AD7720 Parameter B Version Units Test Conditions/Comments LOGIC INPUTS V , Input High Voltage 2 V min IH V , Input Low Voltage 0.8 V max IL I , Input Current 10 μA max INH C , Input Capacitance 10 pF max IN LOGIC OUTPUTS V , Output High Voltage 2.4 V min |I | ≤ 200 μA OH OUT V , Output Low Voltage 0.4 V max |I | ≤ 1.6 mA OL OUT POWER SUPPLIES AVDD 4.75/5.25 V min/V max DVDD 4.75/5.25 V min/V max I (Total for AVDD, DVDD) Digital Inputs Equal to 0 V or DVDD DD Active Mode 43 mA max Standby Mode 25 μA max NOTES 1 Operating temperature range is as follows: B Version: –40°C to +85°C. 2 Gain Error excludes reference error. The modulator gain is calibrated w.r.t. the voltage on the REF2 pin. 3 Applies after calibration at temperature of interest. 4 Measurement Bandwidth = 0.5 × f ; Input Level = –0.05 dB. MCLK 5 T = +25°C to +85°C/T = T to T . A A MIN MAX Specifications subject to change without notice. 90.625kHz 90.625kHz BIT STREAM DECIMATE DECIMATE 16-BIT BY 32 BY 2 OUTPUT 120dB 90dB FILTER 1 292.969kHz FILTER 2 104.687kHz BANDWIDTH = 90.625 kHz BANDWIDTH = 90.625 kHz TRANSITION = 292.969kHz TRANSITION = 104.687kHz ATTENUATION = 120dB ATTENUATION = 90dB COEFFICIENTS = 384 COEFFICIENTS = 151 Figure 1. Digital Filter (Consists of 2 FIR Filters). This filter is implemented on the AD7722. REV. 0 –3– AD7720 (AVDD = +5 V 6 5%; DVDD = +5 V 6 5%; AGND = DGND = 0 V, REF2 = +2.5 V unless otherwise noted) TIMING CHARACTERISTICS Limit at T , T MIN MAX Parameter (B Version) Units Conditions/Comments f 100 kHz min Master Clock Frequency MCLK 15 MHz max 12.5 MHz for Specified Performance t 67 ns min Master Clock Period 1 t 0.45 × t ns min Master Clock Input High Time 2 MCLK t 0.45 × t ns min Master Clock Input Low Time 3 MCLK t 15 ns min Data Hold Time After SCLK Rising Edge 4 t 10 ns min RESET Pulsewidth 5 t 10 ns min RESET Low Time Before MCLK Rising 6 t 20 × t ns max DVAL High Delay after RESET Low 7 MCLK NOTE Guaranteed by design. I OL 1.6mA TO OUTPUT +1.6V PIN C L 50pF I OH 200 A Figure 2. Load Circuit for Access Time and Bus Relinquish Time t 1 t SCLK (O) 2 t 3 t 4 DATA (O) NOTE: O SIGNIFIES AN OUTPUT Figure 3. Data Timing MCLK (I) t 6 t RESET (I) 5 t 7 DVAL (O) NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT Figure 4. RESET Timing –4– REV. 0 AD7720 1 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (T = +25°C unless otherwise noted) A DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V 1 REF2 28 AVDD AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND 2 27 REF1 AVDD to DVDD . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V NC 3 26 AGND AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V STBY 4 25 AVDD Digital Input Voltage to DGND . . –0.3 V to DVDD + 0.3 V DVAL 5 24 AGND Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V 6 VIN(+) DGND 23 2 AD7720 Input Current to Any Pin Except Supplies . . . . . . . ±10 mA 7 GC 22 RESET TOP VIEW Operating Temperature Range (Not to Scale) 8 BIP 21 VIN(–) Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C MZERO 9 20 AGND Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 10 DATA 19 DVDD Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C 11 SCLK 18 AGND TSSOP Package 12 RESETO 17 XTAL2 θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 120°C/W JA 13 NC 16 XTAL1/MCLK Lead Temperature, Soldering 14 AGND 15 DGND Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C NC = NO CONNECT Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latchup. ORDERING GUIDE Temperature Package Package Model Range Description Option AD7720BRU –40°C to +85°C 28-Lead Thin Shrink Small Outline RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7720 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– AD7720 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 REF2 Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con- nected to AGND. 2, 14, 18, 20, 24, 26 AGND Ground reference point for analog circuitry. 3, 13 NC No Connect. 4 STBY Standby, Logic Input. When STBY is high, the device is placed in a low power mode. When STBY is low, the device is powered up. 5 DVAL Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7720 is an accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is overranged. 6, 15 DGND Ground reference for the digital circuitry. 7 GC Digital Control Input. When GC is high, the gain error of the modulator can be calibrated. 8 BIP Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects bipolar mode. 9 MZERO Digital Control Input. When MZERO is high, the modulator inputs are internally grounded, i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip offsets to be calibrated out. MZERO is low for normal operation. 10 DATA Modulator Bit Stream. The digital bit stream from the sigma-delta modulator is output at DATA. 11 SCLK Serial Clock, Logic Output. The bit stream from the modulator is valid on the rising edge of SCLK. 12 RESETO Reset Logic Output. The signal applied to the RESET pin is made available as an output at RESETO. 16 XTAL1/MCLK CMOS Logic Clock Input. The XTAL1/MCLK pin interfaces the device’s internal oscillator circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency, microprocessor-grade crystal and a 1 MΩ resistor should be connected between the MCLK and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the XTAL1/MCLK pin can be driven with an external CMOS-compatible clock. The part is specified with a 12.5 MHz master clock. 17 XTAL2 Oscillator Output. The XTAL2 pin connects the internal oscillator output to an external crystal. If an external clock is used, XTAL2 should be left unconnected. 19 DVDD Digital Supply Voltage, +5 V ± 5%. 21, 23 VIN(–), VIN(+) Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to (VIN(–) + V ); for bipolar operation, the analog input range on VIN+ is (VIN(–) ± V /2). REF REF The absolute analog input range must lie between 0 and AVDD. The analog input is con- tinuously sampled and processed by the analog modulator. 25, 28 AVDD Analog Positive Supply Voltage, +5 V ± 5%. 22 RESET Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL goes low for 20 MCLK cycles while the modulator is being reset. 27 REF1 Reference Input/Output. REF1 connects via a 3 kΩ resistor to the output of the internal 2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator. This pin can also be overdriven with an external 2.5 V reference. –6– REV. 0 AD7720 TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7720 fundamental. Noise plus distortion is the rms sum of all of the [FIGURE 1]) nonfundamental signals and harmonics to half the output word Integral Nonlinearity rate (f /128), excluding dc. Signal-to-(Noise + Distortion) is MCLK This is the maximum deviation of any code from a straight line dependent on the number of quantization levels used in the passing through the endpoints of the transfer function. The digitization process; the more levels, the smaller the quantiza- endpoints of the transfer function are zero scale (not to be con- tion noise. The theoretical Signal-to-(Noise + Distortion) ratio fused with bipolar zero), a point 0.5 LSB below the first code for a sine wave input is given by transition (100...00 to 100...01 in bipolar mode and Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB 000...00 to 000...01 in unipolar mode) and full scale, a where N is the number of bits. point 0.5 LSB above the last code transition (011...10 to 011...11 in bipolar mode and 111...10 to 111...11 in Total Harmonic Distortion unipolar mode). The error is expressed in LSBs. Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the Differential Nonlinearity AD7720, THD is defined as This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC. 2 2 2 2 2 (V +V +V +V +V ) 2 3 4 5 6 Common-Mode Rejection Ratio THD = 20 log V 1 The ability of a device to reject the effect of a voltage applied to both input terminals simultaneously—often through variation of where V is the rms amplitude of the fundamental and V , V , 1 2 3 a ground level—is specified as a common-mode rejection ratio. V , V and V are the rms amplitudes of the second through the 4 5 6 CMRR is the ratio of gain for the differential signal to the gain sixth harmonic. for the common-mode signal. Spurious Free Dynamic Range Unipolar Offset Error Spurious free dynamic range is the difference, in dB, between Unipolar offset error is the deviation of the first code transition the peak spurious or harmonic component in the ADC output from the ideal VIN(+) voltage which is (VIN(–) + 0.5 LSB) spectrum (up to f /128 and excluding dc) and the rms value MCLK when operating in the unipolar mode. of the fundamental. Normally, the value of this specification will Bipolar Offset Error be determined by the largest harmonic in the output spectrum This is the deviation of the midscale transition (111...11 of the FFT. For input signals whose second harmonics occur in to 000... 00) from the ideal VIN(+) voltage which is (VIN(–) the stop band region of the digital filter, a spur in the noise floor –0.5 LSB) when operating in the bipolar mode. limits the spurious free dynamic range. Gain Error Intermodulation Distortion The first code transition should occur at an analog value 1/2 With inputs consisting of sine waves at two frequencies, fa and LSB above minus full scale. The last code transition should fb, any active device with nonlinearities will create distortion occur for an analog value 3/2 LSB below the nominal full scale. products at sum and difference frequencies of mfa ± nfb where Gain error is the deviation of the actual difference between first m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are and last code transitions and the ideal difference between first those for which neither m or n are equal to zero. For example, and last code transitions. the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and Signal-to-(Noise + Distortion) (fa – 2fb). Signal-to-(Noise + Distortion) is measured signal-to-noise at the output of the ADC. The signal is the rms magnitude of the REV. 0 –7– AD7720–Typical Characteristics (AVDD = DVDD = 5.0 V, T = +258C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; V (+) = 0 V to 2.5 V, V (–) = 1.25 V unless otherwise A IN IN noted) 110 84 –85 85 100 –90 AIN = 1/5 · BW SNR 86 90 –95 87 SFDR 80 88 –100 S/ (N+D) 89 70 –105 SFDR 90 60 –110 91 THD 50 92 –115 –40 –30 –20 –10 0 0 50 100 150 200 250 300 0 20 40 60 80 100 INPUT LEVEL – dB OUTPUT DATA RATE – kSPS INPUT FREQUENCY – kHz Figure 5. S/(N+D) and SFDR vs. Figure 6. S/(N+D) vs. Output Sample Figure 7. SNR, THD, and SFDR vs. Analog Input Level Rate Input Frequency 92.0 –85 84 91.5 85 –90 AIN = 1/5 · BW SNR V (+) = V (–) = 1.25Vpk–pk 91.0 86 IN IN V (+) = V (–) = 1.25Vpk–pk IN IN V = 2.5V CM –95 V = 2.5V CM 90.5 87 THD 90.0 –100 88 89 89.5 –105 90 89.0 SFDR –110 91 88.5 –115 92 88.0 0 20 40 60 80 100 0 50 100 150 200 250 300 –50 0 50 100 INPUT FREQUENCY – kHz OUTPUT DATA RATE – kSPS TEMPERATURE – °C Figure 8. SNR, THD, and SFDR vs. Figure 9. S/(N+D) vs. Output Sample Figure 10. SNR vs. Temperature Input Frequency Rate 1.0 –94 5000 –96 0.8 4500 THD V (+) = V (–) IN IN –98 0.6 4000 CLKIN = 12.5MHz –100 0.4 3500 8k SAMPLES –102 0.2 3000 3RD –104 0 2500 –106 4TH –0.2 2000 –108 –0.4 1500 –110 –0.6 1000 –112 –0.8 500 –114 2ND –1.0 –116 0 0 20000 40000 65535 –50 –25 025 50 75 100 n–3 n–2 n–1 n n+1 n+2 n+3 CODE TEMPERATURE – °C CODES Figure 13. Differential Nonlinearity Figure 11. THD vs. Temperature Figure 12. Histogram of Output Codes with DC Input REV. 0 –8– dB dB dB FREQUENCY OF OCCURENCE dB dB DNL ERROR – LSB dB dB AD7720 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 20000 40000 65535 CODE Figure 14. Integral Nonlinearity Error 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 6.25 0 393.295 kHz FREQUENCY – MHz FREQUENCY – kHz Figure 15. Modulator Output (0 Hz to MCLK/2) Figure 18. Modulator Output (0 to 393.295 kHz) 0 0 CLKIN = 12.5MHz AIN = 90kHz –20 –20 CLKIN = 12.5 MHz SNR = 90.1dB SNR = 89.6dB S/(N+D) = 89.2dB –40 –40 S/(N+D) = 89.6dB SFDR = –99.5dB SFDR = –108.0dB –60 –60 THD = –96.6dB 2ND = –100.9dB –80 –80 3RD = –106.0dB 4TH = –99.5dB –100 –100 –120 –120 –140 –140 –154 –154 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 98E+3 Figure 16. 16K Point FFT Figure 19. 16K Point FFT 0 0 XTAL = 12.288MHz AIN = 90kHz –20 –20 SNR = 89.0dB XTAL = 12.288MHz S/(N+D) = 87.8dB SNR = 88.1dB –40 –40 SFDR = –94.3dB S/(N+D) = 88.1dB THD = –93.8dB SFDR = –103.7dB –60 –60 2ND = –94.3dB –80 3RD = –108.5dB –80 4TH = –105.7dB –100 –100 –120 –120 –140 –140 –154 –154 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3 0E+0 10E+3 20E+3 30E+3 40E+3 50E+3 60E+3 70E+3 80E+3 90E+3 96E+3 Figure 17. 16K Point FFT Figure 20. 16K Point FFT REV. 0 –9– dB dB dB INL ERROR – LSB dB dB dB AD7720 CIRCUIT DESCRIPTION A Sigma-Delta ADC 500 VIN(+) 2pF The AD7720 ADC employs a sigma-delta conversion technique B that converts the analog input into a digital pulse train. The 2pF A analog input is continuously sampled by a switched capacitor 500 VIN(–) modulator at twice the rate of the clock input frequency (2 × AC B GROUND f ). The digital data that represents the analog input is in MCLK the one’s density of the bit stream at the output of the sigma- MCLK A B A B delta modulator. The modulator outputs the bit stream at a data rate equal to f . MCLK Figure 22. Analog Input Equivalent Circuit Due to the high oversampling rate, which spreads the quantiza- tion noise from 0 to f /2, the noise energy contained in the Since the AD7720 samples the differential voltage across its MCLK band of interest is reduced (Figure 21a). To reduce the quanti- analog inputs, low noise performance is attained with an input zation noise further, a high order modulator is employed to circuit that provides low differential mode noise at each input. shape the noise spectrum, so that most of the noise energy is The amplifiers used to drive the analog inputs play a critical shifted out of the band of interest (Figure 21b). role in attaining the high performance available from the AD7720. When a capacitive load is switched onto the output of an op amp, the amplitude will momentarily drop. The op amp will try to correct the situation and, in the process, hits its slew rate QUANTIZATION NOISE limit. This nonlinear response, which can cause excessive ring- f /2 MCLK ing, can lead to distortion. To remedy the situation, a low pass BAND OF INTEREST RC filter can be connected between the amplifier and the input a. to the AD7720 as shown in Figure 23. The external capacitor at each input aids in supplying the current spikes created during the sampling process. The resistor in this diagram, as well as NOISE SHAPING creating the pole for the antialiasing, isolates the op amp from the transient nature of the load. f /2 MCLK BAND OF INTEREST b. R VIN(+) Figure 21. Sigma-Delta ADC C ANALOG USING THE AD7720 INPUT R ADC Differential Inputs VIN(–) The AD7720 uses differential inputs to provide common-mode C noise rejection (i.e., the converted result will correspond to the differential voltage between the two inputs). The absolute volt- age on both inputs must lie between AGND and AVDD. Figure 23. Simple RC Antialiasing Circuit In the unipolar mode, the full-scale input range (VIN(+) – The differential input impedance of the AD7720 switched VIN(–)) is 0 V to V . In the bipolar mode configuration, the REF capacitor input varies as a function of the MCLK frequency, full-scale analog input range is ±V /2. The bipolar mode REF2 given by the equation: allows complementary input signals. Alternatively, VIN(–) can 9 Z = 10 /(8 f ) kΩ IN MCLK be connected to a dc bias voltage to allow a single-ended input on VIN(+) equal to V ± V /2. BIAS REF2 Even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the Differential Inputs resolution of the AD7720, as long as the sampling capacitor The analog input to the modulator is a switched capacitor de- charging follows the exponential curve of RC circuits, only the sign. The analog input is converted into charge by highly linear gain accuracy suffers if the input capacitor is switched away too sampling capacitors. A simplified equivalent circuit diagram of early. the analog input is shown in Figure 22. A signal source driving the analog input must be able to provide the charge onto the An alternative circuit configuration for driving the differential sampling capacitors every half MCLK cycle and settle to the inputs to the AD7720 is shown in Figure 24. required accuracy within the next half cycle. –10– REV. 0 AD7720 The AD7720 can operate with its internal reference or an external reference can be applied in two ways. An external reference can C R 2.7nF 100V be connected to REF1, overdriving the internal reference. How- VIN(+) ever, there will be an error introduced due to the offset of the C internal buffer amplifier. For lowest system gain errors when 2.7nF R using an external reference, REF1 is grounded (disabling the 100V VIN(–) internal buffer) and the external reference is connected to REF2. C 2.7nF In all cases, since the REF2 voltage connects to the analog modulator, a 220 nF capacitor must connect directly from REF2 to AGND. The external capacitor provides the charge Figure 24. Differential Input with Antialiasing required for the dynamic load presented at the REF2 pin (Figure 26). A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. This minimizes undesir- able charge transfer from the analog inputs to and from ground. F A The series resistor isolates the operational amplifier from the F B current spikes created during the sampling process and provides 4pF REF2 a pole for antialiasing. The 3 dB cutoff frequency (f ) of the 3 dB 220nF antialias filter is given by Equation 1, and the attenuation of the 4pF F A F B filter is given by Equation 2. f = 1/(2 π R C ) (1) SWITCHED-CAP 3dB EXT EXT DAC REF  2 F F F F 1/ 1+ f /f MCLK A B A B () 3dB Attenuation = 20 log   (2)   Figure 26. REF2 Equivalent Circuit The choice of the filter cutoff frequency will depend on the amount of roll off that is acceptable in the passband of the The AD780 is ideal to use as an external reference with the digital filter and the required attenuation at the first image AD7720. Figure 27 shows a suggested connection diagram. frequency. The capacitors used for the input antialiasing circuit must have O/P 1 NC 8 low dielectric absorption to avoid distortion. Film capacitors +5V SELECT REF2 such as Polypropylene, Polystyrene or Polycarbonate are suitable. 2 +V 7 NC IN 220nF If ceramic capacitors are used, they must have NPO dielectric. 3 TEMP 6 1mF V OUT REF1 22nF 22mF 4 GND TRIM 5 Applying the Reference The reference circuitry used in the AD7720 includes an on-chip AD780 +2.5 V bandgap reference and a reference buffer circuit. The block diagram of the reference circuit is shown in Figure 25. Figure 27. External Reference Circuit Connection The internal reference voltage is connected to REF1 via a Input Circuits 3 kΩ resistor and is internally buffered to drive the analog Figures 28 and 29 show two simple circuits for bipolar mode modulator’s switched capacitor DAC (REF2). When using the operation. Both circuits accept a single-ended bipolar signal internal reference, connect 100 nF between REF1 and AGND. source and create the necessary differential signals at the input If the internal reference is required to bias external circuits, use to the ADC. an external precision op amp to buffer REF1. The circuit in Figure 28 creates a 0 V to 2.5 V signal at the VIN(+) pin to form a differential signal around an initial bias voltage of 1.25 V. For single-ended applications, best THD COMPARATOR 1V performance is obtained with VIN(–) set to 1.25 V rather than REFERENCE 2.5 V. The input to the AD7720 can also be driven differen- BUFFER tially with a complementary input as shown in Figure 29. REF1 SWITCHED-CAP DAC REF In this case, the input common-mode voltage is set to 2.5 V. 100nF The 2.5 V p-p full-scale differential input is obtained with a 3kV 2.5V 1.25 V p-p signal at each input in antiphase. This configuration REFERENCE minimizes the required output swing from the amplifier circuit REF2 and is useful for single supply applications. Figure 25. Reference Circuit Block Diagram REV. 0 –11– AD7720 12pF 1kV 1kV AIN = XTAL MCLK 61.25V 1MV 1/2 VIN(+) OP275 1nF 1kV VIN(–) 1nF DIFFERENTIAL 12pF INPUT = 2.5V p-p Figure 30. Crystal Oscillator Connection VIN(–) BIAS 1kV VOLTAGE = 1.25V An external clock must be free of ringing and have a minimum REF1 rise time of 5 ns. Degradation in performance can result as high 1kV 100nF 1/2 374kV edge rates increase coupling that can generate noise in the sam- OP275 pling process. The connection diagram for an external clock 10nF 374kV source (Figure 31) shows a series damping resistor connected REF2 between the clock output and the clock input to the AD7720. 220nF The optimum resistor will depend on the board layout and the impedance of the trace connecting to the clock input. Figure 28. Single-Ended Analog Input for Bipolar Mode Operation 25–150V CLOCK MCLK CIRCUITRY 12pF 1kV 1kV AIN = Figure 31. External Clock Oscillator Connection 60.625V A low phase noise clock should be used to generate the ADC 1/2 VIN(–) OP275 sampling clock because sampling clock jitter effectively modu- 1nF lates the input signal and raises the noise floor. The sampling 12pF DIFFERENTIAL 1kV clock generator should be isolated from noisy digital circuits, INPUT = 2.5V p-p 1kV COMMON MODE grounded and heavily decoupled to the analog ground plane. VOLTAGE = 2.5V The sampling clock generator should be referenced to the ana- 1/2 VIN(+) log ground plane in a split ground system. However, this is not OP275 1nF always possible because of system constraints. In many cases, R the sampling clock must be derived from a higher frequency REF1 multipurpose system clock that is generated on the digital R 100nF OP07 ground plane. If the clock signal is passed between its origin on a digital plane to the AD7720 on the analog ground plane, the REF2 ground noise between the two planes adds directly to the clock 220nF and will produce excess jitter. The jitter can cause unwanted degradation in the signal-to-noise ratio and also produce un- wanted harmonics. Figure 29. Single-Ended to Differential Analog Input This can be somewhat remedied by transmitting the sampling Circuit for Bipolar Mode Operation clock signal as a differential one, using either a small RF trans- former or a high speed differential driver and receiver such as The 1 nF capacitors at each ADC input store charge to aid the PECL. In either case, the original master system clock should amplifier settling as the input is continuously switched. A resis- be generated from a low phase noise crystal oscillator. tor in series with the drive amplifier output and the 1 nF input capacitor may also be used to create an antialias filter. Clock Generation The AD7720 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the ADC. The connection diagram for use with the crystal is shown in Figure 30. Consult the crystal manufacturer’s recommenda- tion for the load capacitors. –12– REV. 0 AD7720 Offset and Gain Calibration common-mode rejection of the part will remove common-mode The analog inputs of the AD7720 can be configured to measure noise on these inputs. The analog and digital supplies to the offset and gain errors. Pins MZERO and GC are used to config- AD7720 are independent and separately pinned out to minimize ure the part. Before calibrating the device, the part should be coupling between analog and digital sections of the device. reset so that the modulator is in a known state at calibration. The printed circuit board that houses the AD7720 should be When MZERO is taken high, the analog inputs are tied to designed so that the analog and digital sections are separated AGND in unipolar mode and V in bipolar mode. After REF and confined to certain areas of the board. This facilitates the taking MZERO high, 1000 MCLK cycles should be allowed for use of ground planes which can easily be separated. A minimum the circuitry to settle before the bit stream is read from the etch technique is generally best for ground planes as it gives the device. The ideal ones density is 50% when bipolar operation is best shielding. Digital and analog ground planes should only selected and 37.5% when unipolar mode is selected. be joined in one place. If the AD7720 is the only device requir- When GC is taken high, VIN(–) is tied to ground while VIN(+) ing an AGND-to-DGND connection, the ground planes should is tied to V . Again, 1000 MCLK cycles should be allowed for be connected at the AGND and DGND pins of the AD7720. REF the circuitry to settle before the bit stream is read. The ideal If the AD7720 is in a system where multiple devices require ones density is 62.5%. AGND-to-DGND connections, the connection should still be made at one point only, a star ground point that should be The calibration results apply only for the particular analog input established as close as possible to the AD7720. mode (unipolar/bipolar) selected when performing the calibra- tion cycle. On changing to a different analog input mode, a new Avoid running digital lines under the device as these will couple calibration must be performed. noise onto the die. The analog ground plane should be allowed to run under the AD7720 to avoid noise coupling. The power Before calibrating, ensure that the supplies have settled and that supply lines to the AD7720 should use as large a trace as pos- the voltage on the analog input pins is between the supply sible to provide low impedance paths and reduce the effects of voltages. glitches on the power supply line. Fast switching signals like Standby clocks should be shielded with digital ground to avoid radiating The part can be put into a low power standby mode by taking noise to other sections of the board, and clock signals should STBY high. During standby, the clock to the modulator is never be run near the analog inputs. Avoid crossover of digital turned off and bias is removed from all analog circuits. and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of Reset feedthrough through the board. A microstrip technique is by far The RESET pin is used to reset the modulator to a known state. the best, but is not always possible with a double-sided board. When RESET is taken high, the integrator capacitors of the In this technique, the component side of the board is dedi- modulator are shorted and DVAL goes low and remains low cated to ground planes while signals are placed on the other until 20 MCLK cycles after RESET is deasserted. However, an side. additional 1000 MCLK cycles should be allowed before reading the modulator bit stream as the modulator circuitry needs to Good decoupling is important when using high resolution ADCs. settle after the reset. All analog and digital supplies should be decoupled to AGND and DGND respectively, with 100 nF ceramic capacitors in DVAL parallel with 10 μF tantalum capacitors. To achieve the best The DVAL pin is used to indicate that an overrange input signal from these decoupling capacitors, they should be placed as close has resulted in invalid data at the modulator output. As with all as possible to the device, ideally right up against the device. In single bit DAC high order sigma-delta modulators, large overloads systems where a common supply voltage is used to drive both on the inputs can cause the modulator to go unstable. The the AVDD and DVDD of the AD7720, it is recommended that modulator is designed to be stable with signals within the input the system’s AVDD supply is used. This supply should have the bandwidth that exceed full scale by 20%. When instability is recommended analog supply decoupling between the AVDD detected by internal circuits, the modulator is reset to a stable pin of the AD7720 and AGND and the recommended digital state and DVAL is held low for 20 clock cycles. supply decoupling capacitor between the DVDD pins and DGND. Grounding and Layout Since the analog inputs are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent REV. 0 –13– AD7720 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.028 (0.70) 8° 0.0118 (0.30) 0.0256 (0.65) 0° 0.020 (0.50) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) –14– REV. 0 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) –15– –16– PRINTED IN U.S.A. C3235–8–10/97