ANALOG DEVICES AD7719

Low Voltage, Low Power, a Factory-Calibrated 16-/24-Bit Dual �-� ADC AD7719 FEATURES APPLICATIONS HIGH RESOLUTION �-� ADCs Sensor Measurement 2 Independent ADCs (16- and 24-Bit Resolution) Temperature Measurement Factory-Calibrated (Field Calibration Not Required) Pressure Measurement Output Settles in 1 Conversion Cycle (Single Weigh Scales Conversion Mode) Portable Instrumentation Programmable Gain Front End 4 to 20 mA Transmitters Simultaneous Sampling and Conversion of 2 Signal Sources Separate Reference Inputs for Each Channel GENERAL DESCRIPTION Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz The AD7719 is a complete analog front end for low frequency Update Rate measurement applications. It contains two high resolution Σ-∆ ADCs, switchable matched excitation current sources, low-side ISOURCE Select™ power switches, digital I/O port, and temperature sensor. The 24-Bit No Missing Codes—Main ADC 24-bit main channel with PGA accepts fully differential, unipolar, 13-Bit p-p Resolution @ 20 Hz, 20 mV Range and bipolar input signal ranges from 1.024 × REFIN1/128 to 18-Bit p-p Resolution @ 20 Hz, 2.56 V Range 1.024 × REFIN1. Signals can be converted directly from a trans- INTERFACE ducer without the need for signal conditioning. The 16-bit auxiliary 3-Wire Serial channel has an input signal range of REFIN2 or REFIN2/2. ® SPI , QSPI™, MICROWIRE™, and DSP Compatible The device operates from a 32 kHz crystal with an on-chip Schmitt Trigger on SCLK PLL generating the required internal operating frequency. The POWER output data rate from the part is software programmable. The Specified for Single 3 V and 5 V Operation peak-to-peak resolution from the part varies with the programmed Normal: 1.5 mA Typ @ 3 V gain and output data rate. Power-Down: 10 �A (32 kHz Crystal Running) The part operates from a single 3 V or 5 V supply. When oper- ON-CHIP FUNCTIONS ating from 3 V supplies, the power dissipation for the part is Rail-Rail Input Buffer and PGA 4.5 mW with both ADCs enabled and 2.85 mW with only the 4-Bit Digital I/O Port main ADC enabled in unbuffered mode. The AD7719 is housed On-Chip Temperature Sensor in 28-lead SOIC and TSSOP packages. Dual Switchable Excitation Current Sources Low-Side Power Switches Reference Detect Circuit FUNCTIONAL BLOCK DIAGRAM DV REFIN1(+) REFIN1(–) XTAL1 XTAL2 DD DGND AV DD REFERENCE IEXC1 OSC. AND IEXC2 DETECT AD7719 200�A PLL 200�A IOUT1 DOUT IOUT2 SERIAL DIN AV MAIN CHANNEL INTERFACE DD AIN1 SCLK 24-BIT �-� ADC AND AIN2 CS CONTROL MUX1 BUF PGA RDY AIN3 LOGIC RESET AIN4 AV DD AGND I/O PORT AIN5 AUXILIARY CHANNEL MUX2 MUX AIN6 16-BIT �-� ADC TEMP SENSOR AV AGND REFIN2 PWRGND P1/SW1 P2/SW2 P3 P4 DD REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD7719 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Main ADC Offset Calibration Coefficient Registers (OF0): GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 (A3, A2, A1, A0 = 1, 0, 0, 0; SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Power-On Reset = 0x80 0000) . . . . . . . . . . . . . . . . . . . 26 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 Aux ADC Offset Calibration Coefficient Registers (OF1): ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 (A3, A2, A1, A0 = 1, 0, 0, 1; TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 7 Power-On Reset = 0x8000) . . . . . . . . . . . . . . . . . . . . . 26 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Main ADC Gain Calibration Coefficient Registers (GNO): PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 (A3, A2, A1, A0 = 1, 0, 1, 0; PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 Power-On Reset = 0x5X XXX5) . . . . . . . . . . . . . . . . . 26 TYPICAL PERFORMANCE CHARACTERISTICS . . . . 11 Aux ADC Gain Calibration Coefficient Registers (GN1): DUAL-CHANNEL ADC CIRCUIT INFORMATION . . . 12 (A3, A2, A1, A0 = 1, 0, 1, 1; Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-On Reset = 0x59XX) . . . . . . . . . . . . . . . . . . . . . 26 Main Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Auxiliary Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-On Reset = 0x0X) . . . . . . . . . . . . . . . . . . . . . . . 26 Both Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 User Nonprogrammable Test Registers . . . . . . . . . . . . . . 26 MAIN AND AUXILIARY ADC NOISE CONFIGURING THE AD7719 . . . . . . . . . . . . . . . . . . . . . 27 PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MICROCOMPUTER/MICROPROCESSOR ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Communications Register AD7719-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 29 (A3, A2, A1, A0 = 0, 0, 0, 0) . . . . . . . . . . . . . . . . . . . . 19 AD7719-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 29 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; AD7719-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 30 Power-On Reset = 0x00) . . . . . . . . . . . . . . . . . . . . . . . 20 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 30 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-On Reset = 0x00) . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 32 Operating Characteristics when Addressing the Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 32 Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . 22 Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Main ADC Control Register (AD0CON): Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 (A3, A2, A1, A0 = 0, 0, 1, 0; Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power-On Reset = 0x07) . . . . . . . . . . . . . . . . . . . . . . . 22 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Aux ADC Control Registers (AD1CON): Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 (A3, A2, A1, A0 = 0, 0, 1, 1; Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On Reset = 0x01) . . . . . . . . . . . . . . . . . . . . . . . 23 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On Reset = 0x45) . . . . . . . . . . . . . . . . . . . . . . . 24 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O and Current Source Control Register (IOCON): ADC Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 (A3, A2, A1, A0 = 0, 1, 1, 1; Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On Reset = 0x0000) . . . . . . . . . . . . . . . . . . . . . 24 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Main ADC Data Result Registers (DATA0): APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 (A3, A2, A1, A0 = 0, 1, 0, 1; Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Power-On Reset = 0x00 0000) . . . . . . . . . . . . . . . . . . . 26 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 36 Aux ADC Data Result Registers (DATA1): 3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 37 (A3, A2, A1, A0 = 0, 1, 1, 0; Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power-On Reset = 0x0000) . . . . . . . . . . . . . . . . . . . . . 26 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 39 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 –2– REV. A 1 AD7719–SPECIFICATIONS (AV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DD DD REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T to T , unless otherwise noted.) MIN MAX Parameter AD7719B Unit Test Conditions ADC CHANNEL SPECIFICATION Output Update Rate 5.4 Hz min Both Channels Synchronized 105 Hz max 0.732 ms Increments MAIN CHANNEL 2 No Missing Codes 24 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate 18 Bits p-p ±2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables II to V 21 × .024 REFIN1 Integral Nonlinearity ±10 ppm of FSR max Typically 2 ppm. FSR = 3 Gain Offset Error ±3 µV typ 4 Offset Error Drift vs. Temperature ±10 nV/°C typ 5, 6, 7 Full-Scale Error ±10 µV typ At the Calibrated Conditions 4 Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection (PSR) 80 dB min Input Range = ±2.56 V, 100 dB typ. 110 dB typ on ±20 mV Range ANALOG INPUTS Differential Input Voltage Ranges ±1.024 × REFIN1/GAIN V nom REFIN1 = REFIN1(+) – REFIN1(–) GAIN = 1 to 128. ADC Range Matching ±2 µV typ Input Voltage = 19 mV on All Ranges Absolute AIN Voltage Limits AGND + 100 mV V min BUF = 0; Buffered Mode of Operation AV – 100 mV V max DD 2 Analog Input Current BUF = 0 DC Input Current ±1 nA max DC Input Current Drift ±5 pA /°C typ Absolute AIN Voltage Limits AGND – 30 mV V min BUF = 1; Unbuffered mode of operation. AV + 30 mV V max DD Analog Input Current BUF = 1. Unbuffered Mode of Operation. DC Input Current ±125 nA/V typ Input Current Varies with Input Voltage DC Input Current Drift ±2 pA/V/°C typ 2, 8 Normal-Mode Rejection @ 50 Hz 100 dB min 50 Hz ± 1 Hz, 16.65 Hz Update Rate, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68 Common-Mode Rejection @ DC 90 dB min Input Range = ±2.56 V, AIN = 1 V. 100 dB typ. 110 dB typ on ±20 mV Range 2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V 2 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V REFERENCE INPUT (REFIN1) REFIN1 Voltage 2.5 V nom REFIN1 = REFIN1(+) – REFIN1(–) 2 REFIN1 Voltage Range 1V min AV V max DD REFIN1 Common-Mode Range AGND – 30 mV V min AV + 30 mV V max DD Reference DC Input Current 0.5 µA/V typ Reference DC Input Current Drift ±0.01 nA/V/°C typ 2, 8 Normal-Mode Rejection @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF = 68 Common-Mode Rejection @ DC 110 dB typ Input Range = ±2.56 V, AIN = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V Reference Detect Levels 0.3 V min NOXREF Bit Active if VREF < 0.3 V 0.65 V max NOXREF Bit Inactive if VREF > 0.65 V AUXILIARY CHANNEL 2 No Missing Codes 16 Bits min Resolution 16 Bits p-p ±2.5 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables VI and VIII Integral Nonlinearity ±15 ppm of FSR max REV. A –3– AD7719 Parameter AD7719B Unit Test Conditions AUXILIARY CHANNEL (continued) 3 Offset Error ±3 µV typ Selected Channel = AIN5/AIN6 4 Offset Error Drift vs. Temperature ±10 nV/°C typ 6, 7 Full-Scale Error ±0.75 LSB typ 4 Gain Drift vs. Temperature 0.5 ppm/°C typ Negative Full-Scale Error ±1 LSB typ Power Supply Rejection (PSR) 70 dB min AIN= 1 V Input Range = ±2.5 V, Typically 80 dB ANALOG INPUTS Differential Input Voltage Ranges ±REFIN2 V nom ARN = 1 ±REFIN2/2 V nom ARN = 0 Absolute AIN Voltage Limits AGND – 30 mV V min Unbuffered Input AV + 30 mV V max DD Analog Input Current DC Input Current ±125 nA/V typ Input Current Varies with Input Voltage DC Input Current Drift ±2 pA/V/°C typ 2, 8 Normal-Mode Rejection @ 50 Hz 100 dB min 50 Hz ±1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ±1 Hz, SF = 68 Common-Mode Rejection @ DC 85 dB min Input Range = ±2.5 V, AIN = 1 V 2 @ 50 Hz 90 dB min 50 Hz ±1 Hz, Range = 2.5 V, AIN = 1 V 2 @ 60 Hz 90 dB min 60 Hz ±1 Hz, Range = 2.5 V, AIN = 1 V REFERENCE INPUT (REFIN2) With Respect to AGND REFIN2 Voltage 2.5 V nom 2 REFIN2 Range 1V min AV V max DD 2 Reference DC Input Current 0.2 µA/V typ Reference DC Input Current Drift 0.003 nA/V/°C typ EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current 200 µA nom Initial Tolerance at 25°C ±10 % typ Drift 200 ppm/°C typ Initial Current Matching at 25°C±1% typ Matching between IEXC1 and IEXC2 No Load Drift Matching 20 ppm/°C typ Line Regulation (AV ) 2.1 µA/V max AV = 5 V ± 5%. Typically 1.25 µA/V DD DD Load Regulation 300 nA/V typ Output Compliance AVDD – 0.6 V max AGND – 30 mV V min LOW-SIDE POWER SWITCHES (SW1, SW2) R 5 Ω max AV = 5 V. Typically 3 Ω ON DD 7 Ω max AV = 3 V. Typically 4.5 Ω DD 2 Allowable Current 20 mA max Continuous Current per Switch TEMPERATURE SENSOR Accuracy See TPC 5 °C typ TRANSDUCER BURNOUT AIN(+) Current –100 nA typ AIN(–) Current 100 nA typ Initial Tolerance @ 25°C ±15 % typ Drift 0.03 %/°C typ 2, 9 SYSTEM CALIBRATION 10 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max REV. A –4– AD7719 Parameter AD7719B Unit Test Conditions LOGIC INPUTS 2 All Inputs Except SCLK and XTAL1 V , Input Low Voltage 0.8 V max DV = 5 V INL DD 0.4 V max DV = 3 V DD V , Input High Voltage 2.0 V min DV = 3 V or 5 V INH DD 2 SCLK Only (Schmitt-Triggered Input) V 1.4/2 V min/V max DV = 5 V T(+) DD V 0.8/1.4 V min/V max DV = 5 V T(–) DD V – V 0.3/0.85 V min/V max DV = 5 V T(+) T(–) DD V 0.95/2 V min/V max DV = 3 V T(+) DD V 0.4/1.1 V min/V max DV = 3 V T(–) DD V – V 0.3/0.85 V min/V max DV = 3 V T(+) T(–) DD 2 XTAL1 Only V , Input Low Voltage 0.8 V max DV = 5 V INL DD V , Input High Voltage 3.5 V min DV = 5 V INH DD V , Input Low Voltage 0.4 V max DV = 3 V INL DD V , Input High Voltage 2.5 V min DV = 3 V INH DD Input Currents ±10 µA max V = DV IN DD –70 µA max V = DGND, Typically –40 µA at 5 V IN and –20 µA at 3 V 2 Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2) 2 V , Output High Voltage DV – 0.6 V min DV = 3 V, I = 100 µA OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max DV = 3 V, I = 100 µA OL DD SINK 2 V , Output High Voltage 4V min DV = 5 V, I = 200 µA OH DD SOURCE 2 V , Output Low Voltage 0.4 V max DV = 5 V, I = 1.6 mA OL DD SINK Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance ±10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode 11 I/O PORT I/O Port Voltages Are with Respect to and AGND AV DD 2 V , Input Low Voltage 0.8 V max AV = 5 V INL DD = 3 V 0.4 V max AV DD 2 V , Input High Voltage 2.0 V min AV = 3 V or 5 V INH DD = AV Input Currents ±10 µA max V IN DD –70 µA max V = AGND, Typically –40 µA at AV = 5 V IN DD = 3 V and –20 µA at AV DD Input Capacitance 10 pF typ All Digital Inputs 2 , Output High Voltage AV – 0.6 V min AV = 3 V, I = 100 µA V OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max AV = 3 V, I = 100 µA OL DD SINK 2 , Output High Voltage 4V min AV = 5 V, I = 200 µA V OH DD SOURCE 2 V , Output Low Voltage 0.4 V max AV = 5 V, I = 1.6 mA OL DD SINK Floating-State Output Leakage Current ±10 µA max Floating-State Output Capacitance ±10 pF typ START-UP TIME From Power-On 300 ms typ From Idle Mode 1 ms typ From Power-Down Mode 1 ms typ Osc. Active in Power-Down 300 ms typ Osc. Powered Down POWER REQUIREMENTS Power Supply Voltages AV – AGND 2.7/3.6 V min/max AV = 3 V nom DD DD 4.75/5.25 V min/max AV = 5 V nom DD DV – DGND 2.7/3.6 V min/max DV = 3 V nom DD DD 4.75/5.25 V min DV = 5 V nom DD Power Supply Currents 12 DI Current (Normal Mode) 0.6 mA max DV = 3 V, 0.5 mA typ DD DD 0.75 mA max DV = 5 V, 0.6 mA typ DD REV. A –5– AD7719 Parameter AD7719B Unit Test Conditions Power Supply Currents (Continued) AI Current (Main ADC) 1.1 mA max AV = 3 V or 5 V, Buffered Mode, DD DD 0.85 mA typ 0.55 mA max AV = 3 V or 5 V, Unbuffered Mode, DD 0.45 mA typ AI Current (Aux ADC) 0.3 mA max AV = 3 V or 5 V, 0.25 mA typ DD DD Current (Main and Aux ADC) 1.25 mA max AV = 3 V or 5 V, Main ADC Buffered, AI DD DD 1 mA typ 13 (ADC Disable Mode) 0.35 mA max DV = 3 V, 0.25 mA typ DI DD DD 0.4 mA max DV = 5 V, 0.3 mA typ DD (ADC Disable Mode) 0.15 mA max AV = 3 V or 5 V AI DD DD DI (Power-Down Mode) 10 µA max DV = 3 V, 32.768 kHz Osc. Running DD DD = 3 V, Oscillator Powered Down 2 µA max DV DD 30 µA max DV = 5 V, 32.768 kHz Osc. Running DD = 5 V, Oscillator Powered Down 8 µA max DV DD AI (Power-Down Mode) 1 µA max AV = 3 V or 5 V DD DD NOTES 1 Temperature range –40°C to +85°C. 2 Guaranteed by design and/or characterization data on production release. 3 System zero calibration will remove this error. 4 A calibration at any temperature will remove this drift error. 5 The main ADC is factory-calibrated with AV = DV = 4 V, T = 25°C, REFIN1(+) – REFIN1(–) = 2.5 V. If the user power supplies or temperature conditions DD DD A are significantly different from these, internal full-scale calibration will restore this error to the published specification. System calibration can be used to reduce this error to the order of the noise. Full-scale error applies to both positive and negative full scale. 6 A system full-scale calibration will remove this error. 7 A typical gain error of ±10 µV results following a user self-calibration. 8 Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.8 Hz (SF = 69) update rate. Normal mode rejection in this case is 60 dB min. 9 After a calibration if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 10 FS = Full-Scale Input. FS = 1.024 × REFIN1/Gain on the main ADC, where REFIN1 = REFIN1(+) – REFIN1(–). FS = REFIN2 on the aux ADC when ARN = 1 in the aux ADC control register (AD1CON) and REFIN2/2 on the aux ADC when ARN = 0. 11 Input and output levels on the I/O Port are with respect to AV and AGND. DD 12 Normal mode refers to the case where both main and aux ADCs are running. 13 ADC disable is entered by setting both the AD0EN and AD1EN bits in the main and aux ADC control registers to a 0 and setting the mode bits (MD2, MD1, MD0) in the mode register to non-0. Specifications subject to change without notice. 1 ABSOLUTE MAXIMUM RATINGS Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C (T = 25°C, unless otherwise noted.) A SOIC Package θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 71.4°C/W AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V JA DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 23°C/W AV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V JC DD TSSOP Package DV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 97.9°C/W DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V JA DD 2 θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14°C/W AGND to DGND . . . . . . . . . . . . . . . . . . . –20 mV to +20 mV JC Lead Temperature, Soldering PWRGND to AGND . . . . . . . . . . . . . . . . –20 mV to +20 mV Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V DD DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Analog Input Voltage to AGND . . . . –0.3 V to AV +0.3 V DD Reference Input Voltage to AGND . . –0.3 V to AV +0.3 V DD NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA nent damage to the device. This is a stress rating only; functional operation of the Digital Input Voltage to DGND . . . . –0.3 V to DV +0.3 V DD device at these or any other conditions above those listed in the operational Digital Output Voltage to DGND . . . –0.3 V to DV +0.3 V DD sections of this specification is not implied. Exposure to absolute maximum rating Operating Temperature Range . . . . . . . . . . . –40°C to +85°C conditions for extended periods may affect device reliability. 2 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C AGND and DGND are connected internally within the AD7719. ORDERING GUIDE Model Temperature Range Package Description Package Option AD7719BR –40°C to +85°C SOIC R-28 AD7719BRU –40°C to +85°CTSSOP RU-28 EVAL-AD7719EB Evaluation Board REV. A –6– AD7719 1, 2 (AV = 2.7 V to 3.6 V or AV = 4.75 V to 5.25 V; DV = 2.7 V to 3.6 V or DV = 4.75 V to 5.25 V; TIMING CHARACTERISTICS DD DD DD DD AGND = DGND = 0 V; X = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV , unless otherwise noted.) TAL DD Limit at T , T MIN MAX Parameter (B Version) Unit Conditions/Comments t 32.768 kHz typ Crystal Oscillator Frequency 1 t 50 ns min RESET Pulsewidth 2 Read Operation 0 ns min RDY to CS Setup Time t 3 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 4 4 3 t 0 ns min SCLK Active Edge to Data Valid Delay 5 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD 4, 5 3 t 0 ns min CS Falling Edge to Data Valid Delay 5A 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t 100 ns min SCLK High Pulsewidth 6 100 ns min SCLK Low Pulsewidth t 7 3 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 8 6 3 t 10 ns min Bus Relinquish Time after SCLK Inactive Edge 9 80 ns max 3, 7 t 100 ns max SCLK Active Edge to RDY High 10 Write Operation 3 0 ns min CS Falling Edge to SCLK Active Edge Setup Time t 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 100 ns min SCLK High Pulsewidth t 14 t 100 ns min SCLK Low Pulsewidth 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. R F DD 2 See Figures 2 and 3. 3 SCLK active edge is falling edge of SCLK. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5 This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after a read of both ADCs. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice. I (1.6mA WITH DV = 5V SINK DD 100�A WITH DV = 3V) DD TO OUTPUT PIN 1.6V 50pF I (200�A WITH DV = 5V SOURCE DD 100�A WITH DV = 3V) DD Figure 1. Load Circuit for Timing Characterization CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. A –7– AD7719 DIGITAL INTERFACE of the output register to indicate when not to read from the device As previously outlined, the AD7719’s programmable functions are to ensure that a data read is not attempted while the register is controlled using a set of on-chip registers. Data is written to these being updated. CS is used to select the device. It can be used to registers via the part’s serial interface; read access to the on-chip decode the AD7719 in systems where a number of parts are registers is also provided by this interface. All communications to connected to the serial bus. the part must start with a write operation to the Communications Figures 2 and 3 show timing diagrams for interfacing to the register. After power-on or RESET, the device expects a write to AD7719 with CS used to decode the part. Figure 3 is for a read its Communications register. The data written to this register operation from the AD7719’s output shift register while Figure 2 determines whether the next operation to the part is a read or a shows a write operation to the input shift register. It is possible write operation and also determines to which register this read to read the same data twice from the output register even though or write operation occurs. Therefore, write access to any of the the RDY line returns high after the first read operation. Care must other registers on the part starts with a write operation to the be taken, however, to ensure that the read operations have been Communications register followed by a write to the selected completed before the next output update is about to take place. register. A read operation from any other register on the part The AD7719 serial interface can operate in 3-wire mode by tying (including the output data register) starts with a write operation the CS input low. In this case, the SCLK, DIN, and DOUT lines to the Communications register followed by a read operation are used to communicate with the AD7719, and the status of from the selected register. RDY bits (RDY0 and RDY1) can be obtained by interrogating The AD7719’s serial interface consists of five signals: CS, SCLK, the STATUS register. This scheme is suitable for interfacing to DIN, DOUT, and RDY. The DIN line is used for transferring microcontrollers. If CS is required as a decoding signal, it can data into the on-chip registers while the DOUT line is used for be generated from a port bit. For microcontroller interfaces, it is accessing data from the on-chip registers. SCLK is the serial recommended that the SCLK idles high between data transfers. clock input for the device, and all data transfers (either on DIN The AD7719 can also be operated with CS used as a frame syn- or DOUT) take place with respect to this SCLK signal. The chronization signal. This scheme is suitable for DSP interfaces. RDY line is used as a status signal to indicate when data is ready In this case, the first bit (MSB) is effectively clocked out by CS to be read from the AD7719’s data register. RDY goes low when a since CS would normally occur after the falling edge of SCLK new data-word is available in the output register of either the in DSPs. The SCLK can continue to run between data transfers main or aux ADCs. It is reset high when a read operation from provided the timing numbers are obeyed. the data register is complete. It also goes high prior to the updating CS t 11 t t 14 16 SCLK t 15 t 12 t 13 DIN MSB LSB Figure 2. Write Cycle Timing Diagram RDY t t 3 10 CS t 8 t t 4 6 SCLK t t 7 6 t 5 t 9 t 5A DOUT MSB LSB Figure 3. Read Cycle Timing Diagram –8– REV. A AD7719 The serial interface can be reset by exercising the RESET input Some microprocessor or microcontroller serial interfaces have a on the part. It can also be reset by writing a series of 1s on the single serial data line. In this case, it is possible to connect the DIN input. If a logic 1 is written to the AD7719 DIN line for at AD7719’s DATA OUT and DATA IN lines together and connect least 32 serial clock cycles, the serial interface is reset. This ensures them to the single data line of the processor. A 10 kΩ pull-up that in 3-wire systems, if the interface gets lost, either via a software resistor should be used on this single data line. In this case, if the error or by some glitch in the system, it can be reset back to a interface gets lost, because the read and write operations share known state. This state returns the interface to where the AD7719 the same line, the procedure to reset it to a known state is is expecting a write operation to its Communications register. This somewhat different than previously described. It requires a read operation resets the contents of all registers to their power-on operation of 24 serial clocks followed by a write operation where reset values. a logic 1 is written for at least 32 serial clock cycles to ensure that the serial interface is back in a known state. PIN CONFIGURATION 1 IOUT1 XTAL1 28 2 IOUT2 XTAL2 27 AV 3 DV DD 26 DD AGND 4 DGND 25 REFIN1(–) 5 DIN 24 AD7719 REFIN1(+) 6 23 DOUT TOP VIEW (Not to Scale) AIN1 7 22 RDY AIN2 8 21 CS AIN3 9 20 SCLK AIN4 10 19 RESET AIN5 11 P1/SW1 18 AIN6 12 PWRGND 17 REFIN2 13 16 P2/SW2 P4 14 15 P3 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 IOUT1 Output for Internal 200 µA Excitation Current Source. Current source IEXC1 and/or IEXC2 can be switched to this output. 2 IOUT2 Output for Internal 200 µA Excitation Current Source. Current source IEXC1 and/or IEXC2 can be switched to this output. 3AV Analog Supply Voltage. DD 4 AGND Analog Ground. 5 REFIN1(–) Negative Reference Input for Main ADC Channel. This reference input can lie anywhere between AGND and AV – 1 V. DD 6 REFIN1(+) Positive Reference Input for Main ADC Channel. REFIN1(+) can lie anywhere between AV and DD AGND + 1 V. The nominal reference voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to AV . DD 7 AIN1 Analog Input. AIN1 is dedicated to the main channel. 8 AIN2 Analog Input. AIN2 is dedicated to the main channel. 9 AIN3 Analog Input. AIN3 can be multiplexed to either the main or auxiliary channel. 10 AIN4 Analog Input. AIN4 can be multiplexed to either the main or auxiliary channel. 11 AIN5 Analog Input. AIN5 is dedicated to the auxiliary channel and is referenced to AIN6 or AGND. 12 AIN6 Analog Input. AIN6 is dedicated to the auxiliary channel. It forms a differential input pair with AIN5 in fully differential input mode or is referenced to AGND in pseudodifferential mode. 13 REFIN2 Single-Ended Reference Input for Auxiliary Channel. The nominal input reference is 2.5 V. The auxiliary channel will function with an input reference range from 1 V to AV . DD 14 P4 General-Purpose I/O Bit. The input and output voltage levels are referenced to AV and AGND. DD 15 P3 General-Purpose I/O Bit. The input and output voltage levels are referenced to AV and AGND. DD REV. A –9– AD7719 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function 16 P2/SW2 Dual-Purpose Pin. It can act as a general-purpose output (P2) bit referenced between AV and AGND DD or as a low-side power switch (SW2) to PWRGND. 17 PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND. 18 P1/SW1 Dual-Purpose Pin. It can act as a general-purpose output (P1) bit referenced between AV and AGND DD or as a low-side power switch (SW1) to PWRGND. 19 RESET Digital Input Used to Reset the ADC to Its Power-On Reset Status. This pin has a weak pull-up internally to DV . DD 20 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7719 in smaller batches of data. A weak pull-up to DV DD is provided on the SCLK input. 21 CS Chip Select Input. This is an active low logic input used to select the AD7719. CS can be used to select the AD7719 in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the AD7719 to be operated in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to DV is provided DD on the CS input. 22 RDY RDY is a logic low status output from the AD7719. RDY is low if either the main ADC or auxiliary ADC channel has valid data in its data register. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update, indicating to the user that a read operation should not be initiated. The RDY pin also returns low following the completion of a calibration cycle. The RDY pin is effectively the digital NOR function of the RDY0 and RDY1 bits in the Status register. If one of the ADCs is disabled, the RDY pin reflects the active ADC. RDY does not return high after a calibration until the mode bits are written to, enabling a new conversion or calibration. Since the RDY pin provides information on both the main and aux ADCs, when either the main or aux ADC is disabled, it is recommended to immediately read its data register to ensure that its RDY bit goes inactive and releases the RDY pin to indicate output data updates on the remaining active ADC. 23 DOUT Serial Data Output Accessing the Output Shift Register of the AD7719. The output shift register can contain data from any of the on-chip data, calibration, or control registers. 24 DIN Serial Data Input Accessing the Input Shift Register on the AD7719. Data in this shift register is transferred to the calibration or control registers within the ADC depending on the selection bits of the Communications register. A weak pull-up to DV is provided on the DIN input. DD 25 DGND Ground Reference Point for the Digital Circuitry. 26 DV Digital Supply Voltage, 3 V or 5 V Nominal. DD 27 XTAL2 Output from the 32 kHz Crystal Oscillator Inverter. 28 XTAL1 Input to the 32 kHz Crystal Oscillator Inverter. –10– REV. A Typical Performance Characteristics–AD7719 8389600 26 8389400 24 8389200 8389000 22 8388800 20 8388600 8388400 18 8388200 16 8388000 0 100 200 300 400 500 600 700 800 900 1000 04 10 20 300 50 60 70 80 90 100 110 READING NO. UPDATE RATE (Hz) MAIN ADC IN BUFFERED MODE AV = DV = 5V DD DD RMS NOISE = 0.58�V rms INPUT RANGE = �20mV T = 25�C REFIN1(+)–REFIN1(–) = 2.5V A UPDATE RATE = 19.79Hz V = 2.5V REF TPC 4. No-Missing-Codes Performance TPC 1. Typical Noise Plot on ±20 mV Input Range with 19.79 Hz Update Rate 1400 9 THE AMBIENT TEMPERATURE VARIES 8 1200 FROM 25�C TO 30�C WHILE RECORDING 7 THE DATA FROM 1000 THE DEVICES. 6 800 5 4 600 3 400 2 200 1 0 0 10 20 30 40 50 TEMPERATURE SENSOR ( C) TPC 5. Temperature Sensor Accuracy TPC 2. Noise Distribution Histogram 3.0 1200 �2.56V RANGE 2.5 1000 2.0 800 AV = DV = 5V DD DD V = 2.5V REF 1.5 INPUT RANGE = �2.56V 600 UPDATE RATE = 19.79Hz T = 25�C A �20mV RANGE 1.0 400 0.5 200 0 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –30 –20 –10 0 10 20 V (V) MAIN CAL ACC. @ 4V (�V) REF TPC 6. Full-Scale Error Distribution TPC 3. RMS Noise vs. Reference Input REV. A –11– CODE READ RMS NOISE (�V) 8388039 8388382 8388449 8388499 8388547 8388579 8388615 8388657 8388687 8388721 8388754 8388779 8388805 8388841 8388874 8388906 8388941 8388985 8389033 8389110 HITS HITS NO MISSING CODES (Min) AD7719 converts the sampled input signal into a digital pulse train whose AV = DV = 5V DD DD 3 T = 25�C duty cycle contains the digital information. A Sinc programmable A low-pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at program- V DD mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping scheme is also employed to minimize ADC channel offset errors. A block diagram of the main ADC OSCILLATOR input channel is shown in Figure 4. The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. The integrator in the modulator shapes the TIME BASE = 100ms/DIV quantization noise (which results from the analog-to-digital TRACE 1 = TRACE 2 = 2V/DIV conversion) so that the noise is pushed toward one-half of the modulator frequency. The output of the Σ-∆ modulator feeds directly into the digital filter. The digital filter then band-limits TPC 7. Typical Oscillator Power-Up the response to a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output 3 from the AD7719 ADC. The AD7719 filter is a low-pass, Sinc , 3 or (SIN(x)/x) filter whose primary function is to remove the DUAL-CHANNEL ADC CIRCUIT INFORMATION quantization noise introduced at the modulator. The cutoff Overview frequency and decimated output data rate of the filter are pro- The AD7719 incorporates two independent Σ-∆ ADC channels grammable via the SF word loaded to the filter register. (main and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals A chopping scheme is employed where the complete signal chain is such as those in weigh-scale, strain gage, pressure transducer, or chopped, resulting in excellent dc offset and offset drift specifi- temperature measurement applications. cations, and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors. Main Channel With chopping, the ADC repeatedly reverses its inputs. The This channel is intended to convert the primary sensor input. 3 decimated digital output words from the Sinc filters therefore This channel can be operated in buffered or unbuffered mode, and have a positive offset and negative offset term included. As a result, can be programmed to have one of eight input voltage ranges a final summing stage is included so that each output word from from ±20 mV to ±2.56 V. This channel can be configured as the filter is summed and averaged with the previous filter output either two fully differential inputs (AIN1/AIN2 and AIN3/AIN4) to produce a new valid output result to be written to the ADC or three pseudodifferential input channels (AIN1/AIN4, AIN2/ data register. AIN4, and AIN3/AIN4). Buffering the input channel means that the part can accommodate significant source impedances on the Auxiliary Channel analog input and that R, C filtering (for noise rejection or RFI The Auxiliary (Aux) channel is intended to convert supplementary reduction) can be placed on the analog inputs if required. Operat- inputs such as those from a cold junction diode or thermistor. ing in unbuffered mode leads to lower power consumption in low This channel is unbuffered and has an input range of ±REFIN2 power applications, but care must be exercised in unbuffered mode or ±REFIN2/2, determined by the ARN bit in the auxiliary ADC because source impedances can introduce gain errors. The main control register (AD1CON). AIN3 and AIN4 can be multiplexed ADC also features sensor burnout currents that can be switched into the auxiliary channel as single-ended inputs with respect to on and off. These currents can be used to check that a transducer AGND, while AIN5 and AIN6 can operate as a differential is still operational before attempting to take measurements. input pair. With AIN6 tied to AGND, AIN5 can be operated as an additional single-ended input. A block diagram of the auxiliary The ADC employs a Σ-∆ conversion technique to realize up to ADC channel is shown in Figure 5. 24 bits of no-missing-codes performance. The Σ-∆ modulator f f f f f CHOP IN MOD CHOP ADC 3 �-� ANALOG 1 1 DIGITAL MUX PGA XOR 3 � (8 � SF ) � BUF � ( ) INPUT 2 OUTPUT 8 � SF MOD0 3 SINC FILTER A + V OS IN A – V IN OS Figure 4. Main ADC Channel Block Diagram –12– REV. A AD7719 f f f f CHOP MOD CHOP ADC �-� 3 1 ANALOG 1 DIGITAL MUX XOR � 3 � (8 � SF ) � ( ) 2 INPUT 8 � SF OUTPUT MOD1 3 SINC FILTER A + V OS IN A – V IN OS Figure 5. Auxiliary ADC Channel Block Diagram at odd integer multiples of f /2. The 3 dB frequency for all Both Channels ADC values of SF obeys the following equation: The operation of the aux channel is identical to the main channel with the exception that there is no PGA on the aux fd30 B=× .24 f () ADC channel. The input chopping is incorporated into the input multiplexer while the output chopping is accomplished by an The signal chain is chopped as shown in Figures 4 and 5. The XOR gate at the output of the modulator. The chopped modulator chop frequency is 3 bit stream is applied to a Sinc filter. The programming of the 3 Sinc decimation factor is restricted to an 8-bit register SF; the  f  ADC f = CHOP   actual decimation factor is the register value times 8. The  2  3 decimated output rate from the Sinc filter (and the ADC 3 conversion rate) will therefore be As shown in the block diagram, the Sinc filter outputs alternately contain +V and –V , where V is the respective channel OS OS OS 1  1  offset. This offset is removed by performing a running average f =× × f ADC MOD   of 2. This average by 2 means that the settling time to any change 3 8 × SF   in programming of the ADC will be twice the normal conversion where: time, while an asynchronous step change on the analog input will not be fully reflected until the third subsequent output. f is the ADC update rate. ADC SF is the decimal equivalent of the word loaded to the  2  t = =× 2 t SETTLE   ADC filter register.  f  ADC f is the modulator sampling rate of 32.768 kHz. MOD The allowable range for SF is 13 to 255, with a default of 69 Programming the filter register determines the update rate for (0x45). The corresponding conversion rates, conversion times, both the main and aux ADC. Both ADCs operate with the same and settling times are tabulated in Table I. Note that the con- update rate. version time increases by 0.732 ms for each increment in SF. The chop rate of the channel is half the output data rate. Table I. ADC Conversion and Settling Times for Various The frequency response of the filter H (f) is as follows: SF Words 3  1 sin (SF××81 π× f / f )   sin (2×× π ff / )  MOD OUT × ××     SF Data Update Rate Settling Time  SF × 8 sin (π ×ff / )   2 sin (π ×ff / )  MOD OUT Word f (Hz) t (ms) ADC SETTLE where: 13 105.3 19.04 f = 32,768 Hz MOD 69 (Default) 19.79 101.07 SF = value programmed into SF SFR. 255 5.35 373.54 f = f /(SF × 8 × 3) OUT MOD Normal mode rejection is the major function of the digital filter The following shows plots of the filter frequency response for on the AD7719. The normal mode 50 Hz ± 1 Hz rejection with an the SF words shown in Table I. The overall frequency response SF word of 82 is typically –100 dB. The 60 Hz ± 1 Hz rejec- 3 3 is the product of a Sinc and a sinc response. There are Sinc tion with SF = 68 is typically –100 dB. Simultaneous 50 Hz and notches at integer multiples of 3 × f and there are sinc notches ADC 60 Hz rejection of better than 60 dB is achieved with an SF of 69. Choosing an SF word of 69 places notches at both 50 Hz and 60 Hz. Figures 6 to 9 show the filter rejection for a selec- tion of SF words. REV. A –13– AD7719 0 0 –20 –20 –40 –40 –60 –60 –80 –100 –80 –120 –100 –140 –120 –160 –140 –180 –200 –160 700 0 50 100 150 200 250 300 350 400 450 500 550 600 650 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) FREQUENCY (Hz) SF = 69 SF = 13 OUTPUT DATA RATE = 19.8Hz OUTPUT DATA RATE = 105Hz INPUT BANDWIDTH = 4.74Hz INPUT BANDWIDTH = 25.2Hz FIRST NOTCH = 9.9Hz FIRST NOTCH = 52.5Hz 50Hz REJECTION = –66dB, 50Hz � 1Hz REJECTION = –60dB 50Hz REJECTION = –23.6dB, 50Hz � 1Hz REJECTION = –20.5dB 60Hz REJECTION = –117dB, 60Hz � 1Hz REJECTION = –94dB 60Hz REJECTION = –14.6dB, 60Hz � 1Hz REJECTION = –13.6dB Figure 6. Filter Profile with SF = 13 Figure 8. Filter Profile with Default SF = 69 Giving Filter Notches at Both 50 Hz and 60 Hz 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) FREQUENCY (Hz) SF = 82 SF = 255 OUTPUT DATA RATE = 16.65Hz OUTPUT DATA RATE = 5.35Hz INPUT BANDWIDTH = 4Hz INPUT BANDWIDTH = 1.28Hz 50Hz REJECTION = –171dB, 50Hz � 1Hz REJECTION = –100dB 50Hz REJECTION = –93dB, 50Hz � 1Hz REJECTION = –93dB 60Hz REJECTION = –58dB, 60Hz � 1Hz REJECTION = –53dB 60Hz REJECTION = –74dB, 60Hz � 1Hz REJECTION = –68dB Figure 7. Filter Profile with SF = 82 Figure 9. Filter Profile with SF = 255 MAIN AND AUXILIARY ADC NOISE PERFORMANCE noise in the semiconductor devices (device noise) used in the Tables II to VII show the output rms noise and output peak-to- implementation of the modulator. Secondly, when the analog peak resolution in bits (rounded to the nearest 0.5 LSB) for a input is converted into the digital domain, quantization noise is selection of output update rates on both the main and auxiliary added. The device noise is at a low level and is independent of ADCs. The numbers are typical and are generated at a differential frequency. The quantization noise starts at an even lower level but input voltage of 0 V. The output update rate is selected via the rises rapidly with increasing frequency to become the dominant SF7 to SF0 bits in the Filter register. It is important to note that noise source. The numbers in the tables are given for the bipolar the peak-to-peak resolution figures represent the resolution for input ranges. For the unipolar ranges, the rms noise numbers which there will be no code flicker within a six-sigma limit. The will be the same as the bipolar range, but the peak-to-peak output noise comes from two sources. The first is the electrical resolution is now based on half the signal range, which effectively means losing one bit of resolution. –14– REV. A ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) AD7719 Table II. Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Buffered Mode) Output RMS Noise in �V Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Buffered Mode) Peak-to-Peak Resolution in Bits Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 18.8 19.2 Table IV. Typical Output RMS Noise vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Output RMS Noise in �V Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 1.27 1.27 1.35 1.48 2.95 3.82 5.69 10.2 69 19.79 0.52 0.56 0.56 0.56 0.56 0.82 1.21 2.00 255 5.35 0.30 0.30 0.32 0.32 0.32 0.44 0.71 1.10 Table V. Peak-to-Peak Resolution vs. Input Range and Update Rate for Main ADC (Unbuffered Mode) Peak-to-Peak Resolution in Bits Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 19 19.5 Table VII. Peak-to-Peak Resolution vs. Update Table VI. Typical Output RMS Noise vs. Update Rate for Auxiliary ADC (Unbuffered Mode) Rate for Auxiliary ADC (Unbuffered Mode) SF Data Update Input Range SF Data Update Input Range Word Rate (Hz) �2.5 V Word Rate (Hz) �2.5 V 13 105.3 16 Bits 13 105.3 10.75 µV 69 19.79 16 Bits 69 19.79 2.00 µV 255 5.35 16 Bits 255 5.35 1.15 µV REV. A –15– AD7719 ON-CHIP REGISTERS Both the main and auxiliary ADC channels are controlled and con- figured via a number of on-chip registers as shown in Figure 10 and described in more detail in the following pages. In the following descriptions, SET implies a logic 1 state and CLEARED implies a logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER DIN WEN R/W 00 A3 A2 A1 A0 DOUT DOUT ADC STATUS REGISTER DIN DOUT MODE REGISTER DIN DOUT MAIN ADC CONTROL REGISTER DIN DOUT AUX ADC CONTROL REGISTER DIN DOUT I/O CONTROL REGISTER DIN DOUT FILTER REGISTER REGISTER SELECT DECODER DOUT MAIN ADC DATA REGISTER DOUT AUX ADC DATA REGISTER DIN DOUT MAIN ADC OFFSET REGISTER DIN DOUT AUX ADC OFFSET REGISTER DIN DOUT MAIN ADC GAIN REGISTER DIN DOUT AUX ADC GAIN REGISTER DOUT ID REGISTER DIN DOUT TEST REGISTER Figure 10. On-Chip Registers –16– REV. A AD7719 Table VIII. Registers—Quick Reference Guide Power-On/Reset Register Name Type Size Default Value Function Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through the Communications register. This controls whether MB SB LS subsequent operations are read or write operations and also selects the register for that subsequent WEN R/W 00 A2 3 A1A0 A operation. Status Register Read Only 8 Bits 0x00 Provides status information on conversions, cali- brations, error conditions, and the validity of the MB SB LS reference voltage. R1 DY0RL DYCF AN0 OREE1 RRE0 RR LOCK Mode Register Read/Write 8 Bits 0x00 Controls functions such as mode of operation, channel configuration, and oscillator operation in power-down. MB SB LS 0 BUF0NCD HCOO2 SCPM1 DM0 D MD Main ADC (AD0CON) Control Register Read/Write 8 Bits 0x07 This register is used to enable the main ADC and to configure the main ADC for range, channel selection, MB SB LS 16-/24-bit operation, and unipolar or bipolar operation. AL D0ENW1C0 H C/ H U BR1 N2R0 N RN Aux ADC (AD1CON) Control Register Read/Write 8 Bits 0x01 This register is used to enable the aux ADC and to configure the Aux ADC for range, channel selection, MB SB LS unipolar or bipolar operation, and input range. A2 D1ENA1 CHA0 CHA/ CH U B 00 ARN I/O (IOCON) Control Register Read/Write 16 Bits 0x0000 This register is used to control and configure the various excitation and burnout current source options available on-chip along with controlling the I/O port. MSB P1 SW2P0 SW BN OIN 2PIIN 1PIIN 2E I1E LSB PR 4DIRPN 3DIPN 2EPT 1EPT 4DAPT 3DAPT 2DA P1DA Filter Register Read/Write 8 Bits 0x45 This register determines the amount of averaging performed by the sinc filter and consequently deter- M M MB MBMB S S S S SB B B L LLB LB LS S S S SB B mines the data update rate of the AD7719. The filter register determines the update rate for both the main S6 F7S5 F S4 F S3 F S2 F S1 F S0 F SF and aux ADCs. REV. A –17– AD7719 Power-On/Reset Register Name Type Size Default Value Function Main ADC (DATA0) Data Register Read Only 16 Bits or 24 Bits 0x00 0000 Provides the most up-to-date conversion result from the main ADC. Main ADC data register length can be programmed to be 16-bit or 24-bit. Aux ADC (DATA1) Data Register Read Only 16 Bits 0x0000 Provides the most up-to-date conversion result from the auxiliary ADC. Aux ADC data register length is 16 bits. Main ADC Offset Register Read/Write 24 Bits 0x80 0000 Contains a 24-bit word that is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are three offset registers on the part and these are associated with input channel pairs as outlined in the AD0CON register. Main ADC Gain Register Read/Write 24 Bits 0x5X XXX5 Contains a 24-bit word that is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are three Gain registers on the part, which are associated with input channel pairs as outlined in the AD0CON register. Aux ADC Offset Register Read/Write 16 Bits 0x8000 Contains a 16-bit word that is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. Aux ADC Gain Register Read/Write 24 Bits 0x59XX Contains a 16-bit word that is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. ID Register Read 8 Bits 0x0X Contains an 8-bit byte that is the identifier for the part. Test Registers Read/Write 16 Bits 0x0000 Controls the test modes of the part, which are used when testing the part. The user is advised not to change the contents of these registers. –18– REV. A AD7719 Communications Register (A3, A2, A1, A0 = 0, 0, 2, 0) register. This is the default state of the interface, and on power-up The Communications register is an 8-bit write-only register. All or after a RESET, the AD7719 is in this default state waiting for a communications to the part must start with a write operation to write operation to the Communications register. In situations where the Communications register. The data written to the Commu- the interface sequence is lost, a write operation of at least 32 serial nications register determines whether the next operation is a read clock cycles with DIN high returns the AD7719 to this default or write operation, and to which register this operation takes state by resetting the part. Table IX outlines the bit designations place. For read or write operations, once the subsequent read or for the Communications register. CR0 through CR7 indicate the write operation to the selected register is complete, the interface bit location, with CR denoting that the bits are in the Commu- returns to where it expects a write operation to the Communications nications register. CR7 denotes the first bit of the data stream. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN (0) R/W (0) 0 (0) 0 (0) A3 (0) A2 (0) A1 (0) A0 (0) Table IX. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications register. CR6 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR5 Zero A 0 must be written to this bit position to ensure correct operation of the AD7719. CR4 Zero A 0 must be written to this bit position to ensure correct operation of the AD7719. CR3–CR0 A3–A0 Register Address Bits. These address bits are used to select which of the AD7719’s registers is being accessed during this serial interface communication. A3 is the MSB of the three selection bits. Table X. Register Selection Table A3 A2 A1 A0 Register 0000Communications Register during a Write Operation 0000 Status Register during a Read Operation 0001Mode Register 0010Main ADC Control Register (AD0CON) 0011Aux ADC Control Register (AD1CON) 0100Filter Register 0101Main ADC Data Register 0110Aux ADC Data Register 0111I/O Control Register 1000Main ADC Offset Calibration Register 1001Aux ADC Offset Calibration Register 1010Main ADC Gain Calibration Register 1011Aux ADC Gain Calibration Register 1100Test 1 Register 1101Test 2 Register 1110Undefined 1111ID Register REV. A –19– AD7719 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On bits A3 to A0 with 0, 0, 0, 0. Table XI outlines the bit designations Reset = 0x00) for the Status register. SR0 through SR7 indicate the bit location, The ADC Status register is an 8-bit read-only register. To access with SR denoting that the bits are in the Status register. SR7 the ADC Status register, the user must write to the Communica- denotes the first bit of the data stream. The number in paren- tions register selecting the next operation to be a read and loading theses indicates the power-on/reset default status of that bit. S6 R7 S5 R S4 R S3 R S2 R S1 R S0 R SR R) DY0 (0)R) DY1 (0C) AL (0N) OXREF (0E) RR0 (0E) RR1 (0() 0 LOCK (0 Table XI. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY0 Ready Bit for Main ADC. Set when data is written to main ADC data registers or on completion of calibration cycle. The RDY0 bit is cleared automatically after the main ADC data register has been read or after a period of time before the data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a conversion or calibration. SR6 RDY1 Ready Bit for Aux ADC. Set when data is written to aux ADC data registers or on completion of calibration cycle. The RDY1 bit is cleared automatically after the aux ADC data register has been read or a period of time before the data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a conversion or calibration. SR5 CAL Calibration Status Bit. Set to indicate completion of calibration. It is set at the same time that the RDY0 and/or RDY1 bits are set high. Cleared by a write to the mode bits to start another ADC conversion or calibration. SR4 NOXREF No External Reference Bit. (Only active if main ADC is active and applies to REFIN1 only.) Set to indicate that one or both of the REFIN1 pins is floating or the applied voltage is below a specified threshold. When Set, conversion results are clamped to all 1s. Cleared to indicate valid reference applied between REFIN1(+) and REFIN1(–). SR3 ERR0 Main ADC Error Bit. Set to indicate that the result written to the main ADC data registers has been clamped to all 0s or all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Error sources include Overrange, Underrange, and NOXREF. Cleared by a write to the mode bits to initiate a conversion or calibration. SR2 ERR1 Aux ADC Error Bit. Set to indicate that the result written to the Aux ADC data registers has been clamped to all 0s or all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Error sources include Overrange, Underrange, and NOXREF. Cleared by a write to the mode bits to initiate a conversion or calibration. SR1 0 Reserved for Future Use. SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies, for example, the LOCK bit should be interrogated and the result discarded if the LOCK bit is 0. –20– REV. A AD7719 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On designations for the Mode register. MR7 through MR0 indicate Reset = 0x00) the bit location, with MR denoting the bits are in the Mode register. The Mode register is an 8-bit register from which data can be MR7 denotes the first bit of the data stream. The number in read or to which data can be written. This register configures the parentheses indicates the power-on/reset default status of that bit. operating modes of the AD7719. Table XII outlines the bit M6 R7 M5 R M4 R M3 R M2 R M1 R M0 R MR 0 (0) BF B B BBF U U U U UF F F (0)0) (0)C) HCON (0O) SCPD (0M) D2 (0M) D1 (0 MD0 (0 Table XII. MODE Register Bit Designations Bit Bit Location Name Description MR7 0 Reserved for Future Use. MR6 BUF Configures the main ADC for buffered or unbuffered mode of operation. If set, the main ADC operates in unbuffered mode, lowering the power consumption of the AD7719. If cleared, the Main ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR5 0 Reserved for Future Use. MR4 CHCON Channel Configure Bit. If this bit is set, the main ADC operates with three pseudodifferential input channels and the aux ADC does not have AIN3/AIN4 as an input option. If cleared, the main ADC operates with two fully differential input channels and the aux channel operates as one fully differential input and two single-ended inputs or as three single-ended inputs. MR3 OSCPD Oscillator Power-Down Bit. If this bit is set, placing the AD7719 in standby mode will stop the crystal oscillator, reducing the power drawn by the AD7719 to a minimum. The oscillator will require 300 ms to begin oscillating when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is taken out of standby. MR2–MR0 MD2–MD0 Main and Aux ADC Mode Bits. These bits select the operational mode of the enabled ADC as follows: MD2 MD1 MD0 Description 000Power-Down Mode (Power-On Default). The current sources, power switches, and PLL are shut off in Power-Down mode. 001 Idle Mode. In Idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 010 Single Conversion Mode. In Single Conversion mode, a single conversion is performed on the enabled channels. On completion of the conversion, the ADC data registers are updated, the relevant flags in the STATUS register are written, and idle mode is entered with the MD2–MD0 being written accordingly to 001. 011Continuous Conversion. In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate (see Filter register). 100 Internal Zero-Scale Calibration. Internal short automatically connected to the enabled channel(s). Returns to Idle mode (001) when complete. 101 Internal Full-Scale Calibration. External V is connected automatically to the ADC input for this calibration. Returns to idle mode when complete. REF 110 System Zero-Scale Calibration. User should connect system zero-scale input to the channel input pins as selected by the CH1/CH0 and ACH1/ACH0 bits in the control registers. 111 System Full-Scale Calibration. User should connect system full-scale input to the channel input pins as selected by the CH1/CH0 and ACH1/ACH0 bits in the control registers. REV. A –21– AD7719 Operating Characteristics when Addressing the Mode and calibration commences. On completion, the appropriate calibra- Control Registers tion registers are written, the relevant bits in STATUS are 1. Any change to the MD bits will immediately reset both ADCs. written, and the MD2–0 bits are reset to 001 to indicate the A write to the MD2–0 bits with no change is also treated as a ADC is back in Idle mode. reset. (See exception to this in Note 3.) 5. Any calibration request of the aux ADC while the temperature 2. If AD0CON is written when AD0EN = 1, or if AD0EN is sensor is selected will fail to complete. changed from 0 to 1, both ADCs are also immediately reset. In 6. Calibrations are performed with the maximum allowable SF other words, the main ADC is given priority over the aux ADC value. SF register is reset to user configuration after calibration. and any change requested on main is immediately responded to. Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0, 3. On the other hand, if AD1CON is written to, only the aux 0, 1, 0; Power-On Reset = 0x07) ADC is reset. For example, if the main ADC is continuously The main ADC control register is an 8-bit register from which data converting when the aux ADC change or enable occurs, the can be read or to which data can be written. This register is used to main ADC continues undisturbed. Rather than allow the aux configure the main ADC for range, channel selection, 16-/24-bit ADC to operate with a phase difference from the main ADC, operation, and unipolar or bipolar coding. Table XIII outlines the aux ADC will fall into step with the outputs of the main the bit designations for the main ADC control register. AD0CON7 ADC. The result is that the first conversion time for the aux through AD0CON0 indicate the bit location, AD0CON denoting channel will be delayed up to three outputs while the aux ADC the bits are in the main ADC control register. AD0CON7 denotes update rate is synchronized to the main ADC. the first bit of the data stream. The number in parentheses 4. Once the MODE has been written with a calibration mode, indicates the power-on/reset default status of that bit. the RDY0/1 bits (STATUS) are immediately reset and the A6 D0CON7A5 D0CONA4 D0CONA3 D0CONA2 D0CONA1 D0CONA0 D0CON AD0CON A) D0EN (0)W) L (0C) H1 (0C/ H0 (0 UB() 0)R) N2 (1R) N1 (1 RN0 (1 Table XIII. Main ADC Control Register (AD0CON) Bit Designations Bit Location Bit Name Description AD0CON7 AD0EN Main ADC Enable Bit. Set by user to enable the main ADC. When set, the main ADC operates according to the MD bits in the mode register. Cleared by the user to power down the Main ADC. AD0CON6 WL 16-/24-Bit Operating Mode. Set by user to enable 16-bit mode. The conversion results from the main ADC will be rounded to 16 bits and the main ADC data register will be 16 bits wide. Cleared by user to enable 24-bit mode. The conversion results from the main ADC will be rounded to 24 bits and the main ADC data register will be 24 bits wide. AD0CON5 CH1 Main ADC Channel Selection Bits. AD0CON4 CH0 Written by the user to select the differential input pairs used by the main ADC as follows: (Note: The CHCON bit resides in the Mode register.) CHCON CH1 CH0 Positive Input Negative Input Calibration Register Pair 00 0 AIN1 AIN2 0 00 1 AIN3 AIN4 1 01 0 AIN2 AIN2 0 01 1 AIN3 AIN2 1 10 0 AIN1 AIN4 0 10 1 AIN3 AIN4 1 11 0 AIN4 AIN4 0 11 1 AIN2 AIN4 2 AD0CON3 U/B Main ADC Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x00 0000 output and a full-scale differential input will result in 0xFF FFFF output when operated in 24-bit mode. Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an output code of 0x00 0000, zero differential input will result in an output code of 0x80 0000, and a Positive full-scale differential input will result in an output code of 0xFF FFFF. –22– REV. A AD7719 Table XIII. Main ADC Control Register (AD0CON) Bit Designations (continued) Bit Location Bit Name Description AD0CON2 RN2 Main ADC Range Bits. AD0CON1 RN1 Written by the user to select the main ADC input range as follows. AD0CON0 RN0 RN2 RN1 RN0 Selected Main ADC Input Range (V = 2.5 V) REF 00 0 ±20 mV 00 1 ±40 mV 01 0 ±80 mV 01 1 ±160 mV 10 0 ±320 mV 10 1 ±640 mV 11 0 ±1.28 V 11 1 ±2.56 V Aux ADC Control Registers (AD1CON): for the aux ADC control register. AD1CON7 through AD1CON0 (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 0x00) indicate the bit location, with AD1CON denoting that the bits The aux ADC control register is an 8-bit register from which data are in the aux ADC control register. AD1CON7 denotes the can be read or to which data can be written. This register is used first bit of the data stream. The number in parentheses indicates to configure the aux ADC for range, channel selection, and uni- the power-on/reset default status of that bit. polar or bipolar coding. Table XIV outlines the bit designations A6 D1CON7A5 D1CONA4 D1CONA3 D1CONA2 D1CONA1 D1CONA0 D1CON AD1CON A) D1EN (0)A) CH2 (0A) CH1 (0A/ CH0 (0 U B() 0)0) (0 0) (0 ARN (1 Table XIV. Aux ADC Control Register (AD1CON) Bit Designations Bit Location Bit Name Description AD1CON7 AD1EN Aux ADC Enable Bit. Set by user to enable the Aux ADC. When set, the aux ADC operates according to the MD bits in the mode register. Cleared by the user to power down the aux ADC. AD1CON6 ACH2 Aux ADC Channel Selection Bits. AD1CON5 ACH1 Written by the user to select the active input channels used by the aux ADC as follows: AD1CON4 ACH0 CHCON ACH2 ACH1 ACH0 Positive Input Negative Input 00 00 AIN3 AGND 00 01 AIN4 AGND 00 10 AIN5 AIN6 00 11Temp Sensor (Temp Sensor Routed to the ADC Inputs) 01 00 AGND AGND (Internal Short) 10 00 AIN5 AGND 10 01 AIN6 AGND 10 10 AIN5 AIN6 10 11Temp Sensor (Temp Sensor Routed to the ADC Inputs) 11 00 AGND AGND (Internal Short) X1 01Not Defined X1 10Not Defined X1 11Not Defined AD1CON3 U/B Aux ADC Unipolar/Bipolar Selection Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x0000 output. Cleared by user to enable bipolar coding, zero differential input will result in 0x8000 output. AD1CON2 0 Must be zero for specified operation. AD1CON1 0 Must be zero for specified operation. AD1CON0 ARN Auxiliary Channel Input Range Bit. When set by the user, the input range is ±REFIN2. When cleared by the user, the input range is ±REFIN2/2. NOTES 1. When the temperature sensor is selected, the AD7719 automatically selects its internal reference. The temperature sensor is not factory calibrated. Temp sensor is suitable for relative temperature measurements. The temperature sensor yields conversion results where a conversion result of 0x8000 equates to typically 0°C. 2. A 1°C change in temperature will normally result in a 256 LSB change in the AD1 data register (ADC conversion result). REV. A –23– AD7719 F6 R7 F5 R F4 R F3 R F2 R F1 R F0 R FR S6 F7 (0) S) F(5 1 S) F(4 0 S) F(3 0 S) F() 0S) F2 (1S) F1 (0 SF0 (1 Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On The allowable range for SF is 13dec to 255dec. Examples of SF Reset = 0x45) values and corresponding conversion rate (f ) and time (t ) ADC ADC The Filter register is an 8-bit register from which data can be are shown in Table XV. It should also be noted that both ADC read or to which data can be written. This register determines input channels are chopped to minimize offset errors. This the amount of averaging performed by the sinc filter. Table XV means that the time for a single conversion or the time to the outlines the bit designations for the Filter register. FR7 through first conversion result is 2 × t . ADC FR0 indicate the bit location, with FR denoting that the bits are in the Filter register. FR7 denotes the first bit of the data stream. Table XV. Update Rate vs. SF WORD The number in parentheses indicates the power-on/reset default SF (dec) SF (Hex) f (Hz) t (ms) ADC ADC status of that bit. The number in this register is used to set the decimation factor and thus the output update rate for the main 13 0D 105.3 9.52 and aux ADCs. The filter register cannot be written to by the 69 45 19.79 50.34 user while either ADC is active. The update rate is used for both 255 FF 5.35 186.77 main and aux ADCs and is calculated as follows: 1 1 f =× × f ADC MOD I/O and Current Source Control Register (IOCON): (A3, A2, 3 8 × SF A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000) where: The IOCON register is a 16-bit register from which data can be f = ADC output update rate ADC read or to which data can be written. This register is used to control f =Modulator clock frequency = 32.768 kHz MOD and configure the various excitation and burnout current source (main and aux ADC) options available on-chip along with controlling the I/O port. SF =Decimal value written to SF register Table XVI outlines the bit designations for this register. IOCON15 through IOCON0 indicate the bit location, with IOCON denoting that the bits are in the I/O and Current Source control register. IOCON15 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and does not reset the ADCs. Thus if a current source is switched while the ADC is converting, the user will have to wait for the full settling time of the filter before getting a fully settled output. Since the ADC is chopped, this equates to three outputs. I4 OCON15I3 OCON1I2 OCON1I1 OCON1I0 OCON1I9 OCON1I8 OCON IOCON P1 SW2 (0) P) SW(0 0 (O 0) B)(N 0 I) 2PI() 0I) 1PIN (1I) 2EN (0 I1EN (0 I6 OCON7I5 OCONI4 OCONI3 OCONI2 OCONI1 OCONI0 OCON IOCON P) 4DIR (0)P) 3DIR (0P) 2EN (0P) 1EN (0P) 4DAT (0P) 3DAT (0P) 2DAT (0 P1DAT (0 –24– REV. A AD7719 Table XVI. IOCON (I/O and Current Source Control Register) Bit Designations Bit Bit Location Name Description IOCON15 PSW2 Power Switch 2 Control Bit. Set by user to enable power switch P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. IOCON14 PSW1 Power Switch 1 Control Bit. Set by user to enable power switch P1 to PWRGND. Cleared by user to enable use as a standard I/O pin. When ADC is in standby mode, the power switches are open. IOCON13 0 This bit must be zero for correct operation. IOCON12 BO Burnout Current Enable Bit. Set by user to enable the 100 nA current sources in the main ADC signal path. A 100 nA current source is applied to the positive input leg while a 100 nA sink is applied to the negative input. Cleared by user to disable both transducer burnout current sources. IOCON11 I2PIN IEXE2, 200 µA Current Source Direction Bit. Set by user to enable IEXC2 current source to IOUT1. Cleared by user to enable IEXC2 current source to IOUT2. IOCON10 I1PIN IEXE1, 200 µA Current Source Direction Bit. Set by user to enable IEXC1 current source to IOUT2. Cleared by user to enable IEXC1 current source to IOUT1. IOCON9 I2EN IEXC2 Current Source Enable Bit. Set by user to turn on the IEXC2 excitation current source. Cleared by user to turn off the IEXC2 excitation current source. IOCON8 I1EN IEXC1 Current Source Enable Bit. Set by user to turn on the IEXC1 excitation current source. Cleared by user to turn off the IEXC1 excitation current source. IOCON7 P4DIR P4, I/O Direction Control Bit. Set by user to enable P4 as an output. Cleared by user to enable P4 as an input. There are weak active pull-ups internally when enabled as an input. IOCON6 P3DIR P3, I/O Direction Control Bit. Set by user to enable P3 as an output. Cleared by user to enable P3 as an input. There are weak active pull-ups internally when enabled as an input. IOCON5 P2EN P2 Digital Output Enable Bit. Set by user to enable P2 as a regular digital output pin. Cleared by user to three-state P2 output. PSW2 takes precedence over P2EN. IOCON4 P1EN P1 Digital Output Enable Bit. Set by user to enable P1 as a regular digital output pin. Cleared by user to three-state P1 output. PSW1 takes precedence over P1EN. IOCON3 P4DAT Digital I/O Port Data Bits. IOCON2 P3DAT The readback values of these bits indicate the status of their respective pin when the I/O port is active as IOCON1 P2DAT an input. IOCON0 P1DAT The values written to these data bits appear at the output port when the I/O bits are enabled as outputs. P2 and P1 are outputs only, so reading P2DAT and P1DAT will return what was last written to these bits. REV. A –25– AD7719 Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = Main ADC Gain Calibration Coefficient Registers (GNO): 0, 1, 0, 1; Power-On Reset = 0x00 0000) (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) The conversion results for the main ADC channel are stored in The gain calibration registers hold the 24-bit data gain calibration the main ADC data register (DATA0). This register is either 16 coefficient for the main ADC. These registers are configured at or 24 bits wide, depending on the status of the WL bit in the power-on with factory calculated internal full-scale calibration main ADC control register (AD0CON). This is a read-only coefficients. Every device will have different coefficients. However, register. On completion of a read from this register, the RDY0 these bytes will be automatically overwritten if an internal or bit in the status register is cleared. system full-scale calibration is initiated by the user via MD2–0 bits in the Mode register. There are three gain calibration registers Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, associated with the main ADC channel. In fully differential 1, 1, 0; Power-On Reset = 0x0000) operating mode, there are two input channels and a register is The conversion results for the aux ADC channel are stored in dedicated to each input. When operating in pseudodifferential the aux ADC data register (DATA1). This register is 16 bits mode, the main ADC can be configured for three input channels wide and is a read-only register. On completion of a read from and there is a dedicated register for each pseudodifferential this register, the RDY1 bit in the status register is cleared. input. These registers are read/write registers. The calibration Main ADC Offset Calibration Coefficient Registers (OF0): registers can only be written to if the ADC is inactive (MD bits (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000) in the mode register = 000 or 001 or both AD0EN and AD1EN The offset calibration registers hold the 24-bit data offset bits in the control registers are cleared). Reading of the calibration coefficient for the main ADC. There are three calibration registers does not clear the RDY1 bit. registers associated with the main ADC channel. In fully Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, differential operating mode, there are two input channels and a A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX) register is dedicated to each input. When operating in The gain calibration register GN1 holds the 16-bit data gain pseudodifferential mode, the main ADC can be configured for calibration coefficient for the aux ADC. This register is configured three input channels and there is a dedicated register for each at power-on with factory calculated internal zero-scale calibration pseudodifferential input. These registers have a power-on reset coefficients. Every device will have different coefficients. However, value of 0x80 0000. The channel bits, in association with the these coefficients will be automatically overwritten if an internal communication register address for the OF0 register, allow or system zero-scale calibration is initiated by the user via the access to these registers. These registers are read/write registers. MD2–0 bits in the Mode register. These registers are read/write The calibration registers can only be written to if the ADC is registers. The calibration registers can only be written to if the inactive (MD bits in the mode register = 000 or 001 or both ADC is inactive (MD bits in the mode register = 000 or 001 or AD0EN and AD1EN bits in the control registers are cleared). both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY0 bit. Reading of the calibration registers does not clear the RDY1 bit. Aux ADC Offset Calibration Coefficient Registers (OF1): ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000) Reset = 0x0X) The offset calibration register OF1 holds the 16-bit data offset This register is a read-only 8-bit register. The contents are used calibration coefficient for the aux ADC. This register has a power- to determine the die revision of the AD7719. Table XVII on-reset value of 0x8000. The channel bits, in association with indicates the bit locations. the communication register address for the OF1 register, allow access to these registers. These registers are read/write registers. User Nonprogrammable Test Registers The calibration registers can only be written to if the ADC is The AD7719 contains two test registers. The bits in this test inactive (MD bits in the mode register = 000 or 001 or both register control the test modes of the AD7719, which are used AD0EN and AD1EN bits in the control registers are cleared). for the testing of the device. The user is advised not to change the Reading of the calibration registers does not clear the RDY1 bit. contents of these registers. Table XVII. ID Register Bit Designations I6 D7 I5 D I4 D I3 D I2 D I1 D I0 D ID 0 000 XXXX –26– REV. A AD7719 CONFIGURING THE AD7719 MICROCOMPUTER/MICROPROCESSOR INTERFACING All user-accessible registers on the AD7719 are accessed via the The AD7719’s flexible serial interface allows for easy interface serial interface. Communication with any of these registers is to most microcomputers and microprocessors. The flowchart of initiated by first writing to the Communications register. Figure 11 outlines the sequence that should be followed when Figure 11 outlines a flow diagram of the sequence used to con- interfacing a microcontroller or microprocessor to the AD7719. figure all registers after a power-up or reset on the AD7719. The Figures 12, 13, and 14 show some typical interface circuits. flowchart shows two methods of determining when it is valid to The serial interface on the AD7719 is capable of operating from read the data register or determine when a calibration cycle is just three wires and is compatible with SPI interface protocols. complete. The first method is hardware polling of the RDY The 3-wire operation makes the part ideal for isolated systems pin and the second method involves software interrogation of where minimizing the number of interface lines minimizes the bits in the status and mode registers. The flowchart details all the number of opto-isolators required in the system. The serial necessary programming steps required to initialize the ADC and clock input is a Schmitt-triggered input to accommodate slow read data from the main and aux channel following a power-on or edges from optocouplers. The rise and fall times of other digital reset. The steps can be broken down as follows: inputs to the AD7719 should be no longer than 1 µs. 1. Configure and initialize the microcontroller or microprocessor Most of the registers on the AD7719 are 8-bit registers, which serial port. facilitates easy interfacing to the 8-bit serial ports of microcon- 2. Initialize the AD7719 by configuring the following registers: trollers. The main channel data register (AD0) on the AD7719 a) IOCON to configure the current sources and digital can be either 16 or 24 bits, the aux ADC data register (AD1) is I/O port. 16 bits wide and the offset and gain registers are 24-bit registers, b) FILTER to configure the update rate for both channels. but data transfers to these registers can consist of multiple 8-bit c) AD1CON to enable the aux channel, select the analog transfers to the serial port of the microcontroller. DSP proces- input, select unipolar or bipolar operation and input range. sors and microprocessors generally transfer 16 bits of data in a d) AD0CON to enable the main ADC channel and select serial data operation. Some of these processors, such as the 16-/24-bit mode, analog input range, and either unipolar ADSP-2105, have the facility to program the amount of cycles or bipolar operation. in a serial transfer. This allows the user to tailor the number of e) MODE to configure the operating mode. Operating mode bits in any transfer to match the register length of the required consists of calibration or conversion. register in the AD7719. All of these operations consist of a write to the communications Even though some of the registers on the AD7719 are only eight register to specify the next operation as a write to a specified bits in length, communicating with two of these registers in register. Data is then written to this register. When each successive write operations can be handled as a single 16-bit sequence is complete, the ADC defaults to waiting for data transfer, if required. For example, if the Filter register is to another write to the Communications register to specify the be updated, the processor must first write to the Communica- next operation. tions register (saying that the next operation is a write to the Filter register) and then write eight bits to the Setup register. If 3. When the operating mode is selected, the user needs to deter- required, this can all be done in a single 16-bit transfer because mine when it is valid to read the data in conversion mode or once the eight serial clocks of the write operation to the Com- when the calibration is complete in calibration mode. This is munications register have been completed, the part immediately accomplished either by polling the RDY pin (hardware polling) sets itself up for a write operation to the Setup register. or by interrogating the bits in either the Status or Mode registers (software polling). Both are shown in Figure 11. It is assumed that both the main and aux ADCs are being used and calibration is required. If the AD7719 is operated at the factory-calibrated conditions, a field calibration will not be required and these steps can be bypassed. REV. A –27– AD7719 START POLL RDY PIN WRITE TO THE COMMUNICA TIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE MODE REGISTER POWER-ON/RESET FOR AD7719 NO RDY READ FROM MODE REGISTER LOW? CONFIGURE AND INITIALIZE �C/�P SERIAL PORT YES WRITE TO THE COMMUNICA TIONS REGISTER NO MD BITS SELECTING NEXT OPERATION TO BE A WRITE WRITE TO THE COMMUNICA TIONS REGISTER = 001? TO THE IOCON REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER YES WRITE TO THE IOCON REGISTER TO CONFIGURE THE CURRENT SOURCES, DIGITAL I/O PORT, WRITE TO MODE REGISTER SELECTING WRITE TO THE COMMUNICA TIONS REGISTER AND POWER SWITCHES CONTINUOUS CONVERSION MODE SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING WRITE TO THE COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE UP NEXT OPERATION TO BE A READ FROM THE FILTER REGISTER WRITE TO MODE REGISTER SELECTING MAIN ADC DATA REGISTER (AD0) CONTINUOUS CONVERSION MODE WRITE TO FILTER REGISTER CONFIRMING POLL RDY PIN WRITE TO THE COMMUNICA TIONS REGISTER THE REQUIRED UPDATE RATE SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE TO THE AUX NO RDY WRITE TO MODE REGISTER SELECTING CHANNEL ADC CONTROL REGISTER (AD1CON) LOW? CONTINUOUS CONVERSION MODE WRITE TO AD1CON REGISTER ENABLING THE AUX YES WRITE TO THE COMMUNICATIONS REGISTER SETTING ADC, SELECT THE INPUT CHANNEL BIPOLAR/ UNIPOLAR OPERATION AND INPUT RANGE UP NEXT OPERATION TO BE A READ OF READ FROM DATA REGISTER (AD0) STATUS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING POLL RDY PIN READ STATUS REGISTER UP NEXT OPERATION TO BE A WRITE TO THE MAIN CHANNEL ADC CONTROL REGISTER (AD0CON) WRITE TO AD1CON REGISTER ENABLING THE MAIN NO RDY NO ADC, SELECT THE INPUT CHANNEL, WORD LENGTH, LOW? RDY0 = 1? BIPOLAR/UNIPOLAR OPERATION, AND INPUT RANGE YES YES WRITE TO THE COMMUNICA TIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE WRITE TO THE COMMUNICATIONS REGISTER SETTING TO THE MODE REGISTER WRITE TO THE COMMUNICA TIONS REGISTER UP NEXT OPERATION TO BE A READ FROM THE SETTING UP NEXT OPERATION TO BE A READ AUX ADC DATA REGISTER (AD1) OF THE MAIN ADC DATA REGISTER (AD0) WRITE TO MODE REGISTER SELECTING FULL-SCALE CALIBRATION READ FROM DATA REGISTER (AD0) READ AD0 WRITE TO THE COMMUNICATIONS REGISTER SETTING HARDWARE SOFTWARE UP NEXT OPERATION TO BE A READ OF SOFTWARE POLLING POLLING STATUS REGISTER POLLING READ STATUS REGISTER HARDWARE WRITE TO THE COMMUNICA TIONS REGISTER POLLING SETTING UP NEXT OPERATION TO BE A READ FROM THE MODE REGISTER NO POLL RDY PIN RDY1 = 1? READ FROM MODE REGISTER YES NO RDY NO MD BITS WRITE TO THE COMMUNICA TIONS REGISTER LOW? = 001? SETTING UP NEXT OPERATION TO BE A READ OF THE AUX ADC DATA REGISTER (AD1) YES YES READ AD1 WRITE TO THE COMMUNICA TIONS REGISTER WRITE TO THE COMMUNICA TIONS REGISTER SETTING UP NEXT OPERATION TO BE A WRITE SETTING UP NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER TO THE MODE REGISTER WRITE TO MODE REGISTER SELECTING WRITE TO MODE REGISTER SELECTING ZERO-SCALE CALIBRATION FULL-SCALE CALIBRATION Figure 11. Flowchart for Initializing, Calibrating, and Reading Data from the AD7719 Main and Aux Channels –28– REV. A AD7719 AD7719-to-68HC11 Interface AD7719-to-8xC51 Interface Figure 12 shows an interface between the AD7719 and the 68HC11 An interface circuit between the AD7719 and the 8xC51 microcon- microcontroller. The diagram shows the minimum (3-wire) inter- troller is shown in Figure 13. The diagram shows the minimum face with CS on the AD7719 hardwired low. In this scheme, the number of interface connections with CS on the AD7719 hard- RDY bits of the Status register are monitored to determine wired low. In the case of the 8xC51 interface, the minimum when the Data register is updated. RDY0 indicates the status of number of interconnects is just two. In this scheme, the RDY the main ADC channel while RDY1 indicates the status of the bits of the Status register are monitored to determine when the aux channel. An alternative scheme, which increases the number Data register is updated. The alternative scheme, which increases of interface lines to four, is to monitor the RDY output line the number of interface lines to three, is to monitor the RDY output from the AD7719. The monitoring of the RDY line can be done in line from the AD7719. The monitoring of the RDY line can be two ways. First, RDY can be connected to one of the 68HC11’s done in two ways. First, RDY can be connected to one of the port bits (such as PC0), which is configured as an input. This 8xC51’s port bits (such as P1.0) that is configured as an input. port bit is then polled to determine the status of RDY. The This port bit is then polled to determine the status of RDY. second scheme is to use an interrupt driven system, in which case the RDY output is connected to the IRQ input of the 68HC11. For DV DD 8xC51 AD7719 interfaces that require control of the CS input on the AD7719, DV one of the port bits of the 68HC11 (such as PC1) that is DD RESET configured as an output, can be used to drive the CS input. 10k� The 68HC11 is configured in the master mode with its CPOL P3.0 DOUT bit set to a logic 1 and its CPHA bit set to a logic 1. When the 68HC11 is configured like this, its SCLK line idles high between data transfers. The AD7719 is not capable of full duplex opera- DIN tion. If the AD7719 is configured for a write operation, no data appears on the DOUT lines even when the SCLK input is active. Simi- P3.1 SCLK larly, if the AD7719 is configured for a read operation, data presented to the part on the DIN line is ignored even when CS SCLK is active. V DD V DD AD7719 68HC11 Figure 13. AD7719-to-8XC51 Interface SS The second scheme is to use an interrupt-driven system, in which RESET case the RDY output is connected to the INT1 input of the 8xC51. For interfaces that require control of the CS input on SCK SCLK the AD7719, one of the port bits of the 8xC51 (such as P1.1) that is configured as an output can be used to drive the CS MISO DOUT input. The 8xC51 is configured in its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DOUT and DIN pins of the AD7719 should be connected MOSI DIN together with a 10 kΩ pull-up resistor. The serial clock on the 8xC51 idles high between data transfers. The 8xC51 outputs the CS LSB first in a write operation, while the AD7719 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the AD7719 outputs the MSB first during a read operation while Figure 12. AD7719-to-68HC11 Interface the 8xC51 expects the LSB first. Therefore, the data read into the serial buffer needs to be rearranged before the correct data word from the AD7719 is available in the accumulator. REV. A –29– AD7719 AD7719-to-ADSP-2103/ADSP-2105 Interface as not to introduce gain errors. On-chip burnout currents are Figure 14 shows an interface between the AD7719 and the available and can be used to check that a transducer on the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, selected channel is still operational before attempting to take the RDY bits of the Status register are again monitored to measurements. determine when the Data register is updated. The alternative The second or auxiliary ADC is intended to convert secondary scheme is to use an interrupt-driven system, in which case the inputs such as those from a cold junction diode or thermistor. RDY output is connected to the IRQ2 input of the ADSP-2103/ This ADC is unbuffered and has a fixed input range of 0 V ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 to REFIN2 (ARN bit = 1) or 0 to REFIN2/2 (ARN bit = 0). is set up for alternate framing mode. The RFS and TFS pins Again, this ADC can be configured for differential or pseudo- of the ADSP-2103/ADSP-2105 are configured as active low differential inputs via the ACH2, ACH1, and ACH0 bits in the outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, auxiliary ADC control register (AD1CON). The auxiliary ADC is also configured as an output. The CS for the AD7719 is active is specified for 16-bit performance and, since its analog inputs when either the RFS or TFS outputs from the ADSP-2103/ are unbuffered, care must be exercised when placing filtering on ADSP-2105 are active. The serial clock rate on the ADSP-2103/ the front end to avoid introducing gain errors into the measure- ADSP-2105 should be limited to 3 MHz to ensure correct opera- ment system. tion with the AD7719. The basic connection diagram for the AD7719 is shown in Figure 15. This shows both the AV and DV pins of the DD DD DV DD ADSP-2103 / AD7719 being driven from the analog 5 V supply. Some appli- AD7719 ADSP-2105 cations will have AV and DV driven from separate supplies. DD DD RESET AV and DV can be operated independently of each other, DD DD allowing the device to be operated with 5 V analog supply and RFS 3 V digital supply or vice versa. An AD780/REF195 precision CS TFS 2.5 V reference provides the reference source for the part. A quartz crystal or ceramic resonator provides the 32 kHz master DR DOUT clock source for the part. In some cases, it will be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating DT DIN frequency. The values of capacitors will vary depending on the manufacturer’s specifications. SCLK SCLK ANALOG 5V SUPPLY 10�F 0.1�F 0.1�F Figure 14. AD7719-to-ADSP-2103/ADSP-2105 Interface 5V CIRCUIT DESCRIPTION AV DV DD DD The AD7719 is a Σ-∆ A/D converter incorporating two indepen- RESET IOUT1 dent Σ-∆ A/D converters with on-chip digital filtering, intended CHIP for the measurement of wide dynamic range, low frequency IOUT2 CS SELECT signals such as those in weigh scale, pressure, temperature, AD7719 RECEIVE AIN1 industrial control, or process control applications. DOUT (READ) The main ADC is intended to convert the primary sensor input. AIN2 SERIAL DIN DATA The main ADC employs a Σ-∆ conversion technique to realize up (WRITE) AIN3 to 24 bits of no-missing-codes performance. The Σ-∆ modulator SERIAL SCLK converts the sampled input signal into a digital pulse train whose CLOCK AIN4 3 duty cycle contains the digital information. A Sinc programmable P1/SW1 low-pass filter is then employed to decimate the modulator output AIN5 data stream to give a valid data conversion result at program- P2/SW2 AIN6 mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz ANALOG 5V SUPPLY P3 (9.52 ms). A Chopping scheme is also employed to minimize REFIN2 ADC offset and offset and gain drift errors. The analog input 10�F P4 REFIN1(+) to the main ADC can be operated in buffered or unbuffered mode and can be programmed for one of eight input ranges from XTAL1 32kHz 0.1�F ±20 mV to ±2.56 V. The input channels can be configured for CRYSTAL XTAL2 either fully differential inputs or pseudodifferential input REFIN1(–) V V IN OUT channels via the CH1 and CH0 bits in the main ADC control register (AD0CON) and the CHCON bit in the mode register. AD780/ PWRGND AGND DGND When configured for buffered mode (BUF = 0), the input channels REF195 are internally buffered, allowing the part to handle significant source impedances on the analog input, allowing R/C filtering GND (for noise rejection or RFI reduction) to be placed on the analog inputs if required. When operating in unbuffered mode, care has Figure 15. Basic Connection Diagram to be exercised when selecting front end source impedances so –30– REV. A AD7719 Analog Input Channels Figure 17 shows the analog input channel configurations avail- The main ADC has four associated analog input pins (labeled able to the user when the CHCON bit in the mode register is AIN1 to AIN4) that can be configured as two fully differential set to 1. In this case, the main ADC is configured as three input channels or three pseudodifferential input channels. pseudodifferential input channels (AIN1/AIN4, AIN2/AIN4, and Channel selection bits CH1 and CH0 in the ADC0CON AIN3/AIN4) and the aux can be configured as two single-ended register, along with the CHCON bit of the mode register, inputs with respect to AGND (AIN5/AGND and AIN6/AGND) detail the different configurations. and one fully differential input (AIN5/AIN6). The temp sensor is available as an internal connection. The auxiliary ADC has four external input pins (labeled AIN3 to AIN6) as well as an internal connection to the internal on-chip PSEUDO- temperature sensor. Channel selection bits ACH2, ACH1, and DIFFERENTIAL MUX1 INPUT ACH0 in the ADC1CON register, along with the CHCON AIN1 AIN1 bit in the mode register, detail the various configurations on AIN1/AIN4 AIN(+) these input channels. AIN2 AIN2 MAIN CHANNEL AIN2/AIN4 Two input multiplexers (MUX1 and MUX2) switch the selected AIN3 AIN3 input channel to the on-chip buffer amplifier in the case of the AIN(–) AIN3/AIN4 main ADC when operated in buffered mode, and directly to the AIN4 AIN4 Σ-∆ modulator input in the case of the auxiliary ADC and when PSEUDO- (MAIN ADC) the main ADC is operated in unbuffered mode. When the analog DIFFERENTIAL INPUT input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. MUX2 Figure 16 shows the analog input channel configurations available AIN3 to the user when the CHCON bit in the mode register is set to a AIN(+) zero. In this case, the main ADC can be configured as one or two AIN4 SINGLE- fully differential input channels (AIN1/AIN2 and AIN3/AIN4) ENDED INPUT AUX CHANNEL and the aux can be configured as two single-ended inputs with AIN5 AIN5 respect to AGND (AIN3/AGND and AIN4/AGND) and one fully FULLY DIFFERENTIAL AIN(–) differential input AIN5/AIN6). The aux can also be configured as AIN6 AIN6 three single-ended inputs with respect to AGND (AIN3/AGND, AIN4/AGND, and AIN5/AGND) by tying AIN6 externally to AGND SINGLE- (AUX ADC) AGND. The temp sensor is available as an internal connection. ENDED INPUT MUX1 Figure 17. Input Channel Configurations with CHCON = 1 AIN1 AIN1 In buffered mode (BUF = 0), the output of the main ADC multi- FULLY DIFFERENTIAL AIN(+) plexer feeds into a high impedance input stage of the buffer AIN2 AIN2 amplifier. As a result, the main ADC inputs can handle significant MAIN CHANNEL source impedances and are tailored for direct connection to AIN3 AIN3 AIN(–) external resistive-type sensors like strain gages or resistance FULLY DIFFERENTIAL temperature detectors (RTDs). AIN4 AIN4 (MAIN ADC) The auxiliary ADC and the main ADC when operated with BUF = 1, however, are unbuffered, resulting in higher analog SINGLE- input current. It should be noted that these unbuffered input ENDED MUX2 INPUT paths provide a dynamic load to the driving source. Therefore, AIN3 SINGLE- resistor/capacitor combinations on the input pins can cause dc ENDED gain errors, depending on the output impedance of the source INPUT AIN(+) AIN4 that is driving the ADC inputs. Table XVIII and XIX show the allowable external resistance/capacitance values for unbuffered AUX CHANNEL AIN5 AIN5 mode such that no gain error at the 16- and 20-bit level, FULLY DIFFERENTIAL AIN(–) respectively, is introduced. AIN6 AIN6 The absolute input voltage range on the main ADC when oper- AGND ated in buffered mode is restricted to a range between AGND + (AUX ADC) 100 mV and AV – 100 mV. Care must be taken in setting up DD the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in Figure 16. Input Channel Configurations with CHCON = 0 linearity and noise performance. REV. A –31– AD7719 Table XVIII. Max Resistance for No 16-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 111.3K 27.8K 16.7K 4.5K 2.58K 700 2 53.7K 13.5K 8.1K 2.2K 1.26K 360 4 25.4K 6.4K 3.9K 1.0K 600 170 8–128 10.7K 2.9K 1.7K 480 270 75 Table XIX. Max Resistance for No 20-Bit Gain Error (Unbuffered Mode) External Capacitance Gain 0 pF 50 pF 100 pF 500 pF 1000 pF 5000 pF 1 84.9K 21.1K 12.5K 3.2K 1.77K 440 2 42.0K 10.4K 6.1K 1.6K 880 220 4 20.5K 5.0K 2.9K 790K 430 110 8–128 8.8K 2.3K 1.3K 370 195 50 The absolute input voltage range on the auxiliary ADC and the 19.372 main ADC in unbuffered mode includes the range between 19.371 AGND – 30 mV to AV + 30 mV as a result of being unbuf- DD fered. The negative absolute input voltage limit does allow 19.370 the possibility of monitoring small true bipolar signals with 19.369 respect to AGND. Programmable Gain Amplifier 19.368 The output from the buffer on the main ADC is applied to the 19.367 input of the on-chip programmable gain amplifier (PGA). The PGA can be programmed through eight different unipolar and 19.366 bipolar ranges. The PGA gain range is programmed via the range bits in the ADC0CON register. With an external 2.5 V 19.365 reference applied, the unipolar ranges are 0 mV to 20 mV, 0 mV 19.364 to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 100 200 300 400 500 600 700 800 SAMPLE COUNT 0 mV to 640 mV, 0 V to 1.28 V and 0 V to 2.56 V while bipolar ADC RANGE ranges are ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V, and ±2.56 V. These are the ranges that should appear at the input to the on-chip PGA. The ADC range Figure 18. Main ADC Range Matching matching specification of 2 µV (typ) across all ranges means that calibration need only be carried out on a single range and does Bipolar/Unipolar Configuration not have to be repeated when the PGA range is changed. This is The analog inputs on the AD7719 can accept either unipolar or a significant advantage when compared with similar ADCs bipolar input voltage ranges. Bipolar input ranges do not imply that available on the market. the part can handle negative voltages with respect to system AGND. Unipolar and bipolar signals on the AIN(+) input on Typical matching across ranges is shown in Figure 18. Here, the the main ADC are referenced to the voltage on the respective primary ADC is configured in fully differential, bipolar mode AIN(–) input. AIN(+) and AIN(–) refer to the signals seen by with an external 2.5 V reference, while an analog input voltage the modulator that come from the output of the multiplexer, as of just greater than 19 mV is forced on its analog inputs. The shown in Figures 16 and 17. ADC continuously converts the dc voltage at an update rate of 5.35 Hz, i.e., SF = 0xFF. In total, 800 conversion results are For example, if AIN(–) is 2.5 V and the main ADC is config- gathered. The first 100 results are gathered with the primary ADC ured for an analog input range of 0 mV to 20 mV, the input operating in the ±20 mV range. The ADC range is then switched voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) to ±40 mV and 100 more results are gathered; this continues is 2.5 V and the AD7719 is configured for an analog input range until the last 100 samples are gathered with the ADC configured of ±1.28 V, the analog input range on the AIN(+) input is 1.22 V in the ±2.5 V range. From Figure 18, the variation in the sample to 3.78 V (i.e., 2.5 V ± 1.28 V). Bipolar or unipolar options are mean through each range, i.e., the range matching, is seen to chosen by programming the main and auxiliary U/B bit in the be on the order of 2 µV. ADC0CON and ADC1CON registers, respectively. This pro- grams the relevant ADC for either unipolar or bipolar operation. The auxiliary ADC does not incorporate an eight range PGA. Programming for either unipolar or bipolar operation does not The aux ADC operates at a gain of 1 or a gain of 2 as determined change any of the input signal conditioning; it simply changes the by the ARN bit in the AD1CON register. data output coding and the points on the transfer function where calibrations occur. –32– REV. A ADC INPUT VOLTAGE (mV) �20mV �40mV �80mV �160mV �320mV �640mV �1.28V �2.56V AD7719 Data Output Coding turned off by writing a 0 to the BO bit in the IOCON register. When the ADC is configured for unipolar operation, the output The current sources work over the normal absolute input voltage coding is natural (straight) binary with a zero differential input range specifications with buffers on. voltage resulting in a code of 000 . . . 000, a midscale voltage Excitation Currents resulting in a code of 100 . . . 000, and a full-scale input voltage The AD7719 also contains two matched, software configurable resulting in a code of 111 . . . 111. The output code for any analog 200 µA constant current sources. Both source current from input voltage on the main ADC can be represented as follows: AV that is directed to either the IOUT1 or IOUT2 pins of DD N the device. These current sources are controlled via bits in the Code=× AIN GAIN×21.024 ×V ()() REF IOCON register. The configuration bits enable the current sources and can be configured to source 200 µA individually to Where AIN is the analog input voltage, GAIN is the PGA gain, both pins or a combination of both currents, i.e., 400 µA to i.e., 1 on the 2.56 V range and 128 on the 20 mV range, and either of the selected output pins. These current sources can be N = 16 in 16-bit mode and N = 24 in 24-bit mode of operation. used to excite external resistive bridge or RTD sensors. The output code for any analog input voltage on the aux ADC Crystal Oscillator can be represented as follows: The AD7719 is intended for use with a 32.768 kHz watch crys- N Code=× AIN GAIN× 2 V tal. A PLL internally locks onto a multiple of this frequency to () REF provide a stable 4.194304 MHz clock for the ADC. The modu- Where AIN is the analog input voltage, GAIN is 1 or 2, deter- lator sample rate is the same as the crystal oscillator frequency. mined by the ARN bit in the aux ADC control register, i.e., 1 on The start-up time associated with 32 kHz crystals is typically the VREF range and 2 on the VREF/2 range, and N = 16. 300 ms. The OSPD bit in the mode register can be used to When an ADC is configured for bipolar operation, the coding is prevent the oscillator from powering down when the AD7719 is offset binary with a negative full-scale voltage resulting in a code placed in power-down mode. This avoids having to wait 300 ms of 000 . . . 000, a zero differential voltage resulting in a code of after exiting power-down to start a conversion at the expense of 100 . . . 000, and a positive full-scale voltage resulting in a code raising the power-down current. of 111 . . . 111. The output code from the main ADC for any Reference Input analog input voltage can be represented as follows: The AD7719 has a fully differential reference input capability N –1 for the main channel while the auxiliary channel accepts only a Code=×21 AIN× GAIN .024×V + 1 () () REF [] single-ended reference. On the main channel, the reference inputs REFIN1(+) and REFIN1(–) provide a differential reference Where AIN is the analog input voltage, GAIN is the PGA gain, input capability. The common-mode range for these differential i.e., 1 on the ±2.56 V range and 128 on the ±20 mV range, inputs is from AGND to AV . The reference input is unbuffered, DD N = 16 in 16-bit mode, and N = 24 in 24-bit mode of operation. and therefore excessive R-C source impedances will introduce The output code from the aux ADC for any analog input volt- gain errors. The nominal reference voltage, VREF, (REFIN1(+) age can be represented as follows: – REFIN1(–), for specified operation is 2.5 V, but the AD7719 N –1 is functional with reference voltages from 1 V to AV . In appli- DD Code=×21 AIN× GAIN V + () REF [] cations where the excitation (voltage or current) for the transducer Where AIN is the analog input voltage, GAIN is 1 or 2, determined on the analog input also drives the reference voltage for the part, by the ARN bit in the aux ADC control register, i.e., 1 on the the effect of the low frequency noise in the excitation source ±VREF range, 2 on the ±VREF/2 range, and N = 16. will be removed as the application is ratiometric. If the AD7719 is used in a nonratiometric application, a low noise reference Burnout Currents should be used. Recommended reference voltage sources for The main ADC on the AD7719 contains two 100 nA constant the AD7719 include the AD780, REF43, and REF192. It should current generators, one sourcing current from AV to AIN(+), DD also be noted that the reference inputs provide a high impedance, and one sinking current from AIN(–) to AGND. The currents dynamic load. Because the input impedance of each reference are switched to the selected analog input pair. Both currents are input is dynamic, resistor/capacitor combinations on these inputs either on or off, depending on the Burnout Current Enable (BO) can cause dc gain errors, depending on the output impedance bit in the IOCON register. These currents can be used to verify of the source that is driving the reference inputs. Reference that an external transducer is still operational before attempting voltage sources like those recommended (e.g., AD780) will typi- to take measurements on that channel. Once the burnout currents cally have low output impedances and are therefore tolerant to are turned on, they will flow in the external transducer circuit, having decoupling capacitors on the REFIN1(+) without and a measurement of the input voltage on the analog input introducing gain errors in the system. Deriving the reference channel can be taken. If the resultant voltage measured is full-scale, input voltage across an external resistor, as shown in Figure 19, the user needs to verify why this is the case. A full-scale reading will mean that the reference input sees a significant external could mean that the front end sensor is open circuit; it could source impedance. External decoupling on the REFIN1(+) also mean that the front end sensor is overloaded and is justified and REFIN1(–) pins would not be recommended in this type in outputting full-scale, or that the reference may be absent and of circuit configuration. the NOXREF bit is set, thus clamping the data to all 1s. The auxiliary channel conversion results are based on the volt- When reading all 1s from the output, the user needs to check age applied to REFIN2. This is a single-ended reference input these three cases before making a judgment. If the voltage specified for 2.5 V operation but functional with input voltages measured is 0 V, it may indicate that the transducer has short from 1 V to AV . DD circuited. For normal operation, these burnout currents are REV. A –33– AD7719 Reference Detect ADC Disable Mode The AD7719 includes on-chip circuitry to detect if the part has a This mode is entered by setting both the AD0EN and AD1EN valid reference on the main ADC for conversions or calibrations. bits in the main and max ADC control registers to 0 and setting If the voltage between the external REFIN1(+) and REFIN1(–) the Mode bits (MD2, MD1, MD0) in the Mode register to non-0. pins goes below 0.3 V or either the REFIN1(+) or REFIN1(–) In this mode, the internal PLL is enabled and the user can inputs are open circuit, the AD7719 detects that it no longer activate the current sources and power switches, but the power has a valid reference. In this case, the NOXREF bit of the Status consumption of the ADC is reduced as both ADCs are disabled. register is set to 1. If the AD7719 is performing normal conver- In this mode, the AI is reduced to 0.15 mA and the DI is DD DD sions and the NOXREF bit becomes active, the conversion results reduced to 0.35 mA max at 3 V and to 0.4 mA max with DV = 5 V. DD revert to all 1s. Therefore, it is not necessary to continuously Calibration monitor the status of the NOXREF bit when performing The AD7719 provides four calibration modes that can be pro- conversions. It is only necessary to verify its status if the grammed via the mode bits in the mode register. One of the conversion result read from the ADC data register is all 1s. If the major benefits of the AD7719 is that it is factory-calibrated as AD7719 is performing either an offset or gain calibration and part of the final test process with the generated coefficients the NOXREF bit becomes active, the updating of the respective stored within the ADC. At power-on, the factory gain calibra- calibration registers is inhibited to avoid loading incorrect tion coefficients are automatically loaded to the gain calibration coefficients to these registers, and the ERR0 bit in the Status registers on the AD7719. Each ADC (primary and auxiliary) has register is set. If the user is concerned about verifying that a dedicated calibration register pairs as outlined in the AD0CON valid reference is in place every time a calibration is performed, and AD1CON register descriptions. Given that the ADC is the status of the ERR0 bit should be checked at the end of the factory-calibrated and a chopping scheme is employed that gives calibration cycle. excellent offset and drift performance, it is envisaged that in the Reset Input majority of applications the user will not need to perform any The RESET input on the AD7719 resets all the logic, the digi- field calibrations. tal filter, and the analog modulator while all on-chip registers are However, the factory calibration values in the ADC calibration reset to their default state. RDY is driven high and the AD7719 registers will be overwritten if any one of the four calibration ignores all communications to any of its registers while the options are initiated. Even though an internal offset calibration RESET input is low. When the RESET input returns high, the mode is described below, it should be recognized that both AD7719 operates with its default setup conditions and it is ADCs are chopped. This chopping scheme inherently minimizes necessary to set up all registers and carry out a system calibration offset and means that an internal offset calibration should never if required after a RESET command. be required. Also, because factory 25°C gain calibration coeffi- Power-Down Mode cients are automatically present at power-on, an internal full-scale Loading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC mode calibration will only be required if the part is being operated at register places the AD7719 in device power-down mode. Device temperatures significantly different from 25°C or away from the power-down mode is the default condition for the AD7719 on calibration conditions. The AD7719 offers internal or system power-up. Individual ADCs (main or auxiliary) can be put in calibration facilities. For full calibration to occur on the selected power-down mode using the AD0EN in the main ADC control ADC, the calibration logic must record the modulator output register (AD0CON) to power off the main ADC or the AD1EN for two different input conditions. These are zero-scale and full- in the auxiliary ADC control register (AD1CON) to power off scale points derived by performing a conversion on the different the auxiliary ADC. The AD7719 retains the contents of all its input voltages provided to the input of the modulator during on-chip registers (including the data register) while in power- calibration. The result of the zero-scale calibration conversion is down or ADC disable mode. stored in the offset calibration registers for the appropriate ADC. The result of the full-scale calibration conversion is stored in the The device power-down mode does not affect the digital inter- gain calibration registers for the appropriate ADC. With these face, and it does affect the status of the RDY pin. Putting the readings, the calibration logic can calculate the offset and the gain AD7719 into power-down or idle mode will reset the RDY line slope for the input-to-output transfer function of the converter. high. Placing the part in power-down mode reduces the total current (AI + DI ) to 31 µA max when the part is operated During an internal zero-scale or full-scale calibration, the respec- DD DD at 5 V and the oscillator is allowed to run during power-down tive zero input and full-scale input are automatically connected mode. With the oscillator shuts down, the total I is 3 µA max to the ADC input pins internally to the device. A system DD at 3 V and 9 µA max at 5 V. calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the external ADC pins before Idle Mode the calibration mode is initiated. In this way, external ADC errors The AD7719 also contains an idle mode. The ADC defaults are taken into account and minimized as a result of system to this mode on completion of a calibration sequence and on calibration. It should also be noted that to optimize calibration the completion of a conversion when operating in single con- accuracy, all AD7719 ADC calibrations are automatically version mode. In idle mode, the power consumption of the carried out at the slowest update rate. AD7719 is not reduced below the normal mode dissipation. –34– REV. A AD7719 Internally in the AD7719, the coefficients are normalized before Avoid running digital lines under the device as these will couple being used to scale the words coming out of the digital filter. The noise onto the die. The analog ground plane should be allowed offset calibration coefficient is subtracted from the result prior to run under the AD7719 to prevent noise coupling. The power to the multiplication by the gain coefficient. supply lines to the AD7719 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches From an operational point of view, a calibration should be treated on the power supply line. Fast switching signals like clocks like another ADC conversion. A zero-scale calibration (if required) should be shielded with digital ground to avoid radiating noise should always be carried out before a full-scale calibration. System to other sections of the board, and clock signals should never be software should monitor the relevant ADC RDY0/1 bit in the run near the analog inputs. Avoid crossover of digital and analog Status register to determine end of calibration via a polling signals. Traces on opposite sides of the board should run at right sequence or interrupt driven routine. angles to each other. This will reduce the effects of feedthrough Grounding and Layout through the board. A microstrip technique is by far the best, but is not Since the analog inputs and reference input on the main ADC always possible with a double-sided board. In this technique, the are differential, most of the voltages in the analog modulator are component side of the board is dedicated to ground planes while common-mode voltages. The excellent common-mode rejection signals are placed on the solder side. of the part will remove common-mode noise on these inputs. Good decoupling is important when using high resolution ADCs. The analog and digital supplies to the AD7719 are independent All analog supplies should be decoupled with 10 µF tantalum in and separately pinned out to minimize coupling between the parallel with 0.1 µF capacitors to AGND. To achieve the best from analog and digital sections of the device. The AD7719 can be these decoupling components, they have to be placed as close as operated with 5 V analog and 3 V digital supplies, or vice versa. possible to the device, ideally right up against the device. All logic The digital filter will provide rejection of broadband noise on chips should be decoupled with 0.1 µF ceramic capacitors to the power supplies, except at integer multiples of the modulator DGND. In systems where a common supply voltage is used to sampling frequency. The digital filter also removes noise from drive both the AV and DV of the AD7719, it is recom- DD DD the analog and reference inputs provided these noise sources do mended that the system’s AV supply be used. This supply DD not saturate the analog modulator. As a result, the AD7719 is should have the recommended analog supply decoupling capaci- more immune to noise interference than a conventional high tors between the AV pin of the AD7719 and AGND, and the DD resolution converter. However, because the resolution of the recommended digital supply decoupling capacitor between the AD7719 is so high, and the noise levels from the AD7719 are so DV pin of the AD7719 and DGND. DD low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7719 should be APPLICATIONS designed such that the analog and digital sections are separated The AD7719 provides a low cost, high resolution analog-to- and confined to certain areas of the board. This facilitates the digital function. Because the analog-to-digital function is provided use of ground planes that can be easily separated. A minimum by a Σ-∆ architecture, it makes the part more immune to noisy etch technique is generally best for ground planes as it gives the environments, making it ideal for use in sensor measurement and best shielding. industrial and process control applications. Given the architecture used in the AD7719, where the signal chain is chopped and Although the AD7719 has separate pins for analog and digital the device is factory-calibrated at final test, field calibration ground, the AGND and DGND pins are tied together within can be avoided due to the extremely low offset and gain drifts the device via the substrate. The user must not tie these pins exhibited by this converter. It also provides a programmable external to separate ground planes unless the ground planes are gain amplifier, a digital filter, and system calibration options. Thus, connected together near the AD7719. it provides far more system-level functionality than off-the-shelf In systems where the AGND and DGND are connected some- integrating ADCs without the disadvantage of having to supply a where else in the system, i.e., the system power supply, they should high quality integrating capacitor. In addition, using the AD7719 not be connected again at the AD7719 as a ground loop will in a system allows the system designer to achieve a much higher result. In these situations, it is recommended that the AD7719’s level of resolution because noise performance of the AD7719 is AGND and DGND pins be tied to the AGND plane. In any significantly better than that of integrating ADCs. layout, it is important that the user keep in mind the flow of The on-chip PGA allows the AD7719 to handle an analog input currents in the system, ensuring that the return paths for all voltage range as low as 10 mV full-scale with V = 1.25 V. The currents are as close as possible to the paths the currents took to REF differential inputs of the part allow this analog input range to reach their destinations. Avoid forcing digital currents to flow have an absolute value anywhere between AGND + 100 mV and through the AGND sections of the layout. AV – 100 mV. It allows the user to connect the transducer DD The PWRGND pin is tied internally to AGND on the AD7719. directly to the input of the AD7719. The programmable gain The PWRGND pad internally has a resistance of less then 50 mΩ front end on the AD7719 allows the part to handle unipolar to the PWRGND pin, while the resistance back to the AGND analog input ranges from 0 mV to 20 mV to 0 V to 2.5 V and pad is >3 Ω. This means that 19.5 mA of the maximum speci- bipolar inputs of ±20 mV to ±2.5 V. Because the part operates fied current (20 mA) will flow to PWRGND with the remaining from a single supply, these bipolar ranges are with respect to a 0.5 mA flowing to AGND. PWRGND and AGND should be biased-up differential input. Another key advantage of the AD7719 is tied together at the AD7719 and it is important to minimize the that it contains two Σ-∆ converters operating in parallel; thus the resistance on the ground return lines. user does not need to interrupt the main channel when a second- ary measurement on a different variable needs to be performed. REV. A –35– AD7719 Pressure Measurement The circuit in Figure 20 shows a method that utilizes all three One typical application of the AD7719 is pressure measure- pseudodifferential input channels on the AD7719 main channel ment. Figure 19 shows the AD7719 used with a pressure to temperature-compensate a pressure transducer. transducer, the BP01 from Sensym. 5V The pressure transducer is arranged in a bridge network and AV DD gives a differential output voltage between its OUT(+) and IOUT1 OUT(–) terminals. With rated full-scale pressure (in this case I1 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (i.e., the voltage between its IN(+) and IN(–) terminals). I2 Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the REFIN(+) bridge can be used to directly provide the reference for the ADC 6.25k� as the reference input range includes the supplies. Alternatively, REFIN(–) a suitable resistor divider can be implemented that allows the full dynamic range of the input to be utilized in these applica- AIN2 IN(+) XTAL1 tion. This implementation is fully ratiometric, so variations in AD7719 the excitation voltage do not introduce errors in the system. OUT(+) OUT(–) AIN1 Choosing resistor values of 20 kΩ and 12 kΩ as per Figure 19 give a 1.875 V reference voltage for the AD7719 when the exci- PRESSURE AIN4 XTAL2 BRIDGE tation voltage is 5 V. IN(–) AIN3 AGND EXCITATION VOLTAGE = 5V 250� IN+ 20k� AV DV Figure 20. Temperature-Compensating a Pressure DD DD OUT+ OUT– AIN1 Transducer AIN2 In this application, pseudodifferential input channel AIN1/AIN4 IN– is used to measure the bridge output while pseudodifferential REFIN1(+) 12k� channels AIN2/AIN4 and AIN3/AIN4 measure the voltage REFIN2(–) across the bridge. The voltage measured across the bridge will AD7719 vary proportionally with temperature, and the delta in this volt- P1 age can be used to temperature-compensate the output of the pressure bridge. Temperature Measurement DGND The AD7719 is also useful in temperature measurement applica- AGND PWRGND tions; Figure 21 shows an RTD temperature measurement application. In this application, the transducer is an RTD (resistive temperature device), a PT100. The arrangement is a 4-lead RTD Figure 19. Pressure Measurement Using AD7719 configuration. There are voltage drops across the lead resistances RL1 and RL4, but these simply shift the common-mode voltage. Using the part with a programmed gain of 128 results in the There is no voltage drop across lead resistances RL2 and RL3 as full-scale input span of the AD7719 being 15 mV, which corre- the input current to the AD7719 is very low, looking into a high sponds with the output span from the transducer. input impedance buffer. R is included to shift the analog input CM A second key advantage to using the AD7719 in transducer voltage to ensure that it lies within the common-mode range based applications is that the on-chip low-side power switch can (AGND + 100 mV to AV – 100 mV) of the ADC. In the DD be fully utilized in low power applications. The low-side power application shown, the on-chip 200 µA current source provides the switch is connected in series with the cold side of the bridge. In excitation current for the PT100 and also generates the reference normal operation, the switch is closed and measurements can be voltage for the AD7719 via the 12.5 kΩ resistor. Variations in taken from the bridge. In applications where power is of con- the excitation current do not affect the circuit as both the input cern, the AD7719 can be put in low power mode, substantially voltage and the reference voltage vary ratiometrically with the reducing the power burned in the application. In addition to excitation current. However, the 12.5 kΩ resistor must have a low this, the power switch can be opened while in low power mode temperature coefficient to avoid errors in the reference voltage thus avoiding the unnecessary burning of power in the front end over temperature. transducer. When the AD7719 is taken back out of power-down and the power switch is closed, the user should ensure that the front end circuitry is fully settled before attempting a read from the AD7719. –36– REV. A AD7719 The switched polarity current source is developed using the 5V on-chip current sources and external phase control switches AV DV (A and A) driven from the controller. During the conversion DD DD REFIN(–) process, the AD7719 takes two conversion results, one on each XTAL1 REFIN(+) phase. During Phase 1, the on-chip current source is directed to R RL1 REF IOUT1 and flows top to bottom through the sensor and switch IOUT1 XTAL2 controlled by A. In Phase 2, the current source is directed to 12.5k� 200�A IOUT2 and flows in the opposite direction through the sensor IOUT2 and through switch controlled by A. In all cases, the current RL2 AIN1 flows in the same direction through the reference resistor to DRDY develop the reference voltage for the ADC. All measurements are RTD AD7719 SCLK ratiometrically derived. The results of both conversions are CONTROLLER AIN2 DIN RL3 combined within the microcontroller to produce one output DOUT R CM measurement representing the resistance or temperature of the CS RL4 DGND transducer. For example, if the RTD output during Phase 1 is AGND PWRGND 10 mV, a 1 mV circuit-induced dc error exists due to parasitic thermocouples, and the ADC measures 11 mV. During the second phase, the excitation current is reversed and the ADC measures –10 mV from the RTD and again sees 1 mV dc error, Figure 21. 4-Wire RTD Temperature Measurement giving an ADC output of –9 mV during this phase. These mea- Using the AD7719 surements are processed in the controller (11 mV – (–9 mV)/2 = Figure 22 shows a further enhancement to the circuit shown in 10 mV), thus removing the dc-induced errors within the system. Figure 21. Generally, dc excitation has been accepted as the In the circuit shown in Figure 22, the resistance measurement is normal method of exciting resistive-based sensors like RTDs made using ratiometric techniques. Resistor R , which devel- REF (resistance temperature detectors) in temperature measurement ops the ADC reference, must be stable over temperature to applications. prevent reference-induced errors in the measurement output. With dc excitation, the excitation current through the sensor 3-Wire RTD Configurations must be large enough so that the smallest temperature/resistance To fully optimize a 3-wire RTD configuration, two identically change to be measured results in a voltage change that is larger matched current sources are required. The AD7719, which than the system noise, offset, and drift of the system. The purpose contains two well-matched current sources, is ideally suited to of switching the excitation source is to eliminate dc-induced these applications. One possible 3-wire configuration using the errors. DC errors (EMF1 and EMF2) due to parasitic thermo- AD7719 is outlined in Figure 23. couples produced by differential metal connections (solder and copper track) within the circuit are also eliminated when using 5V this switching arrangement. This excitation is a form of synchro- nous detection where the sensor is excited with an alternating DV AV DD DD excitation source and the ADC only measures information in the IOUT1 XTAL1 same phase as the excitation source. 200�A REFIN(+) XTAL2 AV DD 12.5k� EMF1 IOUT1 REFIN(–) I1 RL1 AIN1 IOUT2 200�A DRDY AIN2 RTD RESISTIVE SCLK TRANSDUCER RL2 IOUT2 CONTROLLER DIN BUF AIN1 AND RL3 200�A DOUT EMF2 PGA AIN2 CS R CM MUX1 AIN3 AGND AD7719 AIN4 DGND A A REFIN(+) R REF AD7719 REFIN(–) Figure 23. 3-Wire RTD Configuration Using the AD7719 Figure 22. Low Resistance Measurement AD7719 REV. A –37– AD7719 In this 3-wire configuration, the lead resistances will result in in the reference voltage. The typical drift matching between the errors if only one current source is used because the 200 µA will two RTD current sources is less than 1 ppm/°C. The voltage on flow through RL1, developing a voltage error between AIN1 and either I pin can go to within 0.6 V of the AV supply. OUT DD AIN2. In the scheme outlined below, the second RTD current Smart Transmitters source is used to compensate for the error introduced by the Smart transmitters are another key design-in area for the AD7719. 200 µA flowing through RL1. The second RTD current flows The dual Σ-∆ converter, single-supply operation, 3-wire interface through RL2. Assuming RL1 and RL2 are equal (the leads capabilities, and small package size are all of benefit in smart would normally be of the same material and of equal length), transmitters. Here, the entire smart transmitter must operate and IOUT1 and IOUT2 match, the error voltage across RL2 from the 4 to 20 mA loop. Tolerances in the loop mean that the equals the error voltage across RL1, and no error voltage is amount of current available to power the transmitter is as low as developed between AIN1 and AIN2. Twice the voltage is 3.5 mA. Figure 24 shows a block diagram of a smart transmitter, developed across RL3, but since this is a common-mode voltage, which includes the AD7719. it will not introduce errors. R is included so the current CM Not shown in Figure 24 is the isolated power source required to flowing through the combination of RL3 and R develops enough CM power the front end. The advantages of the AD7719 in these voltage that the analog input voltage seen by the AD7719 is applications is the dual-channel operation, meaning that the within the common-mode range of the ADC. The reference user does not have to interrupt the main channel when measur- voltage for the AD7719 is also generated using one of these ing secondary variables, and therefore does not have the latency matched current sources. This reference voltage is developed associated with the settling times of the digital filter. The fact across the 12.5 kΩ resistor as shown, and applied to the differential that the AD7719 is factory-calibrated means that in the majority reference inputs of the AD7719. This scheme ensures that the analog of applications, the user will not have to perform any field cali- input voltage span remains ratiometric to the reference voltage. bration given the excellent offset and gain drift performance of Any errors in the analog input voltage due to the temperature drift the device as a result of the signal chain chopping employed in of the RTD current source is compensated for by the variation the signal chain. DN25D 3.3V 0.01�F 10�F 0.1�F 10�F 1.25V DV AV V REF OUT1 BOOST LV DD DD CC 0.01�F REF OUT2 COMP AIN1 REFIN2 MAIN VARIABLES REF IN DRIVE AIN2 REFIN(+) 4.7�F 1k� AIN3 0.1�F V CC AIN4 REFIN(–) CLOCK 1000pF AD7719 LATCH MICROCONTROLLER AD421 AIN5 DATA SECONDARY GND VARIABLES AIN5 COM CS LOOP POWER DOUT LOOP SCLK RTN COM DIN C1 C2 C3 DGND AGND Figure 24. Smart Transmitter Employing the AD7719 –38– REV. A AD7719 OUTLINE DIMENSIONS 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) � 45� 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8� 1.27 (0.0500) SEATING 0� 0.51 (0.0201) 1.27 (0.0500) 0.32 (0.0126) COPLANARITY PLANE BSC 0.33 (0.0130) 0.40 (0.0157) 0.10 0.23 (0.0091) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8� 0.75 0.30 0.20 0� 0.60 0.19 COPLANARITY SEATING 0.09 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MS-153AE REV. A –39– AD7719 Revision History Location Page 4/03—Data Sheet changed from REV. 0 to REV. A. Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 –40– REV. A C02460–0–4/03(A)