ANALOG DEVICES AD7715

3 V/5 V, 450 μA 16-Bit, Sigma-Delta ADC AD7715 FEATURES FUNCTIONAL BLOCK DIAGRAM AV DV REF IN(–) REF IN(+) DD DD Charge-balancing ADC 16-bits no missing codes CHARGE BALANCING ADC 0.0015% nonlinearity Σ-∆ DIGITAL Programmable gain front end AIN(+) MODULATOR FILTER BUFFER PGA Gains of 1, 2, 32 and 128 AIN(–) Differential input capability A = 1 TO 128 CLOCK MCLK IN GENERATION MCLK OUT Three-wire serial interface RESET SERIAL SPI-, QSPI™-, MICROWIRE™-, and DSP-compatible INTERFACE SCLK Ability to buffer the analog input REGISTER BANK CS 3 V (AD7715-3) or 5 V (AD7715-5) operation DIN DOUT Low supply current: 450 μA maximum @ 3 V supplies AD7715 DRDY Low-pass filter with programmable output update AGND DGND 16-lead SOIC/PDIP/TSSOP Figure 1. GENERAL DESCRIPTION The AD7715 is a complete analog front end for low frequency CMOS construction ensures very low power dissipation, and measurement applications. The part can accept low level input power-down mode reduces the standby power consumption to signals directly from a transducer and outputs a serial digital 50 μW typical. The part is available in a 16-lead, 0.3 inch-wide, word. It employs a Σ-Δ conversion technique to realize up to plastic dual-in-line package (PDIP) as well as a 16-lead 0.3 inch 16 bits of no missing codes performance. The input signal is wide small outline (SOIC_W) package and a 16-lead TSSOP applied to a proprietary programmable gain front end based package. around an analog modulator. The modulator output is processed PRODUCT HIGHLIGHTS by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing 1. The AD7715 consumes less than 450 μA in total supply adjustment of the filter cutoff and output update rate. current at 3 V supplies and 1 MHz master clock, making it ideal for use in low-power systems. Standby current is less The AD7715 features a differential analog input as well as a than 10 μA. differential reference input. It operates from a single supply (3 V 2. The programmable gain input allows the AD7715 to accept or 5 V). It can handle unipolar input signal ranges of 0 mV to input signals directly from a strain gage or transducer 20 mV, 0 mV to 80 mV, 0 V to 1.25 V and 0 V to 2.5 V. It can removing a considerable amount of signal conditioning. also handle bipolar input signal ranges of ±20 mV, ±80 mV, 3. The AD7715 is ideal for microcontroller or DSP processor ±1.25 V and ±2.5 V. These bipolar ranges are referenced to the applications with a three-wire serial interface reducing the negative input of the differential analog input. The AD7715 number of interconnect lines and reducing the number thus performs all signal conditioning and conversion for a of optocouplers required in isolated systems. The part single channel system. contains on-chip registers which allow software control The AD7715 is ideal for use in smart, microcontroller, or DSP- over output update rate, input gain, signal polarity, and based systems. It features a serial interface that can be configured calibration modes. for three-wire operation. Gain settings, signal polarity, and 4. The part features excellent static performance specifications update rate selection can be configured in software using the with 16-bits no missing codes, ±0.0015% accuracy, and low input serial port. The part contains self-calibration and system rms noise (<550 nV). Endpoint errors and the effects of calibration options to eliminate gain and offset errors on the temperature drift are eliminated by on-chip calibration part itself or in the system. options, which remove zero-scale and full-scale errors. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08519-001 AD7715 TABLE OF CONTENTS Features .............................................................................................. 1 Digital Filtering........................................................................... 21 Functional Block Diagram .............................................................. 1 Analog Filtering.......................................................................... 23 General Description ......................................................................... 1 Calibration................................................................................... 23 Product Highlights ........................................................................... 1 Using the AD7715 .......................................................................... 26 Revision History ............................................................................... 2 Clocking and Oscillator Circuit ............................................... 26 Specifications..................................................................................... 3 System Synchronization ............................................................ 26 AD7715-5 ...................................................................................... 3 Reset Input .................................................................................. 27 AD7715-3 ...................................................................................... 5 Standby Mode ............................................................................. 27 Timing Characteristics ................................................................ 8 Accuracy...................................................................................... 27 Absolute Maximum Ratings............................................................ 9 Drift Considerations .................................................................. 27 ESD Caution.................................................................................. 9 Power Supplies............................................................................ 28 Pin Configuration And Function Descriptions.......................... 10 Digital Interface.......................................................................... 29 Terminology .................................................................................... 11 Configuring the AD7715............................................................... 31 On-Chip Registers.......................................................................... 12 Microcontroller/Microprocessor Interfacing ............................. 32 Communications Register (RS1, RS0 = 0, 0) .......................... 13 AD7715 to 68HC11 Interface ................................................... 32 AD7715 to 8XC51 Interface...................................................... 33 Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status: 28 Hex .......................................................................................... 14 AD7715 to ADSP-2103/ADSP-2105 Interface ....................... 33 Test Register (RS1, RS0 = 1, 0).................................................. 15 Code For Setting Up The AD7715............................................... 34 Data Register (RS1, RS0 = 1, 1) ................................................ 15 C Code for Interfacing AD7715 to 68HC11........................... 34 Output Noise ................................................................................... 16 Applications Information .............................................................. 36 AD7715-5 .................................................................................... 16 Pressure Measurement............................................................... 36 AD7715-3 .................................................................................... 17 Temperature Measurement ....................................................... 37 Calibration Sequences.................................................................... 18 Smart Transmitters..................................................................... 38 Circuit Description......................................................................... 19 Outline Dimensions....................................................................... 39 Analog Input ............................................................................... 19 Ordering Guide .......................................................................... 40 Reference Input........................................................................... 21 REVISION HISTORY 12/09—Rev. C to Rev. D Updated Format..................................................................Universal Changes to Table 5............................................................................ 9 Updated Outline Dimensions ....................................................... 39 2/00—Rev. B to Rev. C Rev. D | Page 2 of 40 AD7715 SPECIFICATIONS AD7715-5 AV = 5 V, DV = 3 V or 5 V, REF IN(+) = 2.5 V; REF IN(−) = AGND; f = 2.4576 MHz, unless otherwise noted. All specifications DD DD CLK IN T to T , unless otherwise noted. MIN MAX Table 1. 1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 16 Bits Guaranteed by design; filter notch ≤ 60 Hz Output Noise See Table 15 to Table 18 Depends on filter cutoffs and selected gain Integral Nonlinearity ±0.0015 % of FSR Filter notch ≤ 60 Hz 2 Unipolar Offset Error See Table 15 to Table 22 3 Unipolar Offset Drift 0.5 μV/°C 2 Bipolar Zero Error See Table 15 to Table 22 3 Bipolar Zero Drift 0.5 μV/°C 2, 4 Positive Full-Scale Error See Table 15 to Table 22 3, 5 Full-Scale Drift 0.5 μV/°C 2, 6 Gain Error See Table 15 to Table 22 3, 7 Gain Drift 0.5 ppm of FSR/°C 2 Bipolar Negative Full-Scale Error ±0.0015 % of FSR Typically ±0.0004% 3 1 Bipolar Negative Full-Scale Drift μV/°C For gains of 1 and 2 0.6 μV/°C For gains of 32 and 128 ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN unless noted Input Common-Mode Rejection dB At dc; typically 102 dB (CMR) 90 8 Normal-Mode 50 Hz Rejection 98 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH 8 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH Normal-Mode 60 Hz Rejection 98 8 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH Common-Mode 50 Hz Rejection 150 8 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f Common-Mode 60 Hz Rejection 150 NOTCH 9 Common-Mode Voltage Range AGND AV V AIN for the BUF bit of setup register = 0 and REF IN DD 8 AGND – 0.03 AV + 0.03 V AIN for the BUF bit of setup register = 0 and REF IN Absolute AIN/REF IN Voltage DD Absolute/Common-Mode AIN − 1.5 V BUF bit of setup register = 1 AGND + 0.05 AVDD 9 Voltage 8 AIN DC Input Current nA 1 8 pF AIN Sampling Capacitance 10 10 11 AIN Differential Voltage Range 0 to +V /GAIN nom Unipolar input range (B/U bit of setup register = 1) REF ±V/GAIN nom B REF Bipolar input range ( /U bit of setup register = 0) AIN Input Sampling Rate, f GAIN × f /64 For gains of 1 and 2 S CLK IN f /8 For gains of 32 and 128 CLK IN REF IN(+) − REF IN(−) Voltage 2.5 V nom ±1% for specified performance; functional with lower V REF REF IN Input Sampling Rate, f f /64 S CLK IN LOGIC INPUTS Input Current ±10 μA All Inputs Except MCLK IN V , Input Low Voltage 0.8 V DV = 5 V INL DD V , Input Low Voltage 0.4 V DV = 3.3 V INL DD V , Input High Voltage 2.4 V DV = 5 V INH DD V , Input High Voltage 2.0 V INH MCLK IN Only V , Input Low Voltage 0.8 V DV = 5 V INL DD V , Input Low Voltage 0.4 V DV = 3.3 V INL DD V , Input High Voltage 3.5 V DV = 5 V INH DD V , Input High Voltage 2.5 V DV = 3.3 V INH DD Rev. D | Page 3 of 40 AD7715 1 Parameter Min Typ Max Unit Conditions/Comments LOGIC OUTPUTS (Including MCLK OUT) 12 VOL, Output Low Voltage 0.4 V ISINK = 800 μA except for MCLK OUT ; DVDD = 5 V 12 VOL, Output Low Voltage V 0.4 ISINK = 100 μA except for MCLK OUT ; DVDD = 3.3 V 12 VOH, Output High Voltage V 4.0 ISOURCE = 200 μA except for MCLK OUT ; DVDD = 5 V 12 V , Output High Voltage OH DV − 0.6 V ISOURCE = 100 μA except for MCLK OUT ; DVDD = 3.3 V DD Floating State Leakage Current ±10 μA 13 Floating State Output Capacitance 9 pF Data Output Coding Binary Unipolar mode Offset binary Bipolar mode 1 Temperature range as follows: A version, −40°C to +85°C. 2 A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the temperature of interest. 3 Recalibration at any temperature removes these drift errors. 4 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 5 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 6 Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for bipolar ranges. 7 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed. 8 These numbers are guaranteed by design and/or characterization. 9 This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative than AGND − 30 mV. 10 The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive than AV + 30 mV or go more negative than AGND − 30 mV. DD 11 VREF = REF IN(+) − REF IN(−). 12 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 13 Sample tested at 25°C to ensure compliance. Rev. D | Page 4 of 40 AD7715 AD7715-3 AVDD = 3 V, DVDD = 3 V, REF IN (+) = 1.25 V; REF IN(−) = AGND; fCLK IN = 2.4576 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 16 Bits Guaranteed by design; filter notch ≤ 60 Hz Output Noise Depends on filter cutoffs and selected gain See Table 18 to Table 22 Integral Nonlinearity ±0.0015 % of FSR Filter notch ≤ 60 Hz 2 Unipolar Offset Error See Table 15 to Table 22 3 Unipolar Offset Drift 0.2 μV/°C 2 Bipolar Zero Error See Table 15 to Table 22 3 0.2 μV/°C Bipolar Zero Drift 2, 4 Positive Full-Scale Error See Table 15 to Table 22 3, 5 0.2 μV/°C Full-Scale Drift 2, 6 Gain Error See Table 15 to Table 22 3, 7 0.2 ppm of Gain Drift FSR/°C 2 ±0.003 % of FSR Typically ±0.0004% Bipolar Negative Full-Scale Error 3 1 μV/°C For gains of 1 and 2 Bipolar Negative Full-Scale Drift 0.6 μV/°C For gains of 32 and 128 ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN unless noted Input Common-Mode Rejection 90 dB At dc; tpically 102 dB (CMR) 8 Normal-Mode 50 Hz Rejection 98 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × f NOTCH 8 98 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f Normal-Mode 60 Hz Rejection NOTCH 8 Common-Mode 50 Hz Rejection 150 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH 8 Common-Mode 60 Hz Rejection 150 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH 9 Common-Mode Voltage Range AGND AVDD V AIN for BUF bit of setup register = 0 and REF IN 8 AGND − 0.03 AVDD + 0.03 V AIN for BUF bit of setup register = 0 and REF IN Absolute AIN/REF IN Voltage Absolute/Common-Mode AIN AGND + 0.05 AV − 1.5 V BUF bit of setup register = 1 DD 9 Voltage 8 1 nA AIN DC Input Current 8 10 pF AIN Sampling Capacitance 10 AIN Differential Voltage Range 0 to nom Unipolar input range (B/U bit of setup register = 1) 11 +VREF/GAIN ±VREF/GAIN nom Bipolar input range (B/U bit of setup register = 0) AIN Input Sampling Rate, fS GAIN × fCLK IN/64 For gains of 1 and 2 fCLK IN/8 For gains of 32 and 128 REF IN(+) − REF IN(−) Voltage 1.25 V nom ±1% for specified performance; functional with lower V REF REF IN Input Sampling Rate, f f /64 S CLK IN LOGIC INPUTS Input Current ±10 μA All Inputs Except MCLK IN VINL, Input Low Voltage 0.8 V VINH, Input High Voltage 2.0 V MCLK IN Only VINL, Input Low Voltage 0.4 V V , Input High Voltage 2.5 V INH Rev. D | Page 5 of 40 AD7715 1 Parameter Min Typ Max Unit Conditions/Comments LOGIC OUTPUTS (Including MCLK OUT) 12 VOL, Output Low Voltage 0.4 V ISINK = 100 μA except for MCLK OUT 12 VOH, Output High Voltage DVDD − 0.6 V ISOURCE = 100 μA except for MCLK OUT Floating State Leakage Current ±10 μA 13 Floating State Output Capacitance 9 pF Data Output Coding Binary Unipolar mode Offset binary Bipolar mode 1 Temperature range as follows: A version, −40°C to +85°C. 2 A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the temperature of interest. 3 Recalibration at any temperature removes these drift errors. 4 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 5 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 6 Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for bipolar ranges. 7 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed. 8 These numbers are guaranteed by design and/or characterization. 9 This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AV + 30 mV or go more negative DD than AGND − 30 mV. 10 The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive than AVDD + 30 mV or go more negative than AGND − 30 mV. 11 V = REF IN(+) − REF IN(−). REF 12 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 13 Sample tested at 25°C to ensure compliance. Rev. D | Page 6 of 40 AD7715 AV = 3 V to 5 V, DV = 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to DD DD 2.4576 MHz, unless otherwise noted. All specifications T to T , unless otherwise noted. MIN MAX Table 3. Parameter Min Typ Max Unit Conditions/Comments SYSTEM CALIBRATION 1 Positive Full-Scale Calibration Limit (1.05 × V GAIN Is the selected PGA gain (1, 2, 32, or 128) VREF)/GAIN 1 −(1.05 × V GAIN Is the selected PGA gain (1, 2, 32, or 128) Negative Full-Scale Calibration Limit VREF)/GAIN 2 Offset Calibration Limit −(1.05 × V GAIN Is the selected PGA gain (1, 2, 32, or 128) VREF)/GAIN 2 0.8 × V GAIN Is the selected PGA gain (1, 2, 32, or 128) Input Span V /GAIN REF (2.1 × V )/GAIN V GAIN Is the selected PGA gain (1, 2, 32, or 128) REF POWER REQUIREMENTS Power Supply Voltages AVDD Voltage (AD7715-3) 3 3.6 V For specified performance AVDD Voltage (AD7715-5) 4.75 5.25 V For specified performance DVDD Voltage 3 5.25 V For specified performance Power Supply Currents AVDD Current AVDD = 3.3 V or 5 V. gain = 1 to 128 (fCLK IN = 1 MHz) or gain = 1 or 2 (fCLK IN = 2.4576 MHz) 0.27 mA Typically 0.2 mA; BUF bit of the setup register = 0 0.6 mA Typically 0.4 mA; BUF bit of the setup register = 1, AV DD 3 = 3.3 V or 5 V; gain = 32 or 128 (f = 2.4576 MHz) CLK IN 0.5 mA Typically 0.3 mA; BUF bit of the setup register = 0 1.1 mA Typically 0.8 mA; BUF bit of the setup register = 1 4 DV Current Digital inputs = 0 V or DV ; external MCLK IN DD DD 0.18 mA Typically 0.15 mA. DV = 3.3 V. f = 1 MHz DD CLK IN 0.4 mA Typically 0.3 mA. DV = 5 V. f = 1 MHz DD CLK IN 0.5 mA Typically 0.4 mA. DV = 3.3 V. f = 2.4576 MHz DD CLK IN 0.8 mA Typically 0.6 mA. DV = 5 V. f = 2.4576 MHz DD CLK IN 5 6 Power Supply Rejection Depends on gain dB 4 Normal-Mode Power Dissipation AVDD = DVDD = 3.3 V; digital inputs = 0 V or DVDD; external MCLK IN 1.5 mW BUF bit = 0. all gains 1 MHz clock 2.65 mW BUF bit = 1. all gains 1 MHz clock 3.3 mW BUF bit = 0. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz 5.3 mW BUF bit = 1. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz 4 AVDD = DVDD = 5 V. digital inputs = 0 V or DVDD; external Normal-Mode Power Dissipation MCLK IN 3.25 mW BUF bit = 0; all gains 1 MHz clock 5 mW BUF bit = 1; all gains 1 MHz clock 6.5 mW BUF bit = 0; gain = 32 or 128 @ f = 2.4576 MHz CLK IN 9.5 mW BUF bit = 1; gain = 32 or 128 @ f = 2.4576 MHz CLK IN 7 Standby (Power-Down) Current 20 μA External MCLK IN = 0 V or DV . typically 10 μA; V = 5 V DD DD 7 10 μA External MCLK IN = 0 V or DV . typically 5 μA; V = 3.3 V Standby (Power-Down) Current DD DD 1 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs all 0s. 2 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND − 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 3 Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency. 4 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV current and power dissipation will vary depending on the DD crystal or resonator type (see the Clocking and Oscillator Circuit section). 5 Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter notches of 20 Hz or 60 Hz. 6 PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical. 7 If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see the Standby Mode section). Rev. D | Page 7 of 40 AD7715 TIMING CHARACTERISTICS DVDD = 3 V to 5.25 V; AVDD = 3 V to 5.25 V; AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted. Table 4. Limit at T , T MIN MAX 1, 2 (A Version) Parameter Unit Conditions/Comments 3, 4 f 400 kHz min CLKIN Master clock frequency: crystal oscillator or externally supplied for specified performance 2.5 MHz max tCLK IN LO 0.4 × tCLK IN ns min Master clock input low time; tCLK IN = 1/fCLK IN tCLK IN HI 0.4 × tCLK IN ns min Master clock input high time DRDY high time t1 500 × tCLK IN ns nom 100 ns min RESET pulsewidth t2 Read Operation 0 ns min DRDY to CS setup time t3 120 ns min CS falling edge to SCLK rising edge setup time t4 5 t5 0 ns min SCLK falling edge to data valid delay 80 ns max DV = 5 V DD 100 ns max DV = 3.3 V DD t 100 ns min SCLK high pulsewidth 6 t7 100 ns min SCLK low pulsewidth 0 ns min CS rising edge to SCLK rising edge hold time t8 6 t 10 ns min Bus relinquish time after SCLK rising edge 9 60 ns max DV = +5 V DD 100 ns max DV = +3.3 V DD 7 t 100 ns max SCLK falling edge to DRDY high 10 Write Operation 120 ns min CS falling edge to SCLK rising edge setup time t11 t 30 ns min Data valid to SCLK rising edge setup time 12 t 20 ns min Data valid to SCLK rising edge hold time 13 t 100 ns min SCLK high pulsewidth 14 t15 100 ns min SCLK low pulsewidth t 0 ns min CS rising edge to SCLK rising edge hold time 16 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 8 and Figure 9. 3 CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7715 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while is high although take care that subsequent reads do not occur close to the next output update. I (800µA AT DV = 5V SINK DD 100µA AT DV = 3.3V) DD TO +1.6V OUTPUT PIN 50pF I (200µA AT DV = 5V SOURCE DD 100µA AT DV = 3.3V) DD Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. D | Page 8 of 40 08519-002 AD7715 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational AV to AGND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute AV to DGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect AVDD to DVDD −0.3 V to +7 V device reliability. DVDD to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V DGND to AGND −0.3 V to +7 V ESD CAUTION Analog Input Voltage to AGND −0.3 V to AV + 0.3 V DD Reference Input Voltage to AGND −0.3 V to AV + 0.3 V DD Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V Operating Temperature Range Commercial (A Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Plastic DIP Package, Power Dissipation 450 mW θJA Thermal Impedance 105°C/W Lead Temperature, (Soldering, 10 sec) 260°C SOIC Package, Power Dissipation 450 mW θ Thermal Impedance 75°C/W JA Lead Temperature, Reflow Soldering 260°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 128°C/W Lead Temperature, Reflow Soldering +260°C Power Dissipation (Any Package) to +75°C 450 mW ESD Rating >4000 V Rev. D | Page 9 of 40 AD7715 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 16 DGND MCLK IN 2 15 DV DD MCLK OUT 3 14 DIN AD7715 4 13 DOUT CS TOP VIEW 5 12 RESET DRDY (Not to Scale) AV 6 11 AGND DD AIN(+) 7 10 REF IN(–) AIN(–) 8 9 REF IN(+) Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Logic input. An external serial clock is applied to this input to access serial data from the AD7715. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7715 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock input frequencies of both 1 MHz and 2.4576 MHz. 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry. 4 CS Chip Select. Active low logic input used to select the AD7715. With this input hardwired low, the AD7715 can operate in its three-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7715. 5 RESET Logic Input. Active low input which resets the control logic, interface logic, calibration coefficients, digital filter, and analog modulator of the part to power-on status. 6 AV Analog Positive Supply Voltage, 3.3 V nominal (AD7715-3) or 5 V nominal (AD7715-5). DD 7 AIN(+) Analog Input. Positive input of the programmable gain differential analog input to the AD7715. 8 AIN(−) Analog Input. Negative input of the programmable gain differential analog input to the AD7715. 9 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7715. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere between AV and AGND. DD 10 REF IN(−) Reference Input. Negative input of the differential reference input to the AD7715. The REF IN(−) can lie anywhere between AV and AGND provided REF IN(+) is greater than REF IN(–). DD 11 AGND Ground Reference Point for Analog Circuitry. For correct operation of the AD7715, no voltage on any of the other pins should go more than 30 mV negative with respect to AGND. 12 DRDY Logic Output. A logic low on this output indicates that a new output word is available from the AD7715 data register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has taken place between output updates, the DRDY line returns high for 500 × t cycles prior to the next output update. While CLK IN DRDY is high, a read operation should not be attempted or in progress to avoid reading from the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY is also used to indicate when the AD7715 has completed its on-chip calibration sequence. 13 DOUT Serial data output with serial data being read from the output shift register on the part. This output shift register can contain information from the setup register, communications register or data register depending on the register selection bits of the communications register. 14 DIN Serial data input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the setup register or communications register depending on the register selection bits of the communications register. 15 DV Digital Supply Voltage, 3.3 V or 5 V nominal. DD 16 DGND Ground reference point for digital circuitry. Rev. D | Page 10 of 40 08519-003 AD7715 TERMINOLOGY Positive Full-Scale Overrange Integral Nonlinearity Positive full-scale overrange is the amount of overhead available This is the maximum deviation of any code from a straight to handle input voltages on AIN(+) input greater than AIN−) + line passing through the endpoints of the transfer function. VREF/GAIN (for example, noise peaks or excess voltages due The endpoints of the transfer function are zero-scale (not to to system gain errors in system calibration routines) without be confused with bipolar zero), a point 0.5 LSB below the first introducing errors due to overloading the analog modulator code transition (000 … 000 to 000 … 001) and Full-Scale, a or overflowing the digital filter. point 0.5 LSB above the last code transition (111 … 110 to 111 … 111). The error is expressed as a percentage of full scale. Negative Full-Scale Overrange This is the amount of overhead available to handle voltages Positive Full-Scale Error on AIN(+) below AIN(−) −VREF/GAIN without overloading the Positive Full-Scale Error is the deviation of the last code analog modulator or overflowing the digital filter. Note that the transition (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) analog input accepts negative voltage peaks even in the unipolar voltage (AIN(−) + VREF/GAIN −3/2 LSBs). It applies to both mode provided that AIN(+) is greater than AIN(−) and greater unipolar and bipolar analog input ranges. than AGND − 30 mV. Unipolar Offset Error Offset Calibration Range Unipolar Offset Error is the deviation of the first code transition In the system calibration modes, the AD7715 calibrates its from the ideal AIN(+) voltage (AIN(−) + 0.5 LSB) when operating offset with respect to the analog input. The offset calibration in the unipolar mode. range specification defines the range of voltages that the AD7715 Bipolar Zero Error can accept and still calibrate offset accurately. This is the deviation of the midscale transition (0111 . . . 111 to Full-Scale Calibration Range 1000 . . . 000) from the ideal AIN(+) voltage (AIN(−) − 0.5 LSB) This is the range of voltages that the AD7715 can accept in the when operating in the bipolar mode. system calibration mode and still calibrate full scale correctly. Gain Error Input Span This is a measure of the span error of the ADC. It includes full- In system calibration schemes, two voltages applied in sequence scale errors but not zero-scale errors. For unipolar input ranges to the AD7715’s analog input define the analog input range. The it is defined as (full scale error—unipolar offset error) while for input span specification defines the minimum and maximum bipolar input ranges it is defined as (full-scale error—bipolar input voltages from zero to full scale that the AD7715 can accept zero error). and still calibrate gain accurately. Bipolar Negative Full-Scale Error This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(−) − VREF/GAIN + 0.5 LSB), when operating in the bipolar mode. Rev. D | Page 11 of 40 AD7715 ON-CHIP REGISTERS The AD7715 contains four on-chip registers, which can be the output data register) starts with a write operation to the accessed by via the serial port on the part. The first of these communications register followed by a read operation from the is a communications register that decides whether the next selected register. The communication register also controls the operation is a read or write operation and also decides which standby mode and the operating gain of the part. The DRDY status register the read or write operation accesses. All communi- is also available by reading from the communications register. The cations to the part must start with a write operation to the second register is a setup register that determines calibration communications register. After power-on or RESET, the modes, filter selection and bipolar/unipolar operation. The device expects a write to its communications register. The data third register is the data register from which the output data written to this register determines whether the next operation from the part is accessed. The final register is a test register to the part is a write or a read operation and also determines to that is accessed when testing the device. It is advised that the which register this read or write operation occurs. Therefore, user does not attempt to access or change the contents of the write access to any of the other registers on the part starts with test register as it may lead to unspecified operation of the a write operation to the communications register followed by a device. The registers are discussed in more detail in the write to the selected register. A read operation from any register following sections. on the part (including the communications register itself and Rev. D | Page 12 of 40 AD7715 COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an eight-bit register from which data can either be read or to which data can be written. All communica- tions to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and to which register this operation takes place. Once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface, and on power-up or after a reset, the AD7715 is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, if a write operation to the device of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7715 returns to this default state. Table 7 outlines the bit designations for the communications register. Table 7. Communications Register 0/DRDY ZERO RS1 RS0 R/W STBY G1 G0 Table 8. Bit Name Description DRDY For a write operation, a 0 must be written to this bit so that the write operation to the communications register actually takes 0/ place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. Instead, it stays at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next 7 bits are loaded to the communications register. For a read DRDY DRDY operation, this bit provides the status of the flag from the part. The status of this bit is the same as the output pin. ZERO For a write operation, a 0 must be written to this bit for correct operation of the part. Failure to do this results in unspecified operation of the device. For a read operation, a 0 is read back from this bit location. RS1, RS0 Register Selection Bits. These bits select to which one of four on-chip registers the next read or write operation takes place as shown in Table 9 along with the register size. When the read or write to the selected register is complete, the part returns to where it is waiting for a write operation to the Communications Register. It does not remain in a state where it continues to access the selected register. W Read/Write Select. This bit selects whether the next operation R/ is a read or write operation to the selected register. A 0 indicates a write cycle as the next operation to the appropriate register, while a 1 indicates a read operation from the appropriate register. STBY Standby. Writing a 1 to this bit puts the part in its standby or power-down mode. In this mode, the part consumes only 10 μA of power supply current. The part retains its calibration and control word information when in STANDBY. Writing a 0 to this bit places the part in its normal operating mode. The default value for this bit after power-on or RESET is 0. G1, G0 Gain Select bits. See Table 10. Table 9. Register Section RS1 RS0 Register Register Size 0 0 Communications register 8 bits 0 1 Setup register 8 bits 1 0 Test register 8 bits 1 1 Data register 16 bits Table 10. G2 G1 Gain Setting 0 0 1 0 1 2 1 0 32 1 1 128 Rev. D | Page 13 of 40 AD7715 SETUP REGISTER (RS1, RS0 = 0, 1); POWER ON/RESET STATUS: 28 HEX The setup register is an eight-bit register from which data can either be read or to which data can be written. This register controls the setup that the device is to operate in such as the calibration mode, and output rate, unipolar/bipolar operation etc. Table 11 outlines the bit designations for the setup register. Table 11. Setup Register MD1 MD0 CLK FS1 FS0 B/U BUF FSYNC Table 12. Bit Name Description MD1, MD0 Mode select bits. These bits select the operating mode of the AD7715 (see Table 13). CLK The clock bit (CLK) should be set in accordance with the operating frequency of the AD7715. If the device has a master clock frequency of 2.4576 MHz, then this bit should be set to a 1. If the device has a master clock frequency of 1 MHz, then this bit should be set to a 0. This bit sets up the correct scaling currents for a given master clock and also chooses (along with FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the master clock frequency of the device, then the device may not operate to specification. The default value for this bit after power-on or reset is 1. FS1, FS0 Along with the CLK bit, FS1 and FS0 determine the output update rate, filter first notch and −3 dB frequency as outlined in 3 3 Table 14. The on-chip digital filter provides a sinc (or (Sinx/x) ) filter response. In association with the gain selection, it also determines the output noise (and therefore, the resolution) of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Table 15 through Table 22 show the effect of the filter notch frequency and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. The default value for these bits is 1, 0. The settling-time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is 80 ms maximum. If the first notch is at 500 Hz, the settling time of the filter to a full-scale input step is 8 ms max. This settling-time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling-time time is 3 × 1/(output data rate) from when FSYNC returns low. The −3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter −3 dB frequency = 0.262 × filter first notch frequency B/U A 0 in this bipolar/unipolar operation bit selects bipolar operation. This is the default (power-on or reset) status of this bit. A 1 in this bit selects unipolar operation. BUF With this buffer control bit low, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current flowing in the AVDD line is reduced to 250 μA (all gains at fCLK IN = 1 MHz and gain of 1 or 2 at fCLK IN = 2.4576 MHz) or 500 μA (gains of 32 and 128 @ fCLK IN = 2.4576 MHz) and the output noise from the part is at its lowest. When this bit is high, the on- chip buffer is in series with the analog input allowing the input to handle higher source impedances. FSYNC When this filter synchronization bit is high, the nodes of the digital filter, the filter control logic and the this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), that is, the settling-time of DRDY the filter. This FSYNC bit does not affect the digital interface and does not reset the output if it is low. Rev. D | Page 14 of 40 AD7715 Table 13. MD1 MD0 Operating Mode 0 0 Normal mode. This operating mode is the default mode of operation of the device whereby the device is performing normal conversions. The AD7705 is placed in this mode after power-on or reset. 0 1 Self-calibration. This is a one step calibration sequence and when complete the part returns to normal mode with MD1 and DRDY DRDY MD0 returning to 0, 0. The output or bit goes high when calibration is initiated and returns low when this self- calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally generated VREF/selected gain. 1 0 Zero-scale system calibration. Zero-scale system calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the DRDY calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0. 1 1 Full-scale system calibration. Full-scale system calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the DRDY DRDY calibration. The output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0. Table 14. Output Update Rates 1 CLK FS1 FS0 Output Update Rate −3 dB Filter Cutoff 0 0 0 20 Hz 5.24 Hz 0 0 1 25 Hz 6.55 Hz 0 1 0 100 Hz 26.2 Hz 0 1 1 200 Hz 52.4 Hz 1 0 0 50 Hz 13.1 Hz 1 0 1 60 Hz 15.7 Hz (default status) 1 1 0 250 Hz 65.5 Hz 1 1 1 500 Hz 131 Hz 1 Assumes correct clock frequency at MCLK IN pin. TEST REGISTER (RS1, RS0 = 1, 0) DATA REGISTER (RS1, RS0 = 1, 1) The part contains a test register, which is used in testing the The data register on the part is a read-only 16-bit register device. The user is advised not to change the status of any of the that contains the most up-to-date conversion result from the bits in this register from the default (power-on or reset) status AD7715. If the communications register data sets up the part of all 0s as the part will be placed in one of its test modes and for a write operation to this register, a write operation must will not operate correctly. If the part enters one of its test modes, actually take place to return the part to where it is expecting RESET a write operation to the communications register (the default exercising will exit the part from the mode. An alterna- state of the interface). However, the 16 bits of data written to tive scheme for getting the part out of one of its test modes, is to the part will be ignored by the AD7715. reset the interface by writing 32 successive 1s to the part and then load all 0s to the test register. Rev. D | Page 15 of 40 AD7715 OUTPUT NOISE the resolution for which there is no code flicker. They are not AD7715-5 calculated based on rms noise but on peak-to-peak noise. The Table 15 shows the AD7715-5 output rms noise for the selecta- numbers given are for the bipolar input ranges with a VREF of ble notch and −3 dB frequencies for the part, as selected by FS1 2.5 V and for the BUF bit of the setup register = 0. These num- and FS0 of the setup register. The numbers given are for the bers are typical, are generated at an analog input voltage of 0 V bipolar input ranges with a VREF of 2.5 V. These numbers are and are rounded to the nearest LSB. typical and are generated at a differential analog input voltage Meanwhile, Table 17 and Table 18 show rms noise and peak- of 0 V with the part used in unbuffered mode (BUF bit of the to-peak resolution respectively with the AD7715-5 operating setup register = 0). Table 16 meanwhile shows the output peak- under the same conditions as above except that now the part is to-peak noise for the selectable notch and −3 dB frequencies operating in buffered mode (BUF bit of the setup register = 1). for the part. It is important to note that these numbers represent Table 15. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Output RMS Noise (μV) MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 3.8 1.9 0.6 0.52 60 Hz 25 Hz 15.72 Hz 6.55 Hz 4.8 2.4 0.6 0.62 250 Hz 100 Hz 65.5 Hz 26.2 Hz 103 45 3.0 1.6 500 Hz 200 Hz 131 Hz 52.4 Hz 530 250 18 5.5 Table 16. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Unbuffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 16 16 16 14 60 Hz 25 Hz 15.72 Hz 6.55 Hz 16 16 16 13 250 Hz 100 Hz 65.5 Hz 26.2 Hz 13 13 13 12 500 Hz 200 Hz 131 Hz 52.4 Hz 10 10 10 10 Table 17. Output RMS Noise vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Output RMS Noise (μV) MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 4.3 2.2 0.9 0.9 60 Hz 25 Hz 15.72 Hz 6.55 Hz 5.1 3.1 1.0 1.0 250 Hz 100 Hz 65.5 Hz 26.2 Hz 103 50 3.9 2.1 500 Hz 200 Hz 131 Hz 52.4 Hz 550 280 18 6 Table 18. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-5 (Buffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 16 16 15 13 60 Hz 25 Hz 15.72 Hz 6.55 Hz 16 16 15 13 250 Hz 100 Hz 65.5 Hz 26.2 Hz 13 13 13 12 500 Hz 200 Hz 131 Hz 52.4 Hz 10 10 10 10 Rev. D | Page 16 of 40 AD7715 for which there is no code flicker. They are not calculated based AD7715-3 on rms noise but on peak-to-peak noise. The numbers given are Table 19 shows the AD7715-3 output rms noise for the selecta- for the bipolar input ranges with a V of 1.25 V and for the REF ble notch and −3 dB frequencies for the part, as selected by FS1 BUF bit of the setup register = 0. These numbers are typical, and FS0 of the setup register. The numbers given are for the are generated at an analog input voltage of 0 V and are rounded bipolar input ranges with a V of 1.25 V. These numbers are REF to the nearest LSB. typical and are generated at an analog input voltage of 0 V with Meanwhile, Table 21 and Table 22 show rms noise and peak- the part used in unbuffered mode (BUF bit of the setup register to-peak resolution respectively with the AD7715-3 operating = 0). Table 20 meanwhile shows the output peak-to-peak noise under the same conditions as above except that now the part is for the selectable notch and −3 dB frequencies for the part. It is operating in buffered mode (BUF bit of the setup register = 1). important to note that these numbers represent the resolution Table 19. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Output RMS Noise (μV) MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 3.0 1.7 0.7 0.65 60 Hz 25 Hz 15.72 Hz 6.55 Hz 3.4 2.1 0.7 0.7 250 Hz 100 Hz 65.5 Hz 26.2 Hz 45 20 2.2 1.6 500 Hz 200 Hz 131 Hz 52.4 Hz 270 135 9.7 3.3 Table 20. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Unbuffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 16 16 14 12 60 Hz 25 Hz 15.72 Hz 6.55 Hz 16 16 14 12 250 Hz 100 Hz 65.5 Hz 26.2 Hz 13 13 13 11 500 Hz 200 Hz 131 Hz 52.4 Hz 11 11 10 10 Table 21. Output RMS Noise vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Output RMS Noise (μV) MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 4.5 2.4 0.9 0.9 60 Hz 25 Hz 15.72 Hz 6.55 Hz 5.1 2.9 0.9 1.0 250 Hz 100 Hz 65.5 Hz 26.2 Hz 50 25 2.6 2 500 Hz 200 Hz 131 Hz 52.4 Hz 270 135 9.7 3.3 Table 22. Peak-to-Peak Resolution vs. Gain and Output Update Rate for AD7715-3 (Buffered Mode) Filter First Notch and Output Data Rate −3 dB Frequency Typical Peak-to-Peak Resolution in Bits MCLK IN = MCLK IN = MCLK IN = MCLK IN = 2.4576 MHz 1 MHz 2.4576 MHz 1 MHz Gain = 1 Gain = 2 Gain = 32 Gain = 128 50 Hz 20 Hz 13.1 Hz 5.24 Hz 16 16 14 12 60 Hz 25 Hz 15.72 Hz 6.55 Hz 16 16 14 12 250 Hz 100 Hz 65.5 Hz 26.2 Hz 13 13 12 11 500 Hz 200 Hz 131 Hz 52.4 Hz 10 11 10 10 Rev. D | Page 17 of 40 AD7715 CALIBRATION SEQUENCES The AD7715 contains a number of calibration options as these bits return to 0, 0 following a calibration command, it outlined in Table 13. Table 23 summarizes the calibration types, indicates that the calibration sequence is complete. This method the operations involved and the duration of the operations. does not give any indication of there being a valid new result in There are two methods of determining the end of calibration. the data register. However, it gives an earlier indication than DRDY DRDY The first is to monitor when returns low at the end of that calibration is complete. The duration to when the DRDY mode bits (MD1 and MD0) return to 0, 0 represents the the sequence. not only indicates when the sequence is duration of the calibration carried out. The sequence to when complete but also that the part has a valid new sample in its DRDY data register. This valid new sample is the result of a normal goes low also includes a normal conversion and a conversion which follows the calibration sequence. The second pipeline delay, tP, to correctly scale the results of this first method of determining when calibration is complete is to conversion. tP will never exceed 2000 × tCLK IN. The time for both monitor the MD1 and MD0 bits of the setup register. When methods is given in Table 23. Table 23. Calibration Sequences Calibration Type MD1, MD0 Calibration Sequence Duration to Mode Bits Duration to DRDY Self Calibration 0, 1 Internal ZS Cal @ Selected Gain + 6 × 1/Output Rate 9 ×1/Output Rate + tP Internal FS Cal @ Selected Gain ZS System Calibration 1, 0 ZS Cal on AIN @ Selected Gain 3 × 1/Output Rate 4 × 1/Output Rate + tP FS System Calibration 1, 1 FS Cal on AIN @ Selected Gain 3 × 1/Output Rate 4 × 1/Output Rate + t P Rev. D | Page 18 of 40 AD7715 CIRCUIT DESCRIPTION The AD7715 is a Σ-Δ ADC with on-chip digital filtering, The basic connection diagram for the AD7715-5 is shown in intended for the measurement of wide dynamic range, low Figure 4. This shows both the AVDD and DVDD pins of the AD7715 frequency signals such as those in industrial control or process being driven from the analog 5 V supply. Some applications control applications. It contains a Σ-Δ (or charge-balancing) have AVDD and DVDD driven from separate supplies. An AD780, ADC, a calibration microcontroller with on-chip static RAM, a precision 2.5 V reference, provides the reference source for the clock oscillator, a digital filter, and a bidirectional serial commu- part. On the digital side, the part is configured for three-wire nications port. The part consumes only 450 μA of power supply CS operation with tied to DGND. A quartz crystal or ceramic current, making it ideal for battery-powered or loop-powered resonator provides the master clock source for the part. In most instruments. The part comes in two versions, the AD7715-5 cases, it is necessary to connect capacitors on the crystal or which is specified for operation from a nominal 5 V analog supply resonator to ensure that it does not oscillate at overtones of its (AVDD) and the AD7715-3 which is specified for operation from fundamental operating frequency. The values of capacitors vary a nominal 3.3 V analog supply. Both versions can be operated depending on the manufacturer’s specifications. with a digital supply (DV ) voltage of 3.3 V or 5 V. DD ANALOG 5V SUPPLY 10µF 0.1µF 0.1µF The part contains a programmable-gain fully differential analog AV DV DD DD input channel. The selectable gains on this input are 1, 2, 32, AD7715 and 128 allowing the part to accept unipolar signals of between DATA DRDY READY 0 mV to 20 mV and 0 V to 2.5 V or bipolar signals in the range AIN(+) DIFFERENTIAL CS ANALOG INPUT from ±20 mV to ±2.5 V when the reference input voltage equals AIN(–) RECEIVE DOUT 2.5 V. With a reference voltage of 1.25 V, the input ranges are (READ) ANALOG AGND SERIAL from 0 mV to 10 mV to 0 V to +1.25 V in unipolar mode and DIN GROUND DATA ANALOG from ±10 mV to ±1.25 V in bipolar mode. Note that the bipolar SERIAL 5V SUPPLY SCLK ANALOG CLOCK DGND ranges are with respect to AIN(−) and not with respect to GROUND 5V V RESET IN AGND. V REF IN(+) OUT The input signal to the analog input is continuously sampled at 10µF 0.1µF AD780 MCLK IN CRYSTAL OR GND a rate determined by the frequency of the master clock, MCLK REF IN(–) CERAMIC RESONATOR IN, and the selected gain. A charge-balancing ADC (Σ-Δ mod- MCLK OUT ulator) converts the sampled signal into a digital pulse train whose Figure 4. AD7715-5 Basic Connection Diagram duty cycle contains the digital information. The programmable ANALOG INPUT gain function on the analog input is also incorporated in this Σ-Δ modulator with the input sampling frequency being modified Analog Input Ranges 3 to give the higher gains. A sinc digital low-pass filter processes The AD7715 contains a differential analog input pair AIN(+) the output of the Σ-Δ modulator and updates the output register and AIN(−). This input pair provides a programmable-gain, at a rate determined by the first notch frequency of this filter. differential input channel which can handle either unipolar or The output data can be read from the serial port randomly or bipolar input signals. It should be noted that the bipolar input periodically at any rate up to the output register update rate. signals are referenced to the respective AIN(−) input of the The first notch of this digital filter (and therefore its –3 dB input pair. frequency) can be programmed via the setup register bits, FS0 In unbuffered mode, the common-mode range of the input is and FS1. With a master clock frequency of 2.4576 MHz, the from AGND to AV provided that the absolute value of the DD programmable range for this first notch frequency is from 50 Hz analog input voltage lies between AGND − 30 mV and AV + DD to 500 Hz giving a programmable range for the −3 dB frequency 30 mV. This means that in unbuffered mode the part can handle of 13.1 Hz to 131 Hz. With a master clock frequency of 1 MHz, both unipolar and bipolar input ranges for all gains. In buffered the programmable range for this first notch frequency is from mode, the analog inputs can handle much larger source imped- 20 Hz to 200 Hz giving a programmable range for the −3 dB ances but the absolute input voltage range is restricted to between frequency of 5.24 Hz to 52.4 Hz. AGND + 50 mV to AVDD − 1.5 V, which also places restrictions on the common-mode range. This means that in buffered mode there are some restrictions on the allowable gains for bipolar input ranges. Care must be taken in setting up the common- mode voltage and input voltage range so that the above limits are not exceeded, otherwise there is a degradation in linearity performance. Rev. D | Page 19 of 40 08519-004 AD7715 In unbuffered mode, the analog inputs look directly into the Input Sample Rate input sampling capacitor, C . The dc input leakage current in SAMP The modulator sample frequency for the AD7715 remains at this unbuffered mode is 1 nA maximum. As a result, the analog fCLK IN/128 (19.2 kHz @ fCLK IN = 2.4576 MHz) regardless of the inputs see a dynamic load that is switched at the input sample selected gain. However, gains greater than 1 are achieved by a rate (see Figure 5). This sample rate depends on master clock combination of multiple input samples per modulator cycle and frequency and selected gain. CSAMP is charged to AIN(+) and a scaling of the ratio of reference capacitor to input capacitor. As discharged to AIN(−) every input sample cycle. The effective a result of the multiple sampling, the input sample rate of the device on-resistance of the switch, RSW, is typically 7 kΩ . varies with the selected gain (see Table 25). In buffered mode, the input is buffered before the input sampling capacitor. In unbuffered AIN(+) mode, where the analog input looks directly into the sampling R (7kΩ TYP) HIGH SW IMPEDANCE capacitor, the effective input impedance is 1/CSAMP × fS where >1GΩ C SAMP AIN(–) (10pF) CSAMP is the input sampling capacitance and fS is the input V BIAS sample rate. SWITCHING FREQUENCY DEPENDS ON f AND CLKIN SELECTED GAIN Table 25. Input Sampling Frequency vs. Gain Gain Input Sampling Frequency (f ) S Figure 5. Unbuffered Analog Input Structure 1 fCLK IN/64 (38.4 kHz @ fCLK IN = 2.4576 MHz) 2 2 × f /64 (76.8 kHz @ f = 2.4576 MHz) CLK IN CLK IN CSAMP must be charged through RSW and through any external 32 8 × f /64 (307.2 kHz @ f = 2.4576 MHz) CLK IN CLK IN source impedances every input sample cycle. Therefore, in 128 8 × f /64 (307.2 kHz @ f = 2.4576 MHz) CLK IN CLK IN unbuffered mode, source impedances mean a longer charge time for C , and this may result in gain errors on the part. SAMP Bipolar/Unipolar Inputs Table 24 shows the allowable external resistance/capacitance The analog input on the AD7715 can accept either unipolar or values, for unbuffered mode, such that no gain error to the bipolar input voltage ranges. Bipolar input ranges do not imply 16-bit level is introduced on the part. Note that these capacitances that the part can handle negative voltages on its analog input are total capacitances on the analog input, external capacitance since the analog input cannot go more negative than −30 mV to plus 10 pF capacitance from the pins and lead frame of the device. ensure correct operation of the part. The input channel is fully Table 24. External R, C Combination for No 16-Bit Gain differential. As a result, the voltage to which the unipolar and Error (Unbuffered Mode Only) bipolar signals on the AIN(+) input are referenced is the voltage External Capacitance (pF) on the respective AIN(−) input. For example, if AIN(−) is Gain 10 50 100 500 1000 5000 2.5 V and the AD7715 is configured for unipolar operation with 1 152 kΩ 53.9 kΩ 31.4 kΩ 8.4 kΩ 4.76 kΩ 1.36 kΩ a gain of 2 and a V REF of 2.5 V, the input voltage range on the 2 75.1 kΩ 26.6 kΩ 15.4 kΩ 4.14 kΩ 2.36 kΩ 670 Ω AIN(+) input is 2.5 V to 3.75 V. If AIN(−) is 2.5 V and the 32 16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω 150 Ω AD7715 is configured for bipolar mode with a gain of 2 and a 128 16.7 kΩ 5.95 kΩ 3.46 kΩ 924 Ω 526 Ω 150 Ω VREF of 2.5 V, the analog input range on the AIN(+) input is 1.25 V to 3.75 V (that is, 2.5 V ± 1.25 V). If AIN(−) is at AGND, In buffered mode, the analog inputs look into the high impedance the part cannot be configured for bipolar ranges in excess of inputs stage of the on-chip buffer amplifier. C is charged via SAMP ±30 mV. this buffer amplifier such that source impedances do not affect the charging of C . This buffer amplifier has an offset leakage SAMP Bipolar or unipolar options are chosen by programming the current of 1 nA. In this buffered mode, large source impedances B/U bit of the setup register. This programs the channel for result in a small dc offset voltage developed across the source either unipolar or bipolar operation. Programming the channel impedance but not in a gain error. for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. Rev. D | Page 20 of 40 08519-005 AD7715 REFERENCE INPUT DIGITAL FILTERING The reference inputs of the AD7715, REF IN(+) and REF IN(−), The AD7715 contains an on-chip low-pass digital filter that provide a differential reference input capability. The common- processes the output of the part’s Σ-Δ modulator. Therefore, the mode range for these differential inputs is from AGND to AVDD. part not only provides the analog-to-digital conversion function The nominal reference voltage, V (REF IN(+) − REF IN(−)), but it also provides a level of filtering. Users should be aware REF for specified operation is 2.5 V for the AD7715-5 and 1.25 V for that there are a number of system differences when the filtering the AD7715-3. The part is functional with V voltages down function is provided in the digital domain rather than the REF analog domain. to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF IN(+) must always be First, since digital filtering occurs after the A-to-D conversion greater than REF IN(−) for correct operation of the AD7715. process, it can remove noise injected during the conversion Both reference inputs provide a high impedance, dynamic load process. Analog filtering cannot do this. Also, the digital filter similar to the analog inputs in unbuffered mode. The maximum can be made programmable far more readily than an analog dc input leakage current is ±1 nA over temperature and source filter. Depending on the digital filter design, this gives the user resistance may result in gain errors on the part. In this case, the capability of programming cutoff frequency and output the sampling switch resistance is 5 kΩ typical and the reference update rate. capacitor (CREF) varies with gain. The sample rate on the refer- On the other hand, analog filtering can remove noise super- ence inputs is fCLK IN/64 and does not vary with gain. For gains imposed on the analog signal before it reaches the ADC. Digital of 1 and 2, CREF is 8 pF; for a gain of 32, it is 4.25 pF, and for a filtering cannot do this and noise peaks riding on signals near gain of 128, it is 3.3125 pF. full scale have the potential to saturate the analog modulator The output noise performance outlined in Table 15 through and digital filter, even though the average value of the signal is Table 22 is for an analog input of 0 V which effectively removes within limits. To alleviate this problem, the AD7715 has overrange the effect of noise on the reference. To obtain the same noise headroom built into the Σ-Δ modulator and digital filter which allows overrange excursions of 5% above the analog input range. If performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7715. If noise signals are larger than this, consideration should be given the reference noise in the bandwidth of interest is excessive, it to analog input filtering, or to reducing the input channel voltage will degrade the performance of the AD7715. In applications so that its full scale is half that of the analog input channel full where the excitation voltage for the bridge transducer on the scale. This provides an overrange capability greater than 100% analog input also derives the reference voltage for the part, at the expense of reducing the dynamic range by 1 bit (50%). the effect of the noise in the excitation voltage will be removed In addition, the digital filter does not provide any rejection at as the application is ratiometric. Recommended reference integer multiples of the digital filter’s sample frequency. However, voltage sources for the AD7715-5 include the AD780, REF43 the input sampling on the part provides attenuation at multiples and REF192, while the recommended reference sources for of the digital filter’s sampling frequency so that the unattenuated the AD7715-3 include the AD589 and AD1580. It is generally bands actually occur around multiples of the sampling frequency recommended to decouple the output of these references to fS (as defined in Table 25). Thus the unattenuated bands occur further reduce the noise level. at n × f (where n = 1, 2, 3 … ). At these frequencies, there are S frequency bands, ±f wide (f is the cutoff frequency of the 3 dB 3 dB digital filter) at either side where noise passes unattenuated to the output. Rev. D | Page 21 of 40 AD7715 Filter Characteristics Because the AD7715 contains this on-chip, low-pass filtering, 3 there is a settling time associated with step function inputs and The AD7715’s digital filter is a low-pass filter with a (sinx/x) 3 data on the output is invalid after a step change until the settling response (also called sinc ). The transfer function for this filter time has elapsed. The settling time depends upon the output is described in the z-domain by rate chosen for the filter. The settling time of the filter to a full- 3 −N ⎡ ⎤ 1−z scale step input can be up 4 times the output data period. For a 1 H(z)= × ⎢ ⎥ −1 synchronized step input (using the FSYNC function), the N 1−z ⎢ ⎥ ⎣ ⎦ settling time is 3 times the output data period. and in the frequency domain by Post-Filtering 3 ⎛ ⎞ f The on-chip modulator provides samples at a 19.2 kHz output ⎜ ⎟ Sin N×π× ⎜ ⎟ rate with fCLK IN at 2.4576 MHz. The on-chip digital filter decimates f 1 ⎝ S⎠ H(f )= × these samples to provide data at an output rate that corresponds N ⎛ ⎞ f ⎜ ⎟ to the programmed output rate of the filter. Because the output Sinπ× ⎜ ⎟ f ⎝ S⎠ data rate is higher than the Nyquist criterion, the output rate for a given bandwidth satisfys most application requirements. where N is the ratio of the modulator rate to the output rate and However, there may be some applications that require a higher f is the modulator rate. MOD data rate for a given bandwidth and noise performance. Figure 6 shows the filter frequency response for a cutoff frequency Applications that need this higher data rate do require some of 15.72 Hz which corresponds to a first filter notch frequency post-filtering following the digital filter of the AD7715. of 60 Hz. The plot is shown from dc to 390 Hz. This response is For example, if the required bandwidth is 7.86 Hz but the repeated at either side of the digital filter’s sample frequency required update rate is 100 Hz, the data can be taken from the and at either side of multiples of the filter’s sample frequency. AD7715 at the 100 Hz rate giving a −3 dB bandwidth of 26.2 Hz. 0 Post-filtering can be applied to this to reduce the bandwidth –20 and output noise, to the 7.86 Hz bandwidth level, while –40 maintaining an output rate of 100 Hz. –60 –80 Post-filtering can also be used to reduce the output noise from –100 the device for bandwidths below 13.1 Hz. At a gain of 128 and –120 a bandwidth of 13.1 Hz, the output rms noise is 520 nV. This is –140 essentially device noise or white noise and because the input is –160 chopped, the noise has a primarily flat frequency response. By –180 reducing the bandwidth below 13.1 Hz, the noise in the resultant –200 pass-band can be reduced. A reduction in bandwidth by a factor –220 of 2 results in a reduction of approximately 1.25 in the output –240 rms noise. This additional filtering results in a longer settling time. 0 60 120 180 240 300 360 FREQUENCY (Hz) Figure 6. Frequency Response of AD7715 Filter The response of the filter is similar to that of an averaging filter but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Thus, for the plot of Figure 6 where the output rate is 60 Hz, the first notch of the filter is at 60 Hz. The 3 notches of this (sinx/x) filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. The cutoff frequency of the digital filter is determined by the value loaded to the FS0 to FS1 bits in the setup register. program- ming a different cutoff frequency via FS0 and FS1 does not alter the profile of the filter response; it changes the frequency of the notches. The output update of the part and the frequency of the first notch correspond. Rev. D | Page 22 of 40 GAIN (dB) 08519-006 AD7715 The AD7715 offers self-calibration and system-calibration ANALOG FILTERING facilities. For full calibration to occur on the selected channel, The digital filter does not provide any rejection at integer mul- the on-chip microcontroller must record the modulator output tiples of the modulator sample frequency, as outlined earlier. for two different input conditions. These are zero-scale and However, due to the high oversampling ratio of AD7715, these full-scale points. These points are derived by performing a bands occupy only a small fraction of the spectrum and most conversion on the different input voltages provided to the input broadband noise is filtered. This means that the analog filtering of the modulator during calibration. As a result, the accuracy requirements in front of the AD7715 are considerably reduced of the calibration can only be as good as the noise level that it vs. a conventional converter with no on-chip filtering. In addition, provides in normal mode. The result of the zero-scale calibration because the part’s common-mode rejection performance of 95 dB conversion is stored in the zero-scale calibration register while extends out to several kilohertz, common-mode noise in this the result of the full-scale calibration conversion is stored in the frequency range is substantially reduced. full-scale calibration register. With these readings, the on-chip Depending on the application, however, it may be necessary to microcontroller can calculate the offset and the gain slope for provide attenuation in front of the AD7715 to eliminate the input to output transfer function of the converter. Internally, the unwanted frequencies from these bands which the digital filter part works with a resolution of 33 bits to determine its conversion will pass. It may also be necessary in some applications to result of 16 bits. provide analog filtering in front of the AD7715 to ensure that Self-Calibration differential noise signals outside the band of interest do not A self-calibration is initiated on the AD7715 by writing the saturate the analog modulator. appropriate values (0, 1) to the MD1 and MD0 bits of the setup If passive components are placed in front of the AD7715, in register. In the self-calibration mode with a unipolar input unbuffered mode, take care to ensure that the source impedance range, the zero-scale point used in determining the calibration is low enough so as not to introduce gain errors in the system. coefficients is with the inputs of the differential pair internally This significantly limits the amount of passive antialiasing shorted on the part (that is, AIN(+) = AIN(−) = internal bias filtering which can be provided in front of the AD7715 when it voltage). The PGA is set for the selected gain (as per G1 and is used in unbuffered mode. However, when the part is used G0 bits in the communications register) for this zero-scale in buffered mode, large source impedances simply result in a calibration conversion. The full-scale calibration conversion small dc offset error (a 10 kΩ source resistance causes an offset is performed at the selected gain on an internally generated error of less than 10 μV). Therefore, if the system requires any voltage of VREF/selected gain. significant source impedances to provide passive analog The duration time for the calibration is 6 × 1/output rate. This filtering in front of the AD7715, it is recommended that the is made up of 3 × 1/output rate for the zero-scale calibration part be operated in buffered mode. and 3 × 1/output rate for the full-scale calibration. At this time, CALIBRATION the MD1 and MD0 bits in the setup register return to 0, 0. The AD7715 provides a number of calibration options that This gives the earliest indication that the calibration sequence can be programmed via the MD1 and MD0 bits of the setup is complete. The DRDY line goes high when calibration is register. The different calibration options are outlined in the initiated and does not return low until there is a valid new word setup register and calibration sequences sections. A calibration in the data register. The duration time from the calibration cycle may be initiated at any time by writing to the MD1 and DRDY command being issued to going low is 9 × 1/output rate. MD0 bits of the setup register. Calibration on the AD7715 This is made up of 3 × 1/output rate for the zero-scale calibration, removes offset and gain errors from the device. A calibration 3 × 1/output rate for the full-scale calibration, 3 × 1/output rate routine should be initiated on the device whenever there is a for a conversion on the analog input and some overhead to set change in the ambient operating temperature or supply voltage. up the coefficients correctly. If DRDY is low before (or goes low It should also be initiated if there is a change in the selected during) the calibration command write to the setup register, gain, filter notch or bipolar/unipolar input range. it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. DRDY Therefore, should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above, but because the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. Rev. D | Page 23 of 40 AD7715 System Calibration In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function. In the System calibration allows the AD7715 to compensate for system bipolar mode, it is performed between midscale (zero differential gain and offset errors as well as its own internal errors. System voltage) and positive full scale. calibration performs the same slope factor calculations as self calibration but uses voltage values presented by the system to The fact that the system calibration is a two-step calibration the AIN inputs for the zero- and full-scale points. full system offers another feature. After the sequence of a full system cali- calibration requires a two step process, a zero-scale system bration has been completed, additional offset or gain calibrations calibration followed by a full-scale system calibration. can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the For a full system calibration, the zero-scale point must be parameters, either system offset or system gain, does not presented to the converter first. It must be applied to the affect the other parameter. converter before the calibration step is initiated and remain stable until the step is complete. Once the system zero scale System calibration can also be used to remove any errors from voltage has been set up, a zero-scale system calibration is then source impedances on the analog input when the part is used in initiated by writing the appropriate values (1, 0) to the MD1 unbuffered mode. A simple R, C antialiasing filter on the front and MD0 bits of the setup register. The zero-scale system end may introduce a gain error on the analog input voltage but calibration is performed at the selected gain. The duration of the system calibration can be used to remove this error. the calibration is 3 × 1/output rate. At this time, the MD1 and Span and Offset Limits MD0 bits in the setup register return to 0, 0. This gives the Whenever a system calibration mode is used, there are limits earliest indication that the calibration sequence is complete. The on the amount of offset and span which can be accommodated. DRDY line goes high when calibration is initiated and does not The overriding requirement in determining the amount of return low until there is a valid new word in the data register. offset and gain that can be accommodated by the part is the The duration time from the calibration command being issued requirement that the positive full-scale calibration limit is DRDY to going low is 4 × 1/output rate as the part performs a ≤ 1.05 × V /GAIN. This allows the input range to go 5% REF DRDY normal conversion on the AIN voltage before goes low. above the nominal range. The in-built headroom in the If DRDY is low before (or goes low during) the calibration analog modulator of the AD7715 ensures that the part still command write to the setup register, it may take up to one operates correctly with a positive full-scale voltage which is modulator cycle (MCLK IN/128) before DRDY goes high to 5% beyond the nominal. indicate that calibration is in progress. Therefore, DRDY should The range of input span in both the unipolar and bipolar modes be ignored for up to one modulator cycle after the last bit is has a minimum value of 0.8 × V /GAIN and a maximum value REF written to the setup register in the calibration command. of 2.1 × V /GAIN. However, the span (which is the difference REF After the zero-scale point is calibrated, the full-scale point is between the bottom of the AD7715’s input range and the top applied to AIN and the second step of the calibration process is of its input range) must take into account the limitation on the initiated by again writing the appropriate values (1, 1) to MD1 positive full-scale voltage. The amount of offset that can be and MD0. Again, the full-scale voltage must be set up before the accommodated depends on whether the unipolar or bipolar calibration is initiated and it must remain stable throughout the mode is being used. Once again, the offset must take into account calibration step. The full-scale system calibration is performed the limitation on the positive full-scale voltage. In unipolar at the selected gain. The duration of the calibration is 3 × 1/output mode, there is considerable flexibility in handling negative rate. At this time, the MD1 and MD0 bits in the setup register (with respect to AIN(−)) offsets. In both unipolar and bipolar return to 0, 0. This gives the earliest indication that the calibration modes, the range of positive offsets which can be handled by the sequence is complete. The DRDY line goes high when calibration is part depends on the selected span. Therefore, in determining the initiated and does not return low until there is a valid new word limits for system zero-scale and full-scale calibrations, the user in the data register. The duration time from the calibration has to ensure that the offset range plus the span range does exceed command being issued to DRDY going low is 4 × 1/output rate 1.05 × VREF/GAIN. This is best illustrated by looking at the as the part performs a normal conversion on the AIN voltage following examples. DRDY DRDY before goes low. If is low before (or goes low during) the calibration command, write to the setup register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. Rev. D | Page 24 of 40 AD7715 If the part is used in unipolar mode with a required span of Power-Up and Calibration 0.8 × V /GAIN, then the offset range which the system REF On power-up, the AD7715 performs an internal reset that sets calibration can handle is from −1.05 × V /GAIN to +0.25 × REF the contents of the internal registers to a known state. There are VREF/GAIN. If the part is used in unipolar mode with a required default values loaded to all registers after a power-on or reset. span of VREF/GAIN, then the offset range which the system The default values contain nominal calibration coefficients for calibration can handle is from −1.05 × VREF/GAIN to +0.05 × the calibration registers. However, to ensure correct calibration VREF/GAIN. Similarly, if the part is used in unipolar mode and for the device a calibration routine should be performed after required to remove an offset of 0.2 × V /GAIN, then the span REF power-up. range which the system calibration can handle is 0.85 × The power dissipation and temperature drift of the AD7715 V /GAIN. REF are low, and no warm-up time is required before the initial If the part is used in bipolar mode with a required span of ±0.4 × calibration is performed. However, if an external reference is VREF/GAIN, then the offset range which the system calibration being used, this reference must have stabilized before calibration is can handle is from −0.65 × VREF/GAIN to +0.65 × VREF/GAIN. If initiated. Similarly, if the clock source for the part is generated the part is used in bipolar mode with a required span of ±VREF/ from a crystal or resonator across the MCLK pins, the start-up GAIN, then the offset range which the system calibration can time for the oscillator circuit should elapse before a calibration handle is from −0.05 × V /GAIN to +0.05 × V /GAIN. REF REF is initiated on the part (see the Clocking and Oscillator Circuit Similarly, if the part is used in bipolar mode and required to section). remove an offset of ±0.2 × V /GAIN, then the span range REF which the system calibration can handle is ±0.85 × V /GAIN. REF Rev. D | Page 25 of 40 AD7715 USING THE AD7715 When operating with a clock frequency of 1 MHz, the ESR CLOCKING AND OSCILLATOR CIRCUIT value for different crystal types varies significantly. As a result, The AD7715 requires a master clock input, which may be an the DVDD current drain varies across crystal types. When using external CMOS compatible clock signal applied to the MCLK a crystal with an ESR of 700 Ω or when using a ceramic resonator, IN pin with the MCLK OUT pin left unconnected. Alternatively, the increase in the typical DV current over an externally- DD a crystal or ceramic resonator of the correct frequency can be applied clock is 50 μA with DV = 3 V and 175 μA with DV DD DD connected between MCLK IN and MCLK OUT in which case = 5 V. When using a crystal with an ESR of 3 kΩ, the increase in the clock circuit functions as an oscillator, providing the clock the typical DV current over an externally applied clock is 100 μA DD source for the part. The input sampling frequency, the modula- with DVDD = 3 V and 400 μA with DVDD = 5 V. tor sampling frequency, the −3 dB frequency, output update rate and calibration time are all directly related to the master The on-chip oscillator circuit also has a start-up time associated clock frequency, f . Reducing the master clock frequency by with it before it is oscillating at its correct frequency and correct CLK IN a factor of 2 will halve the above frequencies and update rate, voltage levels. The typical start-up time for the circuit is 10 ms with a DV of 5 V and 15 ms with a DV of 3 V. At 3 V supplies, and double the calibration time. The current drawn from the DD DD depending on the loading capacitances on the MCLK pins, a DVDD power supply is also directly related to fCLK IN. Reducing 1 MΩ feedback resistor may be required across the crystal or fCLK IN by a factor of 2 will halve the DVDD current but does not resonator to keep the start up times around the 15 ms duration. affect the current drawn from the AVDD power supply. Using the part with a crystal or ceramic resonator between the The master clock of AD7715 appears on the MCLK OUT pin MCLK IN and MCLK OUT pins generally causes more current of the device. The maximum recommended load on this pin is to be drawn from DV than when the part is clocked from a one CMOS load. When using a crystal or ceramic resonator to DD generate the clock of the AD7715, it may be desirable to then driven clock signal at the MCLK IN pin. This is because the on- use this clock as the clock source for the system. In this case, it chip oscillator circuit is active in the case of the crystal or ceramic is recommended that the MCLK OUT signal is buffered with a resonator. Therefore, the lowest possible current on the AD7715 CMOS buffer before being applied to the rest of the circuit. is achieved with an externally applied clock at the MCLK IN pin with MCLK OUT unconnected and unloaded. SYSTEM SYNCHRONIZATION The amount of additional current taken by the oscillator depends The FSYNC bit of the setup register allows the user to reset the on a number of factors—first, the larger the value of capacitor modulator and digital filter without affecting any of the setup placed on the MCLK IN and MCLK OUT pins, then the larger conditions on the part. This allows the user to start gathering the DVDD current consumption on the AD7715. Take care not samples of the analog input from a known point in time, that is, to exceed the capacitor values recommended by the crystal and when the FSYNC is changed from 1 to 0. ceramic resonator manufacturers to avoid consuming unnecessary With a 1 in the FSYNC bit of the setup register, the digital filter DVDD current. Typical values recommended by crystal or and analog modulator are held in a known reset state and the ceramic resonator manufacturers are in the range of 30 pF to part is not processing any input samples. When a 0 is then 50 pF, and if the capacitor values on MCLK IN and MCLK OUT written to the FSYNC bit, the modulator and filter are taken are kept in this range, they will not result in any excessive DV DD out of this reset state and on the next master clock edge the current. Another factor that influences the DV current is the DD part starts to gather samples again. effective series resistance (ESR) of the crystal which appears between the MCLK IN and MCLK OUT pins of the AD7715. The FSYNC input can also be used as a software start convert As a general rule, the lower the ESR value then the lower the command allowing the AD7715 to be operated in a conven- current taken by the oscillator circuit. tional converter fashion. In this mode, writing to the FSYNC bit DRDY starts a conversion and the falling edge of indicates when When operating with a clock frequency of 2.4576 MHz, there the conversion is complete. The disadvantage of this scheme is is 50 μA difference in the DV current between an externally DD that the settling time of the filter has to be taken into account applied clock and a crystal resonator when operating with a for every data register update. This means that the rate at which DVDD of 3 V. With DVDD = 5 V and fCLK IN = 2.4576 MHz, the the data register is updated is three times slower in this mode. typical DVDD current increases by 200 μA for a crystal/resonat or supplied clock vs. an externally applied clock. The ESR values for crystals and resonators at this frequency tend to be low and as a result there tends to be little difference between different crystal and resonator types. Rev. D | Page 26 of 40 AD7715 Because the FSYNC bit resets the digital filter, the full settling The STBY bit does not affect the digital interface, and it does time of 3 × 1/output rate must elapse before there is a new word DRDY DRDY not affect the status of the line. If is high when the DRDY loaded to the output register on the part. If the signal is STBY bit is brought low, it will remain high until there is a valid low when FSYNC goes to a 0, the DRDY signal will not be reset new word in the data register. If DRDY is low when the STBY high by the FSYNC command. This is because the AD7715 bit is brought low, it will remain low until the data register is recognizes that there is a word in the data register that has not updated at which time the DRDY line returns high for 500 × been read. The DRDY line stays low until an update of the data t before returning low again. If DRDY is low when the part CLK IN register takes place at which time it goes high for 500 × t CLK IN enters its standby mode (indicating a valid unread word in the before returning low again. A read from the data register resets data register), the data register can be read while the part is in DRDY the signal high, and it does not return low until the DRDY standby. At the end of this read operation, the line will settling time of the filter has elapsed (from the FSYNC command) be reset high as normal. and there is a valid new word in the data register. If the DRDY Placing the part in standby mode reduces the total current to line is high when the FSYNC command is issued, the DRDY 5 μA typical when the part is operated from an external master line will not return low until the settling time of the filter has clock provided this master clock is stopped. If the external clock elapsed. continues to run in standby mode, the standby current increases to 150 μA typical with 5 V supplies and 75 μA typical with 3.3 V RESET INPUT supplies. If a crystal or ceramic resonator is used as the clock The RESET input on the AD7715 resets all the logic, the digital source, then the total current in standby mode is 400 μA typical filter, and the analog modulator while all on-chip registers are with 5 V supplies and 90 μA with 3.3 V supplies. This is because DRDY reset to their default state. is driven high and the AD7715 the on-chip oscillator circuit continues to run when the part is ignores all communications to any of its registers while the in its standby mode. This is important in applications where the RESET RESET input is low. When the input returns high, the system clock is provided by the clock of the AD7715, so that the DRDY AD7715 starts to process data, and returns low in 3 × AD7715 produces an uninterrupted master clock even when it 1/output rate indicating a valid new word in the data register. is in its standby mode. However, the AD7715 operates with its default setup conditions ACCURACY after a reset and it is generally necessary to set up all registers Σ-Δ ADCs, like VFCs and other integrating ADCs, do not and carry out a calibration after a reset command. contain any source of nonmonotonicity and inherently offer The on-chip oscillator circuit of the AD7715 continues to func- no missing codes performance. The AD7715 achieves excellent RESET tion even when the input is low. The master clock signal linearity by the use of high quality, on-chip capacitors, which continues to be available on the MCLK OUT pin. Therefore, in have a very low capacitance/voltage coefficient. The device also applications where the system clock is provided by the clock of the achieves low input drift through the use of chopper-stabilized AD7715, the AD7715 produces an uninterrupted master clock techniques in its input stage. To ensure excellent performance during RESET commands. over time and temperature, the AD7715 uses digital calibration STANDBY MODE techniques which minimize offset and gain error. The STBY bit in the communications register of the AD7715 DRIFT CONSIDERATIONS allows the user to place the part in a power-down mode when it The AD7715 uses chopper stabilization techniques to minimize is not required to provide conversion results. The AD7715 retains input offset drift. Charge injection in the analog switches and dc the contents of all its on-chip registers (including the data register) leakage currents at the sampling node are the primary sources while in standby mode. When released from standby mode, the of offset voltage drift in the converter. The dc input leakage part starts to process data and a new word is available in the current is essentially independent of the selected gain. Gain data register in 3 × 1/output rate from when a 0 is written to drift within the converter depends primarily upon the temperature the STBY bit. tracking of the internal capacitors. It is not affected by leakage currents. Measurement errors due to offset drift or gain drift can be eliminated at any time by recalibrating the converter. Using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential linearity errors are not significantly affected by temperature changes. Rev. D | Page 27 of 40 AD7715 saturate the analog modulator. As a result, the AD7715 is more POWER SUPPLIES immune to noise interference than a conventional high There is no specific power sequence required for the AD7715; resolution converter. However, because the resolution of the either the AVDD or the DVDD supply can come up first. While AD7715 is so high and the noise levels from the AD7715 so low, the latch-up performance of the AD7715 is good, it is important care must be taken with regard to grounding and layout. that power is applied to the AD7715 before signals at REF IN, AIN, or the logic input pins to avoid excessive currents. If this The printed circuit board that houses the AD7715 should be is not possible, then the current that flows in any of these pins designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the should be limited. If separate supplies are used for the AD7715 use of ground planes which can be separated easily. A minimum and the system digital circuitry, then the AD7715 should be etch technique is generally best for ground planes as it gives the powered up first. If it is not possible to guarantee this, then best shielding. Digital and analog ground planes should only be current limiting resistors should be placed in series with the logic inputs to again limit the current. joined in one place. If the AD7715 is the only device requiring an AGND to DGND connection, then the ground planes During normal operation the AD7715 analog supply (AV ) DD should be connected at the AGND and DGND pins of the should always be greater than or equal to its digital supply (DV ). DD AD7715. If the AD7715 is in a system where multiple devices Supply Current require AGND to DGND connections, the connection should The current consumption on the AD7715 is specified for supplies still be made at one point only, a star ground point which in the range 3 V to 3.6 V and in the range 4.75 V to 5.25 V. The should be established as close as possible to the AD7715. part operates over a 2.85 V to 5.25 V supply range and the I DD Avoid running digital lines under the device as these couples for the part varies as the supply voltage varies over this range. noise onto the die. The analog ground plane should be allowed Figure 7 shows the variation of the typical I with V voltage DD DD to run under the AD7715 to avoid noise coupling. The power for both a 1 MHz external clock and a 2.4576 MHz external supply lines to the AD7715 should use as large a trace as clock at 25°C. The AD7715 is operated in unbuffered mode. possible to provide low impedance paths and reduce the effects The relationship shows that the IDD is minimized by operating of glitches on the power supply line. Fast switching signals like the part with lower VDD voltages. IDD on the AD7715 is also clocks should be shielded with digital ground to avoid radiating minimized by using an external master clock or by optimizing noise to other sections of the board and clock signals should external components when using the on-chip oscillator circuit. never be run near the analog inputs. Avoid crossover of digital 1.0 and analog signals. Traces on opposite sides of the board should 0.9 run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far 0.8 the best but is not always possible with a double-sided board. In 0.7 MCLK IN = 2.4576MHz this technique, the component side of the board is dedicated to 0.6 ground planes while signals are placed on the solder side. 0.5 Good decoupling is important when using high resolution ADCs. MCLK IN = 1MHz 0.4 All analog supplies should be decoupled with 10 μF tantalum in 0.3 parallel with 0.1 μF capacitors to AGND. To achieve the best 0.2 from these decoupling components, they must be placed as close 0.1 as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 μF disc ceramic capacitors 0 2.85 3.15 3.45 3.75 4.05 4.35 4.65 4.95 5.25 to DGND. In systems where a common supply voltage is used to SUPPLY VOLTAGE, AV AND DV (V) DD DD drive both the AV and DV of the AD7715, it is recommended DD DD Figure 7. I vs. Supply Voltage DD that the AVDD supply of the system is used. This supply should Grounding and Layout have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7715 and AGND and the Because the analog inputs and reference input are differential, recommended digital supply decoupling capacitor between most of the voltages in the analog modulator are common- the DVDD pin of the AD7715 and DGND. mode voltages. The excellent common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7715 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided those noise sources do not Rev. D | Page 28 of 40 SUPPLY CURRENT, AV AND DV (mA) DD DD 08519-007 AD7715 Evaluating the AD7715 Performance DIGITAL INTERFACE The recommended layout for the AD7715 is outlined in the The programmable functions of the AD7715 are controlled evaluation board for the AD7715. The evaluation board using a set of on-chip registers as outlined previously. Data is package includes a fully assembled and tested evaluation board, written to these registers via the serial interface of the part and documentation, software for controlling the board over the USB read access to the on-chip registers is also provided by this port of a PC and software for analyzing the performance of the interface. All communications to the part must start with a AD7715 on the PC. The evaluation board model number is write operation to the communications register. After power-on EVAL-AD7715-3EBZ . or RESET, the device expects a write to its communications register. The data written to this register determines whether Noise levels in the signals applied to the AD7715 may also affect the next operation to the part is a read or a write operation and performance of the part. The AD7715 software evaluation also determines to which register this read or write operation package allows the user to evaluate the true performance of the occurs. Therefore, write access to any of the other registers on part, independent of the analog input signal. The scheme the part starts with a write operation to the communications involves using a test mode on the part where the differential register followed by a write to the selected register. A read inputs to the AD7715 are internally shorted together to provide operation from any other register on the part (including the a zero differential voltage for the analog modulator. External to output data register) starts with a write operation to the the device, connect the AIN(−) input to a voltage which is communications register followed by a read operation from the within the allowable common-mode range of the part. This selected register. scheme should be used after a calibration has been performed on the part. CS The serial interface of the AD7715 consists of five signals, , DRDY SCLK, DIN, DOUT, and . The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the data register of the AD7715. DRDY goes low when a new data word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the AD7715 in systems where a number of parts are connected to the serial bus. Rev. D | Page 29 of 40 AD7715 Figure 8 and Figure 9 show timing diagrams for interfacing to RESET The serial interface can be reset by exercising the input CS the AD7715 with used to decode the part. Figure 8 is for a on the part. It can also be reset by writing a series of 1s on the read operation from the AD7715’s output shift register, while DIN input. If a Logic 1 is written to the AD7715 DIN line for Figure 9 shows a write operation to the input shift register. It is at least 32 serial clock cycles, the serial interface is reset. This possible to read the same data twice from the output register ensures that in three-wire systems that if the interface gets lost even though the DRDY line returns high after the first read either via a software error or by some glitch in the system, it can be reset back into a known state. This state returns the interface operation. Take care, however, to ensure that the read operations to where the AD7715 is expecting a write operation to its com- have been completed before the next output update is about to munications register. This operation in itself does not reset the take place. contents of any registers, but because the interface was lost, the The AD7715 serial interface can operate in three-wire mode by information that was written to any of the registers is unknown CS tying the input low. In this case, the SCLK, DIN and DOUT and it is advisable to set up all registers again. lines are used to communicate with the AD7715 and the status Some microprocessor or microcontroller serial interfaces have of DRDY can be obtained by interrogating the MSB of the com- a single serial data line. In this case, it is possible to connect munications register. This scheme is suitable for interfacing to the DOUT and DIN lines of the AD7715 together and connect CS microcontrollers. If is required as a decoding signal, it can them to the single data line of the processor. A 10 kΩ pull-up be generated from a port bit. For microcontroller interfaces, it is resistor should be used on this single data line. In this case, if recommended that the SCLK idles high between data transfers. the interface gets lost, because the read and write operations CS The AD7715 can also be operated with used as a frame share the same line the procedure to reset it back to a known synchronization signal. This scheme is suitable for DSP state is somewhat different than described previously. It requires interfaces. In this case, the first bit (MSB) is effectively clocked a read operation of 24 serial clocks followed by a write operation out by CS because CS would normally occur after the falling where a Logic 1 is written for at least 32 serial clock cycles to edge of SCLK in DSPs. The SCLK can continue to run between ensure that the serial interface is back into a known state. data transfers provided the timing numbers are obeyed. DRDY t t 10 3 CS t t 4 t 8 6 SCLK t t t 5 7 9 DOUT MSB LSB Figure 8. Read Cycle Timing Diagram CS t t 16 11 t 14 SCLK t t 15 12 t 13 LSB DIN MSB Figure 9. Write Cycle Timing Diagram Rev. D | Page 30 of 40 08519-009 08519-008 AD7715 CONFIGURING THE AD7715 The AD7715 contains three on-chip registers which the user the data register has taken place, the second where the DRDY accesses via the serial interface. Communication with any of bit of the communications register is interrogated to see if a these registers is initiated by writing to the communications data register update has taken place. Also included in the register first. Figure 10 outlines a flow chart of the sequence flowing diagram is a series of words which should be written which is used to configure all registers after a power-up or reset. to the registers for a particular set of operating conditions. The flowchart also shows two different read options—the first These conditions are gain of 1, no filter sync, bipolar mode, DRDY where the pin is polled to determine when an update of buffer off, clock of 2.4576 MHz, and an output rate of 60 Hz. START POWER-ON/RESET FOR AD7715 CONFIGURE AND INITIALIZE MICROCONTROLLER/MICROPROCESSOR SERIAL PORT WRITE TO COMMUNICATIONS REGISTER SETTING UP GAIN AND SETTING UP NEXT OPERATION TO BE A WRITE TO THE SETUP REGISTER (10 HEX) WRITE TO SETUP REGISTER SETTING UP REQUIRED VALUES AND INITIATING A SELF CALIBRATION (68 HEX) POLL DRDY PIN WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN AND SETTING UP NEXT OPERATION TO BE A READ FROM THE COMMUNICATIONS REGISTER (08 HEX) NO DRDY LOW? READ FROM COMMUNICATIONS REGISTER YES POLL DRDY BIT OF COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN AND SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) NO DRDY READ FROM DATA REGISTER LOW? YES WRITE TO COMMUNICATIONS REGISTER SETTING UP SAME GAIN AND SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) READ FROM DATA REGISTER Figure 10. Flow Chart for Setting Up and Reading from the AD7715 Rev. D | Page 31 of 40 08519-010 AD7715 MICROCONTROLLER/MICROPROCESSOR INTERFACING The flexible serial interface of the AD7715 allows for easy AD7715 TO 68HC11 INTERFACE interface to most microcontrollers and microprocessors. The Figure 11 shows an interface between the AD7715 and the flow chart of Figure 10 outlines the sequence which should be 68HC11 microcontroller. The diagram shows the minimum followed when interfacing a microcontroller or microprocessor CS (three-wire) interface with on the AD7715 hardwired low. In to the AD7715. Figure 11, Figure 12, and Figure 13 show some this scheme, the DRDY bit of the communications register is typical interface circuits. monitored to determine when the data register is updated. An The serial interface on the AD7715 has the capability of operating alternative scheme, which increases the number of interface from just three wires and is compatible with SPI interface lines to four, is to monitor the DRDY output line from the protocols. The three-wire operation makes the part ideal for DRDY AD7715. The monitoring of the line can be done in isolated systems where minimizing the number of interface DRDY two ways. First, can be connected to one of the 68HC11’s lines minimizes the number of opto-isolators required in the port bits (such as PC0) which is configured as an input. This system. The rise and fall times of the digital inputs to the AD7715 DRDY port bit is then polled to determine the status of . The (especially the SCLK input) should be no longer than 1 μs. second scheme is to use an interrupt driven system, in which Most of the registers on the AD7715 are 8-bit registers. This case the DRDY output is connected to the IRQ input of the facilitates easy interfacing to the 8-bit serial ports of micro- 68HC11. For interfaces that require control of the CS input on controllers. Some of the registers on the part are up to 16 bits, the AD7715, one of the port bits of the 68HC11 (such as PC1), but data transfers to these 16-bit registers can consist of a full CS which is configured as an output, can be used to drive the input. 16-bit transfer or two 8-bit transfers to the serial port of the DV DV DD DD microcontroller. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these SS RESET processors, such as the ADSP-2105, have the facility to program the amount of cycles in a serial transfer. This allows the user to SCK SCLK tailor the number of bits in any transfer to match the register 68HC11 AD7715 length of the required register in the AD7715. MISO DOUT Even though some of the registers on the AD7715 are only MOSI DIN eight bits in length, communicating with two of these registers CS in successive write operations can be handled as a single 16-bit data transfer if required. For example, if the setup register is to Figure 11. AD7715 to 68HC11 Interface be updated, the processor must first write to the communications The 68HC11 is configured in the master mode with its CPOL register (saying that the next operation is a write to the setup bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the register) and then write eight bits to the setup register. This 68HC11 is configured like this, its SCLK line idles high between can all be done in a single 16-bit transfer if required because data transfers. The AD7715 is not capable of full duplex once the eight serial clocks of the write operation to the operation. If the AD7715 is configured for a write operation, no communications register have been completed, the part data appears on the DOUT lines even when the SCLK input is immediately sets itself up for a write operation to the setup active. Similarly, if the AD7715 is configured for a read register. operation, data presented to the part on the DIN line is ignored even when SCLK is active. Coding for an interface between the 68HC11 and the AD7715 is given in the C Code for Interfacing AD7715 to 68HC11 section. In this example, the DRDY output line of the AD7715 is con- nected to the PC0 port bit of the 68HC11 and is polled to determine its status. Rev. D | Page 32 of 40 08519-011 AD7715 AD7715 TO 8XC51 INTERFACE AD7715 TO ADSP-2103/ADSP-2105 INTERFACE An interface circuit between the AD7715 and the 8XC51 Figure 13 shows an interface between the AD7715 and the microcontroller is shown in Figure 12. The diagram shows the ADSP-2103/ADSP-2105 DSP processor. In the interface shown, CS DRDY minimum number of interface connections with on the the bit of the communications register is monitored to AD7715 hardwired low. In the case of the 8XC51 interface, the determine when the data register is updated. The alternative minimum number of interconnects is just two. In this scheme, scheme is to use an interrupt driven system, in which case the DRDY DRDY IRQ2 the bit of the communications register is monitored to output is connected to the input of the ADSP-2103/ determine when the data register is updated. The alternative ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 scheme, which increases the number of interface lines to three, is set up for alternate framing mode. The RFS and TFS pins is to monitor the DRDY output line from the AD7715. The of the ADSP-2103/ADSP-2105 are configured as active low monitoring of the DRDY line can be done in two ways. First, outputs, and the ADSP-2103/ADSP-2105 serial clock line, CS DRDY SCLK, is also configured as an output. The for the AD7715 can be connected to one of the 8XC51’s port bits (such RFS TFS as P1.0) which is configured as an input. This port bit is then is active when either the or outputs from the ADSP- DRDY 2103/ADSP-2105 are active. The serial clock rate on the ADSP- polled to determine the status of . The second scheme 2103/ADSP-2105 should be limited to 3 MHz to ensure correct DRDY is to use an interrupt driven system in which case, the operation with the AD7715. output is connected to the INT1 input of the 8XC51. For DV DD interfaces that require control of the CS input on the AD7715, one of the port bits of the 8XC51 (such as P1.1), which is RESET CS configured as an output, can be used to drive the input. RFS CS TFS The 8XC51 is configured in its Mode 0 serial interface mode. Its AD7715 serial interface contains a single data line. As a result, the ADSP-2103/ ADSP-2105 DOUT and DIN pins of the AD7715 should be connected DR DOUT together with a 10 kΩ pull-up resistor. The serial clock on the DT DIN 8XC51 idles high between data transfers. The 8XC51 outputs SCLK SCLK the LSB first in a write operation while the AD7715 rearranged before being written to the output serial register. Similarly, the AD7715 outputs the MSB first during a read operation while Figure 13. AD7715 to ADSP-2103/ADSP-2105 Interface the 8XC51 expects the LSB first. Therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the AD7715 is available in the accumulator. DV DD RESET DV DD 8XC51 AD7715 10kΩ P3.0 DOUT DIN P3.1 SCLK CS Figure 12. AD7715 to 8XC51 Interface Rev. D | Page 33 of 40 08519-012 08519-013 AD7715 CODE FOR SETTING UP THE AD7715 The C Code for Interfacing AD7715 to 68HC11 section gives The sequence of the events in this program are as follows: a set of read and write routines in C code for interfacing the 1. Write to the communications register, setting the gain to 1 68HC11 microcontroller to the AD7715. The sample program with standby inactive. sets up the various registers on the AD7715 and reads 1000 2. Write to the setup register, setting bipolar mode, buffer samples from the part into the 68HC11. The setup conditions off, no filter synchronization, confirming a clock frequency on the part are exactly the same as those outlined for the of 2.4576 MHz, setting the output rate for 60 Hz and flowchart of Figure 10. In the example code given here, the initiating a self-calibration. DRDY output is polled to determine if a new valid word is DRDY 3. Poll the output. available in the data register. 4. Read the data from the data register. 5. Loop around doing Step 3 and Step 4 until the specified number of samples have been taken. C CODE FOR INTERFACING AD7715 TO 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7715 and the sample program sets the various registers and then reads 1000 samples from the part. */ #include #include #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main() { /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg(0x10); /* set the gain to 1, standby off and set the next operation as write to the setup register */ Writetoreg(0x68); /* set bipolar mode, buffer off, no filter sync, confirm clock as 2.4576MHz, set output rate to 60Hz and do a self calibration */ while(PORTC & 0x10); /* wait for /DRDY to go low */ for(a=0;a