ANALOG DEVICES AD7713

2 LC MOS Loop-Powered Signal Conditioning ADC AD7713 FEATURES FUNCTIONAL BLOCK DIAGRAM Charge Balancing ADC REF REF 24 Bits No Missing Codes AV DV IN(–) IN(+) STANDBY DD DD �0.0015% Nonlinearity AV DD 3-Channel Programmable Gain Front End AD7713 Gains from 1 to 128 1�A 2 Differential Inputs CHARGING BALANCING ADC 1 Single-Ended High Voltage Input Low-Pass Filter with Programmable Filter Cutoffs AUTO-ZEROED AIN1(+) DIGITAL SYNC �-� AIN1(–) FILTER Ability to Read/Write Calibration Coefficients MODULATOR PGA AIN2(+) Bidirectional Microcontroller Serial Interface AIN2(–) A = 1 – 128 MCLK INPUT Single-Supply Operation AIN3 IN CLOCK SCALING GENERATION Low Power (3.5 mW typ) with Power-Down Mode MCLK AV DD 200�A OUT (150 �W typ) SERIAL INTERFACE RTD1 APPLICATIONS CONTROL OUTPUT REGISTER REGISTER 200�A Loop Powered (Smart) Transmitters RTD Transducers RTD2 Process Control Portable Industrial Instruments AGND DGND RFS TFS MODE SDATA SCLK DRDY A0 GENERAL DESCRIPTION CMOS construction ensures low power dissipation, and a hard- The AD7713 is a complete analog front end for low frequency ware programmable power-down mode reduces the standby measurement applications. The device accepts low level signals power consumption to only 150 µW typical. The part is available directly from a transducer or high level signals (4 � V ) and in a 24-lead, 0.3 inch wide, PDIP and CERDIP as well as a 24- REF outputs a serial digital word. It employs �-� conversion lead SOIC package. technique to realize up to 24 bits of no missing codes performance. The input signal is applied to a proprietary pro- PRODUCT HIGHLIGHTS grammable gain front end based around an analog modulator. 1. The AD7713 consumes less than 1 mA in total supply current, The modulator output is processed by an on-chip digital filter. making it ideal for use in loop-powered systems. The first notch of this digital filter can be programmed via the 2. The two programmable gain channels allow the AD7713 to on-chip control register, allowing adjustment of the filter cutoff accept input signals directly from a transducer removing a and settling time. considerable amount of signal conditioning. To maximize The part features two differential analog inputs and one single- the flexibility of the part, the high level analog input accepts ended high level analog input as well as a differential reference 4 � V signals. On-chip current sources provide excitation REF input. It can be operated from a single supply (AV and DV DD DD for 3-wire and 4-wire RTD configurations. at 5 V). The part provides two current sources that can be used 3. No missing codes ensures true, usable, 24-bit dynamic range to provide excitation in 3-wire and 4-wire RTD configurations. coupled with excellent ±0.0015% accuracy. The effects of The AD7713 thus performs all signal conditioning and conver- temperature drift are eliminated by on-chip self-calibration, sion for a single-, dual- or three-channel system. which removes zero-scale and full-scale errors. The AD7713 is ideal for use in smart, microcontroller-based 4. The AD7713 is ideal for microcontroller or DSP processor systems. Gain settings, signal polarity, and RTD current control applications with an on-chip control register, which allows can be configured in software using the bidirectional serial port. control over filter cutoff, input gain, signal polarity, and The AD7713 contains self-calibration, system calibration, and calibration modes. The AD7713 allows the user to read and background calibration options and also allows the user to read write the on-chip calibration registers. and to write the on-chip calibration registers. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. MUX (AV = 5 V � 5%; DV = 5 V � 5%; REF IN(+) = 2.5 V; REF IN(–) = AGND; AD7713–SPECIFICATIONS DD DD MCLK IN = 2 MHz, unless otherwise noted. All specifications T to T , unless otherwise noted.) MIN MAX 1 Parameter A, S Versions Unit Conditions/Comments STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 12 Hz. 22 Bits min For Filter Notch = 20 Hz. 18 Bits min For Filter Notch = 50 Hz. 15 Bits min For Filter Notch = 100 Hz. 12 Bits min For Filter Notch = 200 Hz. Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain. Integral Nonlinearity ±0.0015 % of FSR max Filter Notches ≤ 12 Hz; Typically ±0.0003%. 2, 3, 4 Positive Full-Scale Error 5 Full-Scale Drift 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. 2, 4 Unipolar Offset Error 5 Unipolar Offset Drift 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. 2, 4 Bipolar Zero Error 5 Bipolar Zero Drift 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Gain Drift 2 ppm/°C typ 2 Bipolar Negative Full-Scale Error ±0.0004 % of FSR max Typically ±0.0006%. 5 Bipolar Negative Full-Scale Drift 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. ANALOG INPUTS Input Sampling Rate, f See Table III S 6 Normal-Mode 50 Hz Rejection 100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 � f . NOTCH 6 Normal-Mode 60 Hz Rejection 100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 � f . NOTCH 7 AIN1, AIN2 8 Input Voltage Range For Normal Operation. Depends on Gain Selected. 9 0 to +V V max Unipolar Input Range REF (B/U Bit of Control Register = 1). ±V V max Bipolar Input Range REF (B/U Bit of Control Register = 0). Common-Mode Rejection (CMR) 100 dB min At dc and AV = 5 V. DD 90 dB min At dc and AV = 10 V. DD 6 Common-Mode 50 Hz Rejection 150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 � f NOTCH. 6 Common-Mode 60 Hz Rejection 150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 � f NOTCH. 10 Common-Mode Voltage Range AGND to AV V min to V max DD DC Input Leakage Current @ 25°C10 pA max T to T 1nA max MIN MAX 6 Sampling Capacitance 20 pF max AIN3 Input Voltage Range 0 to + 4 � V V max For Normal Operation. Depends on Gain REF Selected. 11 Gain Error ±0.05 % typ Additional Error Contributed by Resistor Attenuator. Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator. 11 Offset Error 4 mV max Additional Error Contributed by Resistor Attenuator. Input Impedance 30 kΩ min –2– REV. D AD7713 1 Parameter A, S Versions Unit Conditions/Comments REFERENCE INPUT REF IN(+) – REF IN(–) Voltage 2.5 to AV /1.8 V min to V max For Specified Performance. Part Is DD Functional with Lower V Voltages. REF Input Sampling Rate, f f /512 S CLK IN 6 Normal-Mode 50 Hz Rejection 100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 � f . NOTCH 6 Normal-Mode 60 Hz Rejection 100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 � f . NOTCH Common-Mode Rejection (CMR) 100 dB min At DC. 6 Common-Mode 50 Hz Rejection 150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 � f . NOTCH 6 Common-Mode 60 Hz Rejection 150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 � f . NOTCH 10 Common-Mode Voltage Range AGND to AV V min to V max DD DC Input Leakage Current @ 25°C10 pA max T to T 1nA max MIN MAX LOGIC INPUTS Input Current ±10 µA max All Inputs Except MCLK IN V , Input Low Voltage 0.8 V max INL V , Input High Voltage 2.0 V min INH MCLK IN Only V , Input Low Voltage 0.8 V max INL V , Input High Voltage 3.5 V min INH LOGIC OUTPUTS V , Output Low Voltage 0.4 V max I = 1.6 mA. OL SINK V , Output High Voltage 4.0 V min I = 100 µA. OH SOURCE Floating State Leakage Current ±10 µA max 12 Floating State Output Capacitance 9 pF typ TRANSDUCER BURN-OUT Current 1.2 µA nom Initial Tolerance @ 25°C ±10 % typ Drift 0.1 %/°C typ RTD EXCITATION CURRENTS (RTD1, RTD2) Output Current 200 µA nom Initial Tolerance @ 25°C ±20 % max Drift 20 ppm/°C typ Initial Matching @ 25°C ±1% max Matching Between RTD1 and RTD2 Currents. Drift Matching 3 ppm/°C typ Matching Between RTD1 and RTD2 Current Drift. Line Regulation (AV ) 200 nA/V max AV = 5 V. DD DD Load Regulation 200 nA/V max SYSTEM CALIBRATION AIN1, AIN2 13 Positive Full-Scale Calibration Limit +(1.05 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). 13 Negative Full-Scale Calibration Limit –(1.05 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). 14, 15 Offset Calibration Limit –(1.05 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). 14 Input Span +(0.8 � V )/GAIN V min GAIN Is the Selected PGA Gain REF (Between 1 and 128). +(2.1 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). REV. D –3– AD7713 1 Parameter A, S Versions Unit Conditions/Comments AIN3 13 Positive Full-Scale Calibration Limit +(4.2 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). 15 Offset Calibration Limit 0 to V /GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). Input Span +(3.2 � V )/GAIN V min GAIN Is the Selected PGA Gain REF (Between 1 and 128). +(4.2 � V )/GAIN V max GAIN Is the Selected PGA Gain REF (Between 1 and 128). POWER REQUIREMENTS Power Supply Voltages 16 AV Voltage 5 to 10 V nom ±5% for Specified Performance. DD 17 DV Voltage 5V nom ±5% for Specified Performance. DD Power Supply Currents AV Current 0.6 mA max AV = 5 V. DD DD 0.7 mA max AV = 10 V. DD DV Current 0.5 mA max f = 1 MHz. DD CLK IN Digital Inputs 0 V to DV . DD 1 mA max f = 2 MHz. CLK IN Digital Inputs 0 V to DV . DD 18 Power Supply Rejection Rejection w.r.t. AGND. 19 (AV and DV ) dB typ DD DD Power Dissipation Normal Mode 5.5 mW max AV = DV = 5 V, f = 1 MHz; DD DD CLK IN Typically 3.5 mW. Standby (Power-Down) Mode 300 µW max AV = DV = 5 V, Typically 150 µW. DD DD NOTES 1 Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C. 2 Applies after calibration at the temperature of interest. 3 Positive full-scale error applies to both unipolar and bipolar input ranges. 4 These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration or background calibration. 5 Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 These numbers are guaranteed by design and/or characterization. 7 The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recom- mended source resistance depends on the selected gain. 8 The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AV + 30 mV or more DD negative than AGND – 30 mV. 9 V = REF IN(+) – REF IN(–). REF 10 This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV + 30 mV and AGND – 30 mV. DD 11 This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset drift on the AIN3 input is four times the value given in the Static Performance section of the specifications. 12 Guaranteed by design, not production tested. 13 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 14 These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV + 30 mV or go more negative than DD AGND – 30 mV. 15 The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 16 Operating with AV voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range. DD 17 The ±5% tolerance on the DV input is allowed provided that DV does not exceed AV by more than 0.3 V. DD DD DD 18 Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz. 19 PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. Specifications subject to change without notice. –4– REV. D AD7713 (DV = 5 V � 5%; AV = 5 V or 10 V � 5%; AGND = DGND = 0 V; f = 2 MHz; DD DD CLKIN 1, 2 TIMING CHARACTERISTICS Input Logic 0 = 0 V, Logic 1 = DV , unless otherwise noted.) DD Limit at T , T MIN MAX Parameter (A, S Versions) Unit Conditions/Comments 3, 4 f 400 kHz min Master Clock Frequency: Crystal Oscillator or CLK IN 2 MHz max Externally Supplied for Specified Performance t 0.4 � t ns min Master Clock Input Low Time; t = 1/f CLK IN LO CLK IN CLK IN CLK IN t 0.4 � t ns min Master Clock Input High Time CLK IN HI CLK IN 5 t 50 ns max Digital Output Rise Time; Typically 20 ns r 5 t 50 ns max Digital Output Fall Time; Typically 20 ns f t 1000 ns min SYNC Pulse Width 1 Self-Clocking Mode t 0 ns min DRDY to RFS Setup Time 2 t 0 ns min DRDY to RFS Hold Time 3 t 2 � t ns min A0 to RFS Setup Time 4 CLK IN t 0 ns min A0 to RFS Hold Time 5 t 4 � t + 20 ns max RFS Low to SCLK Falling Edge 6 CLK IN 6 t 4 � t +20 ns max Data Access Time (RFS Low to Data Valid) 7 CLK IN 6 t t /2 ns min SCLK Falling Edge to Data Valid Delay 8 CLK IN t /2 + 30 ns max CLK IN t t /2 ns nom SCLK High Pulse Width 9 CLK IN t 3 � t /2 ns nom SCLK Low Pulse Width 10 CLK IN t 50 ns min A0 to TFS Setup Time 14 t 0 ns min A0 to TFS Hold Time 15 t 4 � t + 20 ns max TFS to SCLK Falling Edge Delay Time 16 CLK IN t 4 � t ns min TFS to SCLK Falling Edge Hold Time 17 CLK IN t 0 ns min Data Valid to SCLK Setup Time 18 t 10 ns min Data Valid to SCLK Hold Time 19 External-Clocking Mode f f /5 MHz max Serial Clock Input Frequency SCLK CLK IN t 0 ns min DRDY to RFS Setup Time 20 t 0 ns min DRDY to RFS Hold Time 21 t 2 � t ns min A0 to RFS Setup Time 22 CLK IN t 0 ns min A0 to RFS Hold Time 23 6 t 4 � t ns max Data Access Time (RFS Low to Data Valid) 24 CLK IN 6 t 10 ns min SCLK Falling Edge to Data Valid Delay 25 2 � t + 20 ns max CLK IN t 2 � t ns min SCLK High Pulse Width 26 CLK IN t 2 � t ns min SCLK Low Pulse Width 27 CLK IN t t + 10 ns max SCLK Falling Edge to DRDY High 28 CLK IN 7 t 10 ns min SCLK to Data Valid Hold Time 29 t + 10 ns max CLK IN t 10 ns min RFS/TFS to SCLK Falling Edge Hold Time 30 7 t 5 � t /2 + 50 ns max RFS to Data Valid Hold Time 31 CLK IN t 0 ns min A0 to TFS Setup Time 32 t 0 ns min A0 to TFS Hold Time 33 t 4 � t ns min SCLK Falling Edge to TFS Hold Time 34 CLK IN t 2 � t – SCLK High ns min Data Valid to SCLK Setup Time 35 CLK IN t 30 ns min Data Valid to SCLK Hold Time 36 NOTES 1 Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figures 10 to 13. 3 CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7713 is production tested with f at 2 MHz. It is guaranteed by characterization to operate at 400 kHz. CLK IN 5 Specified using 10% and 90% points on waveform of interest. 6 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 7 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. REV. D –5– AD7713 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (T = 25°C, unless otherwise noted.) A Temperature AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V DD Model Range Package Option* AV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V DD AD7713AN –40°C to +85°C N-24 DV to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD AD7713AR –40°C to +85°C RW-24 DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD AD7713AR-REEL –40°C to +85°C RW-24 AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V AD7713AR-REEL7 –40°C to +85°C RW-24 AIN1, AIN2 Input Voltage AD7713AQ –40°C to +85°C Q-24 to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD AD7713SQ –55°C to +125°C Q-24 AIN3 Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +22 V Reference Input Voltage to AGND . . . –0.3 V to AV + 0.3 V DD *N = PDIP; Q = CERDIP; RW = SOIC. Digital Input Voltage to DGND . . . . . –0.3 V to AV + 0.3 V DD Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V DD Operating Temperature Range Commercial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 105°C/W JA Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C CERDIP Package, Power Dissipation . . . . . . . . . . . . . 450 mW � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 70°C/W JA Lead Temperature, Soldering . . . . . . . . . . . . . . . . . . 300°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 75°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Power Dissipation (Any Package) to 75°C . . . . . . . . . . 450 mW *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.6mA TO OUTPUT PIN 2.1V 100pF 200�A Figure 1. Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7713 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. D AD7713 PIN CONFIGURATION PDIP, CERDIP, AND SOIC 1 24 SCLK DGND MCLK IN 2 23 DV DD 3 22 MCLK OUT SDATA 4 21 A0 DRDY 5 20 SYNC RFS AD7713 6 TOP VIEW 19 MODE TFS (Not to Scale) 7 18 AIN1(+) AGND 8 17 AIN1(–) AIN3 9 16 AIN2(+) RTD2 10 15 AIN2(–) REF IN(+) 11 14 STANDBY REF IN(–) AV 12 13 DD RTD1 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Function 1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK be- comes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when the device has completed transmission of an output word. When MODE is low, the device is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a con- tinuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 2 MHz. 3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. 4A0Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. 5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It resets the nodes of the digital filter. 6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its external clocking mode. 7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source that can be used to check that an external transducer has burnt out or gone open circuit. This output current source can be turned on/off via the control register. 8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input. 9 AIN2(+) Analog Input Channel 2. Positive input of the programmable gain differential analog input. 10 AIN2(–) Analog Input Channel 2. Negative input of the programmable gain differential analog input. 11 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power consumption to less than 100 µW. 12 AV Analog Positive Supply Voltage, 5 V to 10 V. DD 13 RTD1 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as the excitation current for RTDs. This current can be turned on or off via the control register. 14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AV and AGND, provided REF IN(+) is DD greater than REF IN(–). 15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–). REF IN(+) can lie anywhere between AV and AGND. DD REV. D –7– AD7713 Pin No. Mnemonic Function 16 RTD2 Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be used as the excitation current for RTDs. This current can be turned on or off via the control register. This second current can be used to eliminate lead resistanced errors in 3-wire RTD configurations. 17 AIN3 Analog Input Channel 3. High level analog input that accepts an analog input voltage range of 4 � V /GAIN. REF At the nominal V of 2.5 V and a gain of 1, the AIN3 input voltage range is 0 V to ±10 V. REF 18 AGND Ground Reference Point for Analog Circuitry. 19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self- clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7713 has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis- ters and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). Dur- ing a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DV Digital Supply Voltage, 5 V. DV should not exceed AV by more than 0.3 V in normal operation. DD DD DD 24 DGND Ground Reference Point for Digital Circuitry. TERMINOLOGY Positive Full-Scale Overrange Integral Nonlinearity Positive full-scale overrange is the amount of overhead available This is the maximum deviation of any code from a straight line to handle input voltages on AIN1(+) and AIN2(+) inputs passing through the endpoints of the transfer function. The greater than (AIN1(–) + V /GAIN) or on AIN3 of greater REF endpoints of the transfer function are zero scale (not to be con- than 4 � V /GAIN (for example, noise peaks or excess voltages REF fused with bipolar zero), a point 0.5 LSB below the first code due to system gain errors in system calibration routines) without transition (000...000 to 000...001) and full scale, a point 0.5 LSB introducing errors due to overloading the analog modulator or above the last code transition (111...110 to 111...111). The error to overflowing the digital filter. is expressed as a percentage of full scale. Negative Full-Scale Overrange Positive Full-Scale Error This is the amount of overhead available to handle voltages on Positive full-scale error is the deviation of the last code transition AIN1(+) and AIN2(+) below (AIN1(–) – V /GAIN) without REF (111...110 to 111...111) from the ideal input full-scale voltage. overloading the analog modulator or overflowing the digital filter. For AIN1(+) and AIN2(+), the ideal full-scale input voltage is Offset Calibration Range (AIN1(–) + V /GAIN – 3/2 LSBs), where AIN(–) is either REF In the system calibration modes, the AD7713 calibrates its offset AIN1(–) or AIN2(–) as appropriate; for AIN3, the ideal full-scale with respect to the analog input. The offset calibration range voltage is 4 � V /GAIN – 3/2 LSBs. Positive full-scale error REF specification defines the range of voltages that the AD7713 can applies to both unipolar and bipolar analog input ranges. accept and still calibrate offset accurately. Unipolar Offset Error Full-Scale Calibration Range Unipolar offset error is the deviation of the first code transition This is the range of voltages that the AD7713 can accept in the from the ideal voltage. For AIN1(+) and AIN2(+), the ideal system calibration mode and still calibrate full scale correctly. input voltage is (AIN1(–) + 0.5 LSB); for AIN3, the ideal input is 0.5 LSB when operating in the unipolar mode. Input Span In system calibration schemes, two voltages applied in sequence Bipolar Zero Error to the AD7713’s analog input define the analog input range. The This is the deviation of the midscale transition (0111 ... 111 to input span specification defines the minimum and maximum 1000 ... 000) from the ideal input voltage. For AIN1(+) and input voltages from zero to full scale that the AD7713 can accept AIN2(+), the ideal input voltage is (AIN1(–) – 0.5 LSB); AIN3 and still calibrate gain accurately. can accommodate only unipolar input ranges. Bipolar Negative Full-Scale Error This is the deviation of the first code transition from the ideal input voltage. For AIN1(+) and AIN2(+), the ideal input volt- age is (AIN1(–) – V /GAIN + 0.5 LSB); AIN3 can only REF accommodate unipolar input ranges. –8– REV. D AD7713 CONTROL REGISTER (24 BITS) control register. In other words, it is not possible to write just A write to the device with the A0 input low writes data to the the first 12 bits of data into the control register. If more than 24 control register. A read to the device with the A0 input low clock pulses are provided before TFS returns high, then all clock accesses the contents of the control register. The control register pulses after the 24th clock pulse are ignored. Similarly, a read is 24 bits wide. When writing to the register, 24 bits of data operation from the control register should access 24 bits of data. must be written; otherwise, the data will not be loaded to the MSB MD2 MD1 MD0 G2 G1 G0 CH1 CH0 WL RO BO B/U FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 LSB Operating Mode MD2 MD1 MD0 Operating Mode 00 0 Normal Mode. This is the normal mode of operation of the device whereby a read to the device with A0 high accesses data from the data register. This is the default condition of these bits after the internal power-on reset. 00 1Activate Self-Calibration. This activates self-calibration on the channel selected by CH0 and CH1. This is a 1-step calibration sequence, and when complete, the part returns to normal mode (with MD2, MD1, MD0 of the control registers returning to 0, 0, 0). The DRDY output indicates when this self-calibration is complete. For this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs, and the full-scale calibration is done on V . REF 01 0Activate System Calibration. This activates system calibration on the channel selected by CH0 and CH1. This is a 2-step calibration sequence, with the zero-scale calibration done first on the selected input channel and DRDY indicating when this zero-scale calibration is complete. The part returns to normal mode at the end of this first step in the 2-step sequence. 01 1Activate System Calibration. This is the second step of the system calibration sequence with full-scale calibration being performed on the selected input channel. Once again, DRDY indicates when the full- scale calibration is complete. When this calibration is complete, the part returns to normal mode. 10 0 Activate System Offset Calibration. This activates system offset calibration on the channel selected by CH0 and CH1. This is a 1-step calibration sequence and, when complete, the part returns to normal mode with DRDY indicating when this system offset calibration is complete. For this calibration type, the zero-scale calibration is done on the selected input channel, and the full-scale calibration is done internally on V . REF 10 1 Activate Background Calibration. This activates background calibration on the channel selected by CH0 and CH1. If the background calibration mode is on, the AD7713 provides continuous self-calibration of the refer- ence and shorted (zeroed) inputs. This calibration takes place as part of the conversion sequence, extending the conversion time and reducing the word rate by a factor of 6. Its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature. In this mode, the shorted (zeroed) inputs and V , as well as the analog input voltage, are continuously REF monitored, and the calibration registers of the device are updated. 11 0Read/Write Zero-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device with A0 high writes data to the zero-scale calibration coefficients of the channel selected by CH0 and CH1. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise, the new data will not be transferred to the calibration register. 11 1Read/Write Full-Scale Calibration Coefficients. A read to the device with A0 high accesses the contents of the full-scale calibration coefficients of the channel selected by CH0 and CH1. A write to the device with A0 high writes data to the full-scale calibration coefficients of the channel selected by CH0 and CH1. The word length for reading and writing these coefficients is 24 bits, regardless of the status of the WL bit of the control register. Therefore, when writing to the calibration register, 24 bits of data must be written; otherwise, the new data will not be transferred to the calibration register. REV. D –9– AD7713 PGA Gain Filter Selection (FS11 to FS0) 3 3 G2 Gl G0 Gain The on-chip digital filter provides a sinc (or (sinx/x) ) filter 00 01 (Default Condition after the Internal response. The 12 bits of data programmed into these bits deter- Power-On Reset) mine the filter cutoff frequency, the position of the first notch of 00 12 the filter, and the data rate for the part. In association with the 01 04 gain selection, it also determines the output noise (and therefore 01 18 the effective resolution) of the device. 10 016 The first notch of the filter occurs at a frequency determined by 10 132 the relationship: filter first notch frequency = (f /512)/code CLK IN 11 064 where code is the decimal equivalent of the code in Bits FS0 to 11 1128 FS11 and is in the range 19 to 2,000. With the nominal f CLK IN Channel Selection of 2 MHz, this results in a first notch frequency range from CH1 CH0 Channel 1.952 Hz to 205.59 kHz. To ensure correct operation of the 00 AIN1 (Default Condition after the Internal AD7713, the value of the code loaded to these bits must be Power-On Reset) within this range. Failure to do this will result in unspecified 01 AIN2 operation of the device. 10 AIN3 Changing the filter notch frequency, as well as the selected gain, Word Length impacts resolution. Tables I and II and Figures 2a and 2b show WL Output Word Length the effect of the filter notch frequency and gain on the effective 0 16-Bit (Default Condition after the Internal resolution of the AD7713. The output data rate (or effective Power-On Reset) conversion time) for the device is equal to the frequency se- lected for the first notch of the filter. For example, if the first 1 24-Bit notch of the filter is selected at 10 Hz, then a new word is avail- RTD Excitation Currents able at a 10 Hz rate or every 100 ms. If the first notch is at 200 Hz, RO a new word is available every 5 ms. 0Off (Default Condition after the Internal The settling time of the filter to a full-scale step input change is Power-On Reset) worst case 4 � 1/(Output Data Rate). This settling time is to 100% 1On of the final value. For example, with the first filter notch at 100 Hz, the settling time of the filter to a full-scale step input change is Burn-Out Current 400 ms max. If the first notch is at 200 Hz, the settling time of BO the filter to a full-scale input step is 20 ms max. This settling time 0Off (Default Condition after the Internal can be reduced to 3 � l/(Output Data Rate) by synchronizing the Power-On Reset) step input change to a reset of the digital filter. In other words, if 1On the step input takes place with SYNC low, the settling time will Bipolar/Unipolar Selection (Both Inputs) be 3 � l/(Output Data Rate). If a change of channels takes place, B/U the settling time is 3 � l/(Output Data Rate) regardless of the 0 Bipolar (Default Condition after the Internal SYNC input. Power-On Reset) The –3 dB frequency is determined by the programmed first 1 Unipolar notch frequency according to the relationship: Filter−= 30 dB Frequency .262× First Notch Frequency –10– REV. D AD7713 Tables I and II show the output rms noise for some typical higher filter notch frequencies. Meanwhile, device noise is notch and –3 dB frequencies. The numbers given are for the added in the PGA and, therefore, effective resolution suffers a bipolar input ranges with a V of 2.5 V. These numbers are little at high gains for lower notch frequencies. REF typical and are generated with an analog input voltage of 0 V. At the lower filter notch settings (below 12 Hz), the no missing The output noise from the part comes from two sources. First, codes performance of the device is at the 24-bit level. At the there is the electrical noise in the semiconductor devices used in higher settings, more codes will be missed until at 200 Hz notch the implementation of the modulator (device noise). Second, setting, no missing codes performance is guaranteed only to the when the analog input signal is converted into the digital domain, 12-bit level. However, since the effective resolution of the part quantization noise is added. The device noise is at a low level is 10.5 bits for this filter notch setting; this no missing codes and is largely independent of frequency. The quantization noise performance should be more than adequate for all applications. starts at an even lower level but rises rapidly with increasing The effective resolution of the device is defined as the ratio of the frequency to become the dominant noise source. Consequently, output rms noise to the input full scale. This does not remain lower filter notch settings (below 12 Hz approximately) tend to constant with increasing gain or with increasing bandwidth. be device noise dominated while higher notch settings are domi- Table II is the same as Table I except that the output is expressed nated by quantization noise. Changing the filter notch and in terms of effective resolution (the magnitude of the rms noise cutoff frequency in the quantization noise dominated region with respect to 2 � V /GAIN, i.e., the input full scale). It is REF results in a more dramatic improvement in noise performance possible to do post filtering on the device to improve the output than it does in the device noise dominated region as shown in data rate for a given –3 dB frequency and also to further reduce Table I. Furthermore, quantization noise is added after the the output noise (see the Digital Filtering section). PGA, so effective resolution is independent of gain for the Table I. Output Noise vs. Gain and First Notch Frequency First Notch of Typical Output RMS Noise (µV) Filter and O/P –3 dB 1 Data Rate FrequencyGain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 2 2 Hz 0.52 Hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25 2 5 Hz 1.31 Hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38 2 6 Hz 1.57 Hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4 2 10 Hz 2.62 Hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46 2 12 Hz 3.14 Hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56 3 20 Hz 5.24 Hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65 3 50 Hz 13.1 Hz 130 75 25 12 7.5 4 2.7 1.7 3 3 3 100 Hz 26.2 Hz 0.6 � 10 0.26 � 10 140 70 35 25 15 8 3 3 3 3 3 200 Hz 52.4 Hz 3.1 � 10 1.6 � 10 0.7 � 10 0.29 � 10 180 120 70 40 NOTES 1 The default condition (after the internal power-on reset) for the first notch of filter is 60 Hz. 2 For these filter notch frequencies, the output rms noise is primarily dominated by device noise, and, as a result, is independent of the value of the reference voltage. Therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is increased since the output rms noise remains constant as the input full scale increases). 3 For these filter notch frequencies, the output rms noise is dominated by quantization noise, and, as a result, is proportional to the value of the reference voltage. Table II. Effective Resolution vs. Gain and First Notch Frequency First Notch of Effective Resolution* (Bits) Filter and O/P –3 dB Data Rate Frequency Gain of 1 Gain of 2 Gain of 4Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 2 Hz 0.52 Hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5 5 Hz 1.31 Hz 21.5 21 21 20 19.5 18.5 17.5 16.5 6 Hz 1.57 Hz 21 21 20.5 20 19.5 18.5 17.5 16.5 10 Hz 2.62 Hz 20 20 20 19.5 19 18.5 17.5 16.5 12 Hz 3.14 Hz 20 20 20 19.5 19 18 17 16 20 Hz 5.24 Hz 18.5 18.5 18.5 18.5 18 17.5 17 16 50 Hz 13.1 Hz 15 15 15.5 15.5 15.5 15.5 15 14.5 100 Hz 26.2 Hz 13 13 13 13 13 12.5 12.5 12.5 200 Hz 52.4 Hz 10.5 10.5 11 11 11 10.5 10 10 *Effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 � V /GAIN). Table II applies for a V of 2.5 V REF REF and resolution numbers are rounded to the nearest 0.5 LSB. REV. D –11– AD7713 Figures 2a and 2b gives similar information to that outlined in the frequency of the master clock, MCLK IN, and the selected Table I. In this plot, the output rms noise is shown for the full gain (see Table III). A charge balancing ADC (�-� modulator) range of available cutoff frequencies rather than for some typical converts the sampled signal into a digital pulse train whose duty cutoff frequencies as in Tables I and II. The numbers given in cycle contains the digital information. The programmable gain these plots are typical values at 25°C. function on the analog input is also incorporated in this �-� modulator with the input sampling frequency being modified to 3 10000.0 give the higher gains. A sinc digital low-pass filter processes the GAIN OF 1 output of the �-� modulator and updates the output register at GAIN OF 2 a rate determined by the first notch frequency of this filter. The 1000.0 GAIN OF 4 output data can be read from the serial port randomly or peri- GAIN OF 8 odically at any rate up to the output register update rate. The 100.0 first notch of this digital filter (and therefore its –3 dB frequency) can be programmed via an on-chip control register. The programmable range for this first notch frequency is from 10.0 1.952 Hz to 205.59 Hz, giving a programmable range for the –3 dB frequency of 0.52 Hz to 53.9 Hz. 1.0 The basic connection diagram for the part is shown in Figure 3. This shows the AD7713 in the external clocking mode with both the AV and DV pins of the AD7713 being driven DD DD 0.1 10 100 1k 10k from the analog 5 V supply. Some applications will have sepa- NOTCH FREQUENCY (Hz) rate supplies for both AV and DV , and in some of these DD DD cases, the analog supply will exceed the 5 V digital supply (see the Figure 2a. Plot of Output Noise vs. Gain and Notch Power Supplies and Grounding section). Frequency (Gains of 1 to 8) ANALOG 5V 1000.0 SUPPLY 10�F 0.1�F GAIN OF 16 100.0 GAIN OF 32 AV DV DD DD DATA AIN1(+) DRDY DIFFERENTIAL READY GAIN OF 64 ANALOG INPUT AIN1(–) TRANSMIT TFS (WRITE) GAIN OF 128 AIN2(+) DIFFERENTIAL ANALOG INPUT RECEIVE AIN2(–) RFS 10.0 (READ) SINGLE-ENDED SERIAL AD7713 AIN3 SDATA ANALOG INPUT DATA DV DD SERIAL 1.0 STANDBY SCLK CLOCK ANALOG ADDRESS AGND A0 GROUND INPUT DIGITAL 0.1 DGND MODE GROUND 10 100 1k 10k DV DD NOTCH FREQUENCY (Hz) 2.5V REF IN(+) SYNC REFERENCE MCLK IN Figure 2b. Plot of Output Noise vs. Gain and Notch REF IN(–) Frequency (Gains of 16 to 128) MCLK OUT CIRCUIT DESCRIPTION Figure 3. Basic Connection Diagram The AD7713 is a �-� ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals, The AD7713 provides a number of calibration options that can such as those in industrial control or process control applications. It be programmed via the on-chip control register. A calibration contains a �-� (or charge balancing) ADC, a calibration cycle can be initiated at any time by writing to this control regis- microcontroller with on-chip static RAM, a clock oscillator, a ter. The part can perform self-calibration using the on-chip digital filter, and a bidirectional serial communications port. calibration microcontroller and SRAM to store calibration parameters. Other system components may also be included in The part contains three analog input channels, two program- the calibration loop to remove offset and gain errors in the input mable gain differential input channels, and one programmable channel using the system calibration mode. Another option is a gain high-level single-ended input channel. The gain range on background calibration mode where the part continuously both inputs is from 1 to 128. For the AIN1 and AIN2 inputs, performs self-calibration and updates the calibration coeffi- this means that the input can accept unipolar signals of between cients. Once the part is in this mode, the user does not have to 0 mV to 20 mV and 0 V to 2.5 V or bipolar signals in the range worry about issuing periodic calibration commands to the device from ±20 mV to ±2.5 V when the reference input voltage equals or asking the device to recalibrate when there is a change in the 2.5 V. The input voltage range for the AIN3 input is 4 � V / REF ambient temperature or power supply voltage. GAIN and is 0 V to 10 V with the nominal reference of 2.5 V and a ANALOG gain of 1. The input signal to the selected analog input channel is continuously sampled at a rate determined by –12– REV. D OUTPUT NOISE (�V) OUTPUT NOISE (�V) AD7713 The AD7713 gives the user access to the on-chip calibration �-� ADCs are generally described by the order of the analog registers, allowing the microprocessor to read the device’s calibra- low-pass filter. A simple example of a first-order �-� ADC is tion coefficients and also to write its own calibration coefficients shown in Figure 5. This contains only a first-order low-pass 2 to the part from prestored values in E PROM. This gives the filter or integrator. It also illustrates the derivation of the alter- microprocessor much greater control over the AD7713’s calibra- native name for these devices: charge balancing ADCs. tion procedure. It also means that the user can verify that the DIFFERENTIAL device has performed its calibration correctly by comparing the AMPLIFIER INTEGRATOR 2 coefficients after calibration with prestored values in E PROM. COMPARATOR V IN For battery-operated or low power systems, the AD7713 offers a standby mode (controlled by the STANDBY pin) that reduces idle power consumption to typically 150 µW. +FS DAC THEORY OF OPERATION –FS The general block diagram of a �-� ADC is shown in Figure 4. Figure 5. Basic Charge-Balancing ADC It contains the following elements: It consists of a differential amplifier (whose output is the differ- •A sample-hold amplifier ence between the analog input and the output of a 1-bit DAC), •A differential amplifier or subtracter an integrator, and a comparator. The term charge balancing comes •An analog low-pass filter from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at 0 by balanc- •A 1-bit ADC (comparator) ing charge injected by the input voltage with charge injected by •A 1-bit DAC the 1-bit DAC. When the analog input is 0, the only contribu- tion to the integrator output comes from the 1-bit DAC. For the S/H AMP COMPARATOR net charge on the integrator capacitor to be 0, the DAC output ANALOG LOW-PASS must spend half its time at +FS and half its time at –FS. Assum- DIGITAL FILTER FILTER ing ideal components, the duty cycle of the comparator will be 50%. When a positive analog input is applied, the output of the 1-bit DAC DIGITAL DATA DAC must spend a larger proportion of the time at +FS, so the duty cycle of the comparator increases. When a negative input Figure 4. General �-� ADC voltage is applied, the duty cycle decreases. In operation, the analog signal sample is fed to the subtracter, The AD7713 uses a second-order �-� modulator and a digital along with the output of the 1-bit DAC. The filtered difference filter that provides a rolling average of the sampled output. signal is fed to the comparator, whose output samples the differ- After power-up or if there is a step change in the input voltage, ence signal at a frequency many times that of the analog signal there is a settling time that must elapse before valid data is sampling frequency (oversampling). obtained. Oversampling is fundamental to the operation of �-� ADCs. Input Sample Rate Using the quantization noise formula for an ADC The modulator sample frequency for the device remains at SNR=× 60.. 2 Number of Bits+176 dB () f /512 (3.9 kHz @ f = 2 MHz) regardless of the CLK IN CLK IN selected gain. However, gains greater than �1 are achieved by a a 1-bit ADC or comparator yields an SNR of 7.78 dB. combination of multiple input samples per modulator cycle and The AD7713 samples the input signal at a frequency of 7.8 kHz a scaling of the ratio of the reference capacitor to input capaci- or greater (see Table III). As a result, the quantization noise is tor. As a result of the multiple sampling, the input the sample spread over a much wider frequency than that of the band of rate of the device varies with the selected gain (see Table III). interest. The noise in the band of interest is reduced still fur- The effective input impedance is 1/C � f , where C is the input S ther by analog filtering in the modulator loop, which shapes sampling capacitance and f is the input sample rate. S the quantization noise spectrum to move most of the noise energy to frequencies outside the bandwidth of interest. The Table III. Input Sampling Frequency vs. Gain noise performance is thus improved from this 1-bit level to the Gain Input Sampling Frequency (f ) S performance outlined in Tables I and II and in Figures 2a and 2b. 1f /256 (7.8 kHz @ f = 2 MHz) The output of the comparator provides the digital input for the CLK IN CLK IN 22 � f /256 (15.6 kHz @ f = 2 MHz) 1-bit DAC, so that the system functions as a negative feedback CLK IN CLK IN 44 � f /256 (31.2 kHz @ f = 2 MHz) loop that tries to minimize the difference signal. The digital data CLK IN CLK IN 88 � f /256 (62.4 kHz @ f = 2 MHz) that represents the analog input voltage is contained in the duty CLK IN CLK IN 16 8 � f /256 (62.4 kHz @ f = 2 MHz) cycle of the pulse train appearing at the output of the compara- CLK IN CLK IN 32 8 � f /256 (62.4 kHz @ f = 2 MHz) tor. It can be retrieved as a parallel binary data-word using a CLK IN CLK IN 64 8 � f /256 (62.4 kHz @ f = 2 MHz) digital filter. CLK IN CLK IN 128 8 � f /256 (62.4 kHz @ f = 2 MHz) CLK IN CLK IN REV. D –13– AD7713 DIGITAL FILTERING Post Filtering The AD7713’s digital filter behaves like a similar analog filter, The on-chip modulator provides samples at a 3.9 kHz output with a few minor differences. rate. The on-chip digital filter decimates these samples to provide data at an output rate that corresponds to the pro- First, since digital filtering occurs after the A-to-D conversion grammed first notch frequency of the filter. Since the output process, it can remove noise injected during the conversion data rate exceeds the Nyquist criterion, the output rate for a process. Analog filtering cannot do this. given bandwidth will satisfy most application requirements. On the other hand, analog filtering can remove noise superimposed However, there may be some applications that require a higher on the analog signal before it reaches the ADC. Digital filtering data rate for a given bandwidth and noise performance. Appli- cannot do this, and noise peaks riding on signals near full scale cations that need this higher data rate will require some post have the potential to saturate the analog modulator and digital filtering following the digital filter of the AD7713. filter, even though the average value of the signal is within limits. For example, if the required bandwidth is 1.57 Hz but the required To alleviate this problem, the AD7713 has overrange headroom update rate is 20 Hz, the data can be taken from the AD7713 at built into the �-� modulator and digital filter, which allows over- the 20 Hz rate giving a –3 dB bandwidth of 5.24 Hz. Post filtering range excursions of 5% above the analog input range. If noise can be applied to this to reduce the bandwidth and output noise, signals are larger than this, consideration should be given to analog to the 1.57 Hz bandwidth level, while maintaining an output rate input filtering or to reducing the input channel voltage so that its of 20 Hz. full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense Post filtering can also be used to reduce the output noise from of reducing the dynamic range by 1 bit (50%). the device for bandwidths below 0.52 Hz. At a gain of 128, the output rms noise is 250 nV. This is essentially device noise or Filter Characteristics white noise, and since the input is chopped, the noise has a flat The cutoff frequency of the digital filter is determined by the value frequency response. By reducing the bandwidth below 0.52 Hz, loaded to Bits FS0 to FS11 in the control register. At the maxi- the noise in the resultant pass band can be reduced. A reduction mum clock frequency of 2 MHz, the minimum cutoff frequency of in bandwidth by a factor of 2 results in a √2 reduction in the the filter is 0.52 Hz, while the maximum programmable cutoff output rms noise. This additional filtering will result in a longer frequency is 53.9 Hz. settling time. Figure 6 shows the filter frequency response for a cutoff frequency Antialias Considerations of 0.52 Hz, which corresponds to a first filter notch frequency of 3 3 The digital filter does not provide any rejection at integer 2 Hz. This is a (sinx/x) response (also called sinc ) that provides multiples of the modulator sample frequency (n � 3.9 kHz, >100 dB of 50 Hz and 60 Hz rejection. Programming a differ- where n = 1, 2, 3...). This means that there are frequency ent cutoff frequency via FS0 to FS11 does not alter the profile bands, ±f dB wide (f dB is cutoff frequency selected by FS0 3 3 of the filter response; it changes the frequency of the notches as to FS11), where noise passes unattenuated to the output. outlined in the Control Register section. However, due to the AD7713’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most 0 broadband noise is filtered. In any case, because of the high –20 oversampling ratio, a simple, RC, single-pole filter is generally –40 sufficient to attenuate the signals in these bands on the analog –60 input and thus provide adequate antialiasing filtering. –80 If passive components are placed in front of the AIN1 and –100 AIN2 inputs of the AD7713, care must be taken to ensure that –120 the source impedance is low enough so as not to introduce –140 gain errors in the system. The dc input impedance for the –160 AIN1 and AIN2 inputs is over 1 GΩ. The input appears as a –180 dynamic load that varies with the clock frequency and with the –200 selected gain (see Figure 7). The input sample rate, as shown –220 in Table III, determines the time allowed for the analog input –240 capacitor, C , to be charged. External impedances result in a IN 02468 10 12 longer charge time for this capacitor, which result in gain er- FREQUENCY (Hz) rors being introduced on the analog inputs. Both inputs of the Figure 6. Frequency Response of AD7713 Filter differential input channels look into similar input circuitry. Since the AD7713 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and R INT HIGH (7k� TYP) data on the output will be invalid after a step change until the AIN IMPEDANCE settling time has elapsed. The settling time depends upon the C > 1G� INT (11.5pF TYP) notch frequency chosen for the filter. The output data rate V BIAS equates to this filter notch frequency, and the settling time of SWITCHING FREQUENCY DEPENDS ON the filter to a full-scale step input is four times the output data f AND SELECTED GAIN CLKIN period. In applications using both input channels, the settling time of the filter must be allowed to elapse before data from the Figure 7. AIN1, AIN2 Input Impedance second channel is accessed. –14– REV. D GAIN (dB) AD7713 In any case, the error introduced due to longer charging times is The temperature coefficient of the RTD current sources is a gain error that can be removed using the system calibration typically 20 ppm/°C with a typical matching between the capabilities of the AD7713 provided that the resultant span is temperature coefficients of both current sources of 3 ppm/°C. within the span limits of the system calibration techniques for For applications where the absolute value of the temperature the AD7713. coefficient is too large, the following schemes can be used to remove the drift error. The AIN3 input contains a resistive attenuation network as outlined in Figure 8. The typical input impedance on this input The conversion result from the AD7713 is ratiometric to the is 44 kΩ. As a result, the AIN3 input should be driven from a V voltage. Therefore, if the V voltage varies with the RTD REF REF low impedance source. temperature coefficient, the temperature drift from the current source will be removed. For 4-wire RTD applications, the refer- ence voltage can be made ratiometric to the RTD current source 33k� by using the second current with a low TC resistor to generate the AIN3 reference voltage for the part. In this case, if a 12.5 kΩ resistor is 11k� MODULATOR CIRCUIT used, the 200 µA current source generates 2.5 V across the resistor. This 2.5 V can be applied to the REF IN(+) input of the AD7713 V BIAS and the REF IN(–) input at ground will supply a V of 2.5 V for REF Figure 8. AIN3 Input Impedance the part. For 3-wire RTD configurations, the reference voltage for the part is generated by placing a low TC resistor (12.5 kΩ for ANALOG INPUT FUNCTIONS 2.5 V reference) in series with one of the constant current sources. Analog Input Ranges The RTD current sources can be driven to within 2 V of AV . DD The analog inputs on the AD7713 provide the user with consid- The reference input of the AD7713 is differential so the REF IN(+) erable flexibility in terms of analog input voltage ranges. Two of and REF IN(–) of the AD7713 are driven from either side of the the inputs are differential, programmable-gain, input channels resistor. Both schemes ensure that the reference voltage for the part that can handle either unipolar or bipolar input signals. The tracks the RTD current sources over temperature and, thereby, common-mode range of these inputs is from AGND to AV , removes the temperature drift error. DD provided that the absolute value of the analog input voltage lies Bipolar/Unipolar Inputs between AGND – 30 mV and AV + 30 mV. The third analog DD Two analog inputs on the AD7713 can accept either unipolar or input is a single-ended, programmable gain high-level input that bipolar input voltage ranges while the third channel accepts only accepts analog input ranges of 0 to 4 � V /GAIN. REF unipolar signals. Bipolar or unipolar options for AIN1 and AIN2 The dc input leakage current on the AIN1 and AIN2 inputs are chosen by programming the B/U bit of the control register. is 10 pA maximum at 25°C (±1 nA over temperature). This This programs both channels for either unipolar or bipolar opera- results in a dc offset voltage developed across the source tion. Programming the part for either unipolar or bipolar operation impedance. However, this dc offset effect can be compensated does not change any of the input signal conditioning; it simply for by a combination of the differential input capability of the changes the data output coding. The data coding is binary for part and its system calibration mode. The dc input current on unipolar inputs and offset binary for bipolar inputs. the AIN3 input depends on the input voltage. For the nominal The AIN1 and AIN2 input channels are differential, and as a input voltage range of 10 V, the input current is 225 µA typ. result, the voltage to which the unipolar and bipolar signals are Burn Out Current referenced is the voltage on the AIN1(–) and AIN2(–) inputs. For The AIN1(+) input of the AD7713 contains a 1 µA current source example, if AIN1(–) is 1.25 V and the AD7713 is configured for that can be turned on/off via the control register. This current unipolar operation with a gain of 1 and a V of 2.5 V, the input REF source can be used in checking that a transducer has not burnt out voltage range on the AIN1(+) input is 1.25 V to 3.75 V. For the or gone open circuit before attempting to take measurements on AIN3 input, the input signals are referenced to AGND. that channel. If the current is turned on and is allowed flow into the transducer and a measurement of the input voltage on the REFERENCE INPUT AIN1 input is taken, it can indicate that the transducer is not func- The reference inputs of the AD7713, REF IN(+) and REF IN(–), tioning correctly. For normal operation, this burn out current is provide a differential reference input capability. The common- turned off by writing a 0 to the BO bit in the control register. mode range for these differential inputs is from V to AV . The SS DD nominal differential voltage, V (REF IN(+) – REF IN(–)), is REF RTD Excitation Currents 2.5 V for specified operation, but the reference voltage can go to The AD7713 also contains two matched 200 µA constant cur- 5 V with no degradation in performance, provided that the rent sources which are provided at the RTD1 and RTD2 pins of absolute value of REF IN(+) and REF IN(–) does not exceed the device. These currents can be turned on/off via the control its AV and AGND limits. The part is also functional with DD register. Writing a 1 to the RO bit of the control register enables V voltages down to 1 V, but with degraded performance as the REF these excitation currents. output noise will, in terms of LSB size, be larger. REF IN(+) For 4-wire RTD applications, one of these excitation currents is must always be greater than REF IN(–) for correct operation of used to provide the excitation current for the RTD; the second the AD7713. current source can be left unconnected. For 3-wire RTD con- Both reference inputs provide a high impedance, dynamic load figurations, the second on-chip current source can be used similar to the analog inputs. The maximum dc input leakage cur- to eliminate errors due to voltage drops across lead resistances. rent is 10 pA (±1 nA over temperature), and source resistance Figures 19 and 20 in the Application section show some RTD may result in gain errors on the part. The reference inputs configurations with the AD7713. REV. D –15– AD7713 look like the AIN1 analog input (see Figure 7). In this case, R The digital filter will be reset upon issue of a calibration, INT is 5 kΩ typ and C varies with gain. The input sample rate is command (whether it is self-calibration, system calibration or INT f /256 and does not vary with gain. For gains of 1 to 8, background calibration) to the AD7713. This ensures correct CLK IN C is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is operation of the AD7713. In systems where the power-on default INT 5 pF; for a gain of 64, it is 2.5 pF; and for a gain of 128, it is conditions of the AD7713 are acceptable, and no calibration is 1.25 pF. performed after power-on, issuing a SYNC pulse to the AD7713 will reset the AD7713’s digital filter logic. An R, C on the SYNC The digital filter of the AD7713 removes noise from the reference line, with R, C time constant longer than the DV power-on DD input just as it does with the analog input, and the same limita- time, will perform the SYNC function. tions apply regarding lack of noise rejection at integer multiples of the sampling frequency. The output noise performance outlined Accuracy in Tables I and II assumes a clean reference. If the reference �-� ADCs, like VFCs and other integrating ADCs, do not contain noise in the bandwidth of interest is excessive, it can degrade the any source of nonmonotonicity, and inherently offer no missing performance of the AD7713. A recommended reference source codes performance. The AD7713 achieves excellent linearity by for the AD7713 is the AD680, a 2.5 V reference. the use of high quality, on-chip silicon dioxide capacitors, which have a very low capacitance/voltage coefficient. The device also USING THE AD7713 SYSTEM achieves low input drift through the use of chopper stabilized tech- DESIGN CONSIDERATIONS niques in its input stage. To ensure excellent performance over The AD7713 operates differently from successive approxima- time and temperature, the AD7713 uses digital calibration tech- tion ADCs or integrating ADCs. Since it samples the signal niques that minimize offset and gain error. continuously, like a tracking ADC, there is no need for a start Autocalibration convert command. The output register is updated at a rate Autocalibration on the AD7713 removes offset and gain determined by the first notch of the filter, and the output can be errors from the device. A calibration routine should be initi- read at any time, either synchronously or asynchronously. ated on the device whenever there is a change in the ambient Clocking operating temperature or supply voltage. It should also be The AD7713 requires a master clock input, which may be an initiated if there is a change in the selected gain, filter notch, external TTL/CMOS compatible clock signal applied to the or bipolar/unipolar input range. However, if the AD7713 is in MCLK IN pin with the MCLK OUT pin left unconnected. its background calibration mode, the above changes are all Alternatively, a crystal of the correct frequency can be connected automatically taken care of (after the settling time of the filter between MCLK IN and MCLK OUT, in which case the clock has been allowed for). circuit will function as a crystal controlled oscillator. For lower The AD7713 offers self-calibration, system calibration, and clock frequencies, a ceramic resonator may be used instead of the background calibration facilities. For calibration to occur on crystal. For these lower frequency oscillators, external capacitors the selected channel, the on-chip microcontroller must record may be required on either the ceramic resonator or on the crystal. the modulator output for two different input conditions. These The input sampling frequency, the modulator sampling frequency, are zero-scale and full-scale points. With these readings, the the –3 dB frequency, output update rate, and calibration time microcontroller can calculate the gain slope for the input to are all directly related to the master clock frequency, f . output transfer function of the converter. Internally, the part CLK IN Reducing the master clock frequency by a factor of two will halve works with a resolution of 33 bits to determine its conversion the above frequencies and update rate and will double the cali- result of either 16 bits or 24 bits. bration time. The AD7713 also provides the facility to write to the on-chip The current drawn from the DV power supply is also directly calibration registers, and, in this manner, the span and offset for DD related to f . Reducing f by a factor of two will halve the part can be adjusted by the user. The offset calibration register CLK IN CLK IN the DV current but will not affect the current drawn from the contains a value that is subtracted from all conversion results, while DD AV power supply. the full-scale calibration register contains a value that is multiplied DD by all conversion results. The offset calibration coefficient is sub- System Synchronization tracted from the result prior to the multiplication by the full-scale If multiple AD7713s are operated from a common master clock, coefficient. In the first three modes outlined here, the DRDY line they can be synchronized to update their output registers simul- indicates that calibration is complete by going low. If DRDY is low taneously. A falling edge on the SYNC input resets the filter before (or goes low during) the calibration command, it may take and places the AD7713 into a consistent, known state. A com- up to one modulator cycle before DRDY goes high to indicate that mon signal to the AD7713’s SYNC inputs will synchronize their calibration is in progress. Therefore, the DRDY line should be operation. This would normally be done after each AD7713 has ignored for up to one modulator cycle after the last bit of the cali- performed its own calibration or has had calibration coefficients bration command is written to the control register. loaded to it. Self-Calibration The SYNC input can also be used to reset the digital filter in In the self-calibration mode with a unipolar input range, the systems where the turn-on time of the digital power supply zero-scale point used in determining the calibration coefficients (DV ) is very long. In such cases, the AD7713 will start operat- DD is with both inputs shorted and the full-scale point is V . The REF ing internally before the DV line has reached its minimum DD zero-scale coefficient is determined by converting an internal operating level, 4.75 V. With a low DV voltage, the AD7713’s DD shorted inputs node. The full-scale coefficient is determined internal digital filter logic does not operate correctly. Thus, the from the span between this shorted inputs conversion and a AD7713 may have clocked itself into an incorrect operating conversion on an internal V node. The self-calibration mode REF condition by the time that DV has reached its correct level. DD –16– REV. D AD7713 is invoked by writing the appropriate values (0, 0, 1) to the System Offset Calibration MD2, MD1, and MD0 bits of the control register. In this cali- System offset calibration is a variation of both the system cali- bration mode, the shorted inputs node is switched in to the bration and self-calibration. In this case, the zero-scale point modulator first and a conversion is performed; the V node is for the system is presented to the AIN input of the converter. REF then switched in, and another conversion is performed. When System offset calibration is initiated by writing 1, 0, 0 to MD2, the calibration sequence is complete, the calibration coefficients MD1, and MD0. The system zero-scale coefficient is deter- updated, and the filter resettled to the analog input voltage, the mined by converting the voltage applied to the AIN input, while DRDY output goes low. The self-calibration procedure takes the full-scale coefficient is determined from the span between into account the selected gain on the PGA. this AIN conversion and a conversion on V . The zero-scale REF point should be applied to the AIN input for the duration of the For bipolar input ranges in the self-calibrating mode, the sequence calibration sequence. This is a 1-step calibration sequence with is very similar to that just outlined. In this case, the two points DRDY going low when the sequence is completed. In the uni- that the AD7713 calibrates are midscale (bipolar zero) and polar mode, the system offset calibration is performed between positive full scale. the two endpoints of the transfer function; in the bipolar mode, System Calibration it is performed between midscale and positive full scale. System calibration allows the AD7713 to compensate for system Background Calibration gain and offset errors as well as its own internal errors. System The AD7713 also offers a background calibration mode where calibration performs the same slope factor calculations as self- the part interleaves its calibration procedure with its normal calibration but uses voltage values presented by the system to conversion sequence. In the background calibration mode, the the AIN inputs for the zero-scale and full-scale points. System same voltages are used as the calibration points as are used in calibration is a 2-step process. The zero-scale point must be the self-calibration mode, i.e., shorted inputs and V . The REF presented to the converter first. It must be applied to the converter background calibration mode is invoked by writing 1, 0, 1 to before the calibration step is initiated and remain stable until the MD2, MD1, and MD0 of the control register. When invoked, step is complete. System calibration is initiated by writing the the background calibration mode reduces the output data rate of appropriate values (0, 1, 0) to the MD2, MD1, and MD0 bits the AD7713 by a factor of 6 while the –3 dB bandwidth remains of the control register. The DRDY output from the device will unchanged. Its advantage is that the part is continually per- signal when the step is complete by going low. After the zero- forming calibration and automatically updating its calibration scale point is calibrated, the full-scale point is applied and the coefficients. As a result, the effects of temperature drift, supply second step of the calibration process is initiated by again writ- sensitivity and time drift on zero- and full-scale errors are auto- ing the appropriate values (0, 1, 1) to MD2, MD1, and MD0. matically removed. When the background calibration mode is Again, the full-scale voltage must be set up before the calibra- turned on, the part will remain in this mode until Bits MD2, tion is initiated, and it must remain stable throughout the MD1, and MD0 of the control register are changed. With back- calibration step. DRDY goes low at the end of this second step ground calibration mode on, the first result from the AD7713 to indicate that the system calibration is complete. In the unipo- will be incorrect as the full-scale calibration will not have been lar mode, the system calibration is performed between the two performed. For a step change on the input, the second output endpoints of the transfer function; in the bipolar mode, it is update will have settled to 100% of the final value. performed between midscale and positive full scale. Table IV summarizes the calibration modes and the calibration This 2-step system calibration mode offers another feature. points associated with them. It also gives the duration from After the sequence has been completed, additional offset or gain when the calibration is invoked to when valid data is available to calibrations can be performed by themselves to adjust the zero the user. reference point or the system gain. This is achieved by perform- ing the first step of the system calibration sequence (by writing Span and Offset Limits 0, 1, 0 to MD2, MD1, and MD0). This will adjust the zero- Whenever a system calibration mode is used, there are limits on scale or offset point but will not change the slope factor from the amount of offset and span that can be accommodated. The what was set during a full system calibration sequence. range of input span in both the unipolar and bipolar modes for AIN1 and AIN2 has a minimum value of 0.8 � V /GAIN and REF System calibration can also be used to remove any errors from a maximum value of 2.1 � V /GAIN. For AIN3, the mini- REF an antialiasing filter on the analog input. A simple R, C anti- mum value is 3.2 � V /GAIN, while the maximum value is REF aliasing filter on the front end may introduce a gain error on the 4.2 � V /GAIN. REF analog input voltage but the system calibration can be used to remove this error. Table IV. Calibration Truth Table Zero-Scale Full-Scale Calibration Type MD2, MD1, MD0 Calibration Calibration Sequence Duration Self-Calibration 0, 0, 1 Shorted Inputs V 1-Step 9 � 1/Output Rate REF System Calibration 0, 1, 0 AIN 2-Step 4 � 1/Output Rate System Calibration 0, 1, 1 AIN 2-Step 4 � 1/Output Rate System Offset Calibration 1, 0, 0 AIN V 1-Step 9 � 1/Output Rate REF Background Calibration 1, 0, 1 Shorted Inputs V 1-Step 6 � 1/Output Rate REF REV. D –17– AD7713 The amount of offset that can be accommodated depends on It is also important that power is applied to the AD7713 before whether the unipolar or bipolar mode is being used. This offset signals at REF IN, AIN, or the logic input pins in order to avoid range is limited by the requirement that the positive full-scale excessive current. If separate supplies are used for the AD7713 and calibration limit is ≤ 1.05 � V /GAIN for AIN1 and AIN2. the system digital circuitry, then the AD7713 should be powered REF Therefore, the offset range plus the span range cannot exceed up first. If it is not possible to guarantee this, then current limiting 1.05 � V /GAIN for AIN1 and AIN2. If the span is at its resistors should be placed in series with the logic inputs. REF minimum (0.8 � V /GAIN), the maximum the offset can be REF is (0.25 � V /GAIN) for AIN1 and AIN2. For AIN3, both REF DIGITAL 5V ANALOG ranges are multiplied by a factor of 4. SUPPLY SUPPLY In the bipolar mode, the system offset calibration range is 10�F 0.1�F 0.1�F again restricted by the span range. The span range of the AV DV DD DD converter in bipolar mode is equidistant around the voltage AD7713 used for the zero-scale point, thus the offset range plus half the span range cannot exceed (1.05 � V /GAIN) for AIN1 REF Figure 9. Recommended Decoupling Scheme and AIN2. If the span is set to 2 � V /GAIN, the offset REF span cannot move more than ±(0.05 � V /GAIN) before REF DIGITAL INTERFACE the endpoints of the transfer function exceed the input overrange The AD7713’s serial communications port provides a flexible limits ±(1.05 � V /GAIN) for AIN1. If the span range is set to REF arrangement to allow easy interfacing to industry-standard the minimum ±(0.4 � V /GAIN), the maximum allowable REF microprocessors, microcontrollers, and digital signal processors. offset range is ±(0.65 � V /GAIN) for AIN1 and AIN2. The REF A serial read to the AD7713 can access data from the output AIN3 input can only be used in the unipolar mode. register, the control register, or from the calibration registers. A serial write to the AD7713 can write data to the control register POWER-UP AND CALIBRATION or the calibration registers. On power-up, the AD7713 performs an internal reset, which sets the contents of the control register to a known state. How- Two different modes of operation are available, optimized for ever, to ensure correct calibration for the device, a calibration different types of interface where the AD7713 can act either as routine should be performed after power-up. master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the AD7713). These The power dissipation and temperature drift of the AD7713 are two modes, labeled self-clocking mode and external clocking low and no warm-up time is required before the initial calibra- mode, are discussed in detail in the following sections. tion is performed. However, the external reference must have stabilized before calibration is initiated. Self-Clocking Mode The AD7713 is configured for its self-clocking mode by tying Drift Considerations the MODE pin high. In this mode, the AD7713 provides the The AD7713 uses chopper stabilization techniques to minimize serial clock signal used for the transfer of data to and from the input offset drift. Charge injection in the analog switches and dc AD7713. This self-clocking mode can be used with processors leakage currents at the sampling node are the primary sources of that allow an external device to clock their serial port, including offset voltage drift in the converter. The dc input leakage cur- most digital signal processors and microcontrollers, such as the rent is essentially independent of the selected gain. Gain drift 68HC11 and 68HC05. It also allows easy interfacing, to serial within the converter depends primarily upon the temperature parallel conversion circuits in systems with parallel data com- tracking of the internal capacitors. It is not affected by leakage munication, allowing interfacing to 74XX299 universal shift currents. registers without any additional decoding. In the case of shift Measurement errors due to offset drift or gain drift can be elimi- registers, the serial clock line should have a pull-down resistor nated at any time by recalibrating the converter or by operating instead of the pull-up resistor shown in Figure 10 and Figure 11. the part in the background calibration mode. Using the system Read Operation calibration mode can also minimize offset and gain errors in the Data can be read from either the output register, the control signal conditioning circuitry. Integral and differential linearity register, or the calibration registers. A0 determines whether the errors are not significantly affected by temperature changes. data read accesses data from the control register or from the output/calibration registers. This A0 signal must remain valid for POWER SUPPLIES AND GROUNDING the duration of the serial read operation. With A0 high, data is The analog and digital supplies to the AD7713 are independent accessed from either the output register or from the calibration and separately pinned out to minimize coupling between the registers. With A0 low, data is accessed from the control register. analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the power supplies, The function of the DRDY line is dependent on only the output except at integer multiples of the modulator sampling frequency. update rate of the device and the reading of the output data The digital supply (DV ) must not exceed the analog positive DD register. DRDY goes low when a new data-word is available in supply (AV ) by more than 0.3 V. If separate analog and digital DD the output data register. It is reset high when the last bit of data supplies are used, the recommended decoupling scheme is shown (either 16th bit or 24th bit) is read from the output register. If in Figure 9. In systems where AV = 5 V and DV = 5 V, it is DD DD data is not read from the output register, the DRDY line will recommended that AV and DV are driven from the same 5 V DD DD remain low. The output register will continue to be updated at supply, although each supply should be decoupled separately as the output update rate, but DRDY will not indicate this. A read shown in Figure 9. It is preferable that the common supply is the from the device in this circumstance will access the most recent system’s analog 5 V supply. –18– REV. D AD7713 DRDY (O) t t 2 3 A0 (I) t t 4 5 RFS (I) t t 6 9 SCLK (O) t 8 t t 7 10 THREE-STATE SDATA (O) MSB LSB Figure 10. Self-Clocking Mode, Output Data Read Operation A0 (I) t t 14 15 TFS (I) t t t 16 9 17 SCLK (O) t t 18 10 t 19 SDATA (I) MSB LSB Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation word in the output register. If a new data-word becomes avail- Write Operation able to the output register while data is being read from the Data can be written to either the control register or calibration output register, DRDY will not indicate this and the new data- registers. In either case, the write operation is not affected by word will be lost to the user. DRDY is not affected by reading the DRDY line, and the write operation does not have any from the control register or the calibration registers. effect on the status of DRDY. A write operation to the control register or the calibration register must always write 24 bits to Data can be accessed from the output data register only when the respective register. DRDY is low. If RFS goes low with DRDY high, no data trans- fer will take place. DRDY does not have any effect on reading Figure 11 shows a write operation to the AD7713. A0 determines data from the control register or from the calibration registers. whether a write operation transfers data to the control register or to the calibration registers. This A0 signal must remain valid Figure 10 shows a timing diagram for reading from the AD7713 for the duration of the serial write operation. The falling edge of in the self-clocking mode. This read operation shows a read TFS enables the internally generated SCLK output. The serial from the AD7713’s output data register. A read from the con- data to be loaded to the AD7713 must be valid on the rising trol register or calibration registers is similar, but, in these cases, edge of this SCLK signal. Data is clocked into the AD7713 on the DRDY line is not related to the read function. Depending the rising edge of the SCLK signal, with the MSB transferred on the output update rate, it can go low at any stage in the first. On the last active high time of SCLK, the LSB is loaded to control/calibration register read cycle without affecting the read the AD7713. Subsequent to the next falling edge of SCLK, the and its status should be ignored. A read operation from either SCLK output is turned off. (The timing diagram of Figure 11 the control or calibration registers must always read 24 bits of assumes a pull-up resistor on the SCLK line.) data from the respective register. External Clocking Mode Figure 10 shows a read operation from the AD7713. For the The AD7713 is configured for its external clocking mode by timing diagram shown, it is assumed that there is a pull-up tying the MODE pin low. In this mode, SCLK of the AD7713 resistor on the SCLK output. With DRDY low, the RFS input is configured as an input, and an external serial clock must be is brought low. RFS going low enables the serial clock of the provided to this SCLK pin. This external clocking mode is AD7713 and also places the MSB of the word on the serial data designed for direct interface to systems which provide a serial line. All subsequent data bits are clocked out on a high-to-low clock output which is synchronized to the serial data output, transition of the serial clock and are valid prior to the following including microcontrollers, such as the 80C51, 87C51, rising edge of this clock. The final active falling edge of SCLK 68HC11, and 68HC05, and most digital signal processors. clocks out the LSB, and this LSB is valid prior to the final active rising edge of SCLK. Coincident with the next falling edge of Read Operation SCLK, DRDY is reset high. DRDY going high turns off the As with the self-clocking mode, data can be read from either the SCLK and the SDATA outputs, this means that the data hold output register, the control register, or the calibration registers. time for the LSB is slightly shorter than for all other bits. A0 determines whether the data read accesses data from the control register or from the output/calibration registers. This A0 REV. D –19– AD7713 DRDY (O) t t 20 21 A0 (I) t t 22 23 RFS (I) t t 26 28 SCLK (I) t t t t 24 25 27 29 THREE-STATE SDATA (O) MSB LSB Figure 12a. External Clocking Mode, Output Data Read Operation DRDY (O) t 20 A0 (I) t 22 RFS (I) t t 26 30 SCLK (I) t t t 25 t t t 27 31 24 25 24 THREE-STATE SDATA (O) MSB BIT N BIT N+1 Figure 12b. External Clocking Mode, Output Data Read (RFS Returns High During Read Operation) signal must remain valid for the duration of the serial read opera- low at any stage in the control/calibration register read cycle tion. With A0 high, data is accessed from either the output without affecting the read and its status should be ignored. A register or from the calibration registers. With A0 low, data is read operation from either the control or calibration registers accessed from the control register. must always read 24 bits of data from the respective register. The function of the DRDY line is dependent on only the output Figure 12a shows a read operation from the AD7713 where update rate of the device and the reading of the output data RFS remains low for the duration of the data-word transmis- register. DRDY goes low when a new data-word is available in sion. With DRDY low, the RFS input is brought low. The input the output data register. It is reset high when the last bit of data SCLK signal should be low between read and write operations. (either 16th bit or 24th bit) is read from the output register. If RFS going low places the MSB of the word to be read on the data is not read from the output register, the DRDY line will serial data line. All subsequent data bits are clocked out on a remain low. The output register will continue to be updated at high-to-low transition of the serial clock and are valid prior to the output update rate, but DRDY will not indicate this. A read the following rising edge of this clock. The penultimate falling from the device in this circumstance will access the most recent edge of SCLK clocks out the LSB and the final falling edge word in the output register. If a new data-word becomes avail- resets the DRDY line high. This rising edge of DRDY turns off able to the output register while data is being read from the the serial data output. output register, DRDY will not indicate this, and the new data- Figure 12b shows a timing diagram for a read operation where word will be lost to the user. DRDY is not affected by reading RFS returns high during the transmission of the word and from the control register or the calibration register. returns low again to access the rest of the data-word. Timing Data can be accessed from the output data register only when parameters and functions are very similar to that outlined for DRDY is low. If RFS goes low while DRDY is high, no data Figure 12a, but Figure 12b has a number of additional times transfer will take place. DRDY does not have any effect on read- to show timing relationships when RFS returns high in the ing data from the control register or from the calibration registers. middle of transferring a word. Figures 12a and 12b show timing diagrams for reading from the RFS should return high during a low time of SCLK. On the AD7713 in the external clocking mode. Figure 12a shows a rising edge of RFS, the SDATA output is turned off. DRDY situation where all the data is read from the AD7713 in one remains low and will remain low until all bits of the data-word read operation. Figure 12b shows a situation where the data is are read from the AD7713, regardless of the number of times read from the AD7713 over a number of read operations. Both RFS changes state during the read operation. Depending on the read operations show a read from the AD7713’s output data time between the falling edge of SCLK and the rising edge of register. A read from the control register or calibration registers RFS, the next bit (BIT N + 1) may appear on the data bus is similar, but in these cases, the DRDY line is not related to the before RFS goes high. When RFS returns low again, it activates read function. Depending on the output update rate, it can go the SDATA output. When the entire word is transmitted, the –20– REV. D AD7713 A0 (I) t t 32 33 TFS (I) t t 26 34 SCLK (I) t t 35 27 t 36 SDATA (I) LSB MSB Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation A0 (I) t 32 TFS (I) t t 26 30 SCLK (I) t 27 t 36 t 36 t t 35 35 SDATA (I) MSB BIT N BIT N+1 Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation (TFS Returns High During Write Operation) DRDY line will go high, turning off the SDATA output as per the next high level of the SCLK input. On the last active high Figure 12a. time of the SCLK input, the LSB is loaded to the AD7713. Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE Data can be written to either the control register or calibration INTERFACE registers. In either case, the write operation is not affected by In many applications, the user may not require the facility of the DRDY line, and the write operation does not have any writing to the on-chip calibration registers. In this case, the effect on the status of DRDY. A write operation to the control serial interface to the AD7713 in external clocking mode can be register or the calibration register must always write 24 bits to simplified by connecting the TFS line to the A0 input of the the respective register. AD7713 (see Figure 14). This means that any write to the Figure 13a shows a write operation to the AD7713 with TFS device will load data to the control register (since A0 is low remaining low for the duration of the write operation. A0 while TFS is low), and any read to the device will access data determines whether a write operation transfers data to the con- from the output data register or from the calibration registers trol register or to the calibration registers. This A0 signal must (since A0 is high while RFS is low). It should be noted that in remain valid for the duration of the serial write operation. As this arrangement, the user does not have the capability of read- before, the serial clock line should be low between read and ing from the control register. Another method of simplifying the write operations. The serial data to be loaded to the AD7713 interface is to generate the TFS signal from an inverted RFS must be valid on the high level of the externally applied SCLK signal. However, generating the signals the opposite way around signal. Data is clocked into the AD7713 on the high level of this (RFS from an inverted TFS) will cause writing errors. SCLK signal with the MSB transferred first. On the last active high time of SCLK, the LSB is loaded to the AD7713. RFS Figure 13b shows a timing diagram for a write operation to the AD7713 with TFS returning high during the write operation SDATA FOUR and returning low again to write the rest of the data-word. Tim- INTERFACE LINES ing parameters and functions are very similar to that outlined AD7713 SCLK for Figure 13a, but Figure 13b has a number of additional times to show timing relationships when TFS returns high in the TFS middle of transferring a word. A0 Data to be loaded to the AD7713 must be valid prior to the rising edge of the SCLK signal. TFS should return high during Figure 14. Simplified Interface with TFS Connected to A0 the low time of SCLK. After TFS returns low again, the next bit of the data-word to be loaded to the AD7713 is clocked in on REV. D –21– AD7713 MICROCOMPUTER/MICROPROCESSOR INTERFACING memory. Writing data to the serial buffer from the accumulator The AD7713’s flexible serial interface allows easy interface to will generally consist of either two or three write operations, most microcomputers and microprocessors. Figure 15 shows a depending on the size of the serial buffer. flowchart diagram for a typical programming sequence for read- The flowchart also shows the option of the bits being reversed ing data from the AD7713 to a microcomputer, while Figure 16 before being written to the serial buffer. This depends on whether shows a flowchart diagram for writing data to the AD7713. the first bit transmitted by the microprocessor is the MSB or the Figures 17 and 18 show some typical interface circuits. LSB. The AD7713 expects the MSB as the first bit in the data The flowchart in Figure 15 is for continuous read operations stream. In cases where the data is being read or being written in from the AD7713 output register. In the example shown, the bytes and the data has to be reversed, the bits will have to be DRDY line is continuously polled. Depending on the micropro- reversed for every byte. cessor configuration, the DRDY line may come to an interrupt input, in which case the DRDY will automatically generate an START interrupt without being polled. Reading the serial buffer could be anything from one read operation up to three read operations CONFIGURE AND (where 24 bits of data are read into an 8-bit serial register). A INITIALIZE �C/�P SERIAL PORT read operation to the control/calibration registers is similar, but, in this case, the status of DRDY can be ignored. The A0 line is brought low when the RFS line is brought low when reading BRING RFS,TFS AND A0 HIGH from the control register. START LOAD DATA FROM ADDRESS TO ACCUMULATOR CONFIGURE AND INITIALIZE �C/�P SERIAL PORT REVERSE ORDER OF BITS BRING RFS,TFS AND HIGH BRING RFS AND A0 LOW �3 POLL DRDY WRITE DATA FROM ACCUMULATOR TO SERIAL BUFFER BRING TFS AND A0 HIGH DRDY LOW? NO END YES Figure 16. Flowchart for Single Write Operation to the AD7713 BRING RFS LOW AD7713 to 8XC51 Interface �3 Figure 17 shows an interface between the AD7713 and the 8XC51 READ SERIAL BUFFER microcontroller. The AD7713 is configured for its external clock- ing mode, while the 8XC51 is configured in its Mode 0 serial BRING RFS HIGH interface mode. The DRDY line from the AD7713 is connected to the Port P1.2 input of the 8XC51, so the DRDY line is polled by the 8XC51. The DRDY line can be connected to the INT1 input REVERSE ORDER OF BITS of the 8XC51 if an interrupt driven system is preferred. DV DD Figure 15. Flowchart for Continuous Read Operation SYNC to the AD7713 P1.0 RFS The flowchart also shows the bits being reversed after they have P1.1 TFS been read in from the serial port. This depends on whether the P1.2 DRDY 8XC51 AD7713 microprocessor expects the MSB of the word first or the LSB of P1.3 A0 the word first. The AD7713 outputs the MSB first. P3.0 SDATA The flowchart in Figure 16 is for a single 24-bit write operation P3.1 SCLK to the AD7713 control or calibration registers. This shows data being transferred from data memory to the accumulator before MODE being written to the serial buffer. Some microprocessor systems will allow data to be written directly to the serial buffer from data Figure 17. AD7713 to 8XC51 Interface –22– REV. D AD7713 Table V shows some typical 8XC51 code used for a single 24-bit Table VI. 8XC51 Code for Writing to the AD7713 read from the output register of the AD7713. Table V shows MOV SCON,#00000000B; Configure 8051 for MODE 0 some typical code for a single write operation to the control Operation and Enable Serial register of the AD7713. The 8XC51 outputs the LSB first in a Reception write operation while the AD7713 expects the MSB first, so the MOV IE,#10010000B; Enable Transmit Interrupt data to be transmitted has to be rearranged before being written MOV IP,#00010000B; Prioritize the Transmit Interrupt to the output serial register. Similarly, the AD7713 outputs the SETB 91H; Bring TFS High MSB first during a read operation while the 8XC51 expects the SETB 90H; Bring RFS High LSB first. Therefore, the data which is read into the serial buffer MOV R1,#003H; Sets Number of Bytes to Be needs to be rearranged before the correct data-word from the Written in a Write Operation AD7713 is available in the accumulator. MOV R0,#030H; Start Address in RAM for Bytes MOV A,#00H; Clear Accumulator Table V. 8XC51 Code for Reading from the AD7713 MOV SBUF,A; Initialize the Serial Port MOV SCON,#00010001B; Configure 8051 for MODE 0 WAIT: MOV IE,#00010000B; Disable All Interrupts JMP WAIT; Wait for Interrupt SETB 90H; Set P1.0, Used as RFS INT ROUTINE: SETB 91H; Set P1.1, Used as TFS NOP; Interrupt Subroutine SETB 93H; Set P1.3, Used as A0 MOV A,R1; Load R1 to Accumulator MOV R1,#003H; Sets Number of Bytes to Be Read JZ FIN; If Zero Jump to FIN in A Read Operation DEC R1; Decrement R1 Byte Counter MOV R0,#030H; Start Address for Where Bytes MOV A,@R; Move Byte into the Accumulator Will Be Loaded INC R0; Increment Address MOV R6,#004H; Use P1.2 as DRDY RLC A; Rearrange Data—From LSB WAIT: First to MSB First NOP; MOV B.0,C; RLC A; MOV B.1,C; RLC A; MOV A,P1; Read Port 1 MOV B.2,C; RLC A; MOV B.3,C; RLC A; ANL A,R6; Mask Out All Bits Except DRDY MOV B.4,C; RLC A; MOV B.5,C; RLC A; JZ READ; If Zero Read MOV B.6,C; RLC A: MOV B.7,C; MOV A,B; SJMP WAIT; Otherwise Keep Polling CLR 93H; Bring A0 Low READ: CLR 91H; Bring TFS Low CLR 90H; Bring RFS Low MOV SBUF,A; Write to Serial Port CLR 98H; Clear Receive Flag RETI; Return from Subroutine POLL: FIN: JB 98H, READ1 Tests Receive Interrupt Flag SETB 91H; Set TFS High SJMP POLL SETB 93H; Set A0 High READ 1: RETI; Return from Interrupt Subroutine MOV A,SBUF; Read Buffer AD7713 to 68HC11 Interface RLC A; Rearrange Data Figure 18 shows an interface between the AD7713 and the MOV B.0,C; Reverse Order of Bits 68HC11 microcontroller. The AD7713 is configured for its exter- RLC A; MOV B.1,C; RLC A; MOV B.2,C; nal clocking mode, while the SPI port is used on the 68HC11, RLC A; MOV B.3,C; RLC A; MOV B.4,C; which is in its single chip mode. The DRDY line from the AD7713 RLC A; MOV B.5,C; RLC A; MOV B.6,C; is connected to the Port PC2 input of the 68HC11, so the DRDY RLC A; MOV B.7,C; line is polled by the 68HC11. The DRDY line can be connected to MOV A,B; the IRQ input of the 68HC11 if an interrupt driven system is MOV @R0,A; Write Data to Memory preferred. The 68HC11 MOSI and MISO lines should be config- INC R0; Increment Memory Location ured for wired-OR operation. Depending on the interface DEC R1 Decrement Byte Counter configuration, it may be necessary to provide bidirectional buffers MOV A,R1 between the 68HC11 MOSI and MISO lines. JZ END Jump if Zero The 68HC11 is configured in the master mode with its CPOL JMP WAIT Fetch Next Byte bit set to a Logic 0 and its CPHA bit set to a Logic 1. END: SETB 90H Bring RFS High FIN: SJMP FIN REV. D –23– AD7713 DV DV DD DD 3-Wire RTD Configurations Figure 20 shows a 3-wire RTD configuration using the AD7713. SS SYNC In the 3-wire configuration, the lead resistances will result in errors if only one current source is used as the 200 µA will flow PC0 RFS through RL1 developing a voltage error between AIN1(+) and PC1 TFS AIN1(–). In the scheme outlined below, the second RTD cur- PC2 DRDY rent source is used to compensate for the error introduced by 68HC11 AD7713 PC3 A0 the 200 µA flowing through RL1. The second RTD current flows through RL2. Assuming RL1 and RL2 are equal (the leads SCK SCLK would normally be of the same material and of equal length) and MISO SDATA RTD1 and RTD2 match, then the error voltage across RL2 equals MOSI MODE the error voltage across RL1, and no error voltage is developed between AIN1(+) and AIN1(–). Twice the voltage is developed across RL3 but since this is a common-mode voltage, it will not Figure 18. AD7713 to 68HC11 Interface introduce any errors. The reference voltage is derived from one of the current sources. This gives all the benefits of eliminating APPLICATIONS RTD temperature coefficient errors as outlined in Figure 19. 4-Wire RTD Configurations The voltage on either RTD input can go to within 2 V of the Figure 19 shows a 4-wire RTD application where the RTD AV supply. The circuit is shown for a 2.5 V reference. DD transducer is interfaced directly to the AD7713. In the 4-wire configuration, there are no errors associated with lead resis- tances as no current flows in the measurement leads connected AV DV DD DD REF IN(–) REF IN(+) to AIN1(+) and AIN1(–). One of the RTD current sources is used to provide the excitation current for the RTD. A common 200�A RTD1 nominal resistance value for the RTD is 100 Ω and, therefore, the RTD will generate a 20 mV signal, which can be handled directly 12.5k� by the analog input of the AD7713. In the circuit shown, the INTERNAL R AIN(+) L1 CIRCUITRY second RTD excitation current is used to generate the reference PGA AIN(–) voltage for the AD7713. This reference voltage is developed RTD A = 1 – 128 across R and applied to the differential reference inputs. For REF R RTD2 L2 the nominal reference voltage of 2.5 V, R is 12.5 kΩ. This REF 200�A R AGND scheme ensures that the analog input voltage span remains L3 AD7713 ratiometric to the reference voltage. Any errors in the analog input voltage due to the temperature drift of the RTD current DGND source is compensated for by the variation in the reference volt- Figure 20. 3-Wire RTD Application with the AD7713 age. The typical matching between the two RTD current sources is less than 3 ppm/°C. 4–20 mA Loop The AD7713’s high level input can be used to measure the 5V current in 4–20 mA loop applications as shown in Figure 21. In AV DV DD DD this case, the system calibration capabilities of the AD7713 can be used to remove the offset caused by the 4 mA flowing through 200�A RTD2 the 500 Ω resistor. The AD7713 can handle an input span as AD7713 low as 3.2 � V (= 8 V with a V of 2.5 V) even though the REF REF REF IN(+) nominal input voltage range for the input is 10 V. Therefore, INTERNAL the full span of the ADC can be used for measuring the current R REF CIRCUITRY REF IN(–) between 4 and 20 mA. 200�A ANALOG 5V SUPPLY RTD1 REF IN(–) REF IN(+) AV DV DD DD AIN1(+) AV DD RTD PGA 1�A AIN1(–) INTERNAL A = 1 – 128 CIRCUITRY AGND AIN1(+) PGA AIN1(–) A = 1 – 128 DGND AIN3 VOLTAGE ATTENUATION AD7713 4–20mA 500� Figure 19. 4-Wire RTD Application with the AD7713 LOOP AGND DGND Figure 21. 4-20 mA Measurement Using the AD7713 –24– REV. D MUX AD7713 OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 FUNCTIONAL BLOCK DIAGRAM FEATURES REF REF Charge Balancing AV DV V REF OUT DD DD IN(–) IN(+) BIAS 24 Bits No Missing Codes AV DD �0.0015% Nonlinearity 2.5V REFERENCE 2-Channel Programmable Gain Front End 4.5�A Gains from 1 to 128 CHARGING BALANCING A/D CONVERTER Differential Inputs AUTO-ZEROED Low-Pass Filter with Programmable Filter Cutoffs AIN1(+) DIGITAL SYNC �–� FILTER Ability to Read/Write Calibration Coefficients AIN1(–) MODULATOR PGA AIN2(+) Bidirectional Microcontroller Serial Interface MCLK AIN2(–) Internal/External Reference Option A = 1 – 128 IN CLOCK AV DD GENERATION Single- or Dual-Supply Operation MCLK OUT Low Power (25 mW typ) with Power-Down Mode 20�A SERIAL INTERFACE (7 mW typ) CONTROL OUTPUT REGISTER REGISTER RTD APPLICATIONS CURRENT Weigh Scales AD7710 Thermocouples AGND DGND V RFS TFS MODE SDATA SCLK DRDY A0 Smart Transmitters SS Chromatography AD7711 FUNCTIONAL BLOCK DIAGRAM FEATURES REF REF Charge Balancing ADC AV DV V REF OUT DD DD IN(–) IN(+) BIAS 24 Bits No Missing Codes AV DD �0.0015% Nonlinearity 2.5V REFERENCE 2-Channel Programmable Gain Front End 4.5�A Gains from 1 to 128 CHARGING BALANCING A/D CONVERTER 1 Differential Input AUTO-ZEROED 1 Single-Ended Input AIN1(+) DIGITAL SYNC �–� FILTER Low-Pass Filter with Programmable Filter Cutoff AIN1(–) PGA MODULATOR AIN2 Ability to Read/Write Calibration Coefficients A = 1 – 128 MCLK RTD Excitation Current Sources IN CLOCK 200�A AV DD GENERATION Bidirectional Microcontroller Serial Interface MCLK OUT RTD1 Internal/External Reference Option SERIAL INTERFACE Single- or Dual-Supply Operation 200�A CONTROL OUTPUT Low Power (25 mW typ) with Power-Down Mode REGISTER REGISTER RTD2 (7 mW typ) AD7711 APPLICATIONS AGND DGND V RFS TFS MODE SDATA SCLK DRDY A0 RTD Transducers SS Process Control Smart Transmitters Portable Industrial Instruments REV. D –25– MUX MUX AD7713 AD7712 FUNCTIONAL BLOCK DIAGRAM FEATURES REF REF Charge Balancing ADC AV DV V REF OUT DD DD IN(–) IN(+) BIAS 24 Bits No Missing Codes AV DD �0.0015% Nonlinearity 2.5V REFERENCE High Level and Low Level Analog Input Channels 4.5�A Programmable Gain for Both Inputs CHARGING BALANCING A/D CONVERTER Gains from 1 to 128 AUTO-ZEROED Differential Input for Low Level Channel AIN1(+) DIGITAL SYNC �–� FILTER Low-Pass Filter with Programmable Filter Cutoffs AIN1(–) PGA MODULATOR STANDBY Ability to Read/Write Calibration Coefficients A = 1 – 128 MCLK Bidirectional Microcontroller Serial Interface CLOCK IN GENERATION Internal/External Reference Option MCLK VOLTAGE OUT AIN2 Single- or Dual-Supply Operation ATTENUATION SERIAL INTERFACE Low Power (25 mW typ) with Power-Down Mode CONTROL OUTPUT (100 �W typ) REGISTER REGISTER TP APPLICATIONS AD7712 Process Control AGND DGND V RFS TFS MODE SDATA SCLK DRDY A0 Smart Transmitters SS Portable Industrial Instruments –26– REV. D MUX AD7713 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1.185 (30.01) 0.295 (7.49) 1.165 (29.59) 0.285 (7.24) 1.145 (29.08) 0.275 (6.99) 24 13 1 12 0.325 (8.26) 0.310 (7.87) 0.180 0.300 (7.62) 0.015 (0.38) MIN (4.57) 0.150 (3.81) MAX 0.135 (3.43) 0.120 (3.05) 0.150 (3.81) 0.130 (3.30) 0.015 (0.38) 0.100 0.022 (0.56) 0.060 (1.52) SEATING 0.110 (2.79) 0.010 (0.25) (2.54) PLANE 0.018 (0.46) 0.050 (1.27) 0.008 (0.20) BSC 0.014 (0.36) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MO-095AG CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) 0.098 (2.49) 0.005 (0.13) MAX 0.310 (7.87) MIN 0.220 (5.59) 24 13 PIN 1 112 0.060 (1.52) 0.320 (8.13) 0.200 (5.08) 0.015 (0.38) 1.280 (32.51) MAX MAX 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 0.200 (5.08) 15 0 0.125 (3.18) SEATING 0.100 0.070 (1.78) PLANE (2.54) 0.030 (0.76) 0.023 (0.58) BSC 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24) Dimensions shown in millimeters and (inches) 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 12 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) � 45� 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8� 1.27 (0.0500) 0.51 (0.0201) SEATING 0� 1.27 (0.0500) 0.33 (0.0130) COPLANARITY BSC PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) 0.10 COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. D –27– AD7713 Revision History Location Page 3/04—Data Sheet changed from REV. C to REV. D. Updated layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to Self-Calibration section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Changes to AD7713 to 68HC11 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Deleted AD7713 to ADSP-2105 Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Deleted Figure 19 and renumbered succeeding figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 –28– REV. D C01553–0–3/04(D)