ANALOG DEVICES AD7709

16-Bit �-� ADC with a Switchable Current Sources AD7709 FEATURES APPLICATIONS 16-Bit �-� ADC Sensor Measurement Programmable Gain Front End Temperature Measurement Simultaneous 50 Hz and 60 Hz Rejection at 20 Hz Pressure Measurements Update Rate Weigh Scales VREF Select™ Allows Absolute and Ratiometric Portable Instrumentation Measurement Capability 4–20 mA Loops ISOURCE Select™ GENERAL DESCRIPTION 16-Bit No Missing Codes The AD7709 is a complete analog front end for low frequency 13-Bit p-p Resolution @ 20 Hz, 20 mV Range measurement applications. It contains a 16-bit �-� ADC, selectable 16-Bit p-p Resolution @ 20 Hz, 2.56 V Range reference inputs, three switchable matched excitation current INTERFACE sources, low-side power switches, and a digital I/O port. The 3-Wire Serial 16-bit channel with PGA accepts fully differential, unipolar, ® SPI , QSPI™, MICROWIRE™, and DSP Compatible and bipolar input signal ranges from 1.024 � REFIN/128 to Schmitt Trigger on SCLK 1.024 � REFIN. It can be configured as two fully differential input channels or four pseudo-differential input channels. Signals POWER can be converted directly from a transducer without the need for Specified for Single 3 V and 5 V Operation signal conditioning. Normal: 1.25 mA Typ @ 3 V The device operates from a 32.768 kHz crystal with an on-chip Power-Down: 7 �A (32.768 kHz Crystal Running) PLL generating the required internal operating frequency. The ON-CHIP FUNCTIONS output data rate from the part is software programmable. The Rail-to-Rail Input Buffer and PGA p-p resolution from the part varies with the programmed gain Selectable Reference Inputs and output data rate. 3 Switchable, Ratioed Current Sources for The part operates from a single 3 V or 5 V supply. When V Measurements BE operating from 3 V supplies, the power dissipation for the part 4-Bit Digital I/O Port is 3.75 mW. The AD7709 is housed in a 24-lead TSSOP package. Low-Side Power Switches FUNCTIONAL BLOCK DIAGRAM REFIN1(+) REFIN2(+) REFIN1(–) REFIN2(–) XTAL1 XTAL2 V DD IEXC1 IEXC2 IEXC3 OSCILLATOR 8I 8I I AND IOUT1 PLL DOUT DIN I = 25�A SERIAL IOUT2 INTERFACE SCLK AND AIN1 CS CONTROL AIN2 LOGIC RDY PGA 16-BIT �-� ADC BUF AIN3/P3 MUX V RESET DD AIN4/P4 AINCOM I/O PORT AD7709 V GND PWRGND P1/SW1 P2/SW2 DD REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD7709 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MICROCOMPUTER/MICROPROCESSOR GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 AD7709-to-68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 21 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 AD7709-to-8051 Interface . . . . . . . . . . . . . . . . . . . . . . . . 21 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 6 AD7709-to-ADSP-2103/ADSP-2105 Interface . . . . . . . . 21 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 22 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 23 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . 23 TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10 Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . . 11 Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 S-D ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 14 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 26 ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . 18 3-Wire RTD Configurations . . . . . . . . . . . . . . . . . . . . . . 27 CONFIGURING THE AD7709 . . . . . . . . . . . . . . . . . . . . . 19 Smart Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 –2– REV. A AD7709 (V = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 = 1 DD SPECIFICATIONS 32.768 kHz Crystal; all specifications T to T , unless otherwise noted.) MIN MAX Parameter AD7709A, AD7709B Unit Test Conditions ADC CHANNEL SPECIFICATION Output Update Rate 5.4 Hz min 0.732 ms Increments 105 Hz max ADC CHANNEL 2 No Missing Codes 16 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate 16 Bits p-p ±2.56 V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables II to V 21 ¥ .024 REFIN 2 Integral Nonlinearity ±30 ppm of FSR max Typically 2 ppm FSR = GAIN Offset Error ±3 mV typ Offset Error Drift vs. Temperature ±10 nV/∞C typ 3 Full-Scale Error ±0.75 LSB typ B Grade, V = 4 V DD ±0.2 % of FS typ A Grade Gain Drift vs. Temperature ±0.5 ppm/∞C typ Power Supply Rejection (PSR) 85 dB typ Input Range = ±2.56 V 100 dB typ on ±20 mV Range ANALOG INPUTS ±¥ 1.024 REFIN V nom REFIN = REFIN(+) – REFIN(–) Differential Input Voltage Ranges GAIN GAIN = 1 to 128 ADC Range Matching ±2 mV typ Input Voltage = 19 mV on All Ranges 2 Absolute AIN1–AIN4 Voltage Limits GND + 100 mV V min V – 100 mV V max DD AIN1–AIN4 Analog Input Current 2 DC Input Current ±1 nA max DC Input Current Drift ±5 pA /∞C typ 2 Absolute AINCOM Voltage Limits GND – 30 mV V min V + 30 mV V max DD AINCOM Analog Input Current Pseudo-Differential Mode of Operation DC Input Current ±125 nA/V typ Input Current Varies with Input Range DC Input Current Drift ±2 pA/V/∞C typ 2, 4 Normal-Mode Rejection @ 50 Hz 100 dB min 50 Hz ± 1Hz, 16.65 Hz Update Rate, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68 Common-Mode Rejection @ DC 100 dB typ Input Range = ±2.56 V, AIN = 1 V 110 dB typ on ±20 mV Range 2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V 2 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V REFERENCE INPUTS (REFIN1 and REFIN2) REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) 2 REFIN Voltage Range 1V min V V max DD 2 Absolute REFIN Voltage Limits GND – 30 mV V min V + 30 mV V max DD Average Reference Input Current 0.5 mA/V typ Average Reference Input Current Drift ±0.01 nA/V/∞C typ 2, 4 Normal-Mode Rejection @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF = 68 Common-Mode Rejection @ DC 110 dB typ Input Range = ±2.56 V, AIN = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, Range = 2.56 V, AIN = 1 V See Notes on page 5. REV. A –3– AD7709 (continued) SPECIFICATIONS Parameter AD7709A, AD7709B Unit Test Conditions EXCITATION CURRENT SOURCES (IEXC1, IEXC2, and IEXC3) Output Current IEXC1, IEXC2 200 mA nom IEXC3 25 mA nom Initial Tolerance at 25∞C ±10 % typ Drift 200 ppm/∞C typ Initial Current Matching at 25∞C ±2.5 % max B Grade, No Load (between IEXC1 and IEXC2) ±2.5 % typ A Grade, No Load Drift Matching (between IEXC1 and IEXC2) 20 ppm/∞C typ Initial Current Matching at 25∞C ±5% max B Grade, No Load (between 8 � IEXC3 and IEXC1/IEXC2) ±5% typ A Grade, No Load Drift Matching (between 8 � IEXC3 and IEXC1/IEXC2) 20 ppm/∞C typ Line Regulation V = 5 V ± 5% DD IEXC1, IEXC2 1.25 mA/V typ A, B Grades 2.6 mA/V max B Grade IEXC3 1 mA/V max B Grade 1 mA/V typ A Grade Load Regulation 300 nA/V typ Output Compliance V – 0.6 V max DD GND –30 mV V min LOW-SIDE POWER SWITCHES (SW1 and SW2) R 3 W typ V = 5 V, A and B Grade ON DD 5 W max B Grade 4.5 W typ V = 3 V, A and B Grade DD 7 W max B Grade 2 Allowable Current 20 mA max Continuous Current per Switch LOGIC INPUTS 2 All Inputs Except SCLK and XTAL1 V , Input Low Voltage 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD V , Input High Voltage 2.0 V min V = 3 V or 5 V INH DD 2 SCLK Only (Schmitt-Triggered Input) V 1.4/2 V min/V max V = 5 V T(+) DD V 0.8/1.4 V min/V max V = 5 V T(–) DD V – V 0.3/0.85 V min/V max V = 5 V T(+) T(–) DD V 0.95/2 V min/V max V = 3 V T(+) DD V 0.4/1.1 V min/V max V = 3 V T(–) DD – V 0.3/0.85 V min/V max V = 3 V V T(+) T(–) DD 2 XTAL1 Only V , Input Low Voltage 0.8 V max V = 5 V INL DD V , Input High Voltage 3.5 V min V = 5 V INH DD V , Input Low Voltage 0.4 V max V = 3 V INL DD V , Input High Voltage 2.5 V min V = 3 V INH DD Input Currents (except XTAL) ±2 mA max V = V IN DD –70 mA max V = GND, Typically –40 mA @ 5 V and IN –20 mA at 3 V; Weak Pull-Ups on the Logic Inputs Input Capacitance 10 pF typ All Digital Inputs –4– REV. A AD7709 Parameter AD7709A, AD7709BUnit Test Conditions LOGIC OUTPUTS (Excluding XTAL2) 2 V , Output High Voltage V – 0.6 V min V = 3 V, I = 100 mA OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 3 V, I = 100 mA OL DD SINK 2 V , Output High Voltage 4V min V = 5 V, I = 200 mA OH DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 5 V, I = 1.6 mA OL DD SINK Floating-State Leakage Current ±10 mA max Floating-State Output Capacitance ±10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode I/O PORT 2 V , Input Low Voltage 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD 2 V , Input High Voltage 2.0 V min V = 3 V or 5 V INH DD Input Currents ±2 mA max V = V IN DD –70 mA max V = GND, Typically –40 mA @ V = 5 V IN DD and –20 mA at V = 3 V; Weak Pull-Ups on DD the Logic Inputs Input Capacitance 10 pF typ All Digital Inputs 2 V , Output High Voltage V – 0.6 V min V = 3 V, I = 100 mA OH DD DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 3 V, I = 100 mA OL DD SINK 2 V , Output High Voltage 4V min V = 5 V, I = 200 mA OH DD SOURCE 2 V , Output Low Voltage 0.4 V max V = 5 V, I = 1.6 mA OL DD SINK Floating-State Output Leakage Current ±10 mA max Floating-State Output Capacitance ±10 pF typ START-UP TIME From Power-On 300 ms typ From Standby Mode 1 ms typ OSCPD = 0 From Power-Down Mode 300 ms typ OSCPD = 1 POWER REQUIREMENTS Power Supply Voltage V – GND 2.7/3.6 V min/max V = 3 V nom DD DD = 5 V nom 4.75/5.25 V min/max V DD Power Supply Currents I Current 1.5 mA max V = 3 V, 1.25 mA typ DD DD 1.75 mA max V = 5 V, 1.45 mA typ DD I (Low Power Mode) 7 mA max B Grade, V = 3 V, Standby Mode DD DD 7 mA typ A Grade, V = 3 V, Standby Mode DD 1.5 mA max B Grade, V = 3 V, Power-Down Mode DD 1.5 mA typ A Grade, V = 3 V, Power-Down Mode DD 26 mA max B Grade, V = 5 V, Standby Mode DD 26 mA typ A Grade, V = 5 V, Standby Mode DD 6.5 mA max B Grade, V = 5 V, Power-Down Mode DD 6.5 mA typ A Grade, V = 5 V, Power-Down Mode DD 5 I for One Conversion Second 107 mA typ V = 3 V, Standby Mode DD DD 5 134 mA typ V = 5 V, Standby Mode DD NOTES 1 Temperature Range –40∞C to +85∞C. 2 Guaranteed by design and/or characterization data on production release. 3 Full-scale error applies to both positive and negative full scale. 4 Simultaneous 50 Hz and 60 Hz rejection is achieved using 19.79 Hz update rate. Normal mode rejection in this case is 60 dB min. 5 When the part is placed in power-down mode for a single conversion/second, at an update rate of 19.79 Hz, the current consumption is higher compared to when the part is placed in standby mode as the crystal oscillator takes approximately 100 ms to begin clocking. The device will, therefore, use full current for the conversion time and the 100 ms period required for the oscillator to begin clocking. However, if the conversion rate is lower, the current consumption will be reduced so that it is worthwhile to use the power-down rather than the standby mode. Specifications subject to change without notice. REV. A –5– AD7709 (V = 2.7 V to 3.6 V or V = 4.75 V to 5.25 V; GND = 0 V; X = 32.768 kHz; Input Logic 0 = 0 V, DD DD TAL 1, 2 TIMING CHARACTERISTICS Logic 1 = V unless otherwise noted.) DD Limit at T , T MIN MAX Parameter (A, B Version) Unit Conditions/Comments t 30.5176 ms typ Crystal Oscillator Period 1 t 50 ns min RESET Pulsewidth 2 Read Operation 0 ns min RDY to CS Setup Time t 3 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 4 4 3 t 0 ns min SCLK Active Edge to Data Valid Delay 5 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.7 V to 3.6 V DD 4, 5 t 0 ns min CS Falling Edge to Data Valid Delay 5A = 4.75 V to 5.25 V 60 ns max V DD 80 ns max V = 2.7 V to 3.6 V DD t 100 ns min SCLK High Pulsewidth 6 100 ns min SCLK Low Pulsewidth t 7 3 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 8 6 3 t 10 ns min Bus Relinquish Time after SCLK Inactive Edge 9 80 ns max 3, 7 t 100 ns max SCLK Active Edge to RDY High 10 Write Operation 3 0 ns min CS Falling Edge to SCLK Active Edge Setup Time t 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 100 ns min SCLK High Pulsewidth t 14 t 100 ns min SCLK Low Pulsewidth 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DD 2 See Figures 2 and 3. 3 SCLK active edge is falling edge of SCLK. 4 These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5 This specification comes into play only if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics table are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 RDY returns high after a read of the ADC. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. –6– REV. A AD7709 I (1.6mA WITH V = 5V SINK DD 100�A WITH V = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200�A WITH V = 5V SOURCE DD 100�A WITH V = 3V) DD Figure 1. Load Circuit for Timing Characterization CS t 11 t t 14 16 SCLK t 15 t 12 t 13 DIN MSB LSB Figure 2. Write Cycle Timing Diagram RDY t t 3 10 CS t 8 t t 4 6 SCLK t 7 t 5 t 9 t 5A DOUT MSB LSB Figure 3. Read Cycle Timing Diagram REV. A –7– AD7709 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (T = 25∞C, unless otherwise noted.) A V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD 1 IOUT1 24 XTAL1 PWRGND to AGND . . . . . . . . . . . . . . –20 mV to +20 mV 2 IOUT2 23 XTAL2 Analog Input Voltage to GND . . . . . –0.3 V to V + 0.3 V DD V REFIN1(+) 3 22 DD Reference Input Voltage to GND . . . –0.3 V to V + 0.3 V DD REFIN1(–) 4 21 GND Total AIN/REFIN Current (Indefinite) . . . . . . . . . . 30 mA 20 AIN1 5 DIN AD7709 Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V DD 6 AIN2 19 DOUT TOP VIEW Digital Output Voltage to GND . . . . –0.3 V to V + 0.3 V DD (Not to Scale) 18 AIN3/P3 7 RDY Operating Temperature Range . . . . . . . . . . –40∞C to +85∞C 8 17 AIN4/P4 CS Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C 9 16 AINCOM SCLK Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C REFIN2(+) 10 15 RESET q Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9∞C/W JA 11 14 REFIN2(–) P1/SW1 q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14∞C/W JC 12 13 P2/SW2 PWRGND Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option AD7709ARU –40∞C to +85∞C TSSOP RU-24 AD7709BRU –40∞C to +85∞C TSSOP RU-24 EVAL-AD7709EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7709 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended ESD SENSITIVE DEVICE to avoid performance degradation or loss of functionality. –8– REV. A AD7709 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 IOUT1 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina- tion of the current sources, can be switched to this output. 2 IOUT2 Output for Internal Excitation Current Source. Either current source IEXC1, IEXC2, IEXC3, or a combina- tion of the current sources, can be switched to this output. 3 REFIN1(+) Positive Reference Input. REFIN1(+) can lie anywhere between V and GND + 1 V. The nominal refer- DD ence voltage (REFIN1(+) – REFIN1(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V . DD 4 REFIN1(–) Negative Reference Input. This reference input can lie anywhere between GND and V – 1 V. DD 5 AIN1 Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully differential input pair when used with AIN2. 6 AIN2 Analog Input. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully differential input pair when used with AIN1. 7 AIN3/P3 Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the positive input of a fully differential input pair when used with AIN4. This pin can also be programmed as a general-purpose digital input bit. 8 AIN4/P4 Analog Input/Digital Port Bit. Programmable gain input that can be used as a pseudo-differential input when used with AINCOM or as the negative input of a fully-differential input pair when used with AIN3. This pin can also be programmed as a general-purpose digital input bit. 9 AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode. 10 REFIN2(+) Positive Reference Input. REFIN2(+) can lie anywhere between V and GND + 1 V. The nominal reference DD voltage (REFIN2(+) – REFIN2(–)) is 2.5 V, but the part is functional with a reference range from 1 V to V . DD 11 REFIN2(–) Negative Reference Input. This reference input can lie anywhere between GND and V – 1 V. DD 12 P2/SW2 Dual-Purpose Pin. It can act as a general-purpose output (P2) bit or as a low-side power switch (SW2) to PWRGND. 13 PWRGND Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to GND. 14 P1/SW1 Dual-Purpose Pin. It can act as a general-purpose output (P1) bit or as a low-side power switch (SW1) to PWRGND. 15 RESET Digital Input Used to Reset the ADC to Its Power-On-Reset Status. This pin has a weak pull-up internally to V . DD 16 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7709 in smaller batches of data. A weak pull-up to V is provided on the DD SCLK input. 17 CS Chip Select Input. This is an active low logic input used to select the AD7709. CS can be used to select the AD7709 in systems with more than one device on the serial bus or as a frame synchronization signal in com- municating with the device. CS can be hardwired low allowing the AD7709 to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to V is provided on the CS input. DD 18 RDY RDY is a Logic Low Status Output from the AD7709. RDY is low if the ADC has valid data in its data register. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update indicating to the user that a read operation should not be initiated. 19 DOUT Serial Data Output Accessing the Output Shift Register of the AD7709. The output shift register can contain data from any of the on-chip data or control registers. 20 DIN Serial Data Input Accessing the Input Shift Register on the AD7709. Data in this shift register is transferred to the control registers within the ADC, the selection bits of the communications register selecting which control register. A weak pull-up to V is provided on the DIN input. DD 21 GND Ground Reference Point for the AD7709 22 V Supply Voltage, 3 V or 5 V Nominal DD 23 XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter 24 XTAL1 Input to the 32.768 kHz Crystal Oscillator Inverter REV. A –9– AD7709–Typical Performance Characteristics 32772 700 V = 5V DD INPUT RANGE = �20mV 32771 600 UPDATE RATE = 19.79Hz 32770 500 32769 400 32768 300 32767 200 32766 100 V = 2.5V 32765 REF T = 25 C A 32764 0 0 100 200 300 400 500 600 700 800 900 1000 32766 32767 32768 32769 32770 32771 READING NUMBER CODE TPC 1. Typical Noise Plot on ±20 mV Input Range TPC 3. Noise Histogram 3.0 V = 5V DD T = 25�C A �2.56V RANGE 2.5 V DD 2.0 V = 5V DD V = 2.5V REF 1.5 OSCILLATOR INPUT RANGE = �2.56V UPDATE RATE = 19.79Hz T = 25�C A �20mV RANGE 1.0 TIME BASE = 100ms/DIV TRACE 1 = TRACE 2 = 2V/DIV 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V – V REF TPC 2. RMS Noise vs. Reference Input TPC 4. Typical Oscillator Power-Up –10– REV. A CODE READ RMS NOISE – �V OCCURRENCE AD7709 ADC CIRCUIT INFORMATION word from the filter is summed and averaged with the previous Overview filter output to produce a new valid output result to be written to The AD7709 incorporates a �-� ADC channel with on-chip digital the ADC data register. filtering intended for the measurement of wide dynamic range, low The input chopping is incorporated into the input multiplexer frequency signals such as those in weigh-scale, strain-gauge, while the output chopping is accomplished by an XOR gate at pressure transducer, or temperature measurement applications. the output of the modulator. The chopped modulator bit stream 3 3 is applied to a Sinc filter. The programming of the Sinc deci- �-� ADC mation factor is restricted to an 8-bit register SF, the actual This channel can be programmed to have one of eight input decimation factor is the register value × 8. The decimated out- voltage ranges from ±20 mV to ±2.56 V. This channel can be 3 put rate from the Sinc filter (and the ADC conversion rate) will configured as either two fully differential inputs (AIN1/AIN2 therefore be: and AIN3/AIN4) or four pseudo-differential input channels (AIN1/AINCOM, AIN2/AINCOM, AIN3/AINCOM, and 1  1  f =× × f AIN4/AINCOM). Buffering the input channel means that the ADC   MOD 3 8 × SF   part can accommodate significant source impedances on the analog input and that R, C filtering (for noise rejection or RFI where: reduction) can be placed on the analog inputs if required. f is the ADC update rate. ADC The ADC employs a �-� conversion technique to realize up to SF is the decimal equivalent of the word loaded to the 16 bits of no-missing-codes performance. The �-� modulator filter register. converts the sampled input signal into a digital pulse train whose 3 duty cycle contains the digital information. A Sinc programmable f is the modulator sampling rate of 32.768 kHz. MOD low-pass filter is then employed to decimate the modulator output Programming the filter register determines the update rate for the data stream to give a valid data conversion result at programmable ADC. The chop rate of the channel is half the output data rate. output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). The frequency response of the filter H(f ) is as follows: A chopping scheme is also employed to minimize ADC channel offset errors. A block diagram of the ADC input channel is shown 3  1 sin (SF×× 8 π× f / f )  in Figure 4. MOD × ×   SF × 8 sin (π × f/f )   MOD The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. The integrator in  1 sin (2×× π f/f )  OUT × the modulator shapes the quantization noise (which results from   2 sin (π × f/f )  OUT  the analog-to-digital conversion) so that the noise is pushed toward one-half of the modulator frequency. The output of the where: �-� modulator feeds directly into the digital filter. The digital filter then band-limits the response to a frequency significantly f = 32,768 Hz. MOD lower than one-half of the modulator frequency. In this manner, SF = value programmed into Filter Register. the 1-bit output of the comparator is translated into a band- f = f /(SF � 8 � 3) OUT MOD limited, low noise output from the AD7709 ADC. The AD7709 3 3 filter is a low-pass, Sinc , or (SIN(x)/x) filter whose primary The following shows plots of the filter frequency response for the function is to remove the quantization noise introduced at the SF words shown in Table I. The overall frequency response is the 3 3 modulator. The cutoff frequency and decimated output data product of a Sinc and a sinc response. There are Sinc notches rate of the filter are programmable via the SF word loaded to the at integer multiples of 3 � f , and there are sinc notches at odd ADC filter register. integer multiples of f /2. The 3 dB frequency for all values of SF ADC obeys the following equation: A chopping scheme is employed where the complete signal chain is chopped, resulting in excellent dc offset and offset drift speci- fd30 B=× .24 f () ADC fications, and is extremely beneficial in applications where drift, The signal chain is chopped as shown in Figure 4. The chop noise rejection, and optimum EMI rejection are important fac- frequency is: tors. With chopping, the ADC repeatedly reverses its inputs. 3 The decimated digital output words from the Sinc filters there-  f  ADC f = fore have a positive offset and negative offset term included. As a CHOP   2   result, a final summing stage is included so that each output f f f f f CHOP IN MOD CHOP ADC �-� 3 ANALOG 1 1 DIGITAL MUX PGA XOR 3 � (8 � SF ) � BUF � ( ) INPUT 2 OUTPUT 8 � SF MOD 3 SINC FILTER A + V OS IN A – V IN OS Figure 4. ADC Channel Block Diagram REV. A –11– AD7709 3 As shown in the block diagram, the Sinc filter outputs alternately Table I. ADC Conversion and Settling Times for Various contain +V and –V , where V is the respective channel offset. SF Words OS OS OS This offset is removed by performing a running average of 2, which Data Update Rate Settling Time means that the settling time to any change in programming of SF Word f (Hz) t (ms) ADC SETTLE the ADC will be twice the normal conversion time, while an asynchronous step change on the analog input will not be fully 13 105.3 19.04 reflected until the third subsequent output. 69 (Default) 19.79 101.07 255 5.35 373.54 Ê 2 ˆ t = =¥ 2 t SETTLE Á ˜ ADC Normal mode rejection is the major function of the digital filter Ë f ¯ ADC on the AD7709. The normal mode 50 ± 1 Hz rejection with an The allowable range for SF is 13 to 255, with a default of 69 SF word of 82 is typically –100 dB. The 60 ± 1 Hz rejection with (45H). The corresponding conversion rates, conversion times, SF = 68 is typically –100 dB. Simultaneous 50 Hz and 60 Hz and settling times are shown in Table I. Note that the conver- rejection of better than 60 dB is achieved with an SF of 69. sion time increases by 0.732 ms for each increment in SF. Choosing an SF word of 69 places notches at both 50 Hz and 60 Hz. Figures 5 to 8 show the filter rejection for a selection of SF words. 0 0 –20 –20 –40 –60 –40 –80 –60 –100 –80 –120 –100 –140 –160 –120 –180 –140 –200 450 500 550 600 650 700 0 50 100 150 200 250 300 350 400 –160 FREQUENCY – Hz 0 10 20 30 40 50 60 70 80 90 100 SF = 13 FREQUENCY – Hz OUTPUT DATA RATE = 105Hz SF = 69 INPUT BANDWIDTH = 25.2Hz OUTPUT DATA RATE = 19.8Hz FIRST NOTCH = 52.5Hz INPUT BANDWIDTH = 4.74Hz 50Hz REJECTION = –23.6dB, 50Hz � 1Hz REJECTION = –20.5dB FIRST NOTCH = 9.9Hz 60Hz REJECTION = –14.6dB, 60Hz � 1Hz REJECTION = –13.6dB 50Hz REJECTION = –66dB, 50Hz � 1Hz REJECTION = –60dB 60Hz REJECTION = –117dB, 60Hz � 1Hz REJECTION = –94dB Figure 5. Filter Profile with SF = 13 Figure 7. Filter Profile with Default SF = 69 Giving Filter Notches at Both 50 Hz and 60 Hz 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 0 10 20 30 40 50 60 70 80 90 100 –160 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz SF = 82 FREQUENCY – Hz SF = 255 OUTPUT DATA RATE = 16.65Hz OUTPUT DATA RATE = 5.35Hz INPUT BANDWIDTH = 4Hz INPUT BANDWIDTH = 1.28Hz 50Hz REJECTION = –171dB, 50Hz � 1Hz REJECTION = –100dB 50Hz REJECTION = –93dB, 50Hz � 1Hz REJECTION = –93dB 60Hz REJECTION = –58dB, 60Hz � 1Hz REJECTION = –53dB 60Hz REJECTION = –74dB, 60Hz � 1Hz REJECTION = –68dB Figure 6. Filter Profile with SF = 82 Figure 8. Filter Profile with SF = 255 –12– REV. A ATTENUATION – dB ATTENUATION – dB ATTENUATION – dB ATTENUATION – dB AD7709 NOISE PERFORMANCE level and is independent of frequency. The quantization noise starts Tables II and III show the output rms noise and output peak-to- at an even lower level but rises rapidly with increasing frequency peak resolution in bits (rounded to the nearest 0.5 LSB) for a to become the dominant noise source. The numbers in the tables selection of output update rates. The numbers are typical and are given for the bipolar input ranges. For the unipolar ranges, generated at a differential input voltage of 0 V. The output update the rms noise numbers will be the same as the bipolar range, but rate is selected via the SF7–SF0 bits in the Filter Register. It is the peak-to-peak resolution is now based on half the signal range, important to note that the peak-to-peak resolution figures which effectively means losing 1 bit of resolution. represent the resolution for which there will be no code flicker within a six-sigma limit. The output noise comes from two sources. ON-CHIP REGISTERS The first is the electrical noise in the semiconductor devices The AD7709 is controlled and configured via a number of on-chip (device noise) used in the implementation of the modulator. registers, as shown in Figure 9 and described in more detail in the Second, when the analog input is converted into the digital following pages. In the following descriptions, set implies a Logic 1 domain, quantization noise is added. The device noise is at a low state and cleared implies a Logic 0 state, unless otherwise stated. Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise in �V) Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709 (Peak-to-Peak Resolution in Bits) Input Range SF Data Update Word Rate (Hz) �20 mV �40 mV �80 mV �160 mV �320 mV �640 mV �1.28 V �2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 16 16 16 16 255 5.35 14 15 16 16 16 16 16 16 DIN WEN R/W STBY OSCPD 0 0 A1 A0 DOUT DOUT ADC STATUS REGISTER (8 BITS) REGISTER DIN DOUT CONFIGURATION REGISTER SELECT (24 BITS) DECODER DIN DOUT FILTER REGISTER (8 BITS) DOUT ADC DATA REGISTER (16 BITS) Figure 9. On-Chip Registers REV. A –13– AD7709 Communications Register (A1, A0 = 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7709 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7709 to this default state by resetting the part. Table IV outlines the bit designations for the Communications Register. CR0 to CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. C6 R7 C5 R C4 R C3 R C2 R C1 R C0 R CR WEN(0) R/W() 0)S) TBY(0O) SCPD(00) (0 0) (0 A) 1(0 A(0 Table IV. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register. CR6 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR5 STBY Standby Bit Location. A 1 in this location places the AD7709 in low power mode. A 0 in this location powers up the AD7709. CR4 OSCPD Oscillator Power-Down Bit. If this bit is set, placing the AD7709 in standby mode will stop the crystal oscillator also, reducing the power consumed by the part to a minimum. The oscillator will require 300 ms to begin oscillating when the ADC is taken out of power-down mode. If this bit is cleared, the oscillator is not stopped when the ADC is placed in power-down mode. When the ADC is taken out of power-down mode, the oscillator does not require the 300 ms start-up time. CR3–CR2 0 These bits must be programmed with a Logic 0 for correct operation. CR1–CR0 A1–A0 Register Address Bits. These address bits are used to select which of the AD7709 registers are accessed during this serial interface communication. Table V. Register Selection Table A1 A0 Register 00Communications Register during a Write Operation 00 Status Register during a Read Operation 01Configuration Register 10Filter Register 11 ADC Data Register –14– REV. A AD7709 Status Register (A1, A0 = 0, 0; Power-On-Reset = 00H) The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica- tions Register, selecting the next operation to be a read and load bits A1–A0 with 0, 0. Table VI outlines the bit designations for the Status Register. SR0 to SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. S6 R7 S5 R S4 R S3 R S2 R S1 R S0 R SR R) DY(0) 0) (0 0) (0 0) (0 E) RR(0 0) (0S) TBY(0 LOCK(0 Table VI. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY Ready Bit for ADC. Set when data is written to the ADC data register. The RDY bit is cleared automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result. SR6 0This bit is automatically cleared. SR5 0This bit is automatically cleared. SR4 0This bit is automatically cleared. SR3 ERR ADC Error Bit. This bit is set at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones. Error sources include Overrange, Underrange. Cleared by a write to the mode bits to initiate a conversion. SR2 0This bit is automatically cleared. SR1 STBY Standby Bit Indication. When this bit is set, the AD7709 is in power-down mode. This bit is cleared when the ADC is powered up. SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies, etc., the LOCK bit should be interrogated and the result discarded if the LOCK bit is 0. REV. A –15– AD7709 Configuration Register (A1, A0 = 0, 1; Power-On-Reset = 000007H) The Configuration Register is a 24-bit register from which data can either be read or to which data can be written. This register is used to select the input channel and configure the input range, excitation current sources, and I/O port. Table VII outlines the bit designations for this register. CONFIG23 to CONFIG0 indicate the bit location, CONFIG denoting the bits are in the Configuration Register. CONFIG23 denotes the first bit of the data stream. The number in brackets indicates the power-on-reset default status of that bit. A write to the Configuration Register has immediate effect and does not reset the ADC. Therefore, if a current source is switched 3 while the ADC is converting, the user will have to wait for the full settling time of the sinc filter before obtaining a fully settled output. This equates to three outputs. C CC3 C3C2 O O O O ON N N N NF F F F FI I I I IG G G G G2 2 2 2 23 3 3 C CC2 C2C1 O O O O ON N N N NF F F F FI I I I IG G G G G2 2 2 2 22 2 C CC1 C1C0 O O O O ON N N N NF F F F FI I I I IG G G G G2 2 2 2 21 1 C CC0C9 C0 O O O O ON N N N NF F F F FI I I I IG G G G G2 2 2 2 20 0 C CC9 C9C8 O O O O ON N N N NF F F F FI I I I IG G G G G1 1 1 1 19 9 C CC8 C8C7 O O O O ON N N N NF F F F FI I I I IG G G G G1 1 1 1 18 8 C CC7 C7C6 O O O O ON N N N NF F F F FI I I I IG G G G G1 1 1 1 17 7 C CC6 C6 CO O O O ON N N N NF F F F FI I I I IG G G G G1 1 1 1 16 6 P PP) P)P) S S S S SW W W W W2 2 2 2 2( ( ( ( (0 0 0 0 0) ) ) P) P PP) P) S S S S SW W W W W1 1 1 1 1( ( ( ( (0 0 0 0 0) ) I II) I)I) 3 3 3 3 3E E E E EN N N N N1 1 1 1 1( ( ( ( (0 0 0 0 0) ) I II) I)I) 3 3 3 3 3E E E E EN N N N N0 0 0 0 0( ( ( ( (0 0 0 0 0) ) I II) I)I) 2 2 2 2 2E E E E EN N N N N1 1 1 1 1( ( ( ( (0 0 0 0 0) ) I II) I)I) 2 2 2 2 2E E E E EN N N N N0 0 0 0 0( ( ( ( (0 0 0 0 0) ) I II) I)I) 1 1 1 1 1E E E E EN N N N N1 1 1 1 1( ( ( ( (0 0 0 0 0) ) I) I I II) 1 1 1 1 1E E E E EN N N N N0 0 0 0 0( ( ( ( (0 0 0 0 0) ) C4 ONFIG15C3 ONFIG1C2 ONFIG1C1 ONFIG1C0 ONFIG1C9 ONFIG1C8 ONFIG CONFIG P) 4DIG(0)P) 3DIG(0P) 2EN(0P) 1EN(0P) 4DAT(0P) 3DAT(0P) 2DAT(0 P1DAT(0 C CC7 C7C6 O O O O ON N N N NF F F F FI I I I IG G G G G7 7 7 C CC6 C6C5 O O O O ON N N N NF F F F FI I I I IG G G G G6 6 C CC5 C5C4 O O O O ON N N N NF F F F FI I I I IG G G G G5 5 C CC4C3 C4 O O O O ON N N N NF F F F FI I I I IG G G G G4 4 C CC3 C3C2 O O O O ON N N N NF F F F FI I I I IG G G G G3 3 C CC2 C2C1 O O O O ON N N N NF F F F FI I I I IG G G G G2 2 C CC1 C1C0 O O O O ON N N N NF F F F FI I I I IG G G G G1 1 C CC0 C0 CO O O O ON N N N NF F F F FI I I I IG G G G G0 0 RR) RR) R) E E E E EF F F F FS S S S SE E E E EL L L L L( ( ( ( (0 0 0 0 0) ) ) C) C CC) C) H H H H H2 2 2 2 2( ( ( ( (0 0 0 0 0) ) C) C CC) C) H H H H H1 1 1 1 1( ( ( ( (0 0 0 0 0) ) C CC) C)C) H H H H H0 0 0 0 0( ( ( ( (0 0 0 0 0) )U) NI(0R) N2(1R) N1(1 RN0(1 Table VII. Configuration Register Bit Designations Bit Bit Location Name Description CONFIG23 PSW2 Power Switch 2 Control Bit. Set by user to enable power switch SW2/P2 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. CONFIG22 PSW1 Power Switch 1 Control Bit. Set by user to enable power switch SW1/P1 to PWRGND. Cleared by user to enable use as a standard I/O pin. When the ADC is in standby mode, the power switches are open. CONFIG21 I3EN1 IEXC3 Current Source Enable Bit CONFIG20 I3EN0 IEXC3 Current Source Enable Bit I3EN1 I3EN0 Function 00 IEXC3 Current Source OFF 01 IEXC3 Current Source Routed to the IOUT1 Pin 10 IEXC3 Current Source Routed to the IOUT2 Pin 11 Reserved CONFIG19 I2EN1 IEXC2 Current Source Enable Bit CONFIG18 I2EN0 IEXC2 Current Source Enable Bit I2EN1 I2EN0 Function 00 IEXC2 Current Source OFF 01 IEXC2 Current Source Routed to the IOUT1 Pin 10 IEXC2 Current Source Routed to the IOUT2 Pin 11 Reserved CONFIG17 I1EN1 IEXC1 Current Source Enable Bit –16– REV. A AD7709 Table VII. Configuration Register Bit Designations (continued) Bit Bit Location Name Description CONFIG16 I1EN0 IEXC1 Current Source Enable Bit I1EN1 I1EN0 Function 00 IEXC1 Current Source OFF 01 IEXC1 Current Source Routed to the IOUT1 Pin 10 IEXC1 Current Source Routed to the IOUT2 Pin 11 Reserved CONFIG15 P4DIG Digital Input Enable. Set by user to enable pin AIN4/P4 as a digital input. A weak pull-up resistor is activated in this state. Cleared by user to configure pin AIN4/P4 as an analog input. CONFIG14 P3DIG Digital Input Enable. Set by user to enable pin AIN3/P3 as a digital input. A weak pull-up resistor is activated in this state. Cleared by user to configure pin AIN3/P3 as an analog input. CONFIG13 P2EN SW2/P2 Digital Output Enable Bit. Set by user to enable P2 as a regular digital output pin. Cleared by user to three-state the P2 output. PSW2 takes precedence over P2EN. CONFIG12 P1EN SW1/P1 Digital Output Enable Bit. Set by user to enable P1 as a regular digital output pin. Cleared by user to three-state the P1 output. PSW1 takes precedence over P1EN. CONFIG11 P4DAT Digital Input Port Data Bit. P4DAT is read only and will return a zero if P4DIG equals zero. If P4 is enabled as a digital input, the readback value indicates the status of pin P4. CONFIG10 P3DAT Digital Input Port Data Bit. P3DAT is read only and will return a zero if P3DIG equals zero. If P3 is enabled as a digital input, the readback value indicates the status of pin P3. CONFIG9 P2DAT Digital Output Port Data Bit. P2 is a digital output only. When the port is active as an output (P2EN = 1), the value written to this data bit appears at the output port. Reading P2DAT will return the last value written to the P2DAT bit. CONFIG8 P1DAT Digital Output Port Data Bit. P1 is a digital output only. When the port is active as an output (P1EN = 1), the value written to this data bit appears at the output port. Reading P1DAT will return the last value written to the P1DAT bit. CONFIG7 REFSEL ADC Reference Input Select. Cleared by the user to select REFIN1(+) and REFIN1(–) as the ADC reference. Set by the user to select REFIN2(+) and REFIN2(–) as the ADC reference. CONFIG6 CH2 ADC Input Channel Selection Bit. It is used in conjunction with CH1 and CH0 as shown below. CONFIG5 CH1 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH0 as shown below. CONFIG4 CH0 ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH1 as shown below. CH2 CH1 CH0 Positive Input Negative Input Buffer 0 00 AIN1 AINCOM Positive Analog Input 0 01 AIN2 AINCOM Positive Analog Input 0 10 AIN3 AINCOM Positive Analog Input 0 11 AIN4 AINCOM Positive Analog Input 1 00 AIN1 AIN2 Positive and Negative Analog Inputs 1 01 AIN3 AIN4 Positive and Negative Analog Inputs 1 10 AINCOM AINCOM None 1 11 AIN2 AIN2 Positive and Negative Analog Inputs The Buffer column indicates if the analog inputs are buffered or unbuffered. This determines the common-mode input range on each input. If the input is unbuffered (AINCOM), the common-mode input includes ground. REV. A –17– AD7709 Table VII. Configuration Register Bit Designations (continued) Bit Bit Location Name Description CONFIG3 UNI Unipolar/Bipolar Operation Selection Bit. Set by the user to enable unipolar operation. In this mode, the device uses straight binary output coding i.e., 0 differential input will generate a result of 0000h and a full-scale differential input will generate a code of FFFFh. Cleared by the user to enable pseudo-bipolar operation. The device uses offset binary coding, i.e., a nega- tive full-scale differential input will result in a code of 0000h, a 0 differential input will generate a code of 8000h, while a positive full-scale differential input will result in a code of FFFFh. CONFIG2 RN2 This bit is used in conjunction with RN1 and RN0 to select the analog input range as shown below. CONFIG1 RN1 This bit is used in conjunction with RN2 and RN0 to select the analog input range as shown below. CONFIG0 RN0 This bit is used in conjunction with RN2 and RN1 to select the analog input range as shown below. RN2 RN1 RN0 Selected ADC Input Range (V = 2.5 V) REF 00 0 ±20 mV 00 1 ±40 mV 01 0 ±80 mV 01 1 ±160 mV 10 0 ±320 mV 10 1 ±640 mV 11 0 ±1.28 V 11 1 ±2.56 V Table VIII. Filter Register Bit Designations F6 R7F5 R F4 R F3 R F2 R F1 R F0 R FR S) F7(0)S) F6(1S) F5(0S) F4(0S) F3(0S) F2(1S) F1(0 SF0(1 Table IX. Update Rate vs. SF WORD SF (Dec) SF (Hex) f (Hz) t (ms) ADC ADC 13 0D 105.3 9.52 69 45 19.79 50.34 255 FF 5.35 186.77 Filter Register (A1, A0 = 1, 0; Power-On-Reset = 45h) The allowable range for SF is 13dec to 255dec. Examples of SF The Filter Register is an 8-bit register from which data can be values and corresponding conversion rate (f ) and time (t ) ADC ADC read or to which data can be written. This register determines are shown in Table IX. It should also be noted that the ADC the amount of averaging performed by the sinc filter. Table VIII input channel is chopped to minimize offset errors. This means outlines the bit designations for the Filter Register. FR7 through that the time for a single conversion or the time to the first con- FR0 indicate the bit location, FR denoting the bits are in the version result is 2 � t . ADC Filter Register. FR7 denotes the first bit of the data stream. The ADC Data Result Register (A1, A0 = 1, 1; Power-On-Reset = number in brackets indicates the power-on/reset default status 0000h) of that bit. The number in this register is used to set the decima- The conversion result is stored in the ADC Data Register (DATA). tion factor and thus the output update rate for the ADC. The This register is 16-bits wide. This is a read-only register. On Filter Register cannot be written to by the user while the ADC completion of a read from this register, the RDY bit in the is active. The update rate is calculated as follows: Status Register is cleared. 1 1 f =¥ ¥ f ADC MOD 3 8 ¥ SF where: f is the ADC output update rate. ADC f is the Modulator Clock Frequency = 32.768 kHz. MOD SF is the decimal value written to the SF Register. –18– REV. A AD7709 CONFIGURING THE AD7709 2. Initialize the AD7709 by configuring the following registers: The four user-accessible registers on the AD7709 are accessed via a)Filter Register to configure the update rate for the channel. the serial interface. Communication with any of these registers The AD7709 must be placed in standby mode before the is initiated by first writing to the Communications Register. The Filter Register can be written to. AD7709 begins converting on power-up without the need to b)Configuration Register to select the input channel to be write to the registers. The default conditions are used, i.e., the converted, its input range, and reference. This register is also AD7709 operates at a 19.79 Hz update rate that offers 50 Hz used to configure internal current sources, power switches, and 60 Hz rejection. and I/O port. Figure 10 outlines a flow diagram of the sequence used to Both of these operations consist of a write to the Communi- configure all registers after a power-up or reset on the AD7709. cations Register to specify the next operation as a write to a The flowchart shows two methods of determining when it is valid specified register. Data is then written to this register. When to read the data register. The first method is hardware polling of each sequence is complete, the ADC defaults to waiting for the RDY pin and the second method involves software interrogation another write to the Communications Register to specify the of the RDY bit in the status register. The flowchart details all the next operation. necessary programming steps required to initialize the ADC and read data from the ADC channel following a power-on or reset. 3. When configuration is complete, the user needs to determine The steps can be broken down as follows: when it is valid to read the data from the data register. This is accomplished either by polling the RDY pin (hardware polling) 1. Configure and initialize the microcontroller or microproces- or by interrogating the RDY bit in the STATUS register sor serial port. (software polling). Both are shown in Figure 10. HARDWARE SOFTWARE START POLLING POLLING POLL RDY PIN POWER-ON-RESET FOR AD7709 WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE STATUS REGISTER (WRITE 40H TO REGISTER) CONFIGURE AND INITIALIZE �C/�P SERIAL PORT NO READ STATUS REGISTER RDY WRITE TO COMMUNICATIONS REGISTER SETTING LOW? UP NEXT OPERATION TO BE A WRITE TO THE FILTER REGISTER (WRITE 22H TO REGISTER) YES NO RDY = 1 WRITE TO FILTER REGISTER CONFIRMING WRITE TO COMMUNICATIONS REGISTER SETTING THE REQUIRED UPDATE RATE UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (WRITE 43H TO REGISTER) YES WRITE TO COMMUNICATIONS REGISTER SETTING READ 16-BIT DATA RESULT UP NEXT OPERATION TO BE A WRITE TO THE WRITE TO COMMUNICATIONS REGISTER SETTING CONFIGURATION REGISTER UP NEXT OPERATION TO BE A READ FROM THE (WRITE 01H TO REGISTER) DATA REGISTER (WRITE 43H TO REGISTER) WRITE TO CONFIGURATION REGISTER TO SELECT YES ANOTHER READ 16-BIT DATA RESULT THE INPUT CHANNEL, INPUT RANGE, AND READ REFERENCE. CURRENT SOURCES AND I/O PORT CAN ALSO BE CONFIGURED YES ANOTHER READ DATA FROM OUTPUT REGISTER READ YES CHANNEL CHANGE NO HARDWARE SOFTWARE POLLING POLLING YES CHANNEL CHANGE NO NO END END Figure 10. Flowchart for Initializing and Reading Data from the AD7709 REV. A –19– AD7709 DIGITAL INTERFACE The serial interface can be reset by exercising the RESET input As previously outlined, AD7709 programmable functions are on the part. It can also be reset by writing a series of 1s on the controlled using a set of on-chip registers. Data is written to DIN input. If a Logic 1 is written to the AD7709 DIN line for these registers via the part’s serial interface and read access to at least 32 serial clock cycles, the serial interface is reset. This the on-chip registers is also provided by this interface. All com- ensures that in 3-wire systems, if the interface gets lost either via munications to the part must start with a write operation to the a software error or by some glitch in the system, it can be reset Communications Register. After power-on or reset, the device back to a known state. This state returns the interface to where expects a write to its Communications Register. The data writ- the AD7709 is expecting a write operation to its Communications ten to this register determines whether the next operation to the Register. This operation resets the contents of all registers to their part is a read or a write operation and also determines to which power-on reset values. register this read or write operation occurs. Therefore, write Some microprocessor or microcontroller serial interfaces have a access to any of the other registers on the part starts with a write single serial data line. In this case, it is possible to connect the operation to the Communications Register followed by a write AD7709 DOUT and DIN lines together and connect them to the to the selected register. A read operation from any other register single data line of the processor. A 10 kW pull-up resistor should on the part (including the output data register) starts with a be used on this single data line. In this case, if the interface gets write operation to the Communications Register followed by a lost, because the read and write operations share the same line, read operation from the selected register. the procedure to reset it back to a known state is somewhat The AD7709 serial interface consists of five signals: CS, SCLK, different than previously described. It requires a read operation DIN, DOUT, and RDY. The DIN line is used for transferring of 24 serial clocks followed by a write operation where a Logic 1 data into the on-chip registers, while the DOUT line is used for is written for at least 32 serial clock cycles to ensure that the accessing data from the on-chip registers. SCLK is the serial serial interface is back into a known state. clock input for the device, and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The MICROCOMPUTER/MICROPROCESSOR INTERFACING RDY line is used as a status signal to indicate when data is ready The AD7709 flexible serial interface allows for easy interface to to be read from the AD7709 data register. RDY goes low when a most microcomputers and microprocessors. The flowchart of new data-word is available in the output register. It is reset high Figure 10 outlines the sequence that should be followed when when a read operation from the data register is complete. It also interfacing a microcontroller or microprocessor to the AD7709. goes high prior to the updating of the output register to indicate Figures 11, 12, and 13 show some typical interface circuits. The when not to read from the device to ensure that a data read is not serial interface on the AD7709 is capable of operating from just attempted while the register is being updated. CS is used to select three wires and is compatible with SPI interface protocols. The the device. It can be used to decode the AD7709 in systems where 3-wire operation makes the part ideal for isolated systems where a number of parts are connected to the serial bus. minimizing the number of interface lines minimizes the number of opto-isolators required in the system. The serial clock input is Figures 2 and 3 show timing diagrams for interfacing to the a Schmitt-triggered input to accommodate slow edges from AD7709 with CS used to decode the part. Figure 3 is for a read opto-couplers. The rise and fall times of other digital inputs to operation from the AD7709 output shift register while Figure 2 the AD7709 should be no longer than 1 ms. shows a write operation to the input shift register. It is possible to read the same data twice from the output register even though Some of the registers on the AD7709 are 8-bit registers, which the RDY line returns high after the first read operation. Care must facilitates easy interfacing to the 8-bit serial ports of microcon- be taken, however, to ensure that the read operations have been trollers. The Data Register on the AD7709 is 16 bits and the completed before the next output update is about to take place. Configuration Register is 24 bits, but data transfers to these registers can consist of multiple 8-bit transfers to the serial port The AD7709 serial interface can operate in 3-wire mode by of the microcontroller. DSP processors and microprocessors tying the CS input low. In this case, the SCLK, DIN, and generally transfer 16 bits of data in a serial data operation. Some DOUT lines are used to communicate with the AD7709, and of these processors, such as the ADSP-2105, have the facility to the status of the RDY bit can be obtained by interrogating the program the amount of cycles in a serial transfer. This allows the Status Register. This scheme is suitable for interfacing to user to tailor the number of bits in any transfer to match the microcontrollers. If CS is required as a decoding signal, it can register length of the required register in the AD7709. be generated from a port bit. For microcontroller interfaces, it is recommended that the SCLK idles high between data transfers. Even though some of the registers on the AD7709 are only 8 bits in length, communicating with two of these registers in successive The AD7709 can also be operated with CS used as a frame write operations can be handled as a single 16-bit data transfer if synchronization signal. This scheme is suitable for DSP interfaces. required. For example, if the Filter Register is to be updated, the In this case, the first bit (MSB) is effectively clocked out by CS processor must first write to the Communications Register (say- since CS would normally occur after the falling edge of SCLK ing that the next operation is a write to the Filter Register), and in DSPs. The SCLK can continue to run between data transfers then write 8 bits to the Filter Register. If required, this can all be provided the timing numbers are obeyed. done in a single 16-bit transfer because once the eight serial clocks of the write operation to the Communications Register have been completed, the part immediately sets itself up for a write operation to the Filter Register. –20– REV. A AD7709 AD7709-to-68HC11 Interface V DD 8XC51 AD7709 Figure 11 shows an interface between the AD7709 and the V DD 68HC11 microcontroller. The diagram shows the minimum (3-wire) interface with CS on the AD7709 hardwired low. In this RESET 10k� scheme, the RDY bit of the Status Register is monitored to determine when the Data Register is updated. An alternative P3.0 DOUT scheme, which increases the number of interface lines to four, is to monitor the RDY output line from the AD7709. The monitoring of the RDY line can be done in two ways. First, RDY can be DIN connected to one of the 68HC11 port bits (such as PC0), which is configured as an input. This port bit is then polled to determine P3.1 SCLK the status of RDY. The second scheme is to use an interrupt driven system, in which case the RDY output is connected to the IRQ input of the 68HC11. For interfaces that require CS control of the CS input on the AD7709, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input. Figure 12. AD7709-to-8XC51 Interface The 68HC11 is configured in the master mode with its CPOL The second scheme is to use an interrupt-driven system, in which bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the case the RDY output is connected to the INT1 input of the 68HC11 is configured like this, its SCLK line idles high between 8XC51. For interfaces that require control of the CS input on data transfers. The AD7709 is not capable of full-duplex opera- the AD7709, one of the port bits of the 8XC51 (such as P1.1), tion. If the AD7709 is configured for a write operation, no data which is configured as an output, can be used to drive the CS appears on the DOUT lines even when the SCLK input is active. input. The 8XC51 is configured in its Mode 0 serial interface Similarly, if the AD7709 is configured for a read operation, data mode. Its serial interface contains a single data line. As a result, presented to the part on the DIN line is ignored even when the DOUT and DIN pins of the AD7709 should be connected SCLK is active. together with a 10 kW pull-up resistor. The serial clock on the 8XC51 idles high between data transfers. The 8XC51 outputs V DD V 68HC11 AD7709 DD the LSB first in a write operation, while the AD7709 expects the MSB first so the data to be transmitted has to be rearranged before being written to the output serial register. Similarly, the SS RESET AD7709 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data read into SCLK the serial buffer needs to be rearranged before the correct data SCK word from the AD7709 is available in the accumulator. DOUT MISO ADSP-2103/ V DD AD7709 ADSP-2105 DIN MOSI RESET CS RFS CS TFS Figure 11. AD7709-to-68HC11 Interface DR DOUT AD7709-to-8051 Interface An interface circuit between the AD7709 and the 8XC51 microcon- DT DIN troller is shown in Figure 12. The diagram shows the minimum number of interface connections with CS on the AD7709 hard- SCLK wired low. In the case of the 8XC51 interface, the minimum SCLK number of interconnects is just two. In this scheme, the RDY bit of the Status Register is monitored to determine when the Figure 13. AD7709-to-ADSP-2103/ADSP-2105 Interface Data Register is updated. The alternative scheme, which increases AD7709-to-ADSP-2103/ADSP-2105 Interface the number of interface lines to three, is to monitor the RDY output Figure 13 shows an interface between the AD7709 and the line from the AD7709. The monitoring of the RDY line can be ADSP-2103/ADSP-2105 DSP processor. In the interface shown, done in two ways. First, RDY can be connected to one of the the RDY bit of the Status Register is again monitored to 8XC51 port bits (such as P1.0) which is configured as an input. determine when the Data Register is updated. The alternative This port bit is then polled to determine the status of RDY. scheme is to use an interrupt-driven system, in which case the REV. A –21– AD7709 ANALOG 5V RDY output is connected to the IRQ2 input of the ADSP-2103/ SUPPLY 0.1�F 10�F ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 is set up for alternate framing mode. The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low 5V V DD outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also configured as an output. The CS for the AD7709 is RESET IOUT1 active when either the RFS or TFS outputs from the ADSP-2103/ CHIP CS IOUT2 ADSP-2105 are active. The serial clock rate on the ADSP-2103/ SELECT AD7709 ADSP-2105 should be limited to 3 MHz to ensure correct opera- RECEIVE AIN1 DOUT (READ) tion with the AD7709. SERIAL DATA AIN2 DIN (WRITE) CIRCUIT DESCRIPTION SERIAL AIN3/P3 SCLK CLOCK The AD7709 is a �-� A/D converter with on-chip digital filtering, AIN4/P4 intended for the measurement of wide dynamic range, low P1/SW1 frequency signals such as those in weigh scale, pressure, tempera- AINCOM P2/SW2 ture, industrial control, or process control applications. It employs REFIN1(–) a �-� conversion technique to realize up to 16 bits of no-missing- codes performance. The �-� modulator converts the sampled REFIN1(+) ANALOG 5V input signal into a digital pulse train whose duty cycle contains SUPPLY 3 10�F the digital information. A Sinc programmable low-pass filter is REFIN2(+) XTAL1 32.768kHz then employed to decimate the modulator output data stream to CRYSTAL XTAL2 give a valid data conversion result at programmable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping 0.1�F scheme is also employed to minimize ADC offset and offset and REFIN2(–) V V IN OUT PWRGND GND gain drift errors. The channel is buffered and can be programmed for one of eight input ranges from ±20 mV to ±2.56 V. The input AD780/ REF195 channels can be configured for either fully differential inputs or pseudo-differential input channels via the CH2, CH1, and CH0 GND bits in the Configuration Register. Buffering the input channel allows the part to handle significant source impedances on the analog input, allowing R/C filtering (for noise rejection or RFI Figure 14. Basic Connection Diagram reduction) to be placed on the analog inputs if required. These input channels are intended for converting signals directly from sensors without the need for external signal conditioning. Other The output of the ADC multiplexer feeds into a high impedance functions contained on-chip that augment the operation of the input stage of the buffer amplifier. As a result, the ADC inputs can ADC include software configurable current sources, switchable handle significant source impedances and are tailored for direct reference inputs, and low-side power switches. connection to external resistive-type sensors like strain gauges or Resistance Temperature Detectors (RTDs). The basic connection diagram for the AD7709 is shown in Figure 14. An AD780/REF195, precision 2.5 V reference, provides The absolute input voltage range on the ADC inputs when buff- the reference source for the part. A quartz crystal or ceramic ered (AIN1 to AIN4) is restricted to a range between GND + resonator provides the 32.768 kHz master clock source for the 100 mV and V – 100 mV. Care must be taken in setting up DD part. In some cases, it will be necessary to connect capacitors on the common-mode voltage and input voltage range so that these the crystal or resonator to ensure that it does not oscillate at over- limits are not exceeded; otherwise, there will be a degradation in tones of its fundamental operating frequency. The values of linearity and noise performance. capacitors will vary depending on manufacturer specifications. The absolute input voltage range on the ADC inputs when Analog Input Channels unbuffered (AINCOM) includes the range between GND – 30 mV to The main ADC has five associated analog input pins (labeled V + 30 mV as a result of being unbuffered. The negative abso- DD AIN1 to AIN4 and AINCOM) that can be configured as two lute input voltage limit does allow the possibility of monitoring fully differential input channels (AIN1–AIN2 and AIN3–AIN4) small true bipolar signals with respect to GND. or four pseudo-differential input channels (AIN1–AINCOM, AIN2–AINCOM, AIN3–AINCOM, and AIN4–AINCOM). Channel selection bits CH2, CHI, and CH0 in the Configuration Register detail the different configurations. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. –22– REV. A AD7709 Programmable Gain Amplifier The output from the buffer on the ADC is applied to the input MUX of the on-chip programmable gain amplifier (PGA). The PGA AIN1 AIN1 can be programmed through eight different unipolar and bipolar FULLY DIFFERENTIAL AIN(+) ranges. The PGA gain range is programmed via the range bits AIN2 AIN2 in the Configuration Register. With an external 2.5 V reference ADC CHANNEL applied, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV, AIN3 AIN3 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to AIN(–) FULLY DIFFERENTIAL 640 mV, 0 V to 1.28 V, and 0 to 2.56 V, while bipolar ranges AIN4 AIN4 are ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V, and ±2.56 V. These are the ranges that should Figure 16. Fully Differential Mode of Operation appear at the input to the on-chip PGA. Typical matching across ranges is shown in Figure 15. Here, the PSEUDO-DIFFERENTIAL MUX ADC is configured in fully differential, bipolar mode with an INPUT AIN1 AIN1 external 2.5 V reference, while an analog input voltage of just AIN1/AINCOM greater than 19 mV is forced on its analog inputs. The ADC AIN(+) AIN2 AIN2 continuously converts the dc voltage at an update rate of 5.35 Hz, i.e., SF = FFh. A total of 800 conversion results are gathered. AIN2/AINCOM ADC CHANNEL The first 100 results gathered with the ADC operating in the AIN3 AIN3 ±20 mV. The ADC range is then switched to ±40 mV and 100 AIN(–) AIN3/AINCOM more results are gathered, and so on, until the last 100 samples AIN4 AIN4 are gathered with the ADC configured in the ±2.5 V range. From AIN4/AINCOM Figure 15, the variation in the sample mean through each range, AINCOM AINCOM i.e., the range matching, is seen to be on the order of 2 µV. PSEUDO-DIFFERENTIAL INPUT Figure 17. Pseudo-Differential Mode of Operation 19.372 For example, if AIN(–) is 2.5 V and the ADC is configured for 19.371 an analog input range of 0 mV to 20 mV, the input voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and 19.370 the AD7709 is configured for an analog input range of ±1.28 V, 19.369 the analog input range on the AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ±1.28 V). Bipolar or unipolar options are chosen by 19.368 programming the UNI bit in the Configuration Register. This programs the ADC for either unipolar or bipolar operation. 19.367 Programming for either unipolar or bipolar operation does not 19.366 change any of the input signal conditioning; it simply changes the data output coding. 19.365 Data Output Coding 19.364 When the ADC is configured for unipolar operation, the output SAMPLE COUNT 0 100 200 300 400 500 600 700 800 coding is natural (straight) binary with a zero differential input ADC RANGE voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. The output code for any analog Figure 15. ADC Range Matching input voltage on the ADC can be represented as follows: Bipolar/Unipolar Configuration N The analog inputs on the AD7709 can accept either unipolar or AIN×× GAIN 2 () Code = bipolar input voltage ranges. Bipolar input ranges do not imply that 1.024 ×V () REF the part can handle negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input on where: the ADC are referenced to the voltage on the respective AIN(–) AIN is the analog input voltage. input. AIN(+) and AIN(–) refer to the signals seen by the modulator that come from the output of the multiplexer, as shown GAIN is the PGA gain, i.e., 1 on the 2.56 V range and 128 on in Figures 16 and 17. the 20 mV range. N = 16. REV. A –23– ADC INPUT VOLTAGE – mV �20mV �40mV �80mV �160mV �320mV �640mV �1.28V �2.56V AD7709 When the ADC is configured for bipolar operation, the coding because the application is ratiometric. If the AD7709 is used is offset binary with a negative full-scale voltage resulting in a in a nonratiometric application, a low noise reference should be code of 000 . . . 000, a zero differential voltage resulting in a used. Recommended reference voltage sources for the AD7709 code of 100 . . . 000, and a positive full-scale voltage resulting in include the AD780, REF43, and REF192. It should also be noted a code of 111 . . . 111. The output code from the ADC for any that the reference inputs provide a high impedance, dynamic load. analog input voltage can be represented as follows: Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain N -1 Code=¥21 AIN¥ GAIN/.024¥V + 1 errors, depending on the output impedance of the source that is () () REF [] driving the reference inputs. Reference voltage sources like those where: recommended above (e.g., AD780) will typically have low output impedances and are therefore tolerant to having decoupling capaci- AIN is the analog input voltage. tors on the REFIN(+) without introducing gain errors in the system. GAIN in the PGA gain, i.e., 1 on the ±2.56 V range and 128 Deriving the reference input voltage across an external resistor, as on the ±20 mV range. shown in Figure 18, will mean that the reference input sees a N = 16. significant external source impedance. External decoupling on the REFIN pins would not be recommended in this type of circuit Excitation Currents configuration. The AD7709 also contains three software configurable constant current sources. IEXC1 and IEXC2 provide 200 mA of current Reset Input while IEXC3 provides 25 mA of current. All source current The RESET input on the AD7709 resets all the logic, the digital from V is directed to either the IOUT1 or IOUT2 pins of the DD filter, and the analog modulator while all on-chip registers are reset device. These current sources are controlled via bits in the to their default state. RDY is driven high and the AD7709 ignores Configuration Register. The configuration bits enable the current all communications to any of its registers while the RESET sources, and they can be configured to source current individually input is low. When the RESET input returns high, the AD7709 to both pins or a combination of currents, i.e., 400 mA, 225 mA, or operates with its default setup conditions and it is necessary to 425 mA to either of the selected output pins. These current sources set up all registers after a RESET command. can be used to excite external resistive bridge or RTD sensors. Power-Down Mode Crystal Oscillator Loading 0 to the STBY bit in the ADC Communications Register The AD7709 is intended for use with a 32.768 kHz watch crys- places the AD7709 in device power-down mode. The AD7709 tal. A PLL internally locks onto a multiple of this frequency to retains the contents of all its on-chip registers (including the data provide a stable 4.194304 MHz clock for the ADC. The modu- register) while in power-down mode. lator sample rate is the same as the crystal oscillator frequency. The device power-down mode does not affect the digital interface, The start-up time associated with 32.768 kHz crystals is typically but it does affect the status of the RDY pin. Putting the AD7709 300 ms. The OSCPD bit in the Communications Register can into power-down mode will reset the RDY line high. Placing the be used to prevent the oscillator from powering down when the part in power-down mode reduces the total current to 26 mA AD7709 is placed in power-down mode. This avoids having to typical when the part is operated at 5 V with the oscillator running wait 300 ms after exiting power-down to start a conversion at the during power-down mode. With the oscillator shut down, the total expense of raising the power-down current. I is 1.5 mA typical at 3 V and 6.5 mA typical at 5 V. DD Reference Input Grounding and Layout The AD7709 has a fully differential reference input capability Since the analog inputs and reference inputs on the ADC are for the channel. On the channel, the reference inputs can be differential, most of the voltages in the analog modulator are REFIN1(+) and REFIN1(–) or REFIN2(+) and REFIN2(–). common-mode voltages. The excellent common-mode rejection They provide a differential reference input capability. The of the part will remove common-mode noise on these inputs. common-mode range for these differential inputs is from GND The digital filter will provide rejection of broadband noise on to V . The reference input is unbuffered and therefore DD the power supply, except at integer multiples of the modulator excessive R-C source impedances will introduce gain errors. sampling frequency. The digital filter also removes noise from The nominal reference voltage, V , ((REFIN1(+) REF the analog and reference inputs, provided these noise sources do – REFIN1(–) or (REFIN2(+) – REFIN2(–)), for specified not saturate the analog modulator. As a result, the AD7709 is operation is 2.5 V, but the AD7709 is functional with reference more immune to noise interference than a conventional high voltages from 1 V to V . In applications where the excitation DD resolution converter. However, because the resolution of the (voltage or current) for the transducer on the analog input also AD7709 is so high, and the noise levels from the AD7709 so drives the reference voltage for the part, the effect of the low low, care must be taken with regard to grounding and layout. frequency noise in the excitation source will be removed –24– REV. A AD7709 The printed circuit board that houses the AD7709 should be system designer to achieve a much higher level of resolution because designed such that the analog and digital sections are separated noise performance of the AD7709 is significantly better than that and confined to certain areas of the board. A minimum etch of integrating ADCs. technique is generally best for ground planes as it gives the best The on-chip PGA allows the AD7709 to handle an analog input shielding. voltage range as low as 10 mV full scale with V = 1.25 V. The REF It is recommended that the AD7709 GND pin be tied to the differential inputs of the part allow this analog input range to AGND plane of the system. In any layout, it is important that the have an absolute value anywhere between GND + 100 mV and user keep in mind the flow of currents in the system ensuring V – 100 mV. It allows the user to connect the transducer DD that the return paths for all currents are as close as possible to directly to the input of the AD7709. The programmable gain the paths the currents took to reach their destinations. Avoid front end on the AD7709 allows the part to handle unipolar forcing digital currents to flow through the AGND sections of analog input ranges from 0 mV to 20 mV and 0 V to 2.5 V the layout. and bipolar inputs of ±20 mV to ±2.5 V. Because the part oper- ates from a single supply, these bipolar ranges are with respect The PWRGND pin is tied internally to GND on the AD7709. to a biased-up differential input. The PWRGND pad internally has a resistance of less than 50 mW to the PWRGND pin, while the resistance back to the GND pad Pressure Measurement is less than 3 W. This means that 19.5 mA of the maximum speci- One typical application of the AD7709 is pressure measurement. fied current (20 mA) will flow to PWRGND with the remaining Figure 18 shows the AD7709 used with a pressure transducer, 0.5 mA flowing to GND. PWRGND and GND should be tied the BP01 from Sensym. The pressure transducer is arranged in together at the AD7709, and it is important to minimize the a bridge network and gives a differential output voltage between resistance on the ground return lines. its OUT(+) and OUT(–) terminals. With rated full-scale pres- sure (in this case 300 mmHg) on the transducer, the differential Avoid running digital lines under the device since these will output voltage is 3 mV/V of the input voltage (i.e., the voltage couple noise onto the die. The analog ground plane should be between its IN(+) and IN(–) terminals). allowed to run under the AD7709 to prevent noise coupling. The power supply lines to the AD7709 should use as wide a trace as Assuming a 5 V excitation voltage, the full-scale output range possible to provide low impedance paths and reduce the effects of from the transducer is 15 mV. The excitation voltage for the glitches on the power supply line. Fast switching signals like bridge can be used to directly provide the reference for the ADC clocks should be shielded with digital ground to avoid radiating as the reference input range includes the supply. Alternatively, a noise to other sections of the board, and clock signals should suitable resistor divider can be implemented that allows the full never be run near the analog inputs. Avoid crossover of digital dynamic range of the input to be utilized in this application. and analog signals. Traces on opposite sides of the board should This implementation is fully ratiometric, so variations in the run at right angles to each other, which will reduce the effects of excitation voltage do not introduce errors in the system. Choosing feedthrough through the board. A microstrip technique is by far the resistor values of 10 kW and 6 kW as per Figure 18 gives a 1.875 V best, but is not always possible with a double-sided board. In reference voltage for the AD7709 when the excitation voltage is 5 V. this technique, the component side of the board is dedicated to EXCITATION VOLTAGE = 5V ground planes while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. IN+ 10k� The supply should be decoupled with 10 mF tantalum in parallel V DD OUT+ with 0.1 mF capacitors to GND. To achieve the best from these OUT– AIN1 decoupling components, they have to be placed as close as possible; AIN2 chips should be decoupled with 0.1 mF ceramic capacitors to DGND. IN– REFIN1(+) 6k� APPLICATIONS REFIN2(–) The AD7709 provides a low cost, high resolution, analog-to-digital AD7709 function. Because the analog-to-digital function is provided by a P1 �-� architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. Given the architecture used in the AD7709, where the signal chain is chopped and the GND PWRGND device is factory-calibrated at final test, field calibration is not needed due to the extremely low offset and gain drifts exhibited by this converter. It also provides a programmable gain amplifier Figure 18. Pressure Measurement Using the AD7709 and a digital filter. Thus, it provides far more system-level func- Using the part with a programmed gain of 128 results in the tionality than off-the-shelf integrating ADCs without the full-scale input span of the AD7709 being 15 mV, which corre- disadvantage of having to supply a high quality integrating sponds with the output span from the transducer. capacitor. In addition, using the AD7709 in a system allows the REV. A –25– AD7709 A second key advantage to using the AD7709 in transducer-based Temperature Measurement applications is that the on-chip low-side power switch can be fully The AD7709 is also useful in temperature measurement appli- utilized in low power applications. The low-side power switch is cations. Figure 20 shows an RTD temperature measurement connected in series with the cold side of the bridge. In normal application. operation, the switch is closed and measurements can be taken 5V from the bridge. In applications where power is a concern, the AD7709 can be put into low power mode, substantially reducing V AD7709 DD the power burned in the application. In addition to this, the power REFIN(–) switch can be opened while in low power mode, thus avoiding XTAL1 the unnecessary burning of power in the front end transducer. REFIN(+) R When taken back out of power-down, and the power switch is RL1 REF IOUT1 XTAL2 closed, the user should ensure that the front end circuitry is fully 6.25k� settled before attempting a read from the AD7709. 200�A IOUT2 The circuit in Figure 19 shows a method that utilizes three RL2 AIN1 pseudo-differential input channels on the AD7709 to temperature- DRDY RTD compensate a pressure transducer. SCLK AIN2 CONTROLLER DIN 5V RL3 DOUT R CM V DD CS RL4 IOUT1 GND PWRGND I1 I2 Figure 20. 4-Wire RTD Temperature Measurement Using the AD7709 REFIN(+) In this application, the transducer is an RTD (Resistive Tem- 6.25k� perature Device), a PT100. The arrangement is a 4-lead RTD REFIN(–) configuration. There are voltage drops across the lead resistances RL1 and RL4, but these simply shift the common-mode voltage. AIN2 IN(+) XTAL1 There is no voltage drop across lead resistances RL2 and RL3 AD7709 since the input current to the AD7709 is very low, looking into a OUT(+) high input impedance buffer. R is included to shift the analog OUT(–) AIN1 CM input voltage to ensure that it lies within the common-mode PRESSURE AINCOM XTAL2 BRIDGE range (GND + 100 mV to V – 100 mV) of the ADC. In the DD IN(–) GND AIN3 application shown, the on-chip 200 mA current source provides 250� the excitation current for the PT100 and also generates the reference voltage for the AD7709 via the 6.25 kW resistor. Variations in the excitation current do not affect the circuit since both the Figure 19. Temperature-Compensating a Pressure input voltage and the reference voltage vary ratiometrically with the Transducer excitation current. However, the 6.25 kW resistor must have a low temperature coefficient to avoid errors in the reference voltage In this application, pseudo-differential input channel AIN1/ over temperature. AINCOM is used to measure the bridge output while pseuo- differential channels AIN2/AINCOM and AIN3/AINCOM measure the voltage across the bridge. The voltage measured across the bridge will vary proportionally with temperature, and the delta in this voltage can be used to temperature- compensate the output of the pressure bridge. –26– REV. A AD7709 Figure 21 shows a further enhancement to the circuit shown in 3-Wire RTD Configurations Figure 20. Generally, dc excitation has been accepted as the To fully optimize a 3-wire RTD configuration, two identically normal method of exciting resistive based sensors like RTDs in matched current sources are required. The AD7709, which temperature measurement applications. contains two well matched 200 mA current sources, is ideally suited to these applications. One possible 3-wire configuration using the AD7709 is shown in Figure 22. V DD EMF1 IOUT1 5V I1 IOUT2 200�A V DD RESISTIVE IOUT1 XTAL1 TRANSDUCER BUF 200�A AND AIN1 PGA EMF2 REFIN(+) XTAL2 AIN2 MUX1 6.25k� AIN3 REFIN(–) AIN4 A A RL1 P1 AIN1 REFIN(+) DRDY AIN2 RTD P2 AD7709 SCLK R REF RL2 IOUT2 REFIN(–) DIN CONTROLLER RL3 200�A DOUT CS R CM Figure 21. Low Resistance Measurement GND With dc excitation, the excitation current through the sensor AD7709 must be large enough so that the smallest temperature/resis- tance change to be measured results in a voltage change that Figure 22. 3-Wire RTD Configuration Using the AD7709 is larger than the system noise, offset, and drift of the system. The purpose of switching the excitation source is to eliminate In this 3-wire configuration, the lead resistances will result in dc-induced errors. DC errors (EMF1 and EMF2) due to para- errors if only one current source is used since the 200 mA will flow sitic thermocouples produced by differential metal connections through RL1, developing a voltage error between AIN1 and AIN2. (solder and copper track) within the circuit are also eliminated In the scheme outlined below, the second RTD current source when using this switching arrangement. This excitation is a is used to compensate for the error introduced by the 200 mA form of synchronous detection where the sensor is excited with flowing through RL1. The second RTD current flows through an alternating excitation source and the ADC measures infor- RL2. Assuming that RL1 and RL2 are equal (the leads would mation only in the same phase as the excitation source. normally be of the same material and of equal length) and that IOUT1 and IOUT2 match, the error voltage across RL2 equals The switched polarity current source is developed using the the error voltage across RL1 and no error voltage is developed on-chip current sources and external phase control switches (A between AIN1 and AIN2. Twice the voltage is developed across RL3 and A) driven by AD7709 logic outputs P1 and P2. During the but, since this is a common-mode voltage, it will not introduce conversion process, the AD7709 takes two conversion results, errors. R is included so the current flowing through the CM one on each phase. During Phase 1, the on-chip current source is combination of RL3 and R develops enough voltage that the CM directed to IOUT1 and flows top to bottom through the sensor analog input voltage seen by the AD7709 is within the common- and switch controlled by A. In Phase 2, the current source is mode range of the ADC. The reference voltage for the AD7709 directed to IOUT2 and flows in the opposite direction through is also generated using one of these matched current sources. the sensor and through switch controlled by A. In all cases, the current flows in the same direction through the reference resistor This reference voltage is developed across the 6.25 kW resistor to develop the reference voltage for the ADC. All measurements as shown, and applied to the differential reference inputs of the are ratiometrically derived. The results of both conversions are AD7709. This scheme ensures that the analog input voltage span combined within the microcontroller to produce one output remains ratiometric to the reference voltage. Any errors in the measurement representing the resistance or temperature of the analog input voltage due to the temperature drift of the RTD transducer. For example, if the RTD output during Phase 1 is current source is compensated for by the variation in the reference 10 mV, a 1 mV circuit-induced dc error exists due to parasitic voltage. The typical drift matching between the two RTD current thermocouples, the ADC measures 11 mV. During the second sources is less than 20 ppm/∞C. The voltage on either I pin OUT phase, the excitation current is reversed and the ADC measures can go to within 0.6 V of the V supply. DD –10 mV from the RTD and again sees 1 mV dc error, giving an The AD7709 also includes a 25 mA current source that can be used ADC output of –9 mV during this phase. These measurements along with the two 200 mA current sources for V measurement BE are processed in the controller (11 mV – (–9 mV)/2 = 10 mV), where a 17:1 ratio is required from the current sources. thus removing the dc-induced errors within the system. In the circuit shown in Figure 20, the resistance measurement is made using ratiometric techniques. Resistor R , which develops REF the ADC reference, must be stable over temperature to prevent reference-induced errors in the measurement output. REV. A –27– AD7709 Smart Transmitters amount of current available to power the transmitter is as low as Smart transmitters are another key design-in area for the AD7709. 3.5 mA. Figure 23 shows a block diagram of a smart transmitter The �-� converter, single-supply operation, 3-wire interface that includes the AD7709. capabilities, and small package size are all of benefit in smart Not shown in Figure 23 is the isolated power source required to transmitters. Here, the entire smart transmitter must operate power the front end. from the 4–20 mA loop. Tolerances in the loop mean that the DN25D 3.3V 0.01�F 10�F 0.1�F 10�F 1.25V V REF OUT1 BOOST V LV DD CC REF OUT2 AIN1 0.01�F VARIABLES COMP REF IN AIN2 REFIN(+) 4.7�F DRIVE AIN3 0.1�F V CC REFIN(–) 1k� AIN4 CLOCK LATCH MICROCONTROLLER 1000pF DATA AD7709 GND AD421 CS LOOP DOUT POWER LOOP SCLK RTN COM DIN C1 C2 C3 GND Figure 23. Smart Transmitter Employing the AD7709 –28– REV. A AD7709 OUTLINE DIMENSIONS 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8� 0.75 0.30 0� 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD REV. A –29– AD7709 Revision History Location Page 3/03—Data Sheet changed from REV. 0 to REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to Communications Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Table VIII. Filter Register Bit Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 –30– REV. A –31– –32– PRINTED IN U.S.A. C02700–0–3/03(A)