ANALOG DEVICES AD7707

3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC AD7707 FEATURES FUNCTIONAL BLOCK DIAGRAM DV AV DD DD REF IN(–) REF IN(+) Charge balancing ADC AD7707 16 bits, no missing codes ±0.003% nonlinearity CHARGE BALANCING High level (±10 V) and low level (±10 mV) input channels A/D CONVERTER AIN1 True bipolar ±100 mV capability on low level input AIN2 Σ-Δ BUF PGA MUX MODULATOR LOCOM Channels without requiring charge pumps 30kΩ A = 1 ≈ 128 Programmable gain front end AIN3 DIGITAL FILTER 5kΩ Gains from 1 to 128 VBIAS 5kΩ 3-wire serial interface SPI, QSPI™, MICROWIRE™ and DSP compatible 15kΩ HICOM Schmitt trigger input on SCLK SERIAL INTERFACE 30kΩ Ability to buffer the analog input REGISTER BANK SCLK 2.7 V to 3.3 V or 4.75 V to 5.25 V operation CS Power dissipation 1 mW at 3 V MCLK IN DIN CLOCK Standby current 8 μA maximum GENERATION MCLK OUT DOUT 20-lead SOIC and TSSOP packages GENERAL DESCRIPTION AGND DGND DRDY RESET Figure 1. The AD7707 is a complete analog front end for low frequency measurement applications. This 3-channel device can accept for 3-wire operation. Gain settings, signal polarity and update either low level input signals directly from a transducer or high rate selection can be configured in software using the input level (±10 V) signals and produce a serial digital output. It employs serial port. The part contains self-calibration and system calibra- a Σ-Δ conversion technique to realize up to 16 bits of no missing tion options to eliminate gain and offset errors on the part itself codes performance. The selected input signal is applied to a or in the system. proprietary programmable gain front end based around an analog CMOS construction ensures very low power dissipation, and the modulator. The modulator output is processed by an on-chip power-down mode reduces the standby power consumption to digital filter. The first notch of this digital filter can be pro- 20 μW typical. This part is available in a 20-lead wide body (0.3 grammed via an on-chip control register allowing adjustment inch) small outline (SOIC) package and a low profile 20-lead TSSOP. of the filter cutoff and output update rate. PRODUCT HIGHLIGHTS The AD7707 operates from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply. The AD7707 features two low level pseudo differen- 1. The AD7707 consumes less than 1 mW at 3 V supplies and tial analog input channels, one high level input channel and a 1 MHz master clock, making it ideal for use in low power differential reference input. Input signal ranges of 0 mV to 20 mV systems. Standby current is less than 8 μA. through 0 V to 2.5 V can be accommodated on both low level input 2. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V to 10 V, channels when operating with a VDD of 5 V and a reference of and 0 V to 5 V high level input signals to be directly accom- 2.5 V. They can also handle bipolar input signal ranges of ±20 mV modated on the analog inputs without requiring split supplies through ±2.5 V, which are referenced to the LCOM input. The or charge-pumps. AD7707, with a 3 V supply and a 1.225 V reference, can handle 3. The low level input channels allow the AD7707 to accept unipolar input signal ranges of 0 mV to 10 mV through 0 V to input signals directly from a strain gage or transducer 1.225 V. Its bipolar input signal ranges are ±10 mV through ±1.225 V. removing a considerable amount of signal conditioning. 4. The part features excellent static performance specifications The high level input channel can accept input signal ranges of ±10 V, with 16 bits, no missing codes, ±0.003% accuracy, and low ±5 V, 0 V to 10 V and 0 V to 5 V. The AD7707 thus performs all rms noise. Endpoint errors and the effects of temperature signal conditioning and conversion for a 3-channel system. drift are eliminated by on-chip calibration options, which The AD7707 is ideal for use in smart, microcontroller or DSP- remove zero-scale and full-scale errors. based systems. It features a serial interface that can be configured Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08691-001 AD7707 TABLE OF CONTENTS Features .............................................................................................. 1  Span and Offset Limits on the Low Level Input Channels, AIN1 and AIN2 .......................................................................... 31  General Description ......................................................................... 1  Span and Offset Limits on the High Level Input Channel Functional Block Diagram .............................................................. 1  AIN3 ............................................................................................. 31  Product Highlights ........................................................................... 1  Power-Up and Calibration ........................................................ 32  Revision History ............................................................................... 3  Using the AD7707 .......................................................................... 33  Specif ica t ions ..................................................................................... 4  Clocking and Oscillator Circuit ............................................... 33  Timing Characteristics ................................................................ 8  System Synchronization ............................................................ 33  Absolute Maximum Ratings ............................................................ 9  Reset Input .................................................................................. 34  ESD Caution .................................................................................. 9  Standby Mode ............................................................................. 34  Pin Configuration and Function Descriptions ........................... 10  Accuracy ...................................................................................... 34  Typical Performance Characteristics ........................................... 12  Drift Considerations .................................................................. 34  OVtput Noise .................................................................................. 14  Power Supplies ................................................................................ 35  Output Noise For Low Level Input Channels Supply Current ............................................................................ 35  (5 V Operation) .......................................................................... 14  Grounding and Layout .............................................................. 35  Output Noise For Low Level Input Channels (3 V Operation) .......................................................................... 15  Digital Interface .............................................................................. 36  Output Noise For High Level Input Channel AIN3 Configuring the AD7707 ............................................................... 37  (5 V Operation) .......................................................................... 16  Microcomputer/Microprocessor Interfacing .............................. 39  Output Noise For High Level Input Channel AIN3 AD7707to68HC11 Interface .................................................. 39  (3 V Operation) .......................................................................... 17  AD7707to8XC51 Interface ..................................................... 40  On-Chip Registers .......................................................................... 18  Code For Setting Up the AD7707 ................................................ 41  Communications Register (RS2, RS1, RS0 = 0, 0, 0) ............. 18  C Code for Interfacing AD7707 to 68HC11 ........................... 41  Calibration Sequences .................................................................... 23  Applications Information .............................................................. 43  Circuit Description ......................................................................... 24  Data Acquisition ......................................................................... 43  Analog Input ................................................................................... 25  Smart Valve/Actuator Control .................................................. 43  Analog Input Ranges .................................................................. 25  Pressure Measurement ............................................................... 45  Input Sample Rate ...................................................................... 26  Thermocouple Measurement ................................................... 45  Bipolar/Unipolar Inputs ............................................................ 26  RTD Measurement ..................................................................... 45  Reference Input ............................................................................... 27  Chart Recorders .......................................................................... 46  Digital Filtering ............................................................................... 28  Accommodating Various High Level Input Ranges .............. 46  Filter Characteristics .................................................................. 28  Typical Input Currents ............................................................... 46  Postfiltering ................................................................................. 29  Output Noise For High Level Input Channel, AIN3 ................. 47  Analog Filtering .......................................................................... 29  5 V Operation ............................................................................. 47  Calibration ....................................................................................... 30  3 V Operation ............................................................................. 48  Self-Calibration ........................................................................... 30  Outline Dimensions ....................................................................... 49  System Calibration ..................................................................... 30  Ordering Guide .......................................................................... 50  Rev. B | Page 2 of 52 AD7707 REVISION HISTORY 1/10—Rev. A to Rev B Deleted Evaluating the AD7707 Performance Section .............. 27 Updated Format .................................................................. Universal Changes to Digital Filtering Section and Changes to Features Section ............................................................ 1 Filter Characteristics Section ......................................................... 28 Changes to Table 1 ...................................................................................... 4 Deleted AD7707 to ADSP-2103/ADSP-2105 Interface Changes to Table 5 ............................................................................ 9 Section .............................................................................................. 31 Changes to Output Noise For Low Level Input Channels Deleted Figure 23; Renumbered Sequentially ............................. 31 Moved Figure 18 .............................................................................. 33 (3 V Operation) Section ................................................................. 14 Changes to Output Noise For High Level Input Channel AIN3 Changes to Figure 19 and Supply Current Section ..................... 35 (5 V Operation) Section ................................................................. 15 Change to Smart Valve/Actuator Control Section and Changed Output Noise For High Level Input Channel AIN3 Figure 25 ........................................................................................... 43 (5 V Operation) Section Heading to Output Noise For High Changes to Figure 27 ...................................................................... 44 Level Input Channel AIN3 (3 V Operation) ............................... 17 Added Titles to Table 28, Table 29, and Table 30 ........................ 46 Changes to Table 16 ........................................................................ 19 Updated Outline Dimensions ........................................................ 49 Changes to Zero-Scale Calibration Register (RS2, RS1, RS0 = Changes to Ordering Guide ........................................................... 50 1, 1, 0); Power-On/Reset Status: 0x1F4000 Section .................... 22 Changes to Calibration Sequences Section .................................. 23 2/00—Rev. 0 to Rev. A Changes to Circuit Description Section ....................................... 24 Rev. B | Page 3 of 52 AD7707 SPECIFICATIONS AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter B Version Unit Conditions/Comments STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise Depends on filter cutoffs and selected gain See Table 7 to Table 10 2 Integral Nonlinearity ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% 3 Unipolar Offset Error 4 Unipolar Offset Drift 0.5 μV/°C typ 3 Bipolar Zero Error 4 Bipolar Zero Drift 0.5 μV/°C typ For gains of 1, 2, and 4 0.1 μV/°C typ For gains of 8, 16, 32, 64, and 128 3, 5 Positive Full-Scale Error 4, 6 Full-Scale Drift 0.5 μV/°C typ 3, 7 Gain Error 4, 8 Gain Drift 0.5 ppm of FSR/°C typ 2 ±0.003 % of FSR max Typically ±0.0007% Bipolar Negative Full-Scale Error 4 1 μV/°C typ For gains of 1 to 4 Bipolar Negative Full-Scale Drift 0.6 μV/°C typ For gains of 8 to 128 HIGH LEVEL INPUT CHANNEL (AIN3) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise See Table 11 to Depends on filter cutoffs and selected gain Table 13 2 ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% Integral Nonlinearity 9 Unipolar Offset Error ±10 mV max Typically within ±1.5 mV Unipolar Offset Drift 4 μV/°Ctyp 9 Bipolar Zero Error ±10 mV max Typically within ±1.5 mV Bipolar Zero Drift 4 μV/°C typ For gains of 1, 2, and 4 1 μV/°C typ For gains of 8, 16, 32, 64, and 128 Gain Error ±0.2 % typ Typically within ±0.05% Gain Drift 0.5 ppm of FSR/°C typ 2 ±0.0012 % of FSR typ Negative Full-Scale Error LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN, unless otherwise noted 2 Low level input channels, AIN1 and AIN2 Input Common-Mode Rejection (CMR) AV = 5 V DD Gain = 1 100 dB typ Gain = 2 105 dB typ Gain = 4 110 dB typ Gain = 8 to 128 130 dB typ AV = 3 V DD Gain = 1 105 dB typ Gain = 2 110 dB typ Gain = 4 120 dB typ Gain = 8 to 128 130 dB typ 2 98 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × f Normal-Mode 50 Hz Rejection NOTCH 2 Normal-Mode 60 Hz Rejection 98 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH 2 Common-Mode 50 Hz Rejection 150 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Rev. B | Page 4 of 52 AD7707 1 Parameter B Version Unit Conditions/Comments 2 Common-Mode 60 Hz Rejection 150 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × fNOTCH 2 Absolute/Common-Mode REF IN Voltage AGND to AVDD V min to V max 2, 10 Absolute/Common-Mode AIN Voltage AGND – 100 mV V min BUF bit of setup register = 0 AV + 30 mV V max DD AGND + 50 mV V min BUF bit of setup register = 1 AV − 1.5 V V max DD 2 AIN DC Input Current 1 nA max 2 10 pF max BUF = 0 AIN Sampling Capacitance 11, 12 AIN Differential Voltage Range 0 to +V/gain V nom REF Unipolar input range (B/U bit of setup register = 1) ±VREF/gain V nom Bipolar input range (B/U bit of setup register = 0) AIN Input Sampling Rate, fS Gain × fCLKIN/64 Hz nom For gains of 1 to 4 f /8 For gains of 8 to 128 CLKIN Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/max AVDD = 2.7 V to 3.3 V; VREF = 1.225 V ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/max AVDD = 4.75 V to 5.25 V; VREF = 2.5 V ± 1% for specified performance REF IN Input Sampling Rate, f f/64 S CLKIN ±100 mV INPUT RANGE Low level input channels, AIN1 and AIN2; gain = 16, unbuffered mode 2 ±0.003 % of FSR max Filter notch < 60 Hz INL 2 Input Common-Mode Rejection (CMR) 80 dB typ 2 Power Supply Rejection (PSR) 90 dB typ HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 is with respect to HICOM AIN3 Voltage Range +10 V max −10 V min Normal Mode 50 Hz Rejection 78 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × f NOTCH Normal Mode 60 Hz Rejection 78 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH AIN3 Input Sampling Rate, f Gain × f /64 Hz nom For gains of 1 to 4 S CLKIN f /8 Hz nom For gains of 8 to 128 CLKIN 2 AIN3 Input Impedance 27 kΩ min Typically 30 kΩ ± 10%; typical resistor Tempco is −30 ppm/°C 2 AIN3 Sampling Capacitance 10 pF max VBIAS Input Range 0 V/AV V min/max Typically REFIN(+) = 2.5 V DD LOGIC INPUTS Input Current All Inputs Except MCLK IN ±1 μA max Typically ±20 nA MCLK ±10 μA max Typically ±2 m A All Inputs Except SCLK and MCLK IN V , Input Low Voltage 0.8 V max DV = 5 V INL DD 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V max DVDD = 3 V and 5 V SCLK Only (Schmitt Triggered Input) DV = 5 V nominal DD VT+ 1.4/3 V min/V max V 0.8/1.4 V min/V max T− VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt Triggered Input) DVDD = 3 V nominal V 1/2.5 V min/V max T+ VT− 0.4/1.1 V min/V max V − V 0.375/0.8 V min /V max T+ T− Rev. B | Page 5 of 52 AD7707 1 Parameter B Version Unit Conditions/Comments MCLK IN Only DVDD = 5 V nominal V , Input Low Voltage 0.8 V max INL VINH, Input High Voltage 3.5 V min MCLK IN Only DV = 3 V nominal DD V , Input Low Voltage 0.4 V max INL VINH, Input High Voltage 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) 13 V , Output Low Voltage 0.4 V max I = 800 μA except for MCLK OUT ; DV = 5 V OL SINK DD 13 0.4 V max I = 100 μA except for MCLK OUT ; DV = 3 V SINK DD 13 V , Output High Voltage 4 V min OH ISOURCE = 200 μA except for MCLK OUT ; DVDD = 5 V 13 DV − 0.6 V min DD ISOURCE = 100 μA except for MCLK OUT ; DVDD = 3 V Floating State Leakage Current ±10 μA max 14 Floating State Output Capacitance 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) 15 Positive Full-Scale Calibration Limit (1.05 × V max Gain is the selected PGA gain (1 to 128) V )/gain REF 15 Negative Full-Scale Calibration Limit −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain 16 Offset Calibration Limit −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain 16 (0.8 × V )/gain V min Gain is the selected PGA gain (1 to 128) Input Span REF (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) High Level Input Channels (AIN3) 15 Positive Full-Scale Calibration Limit (8.4 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) 15 Negative Full-Scale Calibration Limit −(8.4 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain 16 −(8.4 × V max Gain is the selected PGA gain (1 to 128) Offset Calibration Limit VREF)/gain 16 Input Span (6.4 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (16.8 × V max Gain is the selected PGA gain (1 to 128) V )/gain REF POWER REQUIREMENTS Power Supply Voltages AVDD Voltage 2.7 to 3.3 or 4.75 to 5.25 V min to V max For specified performance DVDD Voltage 2.7 to 5.25 V min to V max For specified performance Power Supply Currents AV Current AV = 3 V or 5 V; gain = 1 to 4 DD DD 0.27 mA max Typically 0.22 mA; BUF = 0; fCLK IN = 1 MHz or 2.4576 MHz 0.6 mA max Typically 0.45 mA; BUF = 1; f = 1 MHz or 2.4576 MHz CLK IN AVDD = 3 V or 5 V; gain = 8 to 128 0.5 mA max Typically 0.38 mA; BUF = 0; fCLK IN = 2.4576 MHz 1.1 mA max Typically 0.81 mA; BUF = 1; f = 2.4576 MHz CLK IN POWER REQUIREMENTS (Continued) 17 DVDD Current Digital inputs = 0 V or DVDD; external MCLK IN 0.080 mA max Typically 0.06 mA; DV = 3 V; f = 1 MHz DD CLK IN 0.15 mA max Typically 0.13 mA; DV = 5 V; f = 1 MHz DD CLK IN 0.18 mA max Typically 0.15 mA; DVDD = 3 V; fCLK IN = 2.4576 MHz 0.35 mA max Typically 0.3 mA; DV = 5 V; f = 2.4576 MHz DD CLK IN 18, 19 Power Supply Rejection dB typ Rev. B | Page 6 of 52 AD7707 1 Parameter B Version Unit Conditions/Comments 17 Normal Mode Power Dissipation AVDD = DVDD = 3 V; digital inputs = 0 V or DVDD; external MCLK IN excluding dissipation in the AIN3 attenuator 1.05 mW max Typically 0.84 mW; BUF = 0; fCLK IN = 1 MHz, all gains 2.04 mW max Typically 1.53 mW; BUF = 1; fCLK IN = 1 MHz; all gains 1.35 mW max Typically 1.11 mW; BUF = 0; f = 2.4576 MHz, CLK IN gain = 1 to 4 2.34 mW max Typically 1.9 mW; BUF = 1; f = 2.457 6 MHz; CLK IN gain = 1 to 4 17 Normal Mode Power Dissipation AVDD = DVDD = 5 V; digital inputs = 0 V or DVDD; external MCLKIN 2.1 mW max Typically 1.75 mW; BUF = 0; fCLK IN = 1 MHz; all gains 3.75 mW max Typically 2.9 mW; BUF = 1; f = 1 MHz; all gains CLK IN 3.1 mW max Typically 2.6 mW; BUF = 0; f = 2.4576 MHz CLK IN 4.75 mW max Typically 3.75 mW; BUF = 1; fCLK IN = 2.4576 MHz 20 Standby (Power-Down) Current 18 μA max External MCLK IN = 0 V or DV ; typically 9 μA; DD AVDD = 5 V 8 μA max External MCLK IN = 0 V or DV ; typically 4 μA; DD AV = 3 V DD 1 Temperature range as follows: B Version, −40°C to +85°C. 2 These numbers are established from characterization or design at initial product release. 3 A calibration is effectively a conversion so these errors are of the order of the conversion noise shown in Table 7 and Table 9 for the low level input channels AIN1 and AIN2. This applies after calibration at the temperature of interest. 4 Recalibration at any temperature removes these drift errors. 5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. 6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges. 7 Gain error does not include zero-scale errors. It is calculated as full-scale error—unipolar offset error for unipolar ranges and full-scale error—bipolar zero error for bipolar ranges. 8 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if POMZ
zero-scale calibrations were performed. 9 Error is removed following a system calibration. 10 This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AV + 30 mV or go more negative DD than AGND − 100 mV. Parts are functional with voltages down to AGND − 200 mV, but with increased leakage at high temperature. 11 The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with respect to the HCOM input on the high level input channel, AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD + 100 mV, or go more negative than GND − 100 mV for specified performance. Input voltages of AGND − 200 mV can be accommodated, but with increased leakage at high temperature. 12 VREF = REF IN(+) − REF IN(−). 13 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load. 14 Sample tested at +25°C to ensure compliance. 15 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. 16 These calibration and span limits apply provided that the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND − 
mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 17 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation varies depending on the crystal or resonator type (see the Clocking and Oscillator Circuit section). 18 Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter notches of 20 Hz or 60 Hz. 19 PSRR depends on both gain and AVDD. See Table 2 and Table 3. 20 If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA typical at 3 V. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see the Standby Mode section). Table 2. Low Level Input Channels, AIN1 and AIN2 Gain 1 2 4 8 to 128 AVDD = 3 V 86 78 85 93 AVDD = 5 V 90 78 84 91 Table 3. High Level Input Channel, AIN3 Gain 1 2 4 8 to 128 AVDD = 3 V 68 60 67 75 AV = 5 V 72 60 66 73 DD Rev. B | Page 7 of 52 AD7707 TIMING CHARACTERISTICS AVDD = DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; input logic = 0, Logic 1 = DVDD, unless otherwise noted. Table 4. Limit at TMIN, TMAX 1, 2 Parameter (B Version) Unit Conditions/Comments 3, 4 fCLKIN 400 kHz min Master clock frequency: crystal oscillator or externally supplied for specified performance 5 MHz max t 0.4 × t ns min Master clock input low time, t = 1/f CLKIN LO CLKIN CLKIN CLKIN t 0.4 × t ns min Master clock input high time CLKIN HI CLKIN t 500 × t ns nom 1 CLKIN DRDY high time t2 100 ns min RESET pulse width Read Operation t 0 ns min DRDY to CS setup time 3 t 120 ns min CS falling edge to SCLK rising edge setup time 4 5 t 0 ns min SCLK falling edge to data valid delay 5 80 ns max DVDD = 5 V 100 ns max DVDD = 3.0 V t6 100 ns min SCLK high pulse width t 100 ns min SCLK low pulse width 7 t 0 ns min CS rising edge to SCLK rising edge hold time 8 6 t 10 ns min Bus relinquish time after SCLK rising edge 9 60 ns max DVDD = 5 V 100 ns max DVDD = 3.0 V 7 t 100 ns max SCLK falling edge to DRDY high 10 Write Operation t 120 ns min CS falling edge to SCLK rising edge setup time 11 t12 30 ns min Data valid to SCLK rising edge setup time t13 20 ns min Data valid to SCLK rising edge hold time t14 100 ns min SCLK high pulse width t 100 ns min SCLK low pulse width 15 t 0 ns min CS rising edge to SCLK rising edge hold time 16 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 2 See Figure 20 and Figure 21. 3 f duty cycle range is 45% to 55%. f must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw CLKIN CLKIN higher current than specified and possibly become uncalibrated. 4 The AD7707 is production tested with f at 2.4576 MHz (1 MHz for some I tests). It is guaranteed by characterization to operate at 400 kHz. CLKIN DD 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subsequent reads do not occur close to the next output update. I (800µA AT V = 5V SINK DD 100µA AT V = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA AT V = 5V SOURCE DD 100µA AT V = 3V) DD Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 8 of 52 08691-002 AD7707 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings TA = +25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to AGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect AV to DGND −0.3 V to +7 V DD device reliability. DVDD to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V AVDD to DVDD −0.3 V to +7 V ESD CAUTION DGND to AGND −0.3 V to +0.3 V AIN1, AIN2 Input Voltage to LOCOM −0.3 V to AV + 0.3 V DD AIN3 Input Voltage to HICOM −11 V to +30 V VBIAS to AGND −0.3 V to AVDD + 0.3 V HICOM, LOCOM to AGND −0.3 V to AVDD + 0.3 V REF IN(+), REF IN(−) to AGND −0.3 V to AV + 0.3 V DD Digital Input Voltage to DGND −0.3 V to DV + 0.3 V DD Digital Output Voltage to DGND −0.3 V to DV + 0.3 V DD Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOIC Package, Power Dissipation 450 mW θ Thermal Impedance 75°C/W JA Lead Temperature, Soldering Reflow 260°C TSSOP Package, Power Dissipation 450 mW θ Thermal Impedance 139°C/W JA Lead Temperature, Soldering Reflow 260°C ESD Rating 2.5 kV Rev. B | Page 9 of 52 AD7707 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 20 DGND MCLK IN 2 19 DV DD MCLK OUT 3 18 DIN CS 4 17 DOUT AD7707 RESET 5 16 DRDY TOP VIEW AV 6 15 AGND DD (Not to Scale) AIN1 7 14 REF IN(–) LOCOM 8 13 REF IN(+) AIN2 9 12 VBIAS AIN3 10 11 HICOM Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock, Schmitt-Triggered Logic Input. An external serial clock is applied to this input to access serial data from the AD7707. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7707 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part can be operated with clock frequencies in the range of 500 kHz to 5 MHz. 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuitry and is capable of driving one CMOS load. If the user does not require it, this MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the part is not wasting unnecessary power driving capacitive loads on MCLK OUT. 4 CS Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7707. 5 RESET Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients, digital filter, and analog modulator of the part to power-on status. 6 AVDD Analog Supply Voltage, 2.7 V to 5.25 V Operation. 7 AIN1 Low Level Analog Input Channel 1. This is used as a pseudo differential input with respect to LOCOM. 8 LOCOM Common Input for Low Level Input Channels. Analog inputs on AIN1 and AIN2 must be referenced to this input. 9 AIN2 Low Level Analog Input Channel 2. This is used as a pseudo differential input with respect to LOCOM. 10 AIN3 Single-Ended High Level Analog Input Channel with respect to HICOM. 11 HICOM Common Input for )igh -evel *nput $hannel. Analog input on AIN3 must be referenced to this input. 12 VBIAS VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that the AIN(+) and AIN(−) signals seen by the internal modulator are within its common-mode range. VBIAS is normally connected to 2.5 V when AV = 5 V and 1.225 V when AV = 3 V. DD DD 13 REF IN(+) Reference Input. Positive input of the differential reference input to the AD7707. The reference input is differential with the provision that REF IN(+) must be greater than REF IN(−). REF IN(+) can lie anywhere between AVDD and AGND. 14 REF IN(−) Reference Input. Negative input of the differential reference input to the AD7707. The REF IN(−) can lie anywhere between AV and AGND provided that REF IN(+) is greater than REF IN(−). DD 15 AGND Analog Ground. Ground reference point for the AD7707’s internal analog circuitry. 16 DRDY Logic Output. A logic low on this output indicates that a new output word is available from the AD7707 data register. The DRDY pin returns high upon completion of a read operation of a full output word. If no data read has taken place between output updates, the DRDY line returns high for 500 × tCLK IN cycles prior to the next output update. While DRDY is high, a read operation should neither be attempted nor in progress to avoid reading from the data register as it is being updated. The DRDY line returns low again when the update has taken place. DRDY is also used to indicate when the AD7707 has completed its on-chip calibration sequence. 17 DOUT Serial Data Output with Serial Data Being Read from the Output Shift Register on the Part. This output shift register can contain information from the setup register, communications register, clock register, or data register, depending on the register selection bits of the communications register. Rev. B | Page 10 of 52 08691-003 AD7707 Pin No. Mnemonic Description 18 DIN Serial Data Input with Serial Data Being Written to the Input Shift Register on the Part. Data from this input shift register is transferred to the setup register, clock register, or communications register, depending on the register selection bits of the communications register. 19 DVDD Digital Supply Voltage, 2.7 V to 5.25 V Operation. 20 DGND Ground Reference Point for the AD7707’s Internal Digital Circuitry. Rev. B | Page 11 of 52 AD7707 TYPICAL PERFORMANCE CHARACTERISTICS 32,771 400 V = 5V T = 25°C DD A V = 2.5V RMS NOISE = 600nV REF 32,770 GAIN = 128 50Hz UPDATE RATE 32,769 300 32,768 200 32,767 32,766 32,765 100 32,764 32,763 0 0100 200 300 400 500 600 700 800 900 1000 32,764 32,765 32,766 32,767 32,768 32,769 32,770 READING NUMBER CODE Figure 4. Typical Noise Plot at Gain = 128 with 50 Hz Update Rate for Low Figure 7. Histogram of Data in Figure 4 Level Input Channel 32,769 800 10Hz UPDATE RATE, UNBUFFERED MODE 10Hz UPDATE RATE GAIN = 2 (±10V INPUT RANGE) UNBUFFERED MODE 700 BIPOLAR MODE BIPOLAR MODE ANALOG INPUT SET ON CODE TRANSITION GAIN = 2 (±10V INPUT RANGE) 600 32,768 500 400 32,767 300 200 100 32,766 0 200 400 600 800 1000 0 READING NUMBER 1 2 32,767 32,768 CODE Figure 5. Typical Noise Plot for AIN3, High Level Input Channel Figure 8. Histogram of Data in Figure 5 10 0.6 LOW LEVEL INPUT CHANNEL HIGH LEVEL INPUT CHANNEL ±10V INPUT RANGE GAIN = 128 9 10Hz UPDATE RATE 10Hz UPDATE RATE 0.5 8 7 0.4 BUFFERED MODE BUFFERED MODE 6 AV = DV = 5V DD DD REF IN(+) = 2.5V 5 0.3 REF IN(–) = AGND T = 25°C A UNBUFFERED MODE 4 0.2 3 UNBUFFERED MODE AV = DV = 5V DD DD REF IN(+) = 2.5V 2 0.1 REF IN(–) = AGND T = +25°C 1 A 0 0 –6 –2 2 6 10 –10 –20 –15 –10 –5 0 5 10 15 20 AIN3 (V) INPUT VOLTAGE (mV) Figure 6. Typical RMS Noise vs. Analog Input Voltage for High Level Input Figure 9. Typical RMS Noise vs. Analog Input Voltage for Low Level Input Channel, AIN3 Channels, AIN1 and AIN2 Rev. B | Page 12 of 52 CODE CODE READ RMS NOISE (µV) 08691-006 08691-004 08691-005 OCCURRENCE RMS NOISE (µV) OCCURRENCE 08691-008 08691-009 08691-007 AD7707 20 TEK STOP: SINGLE SEQ 50.0kSPS V DD 16 1 MCLK IN = 0V OR V DD 12 2 V = 5V DD OSCILLATOR = 4.9152MHz 8 V = 3V DD 4 2 OSCILLATOR = 2.4576MHz 0 CH1 5.00V CH2 2.00V 5ms/DIV –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 10. Typical Crystal Oscillator Power-Up Time Figure 11. Standby Current vs. Temperature Rev. B | Page 13 of 52 08691-010 STANDBY CURRENT (µA) 08691-011 AD7707 OUTPUT NOISE typical and are rounded to the nearest LSB. The numbers apply OUTPUT NOISE FOR LOW LEVEL INPUT for the CLKDIV bit of the clock register set to 0. The output CHANNELS (5 V OPERATION) noise comes from two sources. The first is the electrical noise in Table 7 shows the AD7707 output rms noise and peak-to-peak the semiconductor devices (device noise) used in the resolution in unbuffered mode for the selectable notch and implementation of the modulator. Secondly, when the analog −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 input is converted into the digital domain, quantization noise is of the clock register. The numbers given are for the bipolar added. The device noise is at a low level and is independent of input ranges with a V of 2.5 V and AV = 5 V. These REF DD frequency. The quantization noise starts at an even lower level numbers are typical and are generated at an analog input voltage of but rises rapidly with increasing frequency to become the 0 V. Table 8 shows the rms noise and peak-to-peak resolution dominant noise source. The numbers in Table 7 and Table 8
are when operating in buffered mode. It is important to note that given for the bipolar input ranges. For the unipolar ranges, the the peak-to-peak numbers represent the resolution for which rms noise numbers are the same as the bipolar range but the there is no code flicker. They are not calculated based on rms peak-to-peak resolution is now based on half the signal range, noise but on peak-to-peak noise. The numbers given are for which effectively means losing one bit of resolution. bipolar input ranges with a V of 2.5 V. These numbers are REF Table 7. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Unbuffered Mode Only Filter First Notch Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) and Output Data −3 dB Rate Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 1.2 (16) 0.7 (16) 0.7 (16) 0.54 (16) 0.28 (16) 0.28 (16) 0.28 (15.5) 0.27 (14.5) 50 Hz 13.1 Hz 3.6 (16) 2.1 (16) 1.25 (16) 0.89 (16) 0.62 (16) 0.60 (15.5) 0.56 (14.5) 0.56 (13.5) 60 Hz 15.72 Hz 4.7 (16) 2.6 (16) 1.5 (16) 0.94 (16) 0.73 (16) 0.68 (15.5) 0.66 (14.5) 0.63 (13.5) 250 Hz 65.5 Hz 95 (13) 65 (13) 23.4 (13) 11.6 (13) 6.5 (13) 3.4 (13) 2.1 (12.5) 1.5 (12) 500 Hz 131 Hz 600 (10.5) 316 (10.5) 138 (10.5) 71 (10.5) 38 (10.5) 18 (10.5) 10 (10) 5.7 (10) MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 1.19 (16) 0.69 (16) 0.71 (16) 0.63 (16) 0.27 (16) 0.27 (16) 0.26 (15.5) 0.24 (15) 20 Hz 5.24 Hz 3.68 (16) 2.18 (16) 1.19 (16) 0.94 (16) 0.6 (16) 0.6 (15.5) 0.56 (14.5) 0.56 (13.5) 25 Hz 6.55 Hz 4.78 (16) 2.66 (16) 1.51 (16) 1.07 (16) 0.7 (16) 0.67 (15.5) 0.66 (14.5) 0.65 (13.5) 100 Hz 26.2 Hz 100 (13) 50.1 (13) 23.5 (13) 11.9 (13) 5.83 (13) 3.64 (13) 2.16 (12.5) 1.5 (12) 200 Hz 52.5 Hz 543 (10.5) 318 (10.5) 132 (10.5) 68.1 (10.5) 33.1 (10.5) 17.6 (10.5) 9.26 (10.5) 6.13 (10) Table 8. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN1 and AIN2 Buffered Mode Only Filter First Notch Typical Output RMS /oise in μV (Peak-to-Peak Resolution in Bits) and Output Data −3 dB Rate Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 1.47 (16) 0.95 (16) 0.88 (16) 0.55 (16) 0.42 (16) 0.42 (16) 0.42 (15) 0.41 (14) 50 Hz 13.1 Hz 4.2 (16) 2.6 (16) 1.6 (16) 1 (16) 0.89 (15.5) 0.94 (15) 0.9 (14) 0.9 (13) 60 Hz 15.72 Hz 4.9 (16) 3 (16) 1.8 (16) 1.1 (16) 1 (15.5) 1 (14.5) 0.94 (14) 0.94 (13) 250 Hz 65.5 Hz 104 (13) 52 (13) 26 (13) 14 (13) 6.5 (13) 4.1 (12.5) 2.7 (12.5) 2.3 (11.5) 500 Hz 131 Hz 572 (10.5) 293 (10.5) 125 (10.5) 69 (10.5) 40 (10.5) 19 (10.5) 10 (10.5) 5.9 (10) MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 1.48 (16) 8.95 (16) 0.87 (16) 0.67 (16) 0.41 (16) 0.40 (16) 0.40 (15) 0.40 (14) 20 Hz 5.24 Hz 3.9 (16) 2.46 (16) 1.77 (16) 1.19 (16) 0.94 (16) 0.93 (15) 0.95 (14) 0.9 (13) 25 Hz 6.55 Hz 5.37 (16) 3.05 (16) 1.89 (16) 1.33 (16) 1.11 (15.5) 1.06 (14.5) 1.04 (13.5) 1.02 (12.5) 100 Hz 26.2 Hz 98.9 (13) 52.4 (13) 26.1 (13) 12.7 (13) 6.08 (13) 4.01 (12.5) 2.62 (12.5) 2.33 (11.5) 200 Hz 52.4 Hz 596 (10.5) 298 (10.5) 133 (10.5) 69.3 (10.5) 34.7 (10.5) 16.9 (10.5) 9.67 (10.5) 6.34 (10) Rev. B | Page 14 of 52 AD7707 are rounded to the nearest LSB. The numbers apply for the OUTPUT NOISE FOR LOW LEVEL INPUT CLKDIV bit of the clock register set to 0. The output noise CHANNELS (3 V OPERATION) comes from two sources. The first is the electrical noise in the Table 9 shows the AD7707 output rms noise and peak-to-peak semiconductor devices (device noise) used in the implementa- resolution in unbuffered mode for the selectable notch and tion of the modulator. Secondly, when the analog input is −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 converted into the digital domain, quantization noise is added. of the clock register. The numbers given are for the bipolar The device noise is at a low level and is independent of fre- input ranges with a VREF of 1.225 V and an AVDD = 3 V. These quency. The quantization noise starts at an even lower level but numbers are typical and are generated at an analog input rises rapidly with increasing frequency to become the dominant voltage of 0 V. Table 10 shows the rms noise and peak-to-peak noise source. The numbers in Table 9 and Table 10 are given resolution when operating in buffered mode. It is important to for the bipolar input ranges. For the unipolar ranges, the rms note that the peak-to-peak numbers represent the resolution for noise numbers are the same as the bipolar range but the peak- which there is no code flicker. They are not calculated based on to-peak resolution is now based on half the signal range, which rms noise but on peak-to-peak noise. The numbers given are effectively means losing 1 bit of resolution. for bipolar input ranges with a VREF of 1.225 V and for either buffered or unbuffered mode. These numbers are typical and Table 9. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Unbuffered Mode Only Filter First Notch Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) and Output Data −3 dB Rate Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 1.60 (16) 0.8 (16) 0.48 (16) 0.29 (16) 0.29 (16) 0.27 (15.5) 0.26 (14.5) 0.26 (13.5) 50 Hz 13.1 Hz 3.8 (16) 1.9 (16) 1.1 (16) 0.64 (16) 0.60 (15.5) 0.6 (14.5) 0.6 (13.5) 0.6 (12.5) 60 Hz 15.72 Hz 4.4 (16) 2.2 (16) 1.35 (16) 0.78 (16) 0.7 (15) 0.68 (14.5) 0.64 (13.5) 0.64 (12.5) 250 Hz 65.5 Hz 53 (13) 24 (13) 15 (13) 6.8 (13) 3.6 (12.5) 2.1 (12.5) 1.5 (12) 1.3 (11) 500 Hz 131 Hz 300 (10.5) 138 (10.5) 80 (10.5) 34 (10.5) 18 (10.5) 8.7 (10.5) 4.8 (10) 3.4 (10) MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 1.56 (16) 0.88 (16) 0.52 (16) 0.3 (16) 0.28 (16) 0.27 (15.5) 0.27 (14.5) 0.26 (13.5) 20 Hz 5.24 Hz 3.85 (16) 2.02 (16) 1.15 (16) 0.74 (16) 0.63 (15.5) 0.57 (14.5) 0.61 (13.5) 0.58 (12.5) 25 Hz 6.55 Hz 4.56 (16) 2.4 (16) 1.4 (16) 0.79 (16) 0.68 (15) 0.66 (14.5) 0.64 (13.5) 0.64 (12.5) 100 Hz 26.2 Hz 45.7 (13) 22 (13) 13.7 (13) 5.27 (13) 2.64 (13) 2 (12.5) 1.59 (12) 1.4 (11) 200 Hz 52.4 Hz 262 (10.5) 125 (10.5) 66 (10.5) 32.4 (10.5) 18.4 (10.5) 8.6 (10.5) 4.64 (10.5) 3.3 (10) Table 10. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V AIN1 and AIN2 Buffered Mode Only Filter First Notch Typical Output RMS Noise in μV (Peak-to-Peak Resolution in Bits) and Output Data −3 dB Rate Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 1.80 (16) 1 (16) 0.7 (16) 0.41 (16) 0.41 (16) 0.41 (15) 0.41 (14) 0.41 (13) 50 Hz 13.1 Hz 4.1 (16) 2.4 (16) 1.5 (16) 1 (15.5) 0.91 (15) 0.89 (14) 0.86 (13) 0.83 (12) 60 Hz 15.72 Hz 5.1 (16) 3 (16) 1.8 (16) 1.1 (15.5) 0.94 (14.5) 0.94 (13.5) 0.99 (13) 0.99 (11.5) 250 Hz 65.5 Hz 50 (13) 27 (13) 12.3 (13) 6.4 (13) 4 (12.5) 2.7 (12.5) 2.2 (11.5) 1.8 (11) 500 Hz 131 Hz 275 (10.5) 125 (10.5) 80 (10.5) 39 (10.5) 16 (10.5) 8.9 (10.5) 5.2 (10) 4.2 (9.5) MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 1.75 (16) 1.18 (16) 0.67 (16) 0.44 (16) 0.41 (16) 0.44 (15) 0.43 (14) 0.43 (13) 20 Hz 5.24 Hz 4.21 (16) 2.5 (16) 1.48 (16) 1 (15.5) 0.94 (15) 0.96 (14) 0.89 (13) 0.86 (12) 25 Hz 6.55 Hz 5.15 (16) 2.8 (16) 1.8 (16) 1.15 (15.5) 1 (14.5) 1.02 (13.5) 0.96 (13) 1.03 (11.5) 100 Hz 26.2 Hz 46.1 (13) 24.3 (13) 13.6 (13) 6.71 (13) 4.1 (12.5) 2.54 (12.5) 2.3 (11.5) 2.15 (10.5) 200 Hz 52.4 Hz 282 (10.5) 123 (10.5) 66 (10.5) 35.3 (10.5) 14.8 (10.5) 9.91 (10.5) 5.48 (10) 4.01 (9.5) Rev. B | Page 15 of 52 AD7707 bipolar mode gives the ±5 V operating range. Operating at a gain OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL of 4 in unipolar mode gives an operating range of 0 V to 5 V. AIN3 (5 V OPERATION) Noise for all input ranges is shown in Output Noise For High Level Table 11 shows the AD7707 output rms noise and peak-to-peak Input Channel, AIN3 section. The output noise comes from two resolution in unbuffered mode for the selectable notch and −3 dB sources. The first is the electrical noise in the semiconductor frequencies for the part, as selected by FS0, FS1, and FS2 of the devices (device noise) used in the implementation of the modula- clock register. The numbers given are for the ±10 V, ±5 V, 0 to tor. Secondly, when the analog input is converted into the digital 5 V and 0 V to 10 V ranges with a VREF of 2.5 V, VBIAS = 2.5 V, domain, quantization noise is added. The device noise is at a low HICOM = AGND, and AV = 5 V. These numbers are typical DD level and is independent of frequency. The quantization noise and are generated at an analog input voltage of 0 V. Table 12 starts at an even lower level but rises rapidly with increasing meanwhile shows the output rms noise and peak-to-peak frequency to become the dominant noise source. The numbers resolution in buffered mode. It is important to note that these in Table 11 and Table 12 are given for the bipolar input ranges. numbers represent the resolution for which there is no code For the unipolar ranges the rms noise numbers are the same as flicker. They are not calculated based on rms noise, but on the bipolar range, but the peak-to-peak resolution is now based peak-to-peak noise. Operating the high level channel with a on half the signal range, which effectively means losing 1 bit of gain of 2 in bipolar mode gives an operating range of ±10 V. resolution. Operating at a gain of 2 in unipolar mode gives a range of 0 V to +10 V. Operating the high level channel with a gain of 4 in Table 11. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Unbuffered Mode Only ±10 V Range ±5 V Range 0 V to 10 V Range 0 V to 5 V Range Filter First Notch and Output Data −3 dB RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS P-P (Bits) Rate Frequency (μV) Resolution (μV) Resolution (μV) Resolution Noise (μV) Resolution MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 5.10 16 3.52 16 5.10 16 3.52 16 50 Hz 13.1 Hz 15.82 16 9.77 16 15.82 16 9.77 16 60 Hz 15.72 Hz 20.36 16 12.29 16 20.36 16 12.29 16 250 Hz 65.5 Hz 430 13 212 13 430 12 212 12 500 Hz 131 Hz 2350 10 1287 10 2350 9 1287 9 MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 5.13 16 3.53 16 5.13 16 3.53 16 20 Hz 5.24 Hz 18.9 16 13.25 16 18.9 16 13.25 16 25 Hz 6.55 Hz 23.7 16 15.3 16 23.7 16 15.3 15.5 100 Hz 26.2 Hz 406 13 174 13 406 12 174 12 200 Hz 52.4 Hz 2184 10.5 1144 10.5 2184 9.5 1144 9.5 Table 12. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V AIN3 Buffered Mode Only ±10 V Range ±5 V Range 0 V to 10 V Range 0 to 5 V Range Filter First Notch RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) and Output Data −3 dB Rate Frequency (μV) Resolution (μV) Resolution (μV) Resolution (μV) Resolution MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 7.4 16 5.2 16 7.4 16 5.2 16 50 Hz 13.1 Hz 22.2 16 14.3 16 22.2 16 14.3 16 60 Hz 15.72 Hz 26.6 16 15.85 16 26.6 16 15.85 16 250 Hz 65.5 Hz 475 13 187 13 475 12 187 12 500 Hz 131 Hz 2423 10.5 1097 10.5 2423 9.5 1097 9.5 MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 7.63 16 5.45 16 7.63 16 5.45 16 20 Hz 5.24 Hz 20.25 16 13.3 16 20.25 16 13.3 16 25 Hz 6.55 Hz 23.5 16 14.6 16 23.5 16 14.6 15.5 100 Hz 26.2 Hz 377 13 210 13 377 12 210 12 200 Hz 52.4 Hz 2226 10.5 1132 10.5 2226 9.5 1132 9.5 Rev. B | Page 16 of 52 AD7707 0 V to +10 V. Operating the high level channel with a gain of 2 OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL in bipolar mode provides a ±5 V operating range. Operating at AIN3 (3 V OPERATION) a gain of 2 in unipolar mode provides an operating range of 0 V Table 13 shows the AD7707 output rms noise and peak-to-peak to 5 V. The output noise comes from two sources. The first is resolution for the selectable notch and −3 dB frequencies for the the electrical noise in the semiconductor devices (device noise) part, as selected by FS0, FS1, and FS2 of the clock register. The used in the implementation of the modulator. Secondly, when numbers given are for the ±5 V, 0 V to 5 V and 0 V to 10 V the analog input is converted into the digital domain, quantiza- ranges with a VREF of 1.225 V, VBIAS = 1.225 V, HICOM = tion noise is added. The device noise is at a low level and is AGND, and AV = 3 V. These numbers are typical and are DD independent of frequency. The quantization noise starts at an generated at an analog input voltage of 0 V for unbuffered mode even lower level but rises rapidly with increasing frequency to of operation. The ±5 V, 0 V to 5 V, and 0 V to 10 V operating become the dominant noise source. The numbers in Table 13 ranges are only achievable in unbuffered mode when operating are given for the bipolar input ranges. For the unipolar ranges, at 3 V due to common-mode limitations on the input amplifier. the rms noise numbers are the same as the bipolar range, but It is important to note that these numbers represent the the peak-to-peak resolution is now based on half the signal resolution for which there are no code flicker. They are not range, which effectively means losing 1 bit of resolution. calculated based on rms noise but on peak-to-peak noise. Operating at a gain of 1 in unipolar mode provides a range of Table 13. Output RMS Noise/Peak-to-Peak Resolution vs. Gain and Output Update Rate @ +3 V AIN3 Unbuffered Mode Only 0 V to 10 V Range ±5 V Range 0 to 5 V Range Filter First Notch RMS Noise P-P (Bits) RMS Noise P-P (Bits) RMS Noise P-P (Bits) and Output −3 dB Data Rate Frequency (μV) Resolution (μV) Resolution (μV) Resolution MCLK IN = 2.4576 MHz 10 Hz 2.62 Hz 12.4 16 7.02 16 7.02 16 50 Hz 13.1 Hz 30.35 16 16.4 16 16.4 15.5 60 Hz 15.72 Hz 34.55 16 19.13 16 19.13 15 250 Hz 65.5 Hz 498 12.5 204 13 204 12 500 Hz 131 Hz 2266 10.5 1151 10.5 1151 9.5 MCLK IN = 1 MHz 4.05 Hz 1.06 Hz 13.9 16 7.3 16 7.3 16 20 Hz 5.24 Hz 32.2 16 17.4 16 17.4 15 25 Hz 6.55 Hz 33.4 16 18.57 16 18.57 15 100 Hz 26.2 Hz 430 13 200 13 200 12 200 Hz 52.4 Hz 2207 10.5 1048 10.5 1048 9.5 Rev. B | Page 17 of 52 AD7707 ON-CHIP REGISTERS The AD7707 contains eight on-chip registers that can be the data register from which the output data from the part is accessed via the serial port of the part. The first of these is a accessed. The final registers are the calibration registers, which communications register that controls the channel selection, store channel calibration data. The registers are described in decides whether the next operation is a read or write operation more detail in the following sections. and selects which register the next read or write operation COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, accesses. All communications to the part must start with a write 0, 0) operation to the communications register. After power-on or The communications register is an 8-bit register from which RESET , the device expects a write to its communications register. data can either be read or to which data can be written. All The data written to this register determines whether the next communications to the part must start with a write operation to operation to the part is a read or a write operation and the communications register. The data written to the commu- determines to which register this read or write operation occurs. nications register determines whether the next operation is a Therefore, write access to any of the other registers on the part read or write operation and to which register this operation starts with a write operation to the communications register takes place. When the subsequent read or write operation to the followed by a write to the selected register. A read operation selected register is complete, the interface returns to where it from any other register on the part (including the communications expects a write operation to the communications register. This register itself and the data register) starts with a write operation is the default state of the interface, and on power-up or after a to the communications register followed by a read operation RESET, the AD7707 is in this default state waiting for a write from the selected register. The communications register also operation to the communications register. In situations where controls the standby mode and channel selection and the DRDY the interface sequence is lost, if a write operation of sufficient status is available by reading from the communications register. duration (containing at least 32 serial clock cycles) takes place The second register is a setup register that determines calibration with DIN high, the AD7707 returns to this default state. Table 14 mode, gain setting, bipolar/unipolar operation, and buffered outlines the bit designations for the communications register. mode. The third register is the clock register and contains the filter selection bits and clock control bits. The fourth register is Table 14. Communications Register 0/DRDY (0) RS2 (0) RS1 (0) RS0 (0) R/W (0) STBY (0) CH1 (0) CH0 (0) Table 15. Communications Register Bit Descriptions Bit Description 0/DRDY For a write operation, a 0 must be written to this bit so that the write operation to the communications register actually takes place. If a 1 is written to this bit, the part does not clock on to subsequent bits in the register. The serial interface stays at this bit location until a 0 is written to this bit. Once a 0 is written to this bit, the next seven bits are loaded to the communications register. For a read operation, this bit provides the status of the DRDY flag from the part. The status of this bit is the same as the DRDY output pin. RS2 to Register selection bits. These three bits select to which one of eight on-chip registers the next read or write operation takes RS0 place, as shown in Table 16, along with the register size. When the read or write operation to the selected register is complete, the part waits for a write operation to the communications register. It does not remain in a state where it continues to access the register. R/W Read/Write select. This bit selects whether the next operation is a read or write operation to the selected register. A 0 indicates a write cycle for the next operation to the appropriate register, while a 1 indicates a read operation from the appropriate register. STBY Standby. Writing a 1 to this bit puts the part into its standby or power-down mode. In this mode, the part consumes only 8 μA of power supply current. The part retains its calibration coefficients and control word information when in standby. Writing a 0 to this bit places the part in its normal operating mode. The serial interface on the AD7707 remains operational when the part is in standby mode. CH1, Channel select. These two bits select a channel for conversion or for access to the calibration coefficients as outlined in Table 17. CH0 Three pairs of calibration registers on the part are used to store the calibration coefficients following a calibration on a channel. They are shown in Table 17 for the AD7707 to indicate which channel combinations have independent calibration coefficients. With CH1 at Logic 1 and CH0 at a Logic 0, the part looks at the LOCOM input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the LOCOM input should be connected to an external voltage within the allowable common-mode range for the part. Rev. B | Page 18 of 52 AD7707 Table 16. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications register 8 bits 0 0 1 Setup register 8 bits 0 1 0 Clock register 8 bits 0 1 1 Data register 16 bits 1 0 0 Test register 8 bits 1 0 1 No operation 1 1 0 Zero-scale calibration register 24 bits 1 1 1 Full-scale calibration register 24 bits Table 17. Channel Selection for AD7707 CH1 CH0 AIN Reference Calibration Register Pair 0 0 AIN1 LOCOM Register Pair 0 0 1 AIN2 LOCOM Register Pair 1 1 0 LOCOM LOCOM Register Pair 0 1 1 AIN3 HICOM Register Pair 2 Rev. B | Page 19 of 52 AD7707 Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 The setup register is an eight-bit register from which data can either be read or to which data can be written. Table 18 outlines the bit designations for the setup register. Table 18. Setup Register MD1 (0) MD0 (0) G2 (0) G1 (0) G0 (0) B/U (0) BUF (0) FSYNC (1) Table 19. Bit Description MD1, MD0 Operating mode selection bits. G2 to G0 Gain selection bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 21. B/U Bipolar/unipolar operation. A 0 in this bit selects Bipolar operation. A 1 in this bit selects unipolar operation. BUF Buffer control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current flowing in the AVDD line is reduced. When this bit is high, the on-chip buffer is in series with the analog input allowing the input to handle higher source impedances. FSYNC Filter synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, and the calibration control logic are held in a reset state, and the analog modulator is held in its reset state. When this bit goes low, the modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), that is, the settling time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low. Table 20. Operating Modes MD1 MD0 Operating Mode 0 0 Normal mode: this is the normal mode of operation of the device whereby the device is performing normal conversions. 0 1 Self-calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the communications register. This is a one-step calibration sequence and, when complete, the part returns to normal mode with MD1 and MD0 returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this self- calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally-generated VREF/selected gain. 1 0 Zero-scale (ZS) system calibration: this activates zero-scale system calibration on the channel selected by CH1 and CH0 of the communications register. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to Oormal Node with MD1 and MD0 returning to 0, 0. 1 1 Full-scale (FS) system calibration: this activates full-scale system calibration on the selected input channel. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0. Table 21. Gain Selection G2 G1 G0 Gain Setting 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Rev. B | Page 20 of 52 AD7707 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 The clock register is an 8-bit register from which data can either be read or to which data can be written. Table 22 outlines the bit designations for the clock register. Table 22. Clock Register Zero (0) Zero (0) CLKDIS (0) CLKDIV (0) CLK (1) FS2 (0) FS1 (0) FS0 (1) Table 23. Clock Register Bit Descriptions Bit Description Zero Zero. A zero must be written to these bits to ensure correct operation of the AD7707. Failure to do so may result in unspecified operation of the device. CLKDIS Master clock disable bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock on the MCLK IN pin, the AD7707 continues to have internal clocks and converts normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take place when the CLKDIS bit is active. CLKDIV Clock divider bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two before being used internally by the AD7707. For example, when this bit is set to 1, the user can operate with a 4.9152 MHz crystal between MCLK IN and MCLK OUT, and internally the part operates with the specified 2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used internally by the part. CLK Clock bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set to a 1. If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit should be set to a 0. This bit sets up the appropriate scaling currents for a given operating frequency and also chooses (along with FS2, FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the master clock frequency of the device, then the AD7707 may not operate to specification. FS2, FS1, Filter selection bits. Along with the CLK bit, FS2, FS1, and FS0 determine the output update rate, filter first notch, and −3 dB 3 3 FS0 frequency as outlined in Table 24. The on-chip digital filter provides a sinc (or Sinx/x ) filter response. Placing the first notch at 10 Hz places notches at both 50 Hz and 60 Hz, giving better than 150 dB rejection at these frequencies. In association with the gain selection, the filter cutoff also determines the output noise of the device. Changing the filter notch frequency, as well as the selected gain, impacts resolution. Table 7 to Table 13 show the effect of filter notch frequency and gain on the output noise and effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at 50 Hz, a new word is available at a 50 Hz output rate, or every 20 ms. If the first notch is at 500 Hz, a new word is available every 2 ms. A calibration should be initiated when any of these bits are changed. The settling time of the filter to a full-scale step input is worst-case 4 × 1/(output data rate). For example, with the filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms maximum. If the first notch is at 500 Hz, the settling time is 8 ms maximum. This settling time can be reduced to 3 × 1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step input takes place with the FSYNC bit high, the settling time is 3 × 1/(output data rate) from when the FSYNC bit returns low. The −3 dB frequency is determined by the programmed first notch frequency according to the following relationship: filter − 3 dB frequency = 0.262 × filter first notch frequency Rev. B | Page 21 of 52 AD7707 Table 24. Output Update Rates 1 CLK FS2 FS1 FS0 Output Update Rate −3 dB Filter Cutoff 0 0 0 0 20 Hz 5.24 Hz 0 0 0 1 25 Hz 6.55 Hz 0 0 1 0 100 Hz 26.2 Hz 0 0 1 1 200 Hz 52.4 Hz 1 0 0 0 50 Hz 13.1 Hz 1 0 0 1 60 Hz 15.7 Hz 1 0 1 0 250 Hz 65.5 Hz 1 0 1 1 500 Hz 131 Hz 0 1 0 0 4.054 Hz 1.06 Hz 0 1 0 1 4.23 Hz 1.11 Hz 0 1 1 0 4.84 Hz 1.27 Hz 0 1 1 1 4.96 Hz 1.3 Hz 1 1 0 0 10 Hz 2.62 Hz 1 1 0 1 10.34 Hz 2.71 Hz 1 1 1 0 11.90 Hz 3.13 Hz 1 1 1 1 12.2 Hz 3.2 Hz 1 Assumes correct clock frequency on the MCLK IN pin with the CLKDIV bit set appropriately. correctly scale the output data. As a result, there is a possibility Data Register (RS2, RS1, RS0 = 0, 1, 1) that after accessing the calibration registers (either read or write The data register on the part is a 16-bit read-only register that operation) the first output data read from the part may contain contains the most up-to-date conversion result from the AD7707. incorrect data. In addition, a write to the calibration register If the communications register sets up the part for a write should not be attempted while a calibration is in progress. These operation to this register, a write operation must actually take eventualities can be avoided by taking the FSYNC bit in the place to return the part to where it is expecting a write operation to setup register high before the calibration register operation and the communications register. However, the 16 bits of data taking it low after the operation is complete. written to the part are ignored by the AD7707. Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Power-On/Reset Status: 0x5761AB Status: 0x00 The AD7707 contains independent sets of full-scale registers, The part contains a Uest Segister that is used when testing the one for each of the input channels. Each of these registers is a device. The user is advised not to change the status of any of the 24-bit read/write register; 24 bits of data must be written; otherwise, RESET bits in this register from the default (power-on or ) status no data is transferred to the register. This register is used in of all 0s because the part will be placed in one of its test modes conjunction with its associated zero-scale register to form a and will not operate correctly. register pair. These register pairs are associated with input channel Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); pairs as outlined in Table 17. Although the part is set up to Power-On/Reset Status: 0x1F4000 allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly The AD7707 contains independent sets of zero-scale registers, scale the output data. As a result, there is a possibility that after one for each of the input channels. Each of these registers is a accessing the calibration registers (either read or write 24-bit read/write register; 24 bits of data must be written; otherwise, operation) the first output data read from the part may contain no data is transferred to the register. This register is used in incorrect data. In addition, a write to the calibration register conjunction with its associated full-scale register to form a should not be attempted while a calibration is in progress. These register pair. These register pairs are associated with input eventualities can be avoided by taking UIF
FSYNC bit in the setup channel pairs as outlined in Table 17. Although the part is set register high before the calibration register operation and taking up to allow access to these registers over the digital interface, it low after the operation is complete. the part itself no longer has access to the register coefficients to Rev. B | Page 22 of 52 AD7707 CALIBRATION SEQUENCES The AD7707 contains a number of calibration options as these bits return to 0 (0 following a calibration command), it previously outlined. Table 25 summarizes the calibration types, indicates that the calibration sequence is complete. This method the operations involved, and the duration of the operations. does not give any indication of there being a valid new result in There are two methods of determining the end of calibration. the data register. However, it gives an earlier indication than DRDY DRDY The first is to monitor when returns low at the end of that calibration is complete. The duration to when the DRDY Mode Bits (MD1 and MD0) return to 00 represents the the sequence. not only indicates when the sequence is duration of the calibration carried out). The sequence to when complete, but also that the part has a valid new sample in its DRDY data register. This valid new sample is the result of a normal goes low also includes a normal conversion and a conversion, which follows the calibration sequence. The second pipeline delay, tP, to correctly scale the results of this first method of determining when calibration is complete is to conversion. tP will never exceed 2000 × tCLKIN. The time for both monitor the MD1 and MD0 bits of the setup register. When methods is given in the Table 25. Table 25. Calibration Sequences Duration to DRDY Calibration Type MD1, MD0 Calibration Sequence Duration to Mode Bits Self-Calibration 0, 1 Internal ZS calibration at selected gain + 6 × 1/output rate 9 × 1/output rate + tP Internal FS calibration at selected gain ZS System Calibration 1, 0 ZS calibration on AIN at selected gain 3 × 1/output rate 4 × 1/output rate + tP FS System Calibration 1, 1 FS calibration on AIN at selected gain 3 × 1/output rate 4 × 1/output rate + t P Rev. B | Page 23 of 52 AD7707 CIRCUIT DESCRIPTION modulator) converts the sampled signal into a digital pulse The AD7707 is a Σ-Δ ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency train whose duty cycle contains the digital information. The signals such as those in industrial control or process control programmable gain function on the analog input is also applications. It contains a Σ-Δ (or charge balancing) ADC, a incorporated in this Σ-Δ modulator with the input sampling 3 calibration microcontroller with on-chip static RAM, a clock frequency being modified to give the higher gains. A sinc oscillator, a digital filter, and a bidirectional serial communica- digital low-pass filter processes the output of the Σ-Δ modulator tions port. The part consumes only 320 μA of power supply and updates the output register at a rate determined by the first current, making it ideal for battery-powered or loop-powered notch frequency of this filter. The output data can be read from instruments. On-chip thin-film resistors allow ±10 V, ±5 V, 0 V the serial port randomly or periodically at any rate up to the to 10 V, and 0 V to 5 V high level input signals to be directly output register update rate. The first notch of this digital filter accommodated on the analog input without requiring split (and therefore its −3 dB frequency) can be programmed via the supplies, dc-to-dc converters, or charge pumps. This part operates clock register bits, FS0 to FS2. With a master clock frequency with a supply voltage of 2.7 V to 3.3 V, or 4.75 V to 5.25 V. of 2.4576 MHz, the programmable range for this first notch frequency is from 10 Hz to 500 Hz, giving a programmable range The AD7707 contains two low level (AIN1 and AIN2) pro- for the −3 dB frequency of 2.62 Hz to 131 Hz. With a master clock grammable-gain pseudo differential analog input channels and frequency of 1 MHz, the programmable range for this first notch one high level (AIN3) single-ended input channel. For the low frequency is from 4 Hz to 200 Hz, giving a programmable range for level input channels, the selectable gains are 1, 2, 4, 8, 16, 32, 64, the −3 dB frequency of 1.06 Hz to 52.4 Hz. and 128, allowing the part to accept unipolar signals of between 0 mV to 20 mV and 0 V to 2.5 V, or bipolar signals in the range The basic connection diagram for the AD7707 is shown in from ±20 mV to ±2.5 V when the reference input voltage equals Figure 12. An AD780 or REF192 precision 2.5 V reference 2.5 V. With a reference voltage of 1.225 V, the input ranges are provides the reference source for the part. On the digital side, from 0 mV to 10 mV to 0 V to 1.225 V in unipolar mode, and CS the part is configured for 3-wire operation with tied to from ±10 mV to ±1.225 V in bipolar mode. Note that the signals DGND. A quartz crystal or ceramic resonator provides the master are with respect to the LOCOM input. clock source for the part. In most cases, it is necessary to connect capacitors on the crystal or resonator to ensure that it The high level input channel can directly accept input signals does not oscillate at overtones of its fundamental operating of ±10 V with respect to HICOM when operating with 5 V frequency. The values of capacitors can vary, depending on the supplies and a reference of 2.5 V. With 3 V supplies, ±5 V can manufacturer’s specifications. A similar circuit is applicable for be accommodated on the AIN3 input. operation with 3 V supplies; in this case, a 1.225 V reference The input signal to the analog input is continuously sampled at (AD1580) should be used for specified performance. a rate determined by the frequency of the master clock, MCLK IN, and the selected gain. A charge-balancing ADC (Σ-Δ ANALOG 5V SUPPLY 10µF 0.1µF 0.1µF AV DV DD DD AIN1 DRDY DATA READY LOW LEVEL ANALOG AIN2 INPUT RECEIVE (READ) LOCOM DOUT AIN3 HIGH LEVEL DIN SERIAL DATA ANALOG VBIAS INPUT HICOM SCLK SERIAL CLOCK AD7707 5V AGND ANALOG 5V SUPPLY RESET DGND CS V IN V REF IN(+) OUT MCLK IN 10µF 0.1µF CRYSTAL OR AD780/ CERAMIC REF192 RESONATOR MCLK OUT REF IN(–) GND Figure 12. Basic Connection Diagram for 5 V Operation Rev. B | Page 24 of 52 08691-012 AD7707 ANALOG INPUT this unbuffered mode is 1 nA maximum. As a result, the analog ANALOG INPUT RANGES inputs see a dynamic load that is switched at the input sample The AD7707 contains two low level pseudo differential analog rate (see Figure 14). This sample rate depends on master clock input channels, AIN1 and AIN2. These input pairs provide frequency and selected gain. CSAMP is charged to AIN(+) and programmable-gain, differential input channels that can handle discharged to AIN(−) every input sample cycle. The effective PO either unipolar or pseudo bipolar input signals. It should be resistance of the switch, R , is typically 7 kΩ. SW noted that the bipolar input signals are referenced to the LOCOM C must be charged through R and any additional source input. The AD7707 also has a high level analog input channel SAMP SW impedances every input sample cycle. Therefore, in unbuffered AIN3, which is referenced to HICOM. Figure 13 shows the input structure on the high level input channel. mode, source impedances mean a longer charge time for CSAMP and this may result in gain errors on the part. Table 26 shows In normal 5 V operation, VBIAS is normally connected to 2.5 V the allowable external resistance/capacitance values, for unbuffered and HICOM is connected to AGND. This arrangement ensures mode, such that no gain error to the 16-bit level is introduced that the voltages seen internally are within the common-mode on the part. Note that these capacitances are total capacitances range of the buffer in buffered mode and within the supply range in on the analog input. This external capacitance includes 10 pF unbuffered mode. This device can be programmed to operate in from the pins and lead frame of the device. either buffered or unbuffered mode via the BUF bit in the setup register. Note that the signals on AIN3 are with respect to the AIN(+) R (7kΩ TYP) HICOM input and not with respect to AGND or DGND. SW FIRST INTEGRATOR HIGH INPUT The differential voltage seen by the AD7707 when using the AIN(–) C SAMP IMPEDANCE (7pF) high level input channel is the difference between AIN3(+) and >1G V /2 AIN3(−) on the mux as shown in Figure 13. DD AIN3(+) = (AIN3 + 6 × VBIAS
+ VHICOM)/8 SWITCHING FREQUENCY DEPENDS ON f AND SELECTED GAIN CLKIN 6R AIN3 Figure 14. Unbuffered Analog Input Structure Table 26. External R, C Combination for No 16-Bit Gain 1R = 5kΩ AIN3(+) Error on Low Level Input Channels (Unbuffered Mode Only) VBIAS External Capacitance (pF) MUX 1R Gain 0 50 100 500 1000 5000 AIN3(–) 1 368 kΩ 90.6 kΩ 54.2 kΩ 14.6 kΩ 8.2 kΩ 2.2 kΩ 3R 2 177.2 kΩ 44.2 kΩ 26.4 kΩ 7.2 kΩ 4 kΩ 1.12 kΩ 6R 4 82.8 kΩ 21.2 kΩ 12.6 kΩ 3.4 kΩ 1.94 kΩ 540 Ω HICOM 8 to 128 35.2 kΩ 9.6 kΩ 5.8 kΩ 1.58 Ω 880 Ω 240 Ω Figure 13. AIN3 Input Structure AIN3(−) = V + 0.75 × (VBIAS − V ) HICOM HICOM 400 In unbuffered mode, the common-mode range of the low level input channels is from AGND − 100 mV to AV + 30 mV. This 350 DD GAIN = 1 means that in unbuffered mode, the part can handle both unipolar 300 and bipolar input ranges for all gains. Absolute voltages of 250 AGND − 100 mV can be accommodated on the analog inputs without degradation in performance, but leakage current increases 200 appreciably with increasing temperature. In buffered mode, the GAIN = 2 150 analog inputs can handle much larger source impedances, but the absolute input voltage range is restricted to between AGND GAIN = 8 TO 128 100 + 50 mV to AV − 1.5 V, which also places restrictions on the GAIN = 4 DD 50 common-mode range. This means that in buffered mode, there are some restrictions on the allowable gains for bipolar input 0 0 10 100 1000 10000 ranges. Care must be taken in setting up the common-mode EXTERNAL CAPACITANCE (pF) voltage and input voltage range so that these limits are not Figure 15. External R, C Combination for No 16-Bit Gain Error on Low Level exceeded; otherwise, there will be a degradation in linearity Input Channels (Unbuffered Mode Only) performance. In unbuffered mode, the analog inputs look directly into the 7 pF input sampling capacitor, C . The dc input leakage current in SAMP Rev. B | Page 25 of 52 08691-013 EXTERNAL RESISTANCE (kΩ) 08691-014 08691-015 AD7707 In buffered mode, the analog inputs look into the high impedance Table 27. Input Sampling Frequency vs. Gain inputs stage of the on-chip buffer amplifier. C is charged via SAMP Gain Input Sampling Frequency (f ) S this buffer amplifier such that source impedances do not affect 1 fCLKIN/64 (38.4 kHz at fCLKIN = 2.4576 MHz) the charging of CSAMP. This buffer amplifier has an offset leakage 2 2 × fCLKIN/64 (76.8 kHz at fCLKIN =2.4576 MHz) current of 1 nA. In buffered mode, large source impedances 4 4 × f /64 (76.8 kHz at f =2.4576 MHz) CLKIN CLKIN result in a small dc offset voltage developed across the source 8 to 128 8 × f /64 (307.2 kHz at f = 2.4576 MHz) CLKIN CLKIN impedance, but not in a gain error. BIPOLAR/UNIPOLAR INPUTS INPUT SAMPLE RATE The analog inputs on the low level input channels on the AD7707 The modulator sample frequency for the AD7707 remains at can accept either unipolar or bipolar input voltage ranges with fCLKIN/128 (19.2 kHz at fCLKIN = 2.4576 MHz) regardless of the respect to LOCOM. selected gain. However, gains greater than 1 are achieved by a The high level input channel handles true bipolar signals of ±10 V combination of multiple input samples per modulator cycle and maxJNVN for guaranteed operation. a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the Bipolar or unipolar options are chosen by programming the device varies with the selected gain (see Table 27). In buffered B /U bit of the setup register. This programs the channel for mode, the input impedance is constant. In unbuffered mode, either unipolar or bipolar operation. Programming the channel where the analog input looks directly into the sampling capacitor, for either unipolar or bipolar operation does not change any of the effective input impedance is 1/CSAMP × fS where CSAMP is the the channel conditions, it simply changes the data output coding input sampling capacitance and fS is the input sample rate. and the points on the transfer function where calibrations occur. In unipolar operation, the output coding is straight binary. In bipolar mode, the output coding is offset binary. Rev. B | Page 26 of 52 AD7707 REFERENCE INPUT The AD7707 reference inputs, REF IN(+) and REF IN(−), gain of 32, it is 4.25 pF; for a gain of 64, it is 3.625 pF; and for a provide a differential reference input capability. The common- gain of 128, it is 3.3125 pF. mode range for these differential inputs is from GND to AVDD. The output noise performance outlined in Table 7 through The nominal reference voltage, VREF REF IN(+) − REF IN(−), Table 13 is for an analog input of 0 V, which effectively removes for specified operation is +2.5 V for the AD7707 operated with the effect of noise from the reference. To obtain the same noise an AV of 5 V and 1.225 V for the AD7707 operated with an DD performance as shown in the noise tables over the full input AV of 3 V. The part is functional with V voltages down to DD REF range requires a low noise reference source for the AD7707. If 1 V, but with degraded performance because the LSB size is the reference noise in the bandwidth of interest is excessive, it smaller. REF IN(+) must always be greater than REF IN(−) for degrades the performance of the AD7707. In bridge transducer correct operation of the AD7707. applications where the reference voltage for the ADC is derived Both reference inputs provide a high impedance, dynamic load from the excitation voltage, the effect of the noise in the excitation similar to the analog inputs in unbuffered mode. The maximum voltage is removed because the application is ratiometric. Rec- dc input leakage current is ±1 nA over temperature, and source ommended reference voltage sources for the AD7707 with an resistance may result in gain errors on the part. In this case, the AV of 5 V include the AD780, REF43, and REF192, and the DD sampling switch resistance is 5 kΩ typical and the reference recommended reference sources for the AD7707 operated with capacitor (C ) varies with gain. The sample rate on the an AV of 3 V include the AD589 and AD1580. It is generally REF DD reference inputs is fCLKIN/64 and does not vary with gain. For recommended to decouple the output of these references to gains of 1 and 2, CREF is 8 pF; for a gain of 16, it is 5.5 pF; for a further reduce the noise level. Rev. B | Page 27 of 52 AD7707 DIGITAL FILTERING The AD7707 contains an on-chip low-pass digital filter that Phase response: processes the output of the part’s Σ-Δ modulator. Therefore, the ∠H=− 3π(N− 2)× f / f Rad S part not only provides the analog-to-digital conversion function Figure 16 shows the filter frequency response for a cutoff but also provides a level of filtering. There are a number of system frequency of 2.62 Hz, which corresponds to a first filter notch differences when the filtering function is provided in the digital frequency of 10 Hz. The plot is shown from dc to 65 Hz. This domain rather than the analog domain and the user should be response is repeated at either side of the digital filter’s sample aware of these. frequency and at either side of multiples of the filter’s sample First, because digital filtering occurs after the ADC process, it frequency. can remove noise injected during the conversion process. Analog The response of the filter is similar to that of an averaging filter, filtering cannot do this. Also, the digital filter can be made but with a sharper roll-off. The output rate for the digital filter programmable far more readily than an analog filter. Depending corresponds with the positioning of the first notch of the filter’s on the digital filter design, this gives the user the capability of frequency response. Thus, for the plot of Figure 16 where the programming cutoff frequency and output update rate. output rate is 10 Hz, the first notch of the filter is at 10 Hz. The On the other hand, analog filtering can remove noise superim- 3 notches of this (sinx/x) filter are repeated at multiples of the posed on the analog signal before it reaches the ADC. Digital first notch. The filter provides attenuation of better than 100 dB filtering cannot do this and noise peaks riding on signals near at these notches. full scale have the potential to saturate the analog modulator 0 and digital filter, even though the average value of the signal is –20 within limits. To alleviate this problem, the AD7707 has over- –40 range headroom built into the Σ-Δ modulator and digital filter, –60 which allows overrange excursions of 5% above the analog –80 input range. If noise signals are larger than this, consideration –100 should be given to analog input filtering, or to reducing the input –120 channel voltage so that its full scale is half that of the analog input –140 channel full scale. This provides an overrange capability greater –160 than 100% at the expense of reducing the dynamic range by one –180 bit (50%). –200 In addition, the digital filter does not provide any rejection at –220 integer multiples of the digital filter’s sample frequency. However, –240 0 10 20 30 40 50 60 the input sampling on the part provides attenuation at multiples FREQUENCY (Hz) of the digital filter’s sampling frequency so that the unattenuated Figure 16. Frequency Response of AD7707 Filter bands actually occur around multiples of the sampling frequency, fS Simultaneous 50 Hz and 60 Hz rejection is obtained by placing (as defined in Table 27). Thus, the unattenuated bands occur at the first notch at 10 Hz. Operating with an update rate of 10 Hz n × fS (where n = 1, 2, 3…). At these frequencies, there are places notches at both 50 Hz and 60 Hz giving better than 100 dB frequency bands of ±f3 dB width (f3 dB is the cutoff frequency of rejection at these frequencies. the digital filter) where noise passes unattenuated to the output. The cutoff frequency of the digital filter is determined by the value FILTER CHARACTERISTICS loaded to Bit FS0 to Bit FS2 in the clock register. Programming 3 The AD7707’s digital filter is a low-pass filter with a (sinx/x) a different cutoff frequency via FS0, FS1, and FS2 does not alter 3 response (also called sinc ). The transfer function for this filter the profile of the filter response; it changes the frequency of the is described in the z domain by: notches. The output update of the part and the frequency of the 3 first notch correspond. −N 1− Z 1 H(z)= × −1 Because the AD7707 contains this on-chip, low-pass filtering, a N 1− Z settling time is associated with step function inputs and data on and in the frequency domain by: the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate 3 SIN(N×π× f / f ) 1 S chosen for the filter. The settling time of the filter to a full-scale H( f )− × N SIN(π× f / f step input can be up to four times the output data period. For a S synchronized step input (using the FSYNC function), the settling where N is the ratio of the modulator rate to the output rate. time is three times the output data period. Rev. B | Page 28 of 52 GAIN (dB) 08691-016 AD7707 POSTFILTERING ANALOG FILTERING The on-chip modulator provides samples at a 19.2 kHz output The digital filter does not provide any rejection at integer multiples rate with fCLKIN at 2.4576 MHz. The on-chip digital filter decimates of the modulator sample frequency, as previously outlined. these samples to provide data at an output rate that corresponds However, due to the AD7707’s high oversampling ratio, these bands to the programmed output rate of the filter. Because the output occupy only a small fraction of the spectrum and most broadband data rate is higher than the Nyquist criterion, the output rate for noise is filtered. This means that the analog filtering requirements a given bandwidth satisfies most application requirements. There in front of the AD7707 are considerably reduced vs. a conven- may, however, be some applications that require a higher data tional converter with no on-chip filtering. In addition, because rate for a given bandwidth and noise performance. Applications the part’s common-mode rejection performance of 100 dB that need this higher data rate require some postfiltering follow- extends out to several kHz, common-mode noise in this ing the digital filter of the AD7707. frequency range is substantially reduced. For example, if the required bandwidth is 7.86 Hz, but the Depending on the application, however, it may be necessary to required update rate is 100 Hz, the data can be taken from the provide attenuation prior to the AD7707 to eliminate unwanted AD7707 at the 100 Hz rate, giving a −3 dB bandwidth of 26.2 Hz. frequencies from these bands, which the digital filter will pass. Postfiltering can be applied to this to reduce the bandwidth and It may also be necessary in some applications to provide analog output noise, to the 7.86 Hz bandwidth level, while maintaining filtering in front of the AD7707 to ensure that differential noise an output rate of 100 Hz. signals outside the band of interest do not saturate the analog modulator. Postfiltering can also be used to reduce the output noise from the device for bandwidths below 2.62 Hz. At a gain of 128 and a If passive components are placed in front of the AD7707 in bandwidth of 2.62 Hz, the output rms noise is 450 nV. This is unbuffered mode, care must be taken to ensure that the source essentially device noise or white noise and because the input is impedance is low enough not to introduce gain errors in the chopped, the noise has a primarily flat frequency response. system. This significantly limits the amount of passive antialiasing By reducing the bandwidth below 2.62 Hz, the noise in the filtering, which can be provided in front of the AD7707 when it resultant pass band can be reduced. A reduction in bandwidth is used in unbuffered mode. However, when the part is used in by a factor of 2 results in a reduction of approximately 1.25 in buffered mode, large source impedances simply result in a small the output rms noise. This additional filtering results in a longer dc offset error (a 10 kΩ source resistance causes an offset error settling time. of less than 10 μV). Therefore, if the system requires any TJHOJGJ cant source impedances to provide passive analog GJMUFSJOH
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front of the AD7707, it is recommended that the QBSU
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PQFSBUFE in buffered mode. Rev. B | Page 29 of 52 AD7707 CALIBRATION The AD7707 provides a number of calibration options that low during) the calibration command write to the setup register, can be programmed via the MD1 and MD0 bits of the setup it may take up to one modulator cycle (MCLK IN/ 128) before register. The different calibration options are outlined in the DRDY goes high to indicate that calibration is in progress. Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: Therefore, DRDY should be ignored for up to one modulator 0x01 section and the Calibration Sequences section. A calibration cycle after the last bit is written to the setup register in the cycle can be initiated at any time by writing to these bits of the calibration command. setup register. Calibration on the AD7707 removes offset and For bipolar input ranges in the self-calibrating mode, the gain errors from the device. A calibration routine should be sequence is very similar to that just outlined. In this case, the initiated on the device whenever there is a change in the ambient two points are exactly the same as in the previous case but operating temperature or supply voltage. It should also be because the part is configured for bipolar operation, the shorted initiated if there is a change in the selected gain, filter notch, or inputs point is actually midscale of the transfer function. bipolar/unipolar input range. Errors due to resistor mismatch in the attenuator on the high The AD7707 offers self-calibration and system calibration facili- level input channel AIN3 are not removed by a self-calibration. ties. For full calibration to occur on the selected channel, the SYSTEM CALIBRATION on-chip microcontroller must record the modulator output for two different input conditions. These are zero-scale and full-scale System calibration allows the AD7707 to compensate for system points. These points are derived by performing a conversion on gain and offset errors as well as its own internal errors. System the different input voltages provided to the input of the modula- calibration performs the same slope factor calculations as self- tor during calibration. As a result, the accuracy of the calibration calibration, but uses voltage values presented by the system to can only be as good as the noise level that it provides in normal the AIN inputs for the zero-scale and full-scale points. Full mode. The result of the zero-scale calibration conversion is system calibration requires a two-step process, a ZS system stored in the zero-scale calibration register whereas the result of calibration followed by an FS system calibration. the full-scale calibration conversion is stored in the full-scale For a full system calibration, the zero-scale point must be presented calibration register. With these readings, the microcontroller to the converter first. It must be applied to the converter before can calculate the offset and the gain slope for the input-to- the calibration step is initiated, and remain stable until the step output transfer function of the converter. is complete. Once the system zero-scale voltage has been set up, SELF-CALIBRATION a ZS system calibration is then initiated by writing the appropriate values (1, 0) to the MD1 and MD0 bits of the setup register. The A self-calibration is initiated on the AD7707 by writing the zero-scale system calibration is performed at the selected gain. appropriate values (0, 1) to the MD1 and MD0 bits of the setup The duration of the calibration is 3 × 1/output rate. At this time, register. In the self-calibration mode with a unipolar input the MD1 and MD0 bits in the setup register return to 0, 0. This range, the zero-scale point used in determining the calibration gives the earliest indication that the calibration sequence is coefficients is with the inputs of the differential pair internally DRDY complete. The line goes high when calibration is initiated shorted on the part (that is, AIN1 = LOCOM = internal bias and does not return low until there is a valid new word in the voltage in the case of the AD7707. The PGA is set for the data register. The duration time from the calibration command selected gain (as per the G2, G1, and G0 bits in the setup being issued to DRDY going low is 4 × 1/output rate as the part register) for this zero-scale calibration conversion. The full- scale calibration conversion is performed at the selected gain on performs a normal conversion on the analog input voltage an internally-generated voltage of VREF/selected gain. before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the Tetup Segister, it may take The duration time for the calibration is 6 × 1/output rate. This DRDY up to one modulator cycle (MCLK IN/128) before goes is made up of 3 × 1/output rate for the zero-scale calibration DRDY high to indicate that calibration is in progress. Therefore, and 3 × 1/output rate for the full-scale calibration. At this time, should be ignored for up to one modulator cycle after the last the MD1 and MD0 bits in the setup register return to 0, 0. This bit is written to the setup register in the calibration command. gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated After the zero-scale point is calibrated, the full-scale point is and does not return low until there is a valid new word in the applied to the analog input and the second step of the data register. The duration time from the calibration command calibration process is initiated by again writing the appropriate DRDY being issued to going low is 9 × 1/output rate. This is values (1, 1) to MD1 and MD0. Again, the full-scale voltage made up of 3 × 1/output rate for the zero-scale calibration, 3 × must be set up before the calibration is initiated and it must 1/output rate for the full-scale calibration, 3 × 1/output rate for remain stable throughout the calibration step. The full-scale a conversion on the analog input, and some overhead to system calibration is performed at the selected gain. The duration correctly set up the coefficients. If DRDY is low before (or goes of the calibration is 3 × 1/output rate. At this time, the MD1 and Rev. B | Page 30 of 52 AD7707 MD0 bits in the setup register return to 0, 0. This gives the Therefore, in determining the limits for system zero-scale and earliest indication that the calibration sequence is complete. The full-scale calibrations, the user must ensure that the offset range DRDY plus the span range does exceed 1.05 × V /gain. This is best line goes high when calibration is initiated and does not REF illustrated with the following examples. return low until there is a valid new word in the data register. The duration time from the calibration command being issued If the part is used in unipolar mode with a required span of 0.8 × to DRDY going low is 4 × 1/output rate as the part performs a VREF/gain, the offset range the system calibration can handle is normal conversion on the analog input voltage before DRDY from −1.05 × VREF/gain to +0.25 × VREF/gain. If the part is used DRDY goes low. If is low before (or goes low during) the in unipolar mode with a required span of V /gain, the offset REF calibration command write to the setup register, it may take up range the system calibration can handle is from −1.05 × V /gain REF DRDY to +0.05 × V /gain. Similarly, if the part is used in unipolar to one modulator cycle (MCLK IN/128) before goes REF mode and required to remove an offset of 0.2 × V /gain, the DRDY REF high to indicate that calibration is in progress. Therefore, span range the system calibration can handle is 0.85 × VREF/gain. should be ignored for up to one modulator cycle after the last 1.05 × V /GAIN bit is written to the setup register in the calibration command. REF UPPER LIMIT ON In the unipolar mode, the system calibration is performed between AD7707 INPUT VOLTAGE AD7707 LOW LEVEL INPUT CHANNEL the two endpoints of the transfer function; in the bipolar mode, GAIN CALIBRATIONS EXPAND INPUT RANGE OR CONTRACT THE it is performed between midscale (zero differential voltage) and (0.8 × V /GAIN TO REF AD7707 INPUT RANGE 2.1 × V /GAIN) REF positive full scale. NOMINAL ZERO- 0V DIFFERENTIAL SCALE POINT The fact that the system calibration is a two-step calibration offers OFFSET CALIBRATIONS MOVE INPUT RANGE UP OR DOWN another feature. After the sequence of a full system calibration LOWER LIMIT ON has been completed, additional offset or gain calibrations can AD7707 INPUT VOLTAGE be performed by themselves to adjust the system zero reference –1.05 × V /GAIN REF point or the system gain. Calibrating one of the parameters, either system offset or system gain, does not affect the other Figure 17. Span and Offset Limits for Low Level Input Channels, AIN1 and AIN2 parameter. If the part is used in bipolar mode with a required span of System calibration can also be used to remove any errors from ±0.4 × VREF/gain, the offset range the system calibration can source impedances on the analog input when the part is used in handle is from –0.65 × VREF/gain to +0.65 × VREF/gain. If the unbuffered mode. A simple R, C antialiasing filter on the front part is used in bipolar mode with a required span of ±V /gain, REF end may introduce a gain error on the analog input voltage, but then the offset range that the system calibration can handle is the system calibration can be used to remove this error. from −0.05 × V /gain to +0.05 × V /gain. Similarly, if the REF REF SPAN AND OFFSET LIMITS ON THE LOW LEVEL part is used in bipolar mode and required to remove an offset of INPUT CHANNELS, AIN1 AND AIN2 ±0.2 × VREF/gain, the span range the system calibration can handle Whenever a system calibration mode is used, there are limits on is ±0.85 × VREF/gain. Figure 17 shows a graphical representation of the amount of offset and span that can be accommodated. The the span and offset limits for the low level input channels. overriding requirement in determining the amount of offset SPAN AND OFFSET LIMITS ON THE HIGH LEVEL and gain that can be accommodated by the part is the require- INPUT CHANNEL AIN3 ment that the positive full-scale calibration limit is <1.05 × The exact same reasoning VTFE for low level input channels can VREF/gain. This allows the input range to go 5% above the CF
applied to the high level input channel. When using the high nominal range. The built-in headroom in the AD7707’s analog level channel, the attenuator provides an attenuation factor of 8. modulator ensures that the part will still operate correctly with a All span and offset limits should be multiplied by a factor of 8. positive full-scale voltage that is 5% beyond the nominal. Therefore, the range of input span in both the unipolar and The input span in both the unipolar and bipolar modes has a bipolar modes has a minimum value of 6.4 × VREF/gain and a minimum value of 0.8 × VREF/gain and a maximum value of 2.1 maximum value of 16.8 × V /gain. The offset range plus the REF × VREF/gain. However, the span (which is the difference between span range cannot exceed 8.4 × V /gain. REF the bottom of the AD7707’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommo- dated depends on whether the unipolar or bipolar mode is being used. Once again, the offset has to take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative offsets. In both unipolar and bipolar modes, the range of positive offsets that can be handled by the part depends on the selected span. Rev. B | Page 31 of 52 08691-017 AD7707 The power dissipation and temperature drift of the AD7707 are POWER-UP AND CALIBRATION low and no warm-up time is required before the initial calibration On power-up, the AD7707 performs an internal reset that sets is performed. However, if an external reference is being used, the contents of the internal registers to a known state. There are this reference must stabilize before calibration is initiated. default values loaded to all registers after power-on or reset. The Similarly, if the clock source for the part is generated from a default values contain nominal calibration coefficients for the crystal or resonator across the MCLK pins, the start-up time for calibration registers. However, to ensure correct calibration for the oscillator circuit should elapse before a calibration is the device, a calibration routine should be performed after initiated on the part (see the Clocking and Oscillator Circuit power-up. A calibration should be performed if the update rate section). or gain are changed. Rev. B | Page 32 of 52 AD7707 USING THE AD7707 and resonators at this frequency tend to be low and, as a result CLOCKING AND OSCILLATOR CIRCUIT there tends to be little difference between different crystal and The AD7707 requires a master clock input, which can be an resonator types. external CMOS compatible clock signal applied to the MCLK IN pin with the MCLK OUT pin left unconnected. Alternatively, When operating with a clock frequency of 1 MHz, the ESR value for different crystal types varies significantly. As a result, a crystal or ceramic resonator of the correct frequency can be the current drain varies across crystal types. When using a connected between MCLK IN and MCLK OUT as shown in crystal with an ESR of 700 Ω or when using a ceramic resonator, Figure 18, in which case the clock circuit functions as an oscilla- the increase in the typical current over an externally applied tor, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the −3 dB fre- clock is 20 μA with DVDD = 3 V and 200 μA with DVDD = 5 V. quency, output update rate, and calibration time are all directly When using a crystal with an ESR of 3 kΩ, the increase in the related to the master clock frequency, f . Reducing the typical current over an externally applied clock is again 100 μA CLKIN master clock frequency by a factor of 2 halves these frequencies with DVDD = 3 V but 400 μA with DVDD = 5 V. and update rate, and doubles the calibration time. The current The on-chip oscillator circuit also has a start-up time associated drawn from the DVDD power supply is also related to fCLKIN. with it before it is oscillating at its correct frequency and correct Reducing fCLKIN by a factor of 2 halves the DVDD current but voltage levels. Typical start-up times with DV = 5 V are 6 ms DD does not affect the current drawn from the AVDD. using a 4.9512 MHz crystal, 16 ms with a 2.4576 MHz crystal C1 and 20 ms with a 1 MHz crystal oscillator. Start-up times are MCLK IN typically 20% slower when the power supply voltage is reduced CRYSTAL OR CERAMIC AD7707 to 3 V. At 3 V supplies, depending on the loading capacitances C2 RESONATOR MCLK OUT on the MCLK pins, a 1 MΩ feedback resistor may be required across the crystal or resonator to keep the start-up times around Figure 18. Crystal/Resonator Connection for the AD7707 the 20 ms duration. Using the part with a crystal or ceramic resonator between the The AD7707’s master clock appears on the MCLK OUT pin of MCLK IN and MCLK OUT pins generally causes more current the device. The maximum recommended load on this pin is one to be drawn from DVDD than when the part is clocked from a CMOS load. When using a crystal or ceramic resonator to generate driven clock signal at the MCLK IN pin. This is because the on- the AD7707’s clock, it may be desirable to use this clock as the chip oscillator circuit is active in the case of the crystal or ceramic clock source for the system. In this case, it is recommended that resonator. Therefore, the lowest possible current on the AD7707 the MCLK OUT signal is buffered with a CMOS buffer before is achieved with an externally applied clock at the MCLK IN pin being applied to the rest of the circuit. with MCLK OUT unconnected, unloaded, and disabled. SYSTEM SYNCHRONIZATION The amount of additional current taken by the oscillator depends The FSYNC bit of the setup register allows the user to reset the on a number of factors—first, the larger the value of capacitor modulator and digital filter without affecting any of the setup (C1 and C2) placed on the MCLK IN and MCLK OUT pins, the conditions on the part. This allows the user to start gathering larger the current consumption on the AD7707. Care should be samples of the analog input from a known point in time, that is, taken not to exceed the capacitor values recommended by the when the FSYNC
CJU is changed from 1 to 0. crystal and ceramic resonator manufacturers to avoid consuming With a 1 in the FSYNC bit of the setup register, the digital filter unnecessary current. Typical values for C1 and C2 are recom- and analog modulator are held in a known reset state and the mended by crystal or ceramic resonator manufacturers; these part is not processing any input samples. When a 0 is then are in the range of 30 pF to 50 pF. If the capacitor values on written to the FSYNC bit, the modulator and filter are taken out MCLK IN and MCLK OUT are kept in this range, they do not of this reset state and the part starts to gather samples again on result in any excessive current. Another factor that influences the next master clock edge. the current is the effective series resistance (ESR) of the crystal that appears between the MCLK IN and MCLK OUT pins of The FSYNC input can also be used as a software start convert the AD7707. As a general rule, the lower the ESR value is, the command allowing the AD7707 to be operated in a conventional lower the current taken by the oscillator circuit. converter fashion. In this mode, writing to the FSYNC bit starts conversion and the falling edge of DRDY indicates when con- When operating with a clock frequency of 2.4576 MHz, there is version is complete. The disadvantage of this scheme is that the 50 μA difference in the current between an externally applied settling time of the filter has to be taken into account for every clock and a crystal resonator when operating with a DVDD of data register update. This means that the rate at which the data 3 V. With DVDD = 5 V and fCLKIN = 2.4576 MHz, the typical register is updated is three times slower in this mode. current increases by 250 μA for a crystal/resonator supplied clock vs. an externally applied clock. The ESR values for crystals Rev. B | Page 33 of 52 08691-018 AD7707 Because the FSYNC bit resets the digital filter, the full settling DRDY tCLKIN before returning low again. If is low when the part time of 3 × 1/output rate has to elapse before there is a new enters its standby mode (indicating a valid unread word in the DRDY word loaded to the output register on the part. If the data register), the data register can be read while the part is in signal is low when FSYNC goes to a 0, the DRDY signal is not standby. At the end of this read operation, the DRDY is reset reset high by the FSYNC command. This is because the high as normal. AD7707 recognizes that there is a word in the data register that Placing the part in standby mode reduces the total current to has not been read. The DRDY line stays low until an update of 9 μA typical with 5 V supplies and 4 μA with 3 V supplies when the data register takes place, at which time it goes high for 500 × the part is operated from an external master clock provided this t before returning low again. A read from the data register CLKIN master clock is stopped. If the external clock continues to drive DRDY resets the signal high and it does not return low until the the MCLK IN pin in standby mode, the standby current increases settling time of the filter has elapsed (from the FSYNC command) to 150 μA typical with 5 V supplies and 75 μA typical with 3 V and there is a valid new word in the data register. If the DRDY supplies. If a crystal or ceramic resonator is used as the clock line is high when the FSYNC command is issued, the DRDY source, the total current in standby mode is 400 μA typical with line does not return low until the settling time of the filter has 5 V supplies and 90 μA with 3 V supplies. This is because the elapsed. on-chip oscillator circuit continues to run when the part is in its standby mode. This is important in applications where the system RESET INPUT clock is provided by the AD7707’s clock, so that the AD7707 The RESET input on the AD7707 resets all the logic, the digital produces an uninterrupted master clock even when it is in its filter, and the analog modulator, while all on-chip registers are standby mode. The serial interface remains operational when in DRDY reset to their default state. is driven high and the AD7707 standby mode so that data can be read from the output register RESET ignores all communications to any of its registers while the in standby, regardless of whether or not the master clock is stopped. RESET input is low. When the input returns high, the AD7707 ACCURACY DRDY starts to process data and returns low in 3 × 1/output Σ-Δ ADCs, like voltage–to-frequency converters (VFCs) and rate, indicating a valid new word in the data register. However, other integrating ADCs, do not contain any source of the AD7707 operates with its default setup conditions after a nonmonotonicity and inherently offer no missing codes RESET and it is generally necessary to set up all registers and performance. The AD7707 achieves excellent linearity by the carry out a calibration after a RESET command. use of high quality, on-chip capacitors that have a very low The AD7707’s on-chip oscillator circuit continues to function capacitance/voltage coefficient. The device also achieves low RESET even when the input is low. The master clock signal input drift through the use of chopper-stabilized techniques in continues to be available on the MCLK OUT pin. Therefore, in its input stage. To ensure excellent performance over time and applications where the system clock is provided by the AD7707’s temperature, the AD7707 uses digital calibration techniques clock, the AD7707 produces an uninterrupted master clock that minimize offset and gain error. during RESET commands. DRIFT CONSIDERATIONS STANDBY MODE Charge injection in the analog switches and dc leakage currents The STBY bit in the communications register of the AD7707 at the sampling modes are the primary sources of offset voltage drift in the converter. The dc input leakage current is essentially allows the user to place the part in a power-down mode when it independent of the selected gain. Gain drift within the converter is not required to provide conversion results. The AD7707 depends primarily upon the temperature tracking of the internal retains the contents of all its on-chip registers (including the capacitors. It is not affected by leakage currents. data register) while in standby mode. When released from standby mode, the part starts to process data and a new word is Measurement errors due to offset drift or gain drift can be available in the data register in 3 × 1/output rate from when a 0 eliminated at any time by recalibrating the converter. Using the is written to the STBY bit. system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. Integral and differential The STBY bit does not affect the digital interface, nor does it linearity errors are not significantly affected by temperature affect the status of the DRDY line. If DRDY is high when the changes. STBY bit is brought low, it remains high until there is a valid new word in the data register. If DRDY is low when the STBY bit is brought low, it remains low until the data register is DRDY updated, at which time the line returns high for 500 × Rev. B | Page 34 of 52 AD7707 POWER SUPPLIES The AD7707 operates with power supplies between 2.7 V and GROUNDING AND LAYOUT 5.25 V. There is no specific power supply sequence required for Because the analog inputs and reference input are differential, the AD7707, either the AVDD or the DVDD supply can come up most of the voltages in the analog modulator are common- first. In normal operation, the DVDD must not exceed AVDD by mode voltages. The excellent common-mode rejection of the 0.3 V. "MUIPVHI the latch-up performance of the AD7707 is good, part removes common-mode noise on these inputs. The digital JU
is important that power is applied to the AD7707 before signals filter provides rejection of broadband noise on the power at REF IN, AIN, or the logic input pins to avoid excessive currents. supplies, except at integer multiples of the modulator sampling If this is not possible, the current that flows in any of these pins frequency. The digital filter also removes noise from the analog should be limited to less than 100 mA. If separate supplies are and reference inputs provided UIBU
those noise sources do not used for the AD7707 and the system digital circuitry, the AD7707 saturate the analog modulator. As a result, the AD7707 is more should be powered up first. If it is not possible to guarantee this, immune to noise interference than a conventional high current limiting resistors should be placed in series with the resolution converter. However, because the resolution of the logic inputs to again limit the current. Latch-up current is AD7707 is so high, and the noise levels from the AD7707 so greater than 100 mA. low, care must be taken with regard to grounding and layout. 1600 The printed circuit board that houses the AD7707 should be USING CRYSTAL OSCILLATOR T = 25°C A 1400 designed so that the analog and digital sections are separated UNBUFFERED MODE GAIN = 128 and confined to certain areas of the board. This facilitates the 1200 use of ground planes, which can be separated easily. A 1000 minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground f = 2.4576MHz 800 CLK planes should only be joined in one place to avoid ground 600 loops. If the AD7707 is in a system where multiple devices f = 1MHz CLK require AGND-to-DGND connections, the connection should 400 be made at one point only, a star ground point, which should be 200 established as close as possible to the AD7707. 0 Avoid running digital lines under the device because these may 2.5 3.0 3.54.0 4.55.0 5.5 V (V) couple noise onto the analog circuitry within the AD7707. The DD Figure 19. I vs. Supply Voltage analog ground plane should be allowed to run under the AD7707 DD to reduce noise coupling. The power supply lines to the AD7707 SUPPLY CURRENT should use wide traces to provide low impedance paths and reduce The current consumption on the AD7707 is specified for supplies the effects of glitches on the power supply line. Fast switching in the range 2.7 V to 3.3 V and in the range 4.75 V to 5.25 V. The signals like clocks should be shielded with digital ground to part operates over a 2.7 V to 5.25 V supply range and the IDD for avoid radiating noise to other sections of the board and clock the part varies as the supply voltage varies over this range. There is signals should never be run near the analog inputs. Avoid crossover an internal current boost bit on the AD7707 that is set internally of digital and analog signals. Traces on opposite sides of the board in accordance with the operating conditions. This affects the should run at right angles to each other. This reduces the effects current drawn by the analog circuitry within these devices. of feedthrough through the board. A microstrip technique is by far Minimum power consumption is achieved when the AD7707 is the best, but is not always possible with a double-sided board. operated with an fCLKIN of 1 MHz or at gains of 1 to 4 with fCLKIN In this technique, the component side of the board is dedicated = 2.4575 MHz as the internal boost bit is off reducing the analog to ground planes while signals are placed on the solder side. current consumption. Figure 19 shows the variation of the Good decoupling is important when using high resolution ADCs. typical I with V voltage for both a 1 MHz crystal oscillator DD DD All analog supplies should be decoupled with a 10 μF tantalum and a 2.4576 MHz crystal oscillator at 25°C. The AD7707 is capacitor in parallel with 0.1 μF ceramic capacitors to AGND. operated in unbuffered mode. The relationship shows that the To achieve the best performance from these decoupling IDD is minimized by operating the part with lower AVDD/DVDD components, they must be placed as close as possible to the voltages. AIDD/DIDD on the AD7707 is also minimized by using an device, ideally right up against the device. All logic chips should external master clock or by optimizing external components be decoupled with 0.1 μF disc ceramic capacitors to DGND. when using the on-chip oscillator circuit. Rev. B | Page 35 of 52 I (µA) DD 08691-019 AD7707 DIGITAL INTERFACE As previously outlined, the AD7707’s programmable functions The AD7707 serial interface can operate in 3-wire mode by are controlled using a set of on-chip registers. Data is written to tying the CS input low. In this case, the SCLK, DIN, and DOUT these registers via the part’s serial interface and read access to lines are used to communicate with the AD7707 and the status the on-chip registers is also provided by this interface. All commu- of DRDY can be obtained by interrogating the MSB of the nications to the part must start with a write operation to the communications register. This scheme is suitable for interfacing to RESET communications register. After power-on or , the device CS microcontrollers. If is required as a decoding signal, it can expects a write to its communications register. The data written to be generated from a port bit. For microcontroller interfaces, it is this register determines whether the next operation to the part recommended that SCLK idles high between data transfers. is a read or a write operation and also determines to which register The AD7707 can also be operated with CS used as a frame this read or write operation occurs. Therefore, write access to synchronization signal. This scheme is suitable for DSP interfaces. any of the other registers on the part starts with a write operation to In this case, the first bit (MSB) is effectively clocked out by CS the communications register followed by a write to the selected CS because normally occurs after the falling edge of SCLK in register. A read operation from any other register on the part DSPs. The SCLK can continue to run between data transfers (including the data register) starts with a write operation to the provided UIBU
the timing numbers are obeyed. communications register followed by a read operation from the selected register. RESET The serial interface can be reset by exercising the input on the part. It can also be reset by writing a series of 1s on the The AD7707 serial interface consists of five signals CS, SCLK, DIN input. If a Logic 1 is written to the AD7707 DIN line for at DIN, DOUT, and DRDY. The DIN line is used for transferring least 32 serial clock cycles, the serial interface is reset. This ensures data into the on-chip registers, and the DOUT line is used for that in 3-wire systems, if the interface is lost either via a accessing data from the on-chip registers. SCLK is the serial clock software error or by a glitch in the system, it can be reset back input for the device and all data transfers (either on DIN or to a known state. This state returns the interface to where the DRDY DOUT) take place with respect to this SCLK signal. The AD7707 is expecting a write operation to its communications line is used as a status signal to indicate when data is ready to be register. This operation in itself does not reset the contents of read from the AD7707 data register. DRDY goes low when a any registers but because the interface was lost, the information new data word is available in the output register. It is reset high written to any of the registers is unknown and it is advisable to when a read operation from the data register is complete. It also set up all registers again. goes high prior to the updating of the output register to indicate Some microprocessor or microcontroller serial interfaces have a when not to read from the device to ensure that a data read is single serial data line. In this case, it is possible to connect the CS not attempted while the register is being updated. is used to AD7707’s DATA OUT and DATA IN lines together and connect select the device. It can be used to decode the AD7707 in systems them to the single data line of the processor. A 10 kΩ pull-up where a number of parts are connected to the serial bus. resistor should be used on this single data line. In this case, if Figure 20 and Figure 21 show timing diagrams for interfacing to the interface is lost, because the read and write operations share the AD7707 with CS used to decode the part. Figure 20 is for a the same line, the procedure to reset it back to a known state is read operation from the AD7707’s output shift register whereas somewhat different than previously described. It requires a read Figure 21 shows a write operation to the input shift register. It is operation of 24 serial clocks followed by a write operation possible to read the same data twice from the output register where a Logic 1 is written for at least 32 serial clock cycles to DRDY even though the line returns high after the first read ensure that the serial interface is back into a known state. operation. Care must be taken, however, to ensure that the read operations have been completed before the next output update is about to take place. Rev. B | Page 36 of 52 AD7707 CONFIGURING THE AD7707 The AD7707 contains six on-chip registers that the user can update of the data register has taken place, the second in which accesses via the serial interface. Communication with any of the DRDY bit of the communications register is interrogated to these registers is initiated by writing to the communications determine if a data register update has taken place. Also included register first. Figure 22 outlines a flow diagram of the sequence in the flowing diagram is a series of words that should be writ- used to configure all registers after a power-up or reset on the ten to the registers for a particular set of operating conditions. AD7707. The flowchart also shows two different read options— These conditions are gain of 1, no filter sync, bipolar mode, DRDY the first in which the pin is polled to determine when an buffer off, clock of 4.9512 MHz, and an output rate of 50 Hz. DRDY t t 10 3 CS t 4 t t 8 6 SCLK t t t 5 7 9 DOUT MSB LSB Figure 20. Read Cycle Timing Diagram CS t t 11 t 16 14 SCLK t t 15 12 t 13 LSB DIN MSB Figure 21. Write Cycle Timing Diagram Rev. B | Page 37 of 52 08691-021 08691-020 AD7707 START POWER-ON/RESET FOR AD7707 CONFIGURE AND INITIALIZE MICROCONVERTER/ MICROPROCESSOR SERIAL PORT WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL AND SETTING UP NEXT OPERATION TO BE A WRITE TO THE CLOCK REGISTER (20 HEX) WRITE TO CLOCK REGISTER SETTING THE CLOCK BITS IN ACCORDANCE WITH THE APPLIED MASTER CLOCK SIGNAL AND SELECT UPDATE RATE FOR SELECTED CHANNEL (0C HEX) WRITE TO COMMUNICATIONS REGISTER SELECTING CHANNEL AND SETTING UP NEXT OPERATION TO BE A WRITE TO THE SETUP REGISTER (10 HEX) WRITE TO SETUP REGISTER CLEARING F SYNC, SETTING UP GAIN, OPERATING CONDITIONS AND INITIATING A SELF-CALIBRATION ON SELECTED CHANNEL (40 HEX) POLL DRDY PIN NO WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT DRDY OPERATION TO BE A READ FROM THE COMMUNICATIONS LOW? REGISTER (08 HEX) YES READ FROM COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) POLL DRDY BIT OF COMMUNICATIONS REGISTER READ FROM DATA REGISTER NO DRDY LOW? YES WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION TO BE A READ FROM THE DATA REGISTER (38 HEX) READ FROM DATA REGISTER Figure 22. Flowchart for Setting Up and Reading from the AD7707 Rev. B | Page 38 of 52 08691-022 AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7707’s flexible serial interface allows for easy interface that require control of the CS input on the AD7707, one of the to most microcomputers and microprocessors. The flowchart of port bits of the 68HC11 (such as PC1), which is configured as Figure 22 outlines the sequence that should be followed when an output, can be used to drive the CS input. interfacing a microcontroller or microprocessor to the AD7707. V DD Figure 23 and Figure 24 show some typical interface circuits. AD7707 V DD The serial interface on the AD7707 is capable of operating from SS just three wires and is compatible with SPI interface protocols. RESET 68HC11 The 3-wire operation makes the part ideal for isolated systems in which minimizing the number of interface lines also minimizes SCK SCLK the number of opto-isolators required in the system. The serial clock input is a Schmitt-triggered input to accommodate slow MISO DOUT edges from optocouplers. The rise and fall times of other digital inputs to the AD7707 should be no longer than 1 μs. MOSI DIN Most of the registers on the AD7707 are 8-bit registers, which facilitates easy interfacing to the 8-bit serial ports of microcon- CS trollers. The data register on the AD7707 is 16 bits, and the zero-scale and full-scale calibration registers are 24-bit registers but data transfers to these registers can consist of multiple 8-bit Figure 23. AD7707-to-68HC11 Interface transfers to the serial port of the microcontroller. DSP processors The 68HC11 is configured in master mode with its CPOL bit and microprocessors generally transfer 16 bits of data in a serial set to a Logic 1 and its CPHA bit set to a Logic 1. When the data operation. Some of these processors, such as the ADSP-2105, 68HC11 is configured like this, its SCLK line idles high between have the facility to program the amount of cycles in a serial data transfers. The AD7707 is not capable of full duplex operation. transfer. This allows the user to tailor the number of bits in any If the AD7707 is configured for a write operation, no data appears transfer to match the register length of the required register in on the DATA OUT lines even when the SCLK input is active. the AD7707. Similarly, if the AD7707 is configured for a read operation, data Even though some of the registers on the AD7707 are only eight presented to the part on the DATA IN line is ignored even when bits in length, communicating with two of these registers in SCLK is active. successive write operations can be handled as a single 16-bit Coding for an interface between the 68HC11 and the AD7707 is data transfer if required. For example, if the setup register is to given in the C Code for Interfacing AD7707 to 68HC11 section. be updated, the processor must first write to the communications DRDY In this example, the output line of the AD7707 is register (indicating that the next operation is a write to the connected to the PC0 port bit of the 68HC11 and is polled to setup register) and then write eight bits to the setup register. If determine its status. required, this can all be performed in a single 16-bit transfer because once the eight serial clocks of the write operation to the communications register have been completed, the part immediately sets itself up for a write operation to the setup register. AD7707TO68HC11 INTERFACE Figure 23 shows an interface between the AD7707 and the 68HC11 microcontroller. The diagram shows the minimum (3-wire) CS interface with on the AD7707 hard-wired low. In this DRDY scheme, the bit of the communications register is monitored to determine when the data register is updated. An alternative scheme, which increases the number of interface lines to four, is to monitor the DRDY output line from the AD7707. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 68HC11 port bits (such as PC0), which is configured as an input. This port bit is then DRDY polled to determine the status of . The second scheme is DRDY to use an interrupt driven system, in which case the output is connected to the IRQ input of the 68HC11. For interfaces Rev. B | Page 39 of 52 08691-023 AD7707 data transfers. The 8XC51 outputs the LSB first in a write AD7707TO 8XC51INTERFACE operation; however, the AD7707 expects the MSB first so the An interface circuit between the AD7707 and the 8XC51 data to be transmitted must be rearranged before being written microcontroller is shown in Figure 24. The diagram shows the to the output serial register. Similarly, the AD7707 outputs the MSB CS minimum number of interface connections with on the first during a read operation; however, the 8XC51 expects the AD7707 hard-wired low. In the case of the 8XC51 interface, the LSB first. Therefore, the data read into the serial buffer must be minimum number of interconnects is just two. In this scheme, rearranged before the correct data word from the AD7707 is DRDY the bit of the communications register is monitored to available in the accumulator. determine when the data register is updated. The alternative scheme, which increases the number of interface lines to three, V DD AD7707 is to monitor the DRDY output line from the AD7707. The monitoring of the DRDY line can be done in two ways. First, 8XC51 V DD RESET DRDY can be connected to one of the 8XC51’s port bits (such as P1.0), which is configured as an input. This port bit is then polled P3.0 DOUT DRDY to determine the status of . The second scheme is to use DRDY an interrupt-driven system, in which case the output is DIN connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7707, one of the port P3.1 SCLK bits of the 8XC51 (such as P1.1), which is configured as an output, CS can be used to drive the input. The 8XC51 is configured in CS its Mode 0 serial interface mode. Its serial interface contains a single data line. As a result, the DATA OUT and DATA IN pins of the AD7707 should be connected together with a 10 kΩ pull- Figure 24. AD7707-to-8XC51 Interface up resistor. The serial clock on the 8XC51 idles high between Rev. B | Page 40 of 52 08691-024 AD7707 CODE FOR SETTING UP THE AD7707 The C Code for Interfacing AD7707 to 68HC11 section gives a assumes that the external crystal is 4.9512 MHz. The set of read and write routines in C code for interfacing the update rate is selected to be 50 Hz. 68HC11 microcontroller to the AD7707. The sample program 3. Write to communication register selecting Channel 1 sets up the various registers on the AD7707 and reads 1000 (AIN1) as the active channel and setting the next operation samples from the part into the 68HC11. The setup conditions to be a write to the setup register. on the part are exactly the same as those outlined for the 4. Write to the setup register, setting the gain to 1, setting flowchart of Figure 22. In the example code given here, the bipolar mode, buffer off, clearing the filter synchroniza- DRDY output is polled to determine if a new valid word is tion, and initiating a self-calibration. available in the data register. 5. Poll the DRDY output. The sequence of the events in this program are as follows: 6. Read the data from the data register. 1. Write to the communications register, selecting Channel 1 (AIN1) as the active channel and setting the next operation 7. Repeat Step 5 and Step 6 until the specified number of to be a write to the clock register. samples have been taken from the selected channel. 2. Write to the clock register setting the CLKDIV bit to 1, which divides the external clock internally by two. This C CODE FOR INTERFACING AD7707 TO 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7707 and the sample program sets the various registers and then reads 1000 samples from one channel. */ #include #include #define NUM_SAMPLES 1000 /* change the number of data samples */ #define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */ Writetoreg (int); Read (int,char); char *datapointer = store; char store[NUM_SAMPLES*MAX_REG_LENGTH + 30]; void main () { /* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */ char a; DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */ PORTC | = 0x04; /* make the /CS line high */ Writetoreg (0x20); /* Active Channel is AIN1/LOCOM, next operation as write to the clock register */ Writetoreg (0x18); /* master clock enabled, 4.9512 MHz Clock, set output rate to 50 Hz*/ Writetoreg (0x10); /* Active Channel is AIN1/LOCOM, next operation as write to the setup register */ Writetoreg (0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/ while (PORTC and 0x10); /* wait for /DRDY to go low */ for (a=0;a