ANALOG DEVICES AD7701

2 LC MOS 16-Bit A/D Converter AD7701 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 16-Bit ADC AV DV AV DV SC1 SC2 DD DD SS SS 0.0015% Linearity Error 14 15 7 64 17 On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter AD7701 0.1 Hz to 10 Hz Corner Frequency CALIBRATION CALIBRATION 0 V to +2.5 V or �2.5 V Analog Input Range 13 CAL SRAM MICROCONTROLLER 4 kSPS Output Data Rate Flexible Serial Interface Ultralow Power 16-BIT A/D CONVERTER A IN 9 12 BP/UP 6-POLE GAUSSIAN APPLICATIONS ANALOG LOW-PASS Industrial Process Control MODULATOR V DIGITAL FILTER 10 REF 11 SLEEP Weigh Scales Portable Instrumentation Remote Data Acquisition AGND 8 20 SDATA CLOCK SERIAL INTERFACE GENERATOR LOGIC 19 SCLK DGND 5 3 2 1 16 18 CLKIN CLKOUT MODE CS DRDY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7701 is a 16-bit ADC that uses a sigma-delta conversion 1. The AD7701 offers 16-bit resolution coupled with outstand- technique. The analog input is continuously sampled by an analog ing 0.0015% accuracy. modulator whose mean output duty cycle is proportional to the 2. No missing codes ensures true, usable, 16-bit dynamic range, input signal. The modulator output is processed by an on-chip removing the need for programmable gain and level-setting digital filter with a six-pole Gaussian response, which updates circuitry. the output data register with 16-bit binary words at word rates up 3. The effects of temperature drift are eliminated by on-chip to 4 kHz. The sampling rate, filter corner frequency, and output self-calibration, which removes zero and gain error. External word rate are set by a master clock input that may be supplied circuits can also be included in the calibration loop to remove externally, or by a crystal controlled on-chip clock oscillator. system offsets and gain errors. 4. A flexible synchronous/asynchronous interface allows the The inherent linearity of the ADC is excellent and endpoint AD7701 to interface directly to UARTs or to the serial ports accuracy is ensured by self-calibration of zero and full scale, of industry-standard microcontrollers. which may be initiated at any time. The self-calibration scheme 5. Low operating power consumption and an ultralow power can also be extended to null system offset and gain errors in the standby mode make the AD7701 ideal for loop-powered input channel. remote sensing applications, or battery-powered portable The output data is accessed through a flexible serial port, which instruments. has an asynchronous mode compatible with UARTs and two synchronous modes suitable for interfacing to shift registers or the serial ports of industry-standard microcontrollers. CMOS construction ensures low power dissipation, and a power- down mode reduces the idle power consumption to only 10 µW. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD7701–SPECIFICATIONS (T = 25�C; AV = DV = +5 V; AV = DV = –5 V; V = +2.5 V; f = 4.096 MHz; A DD DD SS SS REF CLKIN 1 Bipolar Mode: MODE = +5 V; A Source Resistance = 1k� with 1 nF to AGND at A ; unless otherwise noted.) IN IN 2 2 Parameter A, S Version B, T Version Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 16 Bits Integral Nonlinearity T to T ±0.0007 % FSR typ MIN MAX ±0.003 ±0.0015 % FSR max Differential Nonlinearity T to T ±0.125 ±0.125 LSB typ Guaranteed No Missing Codes MIN MAX ±0.5 ±0.5 LSB max 3 Positive Full-Scale Error ±0.13 ±0.13 LSB typ ±0.5 ±0.5 LSB max 4 Full-Scale Drift ±1.2 (±2.3 S Version) ±1.2 (±2.3 T Version) LSB typ 3 Unipolar Offset Error ±0.25 ±0.25 LSB typ ±1 ±1 LSB max 4 Unipolar Offset Drift ±1.6 (+3/–25 S Version) ±1.6 (+3/–25 T Version) LSB typ 3 Bipolar Zero Error ±0.25 ±0.25 LSB typ ±1 ± 1 LSB max 4 Bipolar Zero Drift ±0.8 (+1.5/–12.5 S Version) ±0.8 (+1.5/–12.5 T Version) LSB typ 3 Bipolar Negative Full-Scale Error ±0.5 ±0.5 LSB typ ±2 ±2 LSB max 4 Bipolar Negative Full-Scale Drift ±0.6 (±1.2 S Version) ±0.6 (±1.2 T Version) LSB typ Noise (Referred to Output) 0.1 0.1 LSB rms typ DYNAMIC PERFORMANCE Sampling Frequency, f f /256 f /256 Hz S CLKIN CLKIN Output Update Rate, f f /1024 f /1024 Hz OUT CLKIN CLKIN Filter Corner Frequency, f f /409,600 f /409,600 Hz –3 dB CLKIN CLKIN Settling Time to ±0.0007% FS 507904/f 507904/f sec For Full-Scale Input Step CLKIN CLKIN SYSTEM CALIBRATION Applies to unipolar and Positive Full-Scale Overrange V + 0.1 V + 0.1 V max bipolar ranges. After cali- REF REF Positive Full-Scale Overrange V + 0.1 V + 0.1 V max bration, if A > V , the REF REF IN REF Negative Full-Scale Overrange –(V + 0.1) –(V + 0.1) V max device will output all 1s. REF REF 5, 6 Maximum Offset Calibration Range If A < 0 (unipolar) or IN Unipolar Input Range –(V + 0.1) –(V + 0.1) V max –V (bipolar), the device REF REF REF Bipolar Input Range –0.4 V to +0.4 V –0.4 V to +0.4 V V max will output all 0s. REF REF REF REF 7 Input Span 0.8 V 0.8 V V min REF REF 2 V + 0.2 2 V + 0.2 V max REF REF ANALOG INPUT Unipolar Input Range 0 to 2.5 0 to 2.5 V Bipolar Input Range ±2.5 ±2.5 V Input Capacitance 10 10 pF typ 1 Input Bias Current 11 nA typ LOGIC INPUTS All Inputs Except CLKIN V , Input Low Voltage 0.8 0.8 V max INL V , Input High Voltage 2.0 2.0 V min INH CLKIN V , Input Low Voltage 0.8 0.8 V max INL V , Input High Voltage 3.5 3.5 V min INH I , Input Current 10 10 µA max IN LOGIC OUTPUTS V , Output Low Voltage 0.4 0.4 V max I = 1.6 mA OL SINK V , Output High Voltage DV – 1 DV – 1 V min I = 100 µA OH DD DD SOURCE Floating State Leakage Current ±10 ±10 µA max Floating State Output Capacitance 9 9 pF typ –2– REV. E AD7701 2 2 Parameter A, S Version B, T Version Unit Test Conditions/Comments 8 POWER REQUIREMENTS Power Supply Voltages Analog Positive Supply (AV ) 4.5/5.5 4.5/5.5 V min/V max DD Digital Positive Supply (DV ) 4.5/AV 4.5/AV V min/V max DD DD DD Analog Negative Supply (AV ) –4.5/–5.5 –4.5/–5.5 V min/V max SS Digital Negative Supply (DV ) –4.5/–5.5 –4.5/–5.5 V min/V max SS Calibration Memory Retention Power Supply Voltage 2.0 2.0 V min 8 DC Power Supply Currents Analog Positive Supply (AI ) 2.7 2.7 mA max Typically 2 mA DD Digital Positive Supply (DI)2 2 mA max Typically 1 mA DD Analog Negative Supply (AI ) 2.7 2.7 mA max Typically 2 mA SS Digital Negative Supply (DI ) 0.1 0.1 mA max Typically 0.03 mA SS 9 Power Supply Rejection Positive Supplies 70 70 dB typ Negative Supplies 75 75 dB typ Power Dissipation Normal Operation 37 37 mW max SLEEP = Logic 1, Typically 25 mW 10 Standby Operation 20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0, Typically 10 µW NOTES 1 The A pin presents a very high impedance dynamic load that varies with clock frequency. IN 2 Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C. 3 Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges. 4 Total drift over the specified temperature range since calibration at power-up at 25 °C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5 In Unipolar mode, the offset can have a negative value (–V ) such that the Unipolar mode can mimic Bipolar mode operation. REF 6 The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7 For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V +0.1). REF 8 All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9 Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10 CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice. REV. E –3– AD7701 1 ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (T = 25°C, unless otherwise noted.) Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C A Industrial CERDIP (A, B Versions) . . . . . . –40°C to +85°C DV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD Extended CERDIP (S, T Versions) . . . . . –55°C to +125°C DV to AV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DD DD Storage Temperature Range. . . . . . . . . . . . . –65°C to +150°C DV to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V SS Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V SS Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V NOTES Digital Input Voltage to DGND . . . . –0.3 V to DV + 0.3 V DD 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- Analog Input nent damage to the device. This is a stress rating only; functional operation of the Voltage to AGND . . . . . . . . AV – 0.3 V to AV + 0.3 V SS DD device at these or any other conditions above those listed in the operational 2 Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Temperature Linearity Package Model Range Error (% FSR) Options* AD7701AN –40°C to +85°C 0.003 N-20 AD7701BN –40°C to +85°C 0.0015 N-20 AD7701AR –40°C to +85°C 0.003 R-20 AD7701BR –40°C to +85°C 0.0015 R-20 AD7701ARS –40°C to +85°C 0.003 RS-28 AD7701AQ –40°C to +85°C 0.003 Q-20 AD7701BQ –40°C to +85°C 0.0015 Q-20 AD7701SQ –55°C to +125°C 0.003 Q-20 AD7701TQ –55°C to +125°C 0.0015 Q-20 *N = PDIP; Q = CERDIP; R = SOIC; RS = SSOP. PIN CONFIGURATIONS PDIP, CERDIP, SOIC SSOP MODE SDATA MODE 1 1 20 28 SDATA CLKOUT 2 19 SCLK CLKOUT 2 27 SCLK 3 18 DRDY 3 26 CLKIN CLKIN DRDY 17 SC2 4 25 SC2 4 SC1 SC1 AD7701 5 16 CS 5 24 CS DGND DGND TOP VIEW (Not to Scale) DV NC DV 6 15 NC 6 23 SS DD AD7701 AV AV 7 14 NC 7 22 NC SS DD TOP VIEW AGND 8 13 CAL DV 8 21 NC SS (Not to Scale) A 12 BP/UP NC 20 DV 9 9 DD IN V AV 10 11 10 19 AV REF SLEEP SS DD NC NC 11 18 AGND 17 CAL 12 A 13 16 IN BP/UP V 15 REF 14 SLEEP NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7701 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. E AD7701 PIN FUNCTION DESCRIPTIONS Pin No. PDIP, CERDIP, SOIC SSOP Mnemonic Description 11 MODE Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the Asynchronous Communications (AC) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes, each with one start bit and two stop bits. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency of f /4 and 25% duty cycle. CLKlN 22 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. 33 CLKIN Clock Input for External Clock. 4, 17 4, 25 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. 55 DGND Digital Ground. Ground reference for all digital signals. 68 DV Digital Negative Supply, –5 V Nominal. SS 6, 7, 9, 11, NC No Connect. 18, 21, 22, 23 710 AV Analog Negative Supply, –5 V Nominal. SS 812 AGND Analog Ground. Ground reference for all analog signals. 913 A Analog Input. IN 10 14 V Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale REF in the Unipolar mode and of both positive and negative full scale in Bipolar mode. 11 15 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7701 goes into a low power mode with typically 10 µW power consumption. 12 16 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a uni- polar input range going from AGND to V . When Pin 12 is high, the AD7701 is REF configured for a bipolar input range, ±V . REF 13 17 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7701 is reset and performs a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7701s. 14 19 AV Analog Positive Supply, +5 V Nominal. DD 15 20 DV Digital Positive Supply, +5 V Nominal. DD 16 24 CS Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format determined by the state of the MODE pin. 18 26 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after transmission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 27 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, depen- dent on the type of serial data transmission that has been selected by the MODE pin. When configured as an output in the Synchronous Self-Clocking mode, it has a fre- quency of f /4 and a duty cycle of 25%. CLKIN 20 28 SDATA Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial word. The transmission format is determined by the state of the MODE pin. REV. E –5– AD7701 (AV = DV = +5 V � 10%; AV = DV = –5 V � 10%; AGND = DGND = O V; f = DD DD SS SS CLKIN 1, 2 TIMING CHARACTERISTICS 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV ; unless otherwise noted.) DD Limit at T , T Limit at T , T MIN MAX MIN MAX Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments 3, 4 f 200 200 kHz min Master Clock Frequency: Internal Gate Oscillator. CLKIN 55 MHz max Typically 4.096 MHz. 200 200 kHz min Master Clock Frequency: Externally Supplied. 55 MHz max 5 50 50 ns max Digital Output Rise Time. Typically 20 ns. t r 5 t 50 50 ns max Digital Output Fall Time. Typically 20 ns. f t 00 ns min SC1, SC2 to CAL High Setup Time. 1 50 50 ns min SC1, SC2 Hold Time after CAL Goes High. t 2 6 t 1000 1000 ns min SLEEP High to CLKIN High Setup Time. 3 SSC MODE 7 t 3/f 3/f ns max Data Access Time (CS Low to Data Valid). 4 CLKIN CLKIN t 100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ). 5 t 250 250 ns min MSB Data Setup Time. Typically 380 ns. 6 t 300 300 ns max SCLK High Pulsewidth. Typically 240 ns. 7 t 790 790 ns max SCLK Low Pulsewidth. Typically 730 ns. 8 8 t l/f +200 l/f +200 ns max SCLK Rising Edge to Hi-Z Delay (l/f + 100 ns typ). 9 CLKIN CLKIN CLKIN 8, 9 t (4/f ) +200 (4/f ) +200 ns max CS High to Hi-Z Delay. 10 CLKIN CLKIN SEC MODE f 55 MHz Serial Clock Input Frequency. SCLK t 35 35 ns min SCLK Input High Pulsewidth. 11 t 160 160 ns min SCLK Low Pulsewidth. 12 7, 10 t 160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns. 13 11 t 150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns. 14 8 t 250 250 ns max CS High to Hi-Z Delay. 15 8 t 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns. 16 AC MODE 40 40 ns min CS Setup Time. Typically 20 ns. t 17 t 180 180 ns max Data Delay Time. Typically 90 ns. 18 t 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns. 19 NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. r f 2 See Figures 1 to 6. 3 CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7701 is production tested with f at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. CLKIN 5 Specified using 10% and 90% points on waveform of interest. 6 In order to synchronize several AD7701s together using the SLEEP pin, this specification must be met. 7 t and t are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 13 8 t , t , t , and t are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number 9 10 15 16 is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitance. 9 If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 10 If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than four CLKIN cycles plus 160 ns after CS goes low. 11 SDATA is clocked out on the falling edge of the SCLK input. Specifications subject to change without notice. –6– REV. E AD7701 I OL 1.6mA CAL TO + CLKIN OUTPUT 2.1V C PIN L t t 1 2 t 3 100pF I OH SC1, SC2 SC1, SC2 VALID SLEEP 200µA Figure 2a. Calibration Control Timing Figure 1. Load Circuit for Access Figure 2b. SLEEP Mode Timing Time and Bus Relinquish Time DRDY CS t 12 t CS 11 SCLK CS t 15 t t 13 16 t t HI-Z 14 10 DATA SDATA HI-Z HI-Z VALID HI-Z SDATA DB15 DB14 DB0 DB1 DATA SDATA VALID Figure 4a. SEC Mode Data Hold Time Figure 3. SSC Mode Data Figure 4b. SEC Mode Timing Diagram Hold Time CLKIN CS DRDY t 7 CS t 8 HI-Z t 17 SCLK SCLK t t 4 5 t t t 18 19 6 START t 5 HI-Z HI-Z SDATA HI-Z HI-Z DB8 DB7 STOP 1 DB9 STOP 2 SDATA DB15 DB14 DB1 DB0 HIGH BYTE LOW BYTE Figure 5. SSC Mode Timing Diagram Figure 6. AC Mode Timing Diagram DEFINITION OF TERMS Bipolar Zero Error Linearity Error This is the deviation of the midscale transition (0111 . . . 111 to This is the maximum deviation of any code from a straight line 1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating passing through the endpoints of the transfer function. The in the Bipolar mode. It is expressed in microvolts. endpoints of the transfer function are zero scale (not to be Bipolar Negative Full-Scale Error confused with bipolar zero), a point 0.5 LSB below the first This is the deviation of the first code transition from the ideal code transition (000 . . . 000 to 000 . . . 001) and full scale, a (–V + 0.5 LSB) when operating in the Bipolar mode. It is REF point 1.5 LSB above the last code transition (111 . . . 110 to expressed in microvolts. 111 . . . 111). The error is expressed as a percentage of full scale. Positive Full-Scale Overrange Differential Linearity Error Positive full-scale overrange is the amount of overhead available This is the difference between any code’s actual width and the to handle input voltages greater than +V (for example, noise REF ideal (1 LSB) width. Differential linearity error is expressed in peaks or excess voltages due to system gain errors in system LSBs. A differential linearity specification of ±1 LSB or less calibration routines) without introducing errors due to overloading guarantees monotonicity. the analog modulator or overflowing the digital filter. It is Positive Full-Scale Error expressed in millivolts. Positive full-scale error is the deviation of the last code transition Negative Full-Scale Overrange (111 . . . 110 to 111 . . . 111) from the ideal (V ±3/2 LSBs). REF This is the amount of overhead available to handle voltages below It applies to both positive and negative analog input ranges and –V without overloading the analog modulator or overflowing REF is expressed in microvolts. the digital filter. Note that the analog input will accept negative Unipolar Offset Error voltage peaks even in the Unipolar mode. The overhead is Unipolar offset error is the deviation of the first code transition expressed in millivolts. from the ideal (AGND + 0.5 LSB) when operating in the Uni- polar mode. It is expressed in microvolts. REV. E –7– AD7701 The AD7701 can perform self-calibration using the on-chip Offset Calibration Range calibration microcontroller and SRAM to store calibration In the system calibration modes (SC2 low), the AD7701 cali- parameters. A calibration cycle may be initiated at any time brates its offset with respect to the A pin. The offset calibration IN using the CAL control input. range specification defines the range of voltages, expressed as a percentage of V , that the AD7701 can accept and still accu- REF Other system components may also be included in the calibra- rately calibrate offset. tion loop to remove offset and gain errors in the input channel. Full-Scale Calibration Range For battery operation, the AD7701 also offers a standby mode This is the range of voltages that the AD7701 can accept in the that reduces idle power consumption to typically 10 µW. system calibration mode and still correctly calibrate full scale. THEORY OF OPERATION Input Span The general block diagram of a sigma-delta ADC is shown in In system calibration schemes, two voltages applied in sequence Figure 8. It contains the following elements: to the AD7701’s analog input define the analog input range. The input span specification defines the minimum and maxi- 1. A sample-hold amplifier mum input voltages from zero to full scale that the AD7701 can 2. A differential amplifier or subtracter accept and still accurately calibrate gain. The input span is 3. An analog low-pass filter expressed as a percentage of V REF. 4. A 1-bit A/D converter (comparator) 5. A 1-bit DAC GENERAL DESCRIPTION 6. A digital low-pass filter The AD7701 is a 16-bit A/D converter with on-chip digital In operation, the analog signal sample is fed to the subtracter, filtering, intended for the measurement of wide dynamic range, along with the output of the 1-bit DAC. The filtered difference low frequency signals such as those representing chemical, signal is fed to the comparator, whose output samples the differ- physical, or biological processes. It contains a charge-balancing ence signal at a frequency many times that of the analog signal (sigma-delta) ADC, calibration microcontroller with on-chip sampling frequency (oversampling). static RAM, clock oscillator, and serial communications port. The analog input signal to the AD7701 is continuously sampled S/H AMP COMPARATOR at a rate determined by the frequency of the master clock, CLKIN. ANALOG LOW-PASS A charge-balancing A/D converter (sigma-delta modulator) DIGITAL FILTER FILTER converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. A six-pole Gaussian digi- tal low-pass filter processes the output of the modulator and DIGITAL DATA DAC updates the 16-bit output register at a 4 kHz rate. The output data can be read from the serial port randomly or periodically at any rate up to 4 kHz. Figure 8. General Sigma-Delta ADC Oversampling is fundamental to the operation of sigma-delta +5V ANALOG ADCs. Using the quantization noise formula for an ADC: SUPPLY 0.1µF 10µF SNR = (6.02 × number of bits + 1.76) dB AV DV DD DD a 1-bit ADC or comparator yields an SNR of 7.78 dB. 0.1µF VOLTAGE 2.5V SLEEP V REFERENCE REF The AD7701 samples the input signal at 16 kHz, which spreads MODE the quantization noise from 0 kHz to 8 kHz. Since the specified READ DRDY READY analog input bandwidth of the AD7701 is only 0 Hz to 10 Hz, READ CS RANGE the noise energy in this bandwidth would be only 1/800 of the (TRANSMIT) BP/UP SELECT SERIAL total quantization noise, even if the noise energy were spread SCLK CLOCK evenly throughout the spectrum. It is reduced still further by CALIBRATE CAL SERIAL SDATA DATA analog filtering in the modulator loop, which shapes the quanti- AD7701 zation noise spectrum to move most of the noise energy to CLKIN ANALOG A frequencies above 10 Hz. The SNR performance in the 0 Hz to IN INPUT CLKOUT 10 Hz range is conditioned to the 16-bit level in this fashion. The output of the comparator provides the digital input for the SC2 ANALOG AGND 1-bit DAC, so the system functions as a negative feedback loop GROUND DGND 0.1µF 0.1µF that minimizes the difference signal. The digital data that repre- DV AV SS SS sents the analog input voltage is in the duty cycle of the pulse –5V train appearing at the output of the comparator. It can be ANALOG SUPPLY retrieved as a parallel binary data-word using a digital filter. 0.1µF 10µF Sigma-delta ADCs are generally described by the order of the analog low-pass filter. A simple example of a first-order, sigma- delta ADC is shown in Figure 9. This contains only a first-order, Figure 7. Typical System Connection Diagram low-pass filter or integrator. It also illustrates the derivation of the alternative name for these devices: charge-balancing ADCs. –8– REV. E AD7701 C Figure 10 shows the filter frequency response. This is a six-pole CLOCK Gaussian response that provides 55 dB of 60 Hz rejection for a R A 10 Hz cutoff frequency. If the clock frequency is halved to give a IN 5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized TO DIGITAL FILTER s-domain pole-zero plot of the filter is shown in Figure 11. INTEGRATOR STROBED The response of the filter is defined by: COMPARATOR R −05 . 24 6   10++.. 693xx 0 240+ 0.0555x+ Hx = ()   +V 810 12 REF 0.. 00962xx++ 0 00133 0.000154x     –V REF where 1-BIT DAC xf== f ,f f 409600 33 dB dB CLKIN Figure 9. SEC Basic Charge-Balancing ADC and f is the frequency of interest. The term charge-balancing comes from the fact that this system is a negative feedback loop that tries to keep the net charge on 20 the integrator capacitor at zero by balancing charge injected by 0 the input voltage with charge injected by the 1-bit DAC. When f = 4MHz CLK the analog input is zero the only contribution to the integrator –20 output comes from the 1-bit DAC. For the net charge on the –40 integrator capacitor to be zero, the DAC output must spend half its time at +1 V and half its time at –1 V. Assuming ideal com- –60 f = 2MHz CLK ponents, the duty cycle of the comparator will be 50%. –80 When a positive analog input is applied, the output of the 1-bit –100 DAC must spend a larger proportion of the time at +1 V, so the duty cycle of the comparator increases. When a negative input –120 f = 1MHz CLK voltage is applied, the duty cycle decreases. –140 The AD7701 uses a second-order, sigma-delta modulator and a –160 sophisticated digital filter that provides a rolling average of the 1 100 10 FREQUENCY – Hz sampled output. After power-up or if there is a step change in the input voltage, there is a settling time that must elapse before Figure 10. Frequency Response of AD7701 Filter valid data is obtained. jw j2 DIGITAL FILTERING The AD7701’s digital filter behaves like an analog filter, with a few minor differences. j1 First, since digital filtering occurs after the analog-to-digital S1,2 = –1.4663 + j1.8191 s conversion, it can remove noise injected during the conversion S3,4 = –1.7553 + j1.0005 0 –2 –1 process. Analog filtering cannot do this. S5,6 = –1.8739 + j0.32272 On the other hand, analog filtering can remove noise super- –j1 imposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near –j2 full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7701 has over- Figure 11. Normalized Pole-Zero Plot of AD7701 Filter range headroom built into the sigma-delta modulator and digital Since the AD7701 contains this on-chip, low-pass filtering, filter that allows overrange excursions of 100 mV. If noise there is a settling time associated with step function inputs, signals are larger than this, consideration should be given to and data will be invalid after a step change until the settling analog input filtering, or to reducing the gain in the input time has elapsed. The AD7701 is, therefore, unsuitable for channel so that a full-scale input (2.5 V) gives only a half-scale high speed multiplexing, where channels are switched and input to the AD7701 (1.25 V). This will provide an overrange converted sequentially at high rates, as switching between chan- capability greater than 100% at the expense of reducing the nels can cause a step change in the input. Rather, it is intended dynamic range by one bit (50%). for distributed converter systems using one ADC per channel. However, slow multiplexing of the AD7701 is possible, pro- FILTER CHARACTERISTICS vided that the settling time is allowed to elapse before data for The cutoff frequency of the digital filter is f /409600. At the CLK the new channel is accessed. maximum clock frequency of 4.096 MHz, the cutoff frequency of the filter is 10 Hz and the output rate is 4 kHz. REV. E –9– GAIN – dBs AD7701 The output settling of the AD7701 in response to a step input The input sampling frequency, output data rate, filter character- change is shown in Figure 12. The Gaussian response has fast istics, and calibration time are all directly related to the master settling with no overshoot, and the worst-case settling time to clock frequency, f , by the ratios given in the specification CLKIN ±0.0007% (±0.5 LSB) is 125 ms with a 4.096 MHz master table. Therefore, the first step in system design with the AD7701 is clock frequency. to select a master clock frequency suitable for the bandwidth and output data rate required by the application. 100 ANALOG INPUT RANGES The AD7701 performs conversion relative to an externally 80 supplied reference voltage that allows easy interfacing to ratiometric systems. In addition, either unipolar or bipolar input 60 voltage ranges may be selected using the BP/UP input. With BP/UP tied low, the input range is unipolar and the span is 0 to 40 +V . With BP/UP tied high, the input range is bipolar and the REF span is ±V . In the Bipolar mode, both positive and negative REF 20 full scale are directly determined by V . This offers superior REF tracking of positive and negative full scale and better midscale 0 040 80 120 160 (bipolar zero) stability than bipolar schemes that simply scale TIME – ms and offset the input range. Figure 12. AD7701 Step Response The digital output coding for the unipolar range is unipolar binary; for the bipolar range it is offset binary. Bit weights for USING THE AD7701 the Unipolar and Bipolar modes are shown in Table I. The SYSTEM DESIGN CONSIDERATIONS input voltages and output codes for unipolar and bipolar ranges, The AD7701 operates differently from successive approxima- using the recommended +2.5 V reference, are shown in tion ADCs or other integrating ADCs. Since it samples the Table II. signal continuously, like a tracking ADC, there is no need for a start convert command. The 16-bit output register is updated at Table I. Bit Weight Table (2.5 V Reference Voltage) a 4 kHz rate, and the output can be read at any time, either Unipolar Mode Bipolar Mode synchronously or asynchronously. µV LSBs % FS ppm FS LSBs % FS ppm FS CLOCKING 10 0.26 0.0004 4 0.13 0.0002 2 The AD7701 requires a master clock input, which may be an 19 0.5 0.0008 8 0.26 0.0004 4 external TTL/CMOS compatible clock signal applied to the 38 1.00 0.0015 15 0.5 0.0008 8 CLKIN pin (CLKOUT not used). Alternatively, a crystal of 76 2.00 0.0031 31 1.00 0.0015 15 the correct frequency can be connected between CLKIN and 153 4.00 0.0061 61 2.00 0.0031 31 CLKOUT, when the clock circuit will function as a crystal controlled oscillator. Table II. Output Coding Unipolar Mode Bipolar Mode Input Relative to Input Relative to FS and AGND Input (V) FS and AGND Input (V) Output Data 1111 1111 1111 1111 +V – 1.5 LSB +2.499943 +V – 1.5 LSB +2.499886 1111 1111 1111 1110 REF REF +V – 2.5 LSB +2.499905 +V – 2.5 LSB +2.499810 1111 1111 1111 1101 REF REF +V – 3.5 LSB +2.499867 +V – 3.5 LSB +2.499733 1111 1111 1111 1100 REF REF 1000 0000 0000 0001 +V /2 + 0.5 LSB +1.250019 AGND + 0.5 LSB +0.000038 1000 0000 0000 0000 REF +V /2 – 0.5 LSB +1.249981 AGND – 0.5 LSB –0.000038 0111 1111 1111 1111 REF +V /2 – 1.5 LSB +1.249943 AGND – 1.5 LSB –0.000114 0111 1111 1111 1110 REF 0000 0000 0000 0011 AGND + 2.5 LSB +0.000095 –V + 2.5 LSB –2.499810 0000 0000 0000 0010 REF AGND + 1.5 LSB +0.000057 –V + 1.5 LSB –2.499886 0000 0000 0000 0001 REF AGND + 0.5 LSB +0.000019 –V + 0.5 LSB –2.499962 0000 0000 0000 0000 REF NOTES 1. V = 2.5 V REF 2. AGND = 0 V 3. Unipolar Mode, 1 LSB = 2.5 V/655536 = 0.000038 V 4. Bipolar Mode, 1 LSB = 5 V/65536 = 0.000076 V 5. Inputs are voltages at code transitions. –10– REV. E PERCENT OF FINAL VALUE AD7701 INPUT SIGNAL CONDITIONING An RC filter may be added in front of the AD7701 to reduce Reference voltages from 1 V to 3 V may be used with the AD7701 high frequency noise. With an external capacitor added from with little degradation in performance. Input ranges that cannot A to AGND, the following equation will specify the maximum IN be accommodated by this range of reference voltages may be allowable source resistance: achieved by input signal conditioning. This may take the form 62 of gain to accommodate a smaller signal range, or passive attenua- R = S (Max) 100 mV × C /(C + C ) IN IN EXT tion to reduce a larger input voltage range. f ×(C +C ) × ln CLKIN IN EXT   V E   Source Resistance If passive attenuators are used in front of the AD7701, care must The practical limit to the maximum value of source resistance is be taken to ensure that the source impedance is sufficiently low. thermal (Johnson) noise. A practical resistor may be modeled as The AD7701 has an analog input with over 1 GΩ dc input an ideal (noiseless) resistor in series with a noise voltage source resistance. In parallel with this, there is a small dynamic load that or in parallel with a noise current source: varies with the clock frequency (see Figure 13). Each time the analog input is sampled, a 10 pF capacitor draws a charge packet V = 4kTRf Volts n of maximum 1 pC (10 pF × 100 mV) from the analog source i = 4kTRf R Amperes n A R1 IN where AD7701 –23 k is Boltzmann’s constant (1.38 × 10 J/K). R2 T is temperature in degrees Kelvin (°C + 273). C EXT C Active signal conditioning circuits such as op amps generally do IN 10pF not suffer from problems of high source impedance. Their open- V 100mV OS loop output resistance is normally only tens of ohms and, in any AGND case, most modern general-purpose op amps have sufficiently fast closed-loop settling time for this not to be a problem. Offset voltage in op amps can be eliminated in a system calibration Figure 13. Equivalent Input Circuit and Input Attenuator routine. With the wide dynamic range and small LSB size of the AD7701, noise can also be a problem, but the digital filter will with a frequency f /256. For a 4.096 MHz CLKIN, this CLKIN reject most broadband noise above its cutoff frequency. How- yields an average current draw of 16 nA. After each sample, the ever, in certain applications there may be a need for analog AD7701 allows 62 clock periods for the input voltage to settle. input filtering. The equation that defines settling time is: Antialias Considerations −tRC VV=− 1 e OIN [] The digital filter of the AD7701 does not provide any rejection at integer multiples of the sampling frequency (nf /256, CLKlN where where n = 1, 2, 3 . . . ). V is the final settled value. O With a 4.096 MHz master clock, there are narrow (±10 Hz) V is the value of the input signal. IN bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise R is the value of the input source resistance. passes unattenuated to the output. C is the 10 pF sample capacitor. t is equal to 62/f . CLKIN However, due to the AD7701’s high oversampling ratio of 800 (16 kHz to 20 Hz), these bands occupy only a small fraction of From this, the following equation can be developed, which the spectrum and most broadband noise is filtered. The reduc- gives the maximum allowable source resistance, R , for S(MAX) tion in broadband noise is given by: an error of V : E 62 e = e 2 f / f = 0.035 e OUT IN C S IN R = S (MAX ) f ×(10 pF)×ln(100mV /V ) CLKIN E where e and e are rms noise terms referred to the input. lN OUT Provided the source resistance is less than this value, the analog f is the filter –3 dB corner frequency (f /409600). C CLKIN input will settle within the desired error band in the requisite 62 f is the sampling frequency (f /256). S CLKIN clock periods. Insufficient settling leads to offset errors. These can be calibrated in system calibration schemes. Since the ratio of f to f is fixed, the digital filter reduces S CLKIN broadband white noise by 96.5% independent of the master If a limit of 10 µV (0.25 LSB at 16 bits) is set for the maximum clock frequency. offset voltage, then the maximum allowable source resistance is 160 kΩ from the above equation, assuming that there is no external stray capacitance. REV. E –11– AD7701 VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING The voltage applied to the V pin defines the analog input AGND is the ground reference voltage for the AD7701 and is REF range. The specified reference voltage is 2.5 V, but the AD7701 completely independent of DGND. Any noise riding on the will operate with reference voltages from 1 V to 3 V with little AGND input with respect to the system analog ground will degradation in performance. cause conversion errors. AGND should, therefore, be used as the system ground and also as the ground for the analog input The reference input presents exactly the same dynamic load as and reference voltage. the analog input, but in the case of the reference input, source resistance and long settling time introduce gain errors rather The analog and digital power supplies to the AD7701 are inde- than offset errors. Fortunately, most precision references have pendent and separately pinned out to minimize coupling between sufficiently low output impedance and wide enough bandwidth analog and digital sections of the device. The digital filter will to settle to 10 µV within 62 clock cycles. provide rejections of broadband noise on the power supplies, except at integer multiples of the sampling frequency. Therefore, the two analog supplies should be decoupled to AGND using +5V AV DD 100 nF ceramic capacitors to provide power supply noise rejec- LT1019 tions at these frequencies. The two digital supplies should similarly AD7701 be decoupled to DGND. V REF ACCURACY AND AUTOCALIBRATION Sigma-delta ADCs, like VFCs and other integrating ADCs, do AGND not contain any source of nonmonotonicity and inherently offer no-missing-codes performance. The AD7701 achieves excellent linearity (±0.0007%) by the use of high quality, on-chip silicon Figure 14. Typical External Reference Connections dioxide capacitors, which have a very low capacitance/voltage The digital filter of the AD7701 removes noise from the refer- coefficient. ence input, just as it does with noise at the analog input, and the The AD7701 offers two self-calibration modes using the on-chip same limitations apply regarding lack of noise rejection at inte- calibration microcontroller and SRAM. Table III is a truth table ger multiples of the sampling frequency. If reference noise is a for the calibration control inputs SC1 and SC2. problem, some voltage references offer noise reduction schemes In the self-calibration mode, zero scale is calibrated against the using an external capacitor. Alternatively, a simple RC filter AGND pin and full scale is calibrated against the V pin, to REF may be used, as shown in Figure 15. remove internal errors. +5V AV Note that in the Bipolar mode the AD7701 calibrates positive DD AD580 full scale and midscale (bipolar zero). AD7701 RF In the system-calibration mode, the AD7701 calibrates its zero 13k� and full scale to voltages present on the analog input pin in two V REF sequential steps. This allows system offsets and/or gain errors to CF be nulled out. 100pF AGND AD7701 SYSTEM SCLK REF HI Figure 15. Filtered Reference Input SDATA ANALOG CAL A MICRO- SIGNAL IN The same considerations apply to this filter as to a filter at the MUX SC1 CONDITIONING COMPUTER analog input. In this case: SYSTEM SC2 A0 A1 REF LO 62 [R (C +10pF)]= F F 100 mV ×C (C +C ) IN IN F f × ln CLKIN   V FSE   Figure 16. Typical Connections for System Calibration where A typical system calibration scheme is shown in Figure 16. In normal operation, the analog signal is fed to the AD7701 via an f is the master clock frequency. CLKIN analog multiplexer. When the system is to be calibrated, A is IN V is the maximum desired error in volts. FSE first switched to the system REF LO via the multiplexer and CAL is strobed high, with SC1 and SC2 both high. A is then IN switched to the system REF HI and CAL is strobed, with SC1 low and SC2 high. In this way, the effect of all error sources –12– REV. E AD7701 Table III. Calibration Truth Table* CAL SC1 SC2 Calibration Type Zero Reference FS Reference Sequence Calibration Time 00 Self-Calibration AGND V One Step 3,145,655 Clock Cycles REF 11 System Offset A First Step 1,052,599 Clock Cycles IN 01 System Gain A Second Step 1,068,813 Clock Cycles IN 10 System Offset A V One Step 2,117,389 Clock Cycles IN REF *DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7701 has settled to the analog input. In all other modes, DRDY falls as the device begins to settle. between the multiplexer and the AD7701 is removed. Op amps The type of calibration cycle initiated by CAL is determined by and other signal conditioning circuits may be used in front of the SC1 and SC2 inputs, in accordance with Table III. the AD7701 without worrying about their absolute gain or The power dissipation and temperature drift of the AD7701 are offset errors. Note that the absolute value of the reference sup- low, and no warm-up time is required before the initial calibra- plied to the AD7701 is no longer important, provided it has tion is performed. However, the system reference must have adequate short-term stability between calibration cycles, as full stabilized before calibration is initiated. scale is calibrated to the system reference. If system offset errors are important but system gain errors are POWER SUPPLY SEQUENCING not, then a one-step system calibration may be performed with The positive digital supply (DV ) must never exceed the posi- DD SC1 high and SC2 low. In this case, offset is calibrated against tive analog supply (AV ) by more than 0.3 V. Power supply DD A , which should be connected to system REF LO during IN sequencing is, therefore, important. If separate analog and digi- calibration, but full scale is calibrated against the AD7701’s tal supplies are used, care must be taken to ensure that the V input. REF analog supply is powered up first. System calibration schemes will yield better accuracy than It is also important that power is applied to the AD7701 before self-calibration, even if there are no system errors. Using self- signals at V , A , or the logic input pins in order to avoid any REF IN calibration, errors arise due to the mismatch in source impedances possibility of latch-up. If separate supplies are used for the between the references during calibration (AGND and V ) REF AD7701 and the system digital circuitry, then the AD7701 should and the analog input during normal operation. In system cali- be powered up first. bration, the source impedances inherently remain identical such A typical scheme for powering the AD7701 from a single set of that the theoretical limit to system accuracy is calibration reso- ±5 V rails is shown in Figure 7. In this circuit, AV and DV DD DD lution. The practical limit is the noise floor of the AD7701. are brought along separate tracks from the same 5 V supply. Note that in system calibration, REF LO does not necessarily Thus, there is no possibility of the digital supply coming up mean the system ground or 0 V. The AD7701 can be calibrated before the analog supply. to measure between any two voltages that lie within its calibra- tion range by deliberately making REF LO nonzero. For example, GROUNDING if REF LO is 0.5 V and REF HI is 2.5 V, the unipolar span will The AD7701 uses the analog ground connection, AGND, as be between these limits. the measurement reference node. It should be used as the refer- ence node for both the analog input signal and the reference CALIBRATION RANGE voltage at the V pin. REF When designing system calibration schemes, care must be taken The analog and digital power supplies to the AD7701 die are to ensure that the worst-case system errors do not cause the pinned out separately to minimize coupling between the analog overrange headroom of the AD7701 to be exceeded. Although and digital sections of the chip. All four supplies should be the measurement error caused by offset and gain errors can be decoupled separately to their respective grounds as shown in nulled out, the actual error voltages will still be present at the ana- Figure 7. The on-chip digital filtering of the AD7701 further log input and can cause overloading of the analog modulator or enhances power supply rejection by attenuating noise injected overflow of the digital filter. With a 2.5 V reference, the maxi- into the conversion process. mum input voltage is (+V + 100 mV), and the minimum REF input voltage is (–V – 100 mV). REF SINGLE-SUPPLY OPERATION Figure 17 shows a circuit to power the AD7701 from a single POWER-UP AND CALIBRATION 10 V supply, using an op amp to provide a half supply refer- A calibration cycle must be carried out after power-up to initial- ence point for AGND and DGND. As the digital I/O pins are ize the device to a consistent starting condition and correct referenced to this point, level shifting is required for external calibration. The CAL pin must be held high for at least four digital communications. If galvanic isolation is required in the clock cycles, after which calibration is initiated on the falling system, level shifting and isolation can both be provided by edge of CAL and takes a maximum of 3,145,655 clock cycles opto-isolators. (approximately 768 ms, with a 4.096 MHz clock). See Table III. REV. E –13– AD7701 Synchronous Self-Clocking Mode (SSC) 0.1µF The SSC mode (MODE pin high) allows easy interfacing to serial-parallel conversion circuits in systems with parallel data 0.1µF AV DV DD DD communication. This mode allows interfacing to 74XX299 10k� V REF REF universal shift registers without any additional decoding. The SSC mode can also be used with microprocessors such as the AD7701 10V 1V DGND AD707 68HC11 and 68HC05, which allow an external device to clock their serial port. AGND Figure 18 shows the timing diagram for SSC mode. Data is AV DV SS SS 10k� clocked out by an internally generated serial clock. The AD7701 0.1µF divides each sampling interval into 16 distinct periods. Eight periods of 64 clock pulses are for analog settling and eight peri- 0.1µF ods of 64 clock pulses are for digital computation. The status of CS is polled at the beginning of each digital computation period. If Figure 17. Single-Supply Operation it is low at any of these times, SCLK will become active and the data-word currently in the output register will be transmitted, SLEEP MODE MSB first. After the LSB has been transmitted, DRDY goes The low power standby mode is initiated by taking the SLEEP high and SDATA goes three-state. If CS, having been brought input low, which shuts down all analog and digital circuits and low, is taken high again at any time during data transmission, reduces power consumption to 10 µW. The calibration coeffi- SDATA and SCLK will go three-state after the current bit cients are still retained in memory, but as the converter has been finishes. If CS is subsequently brought low, transmission will quiescent, it is necessary to wait for the filter settling time (507,904 resume with the next bit during the subsequent digital computa- cycles) before accessing the output data. tion period. If transmission has not been initiated and completed by the time the next data-word is available, DRDY will go high DIGITAL INTERFACE for four clock cycles then low again as the new word is loaded The AD7701’s serial communications port allows easy inter- into the output register. facing to industry-standard microprocessors. Three different A more detailed diagram of the data transmission in the SSC modes of operations are available, optimized for different types mode is shown in Figure 19. Data bits change on the falling of interface. edge of SCLK and are valid on the rising edge of SCLK. 1024 CLKIN CYCLES 64 CLKIN CYCLES 64 CLKIN CYCLES INTERNAL ANALOG SETTLING DIGITAL COMPUTATION DIGITAL COMPUTATION STATUS 72 CLKIN CYCLES DRDY (O) CS POLLED CS (I) HI-Z HI-Z SCLK (O) MSB LSB HI-Z HI-Z SDATA (O) Figure 18. Timing Diagram for SSC Data Transmission Mode –14– REV. E AD7701 Synchronous External Clock Mode (SEC) SDATA goes three-state. If CS is low and the AD7701 is still The SEC mode (MODE pin grounded) is designed for direct transmitting data when a new data-word becomes available, the interface to the synchronous serial ports of industry-standard old data-word continues to be transmitted and the new data is lost. microprocessors such as the COPS series, 68HC11, and 68HC05. If CS is taken high at any time during data transmission, SDATA The SEC mode also allows customized interfaces, using I/O and SCLK will go three-state immediately. If CS returns low, port pins, to microprocessors that do not have a direct fit with the AD7701 will continue transmission with the same data bit. the AD7701’s other modes. If transmission has not been initiated and completed by the time As shown in Figure 20, a falling edge on CS enables the serial the next data-word becomes available, and if CS is high, DRDY data output with the MSB initially valid. Subsequent data bits will return high for four clock cycles, then fall as the new word change on the falling edge of an externally supplied SCLK. is loaded into the output register. After the LSB has been transmitted, DRDY goes high and CLKIN (I) 72 CLKIN CYCLES DRDY (O) CS (I) HI-Z HI-Z SDATA (O) DB15 (MSB) DB14 DB2 DB1 DB0 (LSB) HI-Z HI-Z SCLK (O) Figure 19. SSC Mode Showing Data Timing Relative to SCLK DRDY (O) CS (I) SCLK (I) HI-Z HI-Z DB0 DB15 SDATA (O) DB14 DB13 DB1 (MSB) (LSB) Figure 20. Timing Diagram for the SEC Mode REV. E –15– AD7701 Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING The AC mode (MODE pin tied to –5 V) offers a UART com- As mentioned earlier, the AD7701 divides its internal timing patible interface that allows the AD7701 to transmit data into two distinct phases, analog sampling and settling and digi- asynchronously from remote locations. An external SCLK sets tal computation. In the SSC mode, data is transmitted only the baud rate and data is transmitted in two bytes in UART during the digital computation periods to minimize the effects compatible format. Using the AC mode, the AD7701 can be of digital noise on analog performance. In the SEC and AC interfaced directly to microprocessors with UART interfaces, modes, data transmission is externally controlled, so this auto- such as the 8051 and TMS70X2. matic safeguard does not exist. Data transmission is initiated by CS going low. If CS is low on a Whatever mode of operation is used, resistive and capacitive falling edge of SCLK, the AD7701 begins transmitting an 8-bit loads on digital outputs should be minimized in order to reduce data byte (DB8 to DB15) with one start bit and two stop bits, crosstalk between analog and digital portions of the circuit. For as in Figure 21. The SDATA output will then go three-state. this reason, connection to low power CMOS logic such as one The second byte is transmitted by bringing CS low again and of the 4000 series or 74C families is recommended. DB0 to DB7 are transmitted in the same format as the first byte. It is especially important to minimize the load on SDATA in the UART baud rates are typically low compared to the AD7701’s AC mode, as transmission in this mode is inherently asynchro- 4 kHz output update rate. If CS is low and data is still being nous. In the SEC mode, the AD7701 should be synchronized to transmitted when a new data-word becomes available, the new the digital system clock via CLKIN. data will be ignored. However, if CS has been taken high between bytes, when a new data-word becomes available, the AD7701 could update the output register before the second byte is trans- mitted. In this case, the UART would receive the first byte of the new word instead of the second byte of the old word. When using the AC mode, care must obviously be taken to ensure that this does not occur. SCLK (I) DRDY (O) CS (I) HI-Z START STOP STOP START STOP STOP DB14 DB15 DB6 SDATA (O) DB8 DB9 DB0 DB1 DB7 BIT BIT BIT BIT BIT BIT Figure 21. Timing Diagram for Asynchronous Communications Mode –16– REV. E AD7701 OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Shrink Small Outline Package [SSOP] (N-20) (RS-28) Dimensions shown in inches and (millimeters) Dimensions shown in millimeters 0.985 (25.02) 10.50 0.965 (24.51) 10.20 0.295 (7.49) 0.945 (24.00) 9.90 0.285 (7.24) 0.275 (6.99) 20 11 28 15 1 10 0.325 (8.26) 5.60 8.20 0.310 (7.87) 0.150 (3.81) 5.30 7.80 0.300 (7.62) 0.180 (4.57) 0.015 (0.38) MIN 0.135 (3.43) 5.00 7.40 MAX 0.120 (3.05) 1 14 0.150 (3.81) 0.130 (3.30) 0.015 (0.38) 0.100 SEATING 0.060 (1.52) 0.110 (2.79) 0.022 (0.56) 0.010 (0.25) (2.54) PLANE 1.85 0.050 (1.27) 0.018 (0.46) BSC 0.008 (0.20) 1.75 0.10 0.045 (1.14) 0.014 (0.36) 1.65 COPLANARITY 2.00 MAX COMPLIANT TO JEDEC STANDARDS MO-095-AE 0.25 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS 0.09 (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8� 0.95 0.65 0.38 0.05 BSC 4� 0.75 0.22 MIN SEATING 0� PLANE 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH 20-Lead Standard Small Outline Package [SOIC] 20-Lead Ceramic Dual In-Line Pacakage [CERDIP] Wide Body (Q-20) Dimensions shown in inches and (millimeters) (R-20) Dimensions shown in millimeters and (inches) 0.005 0.098 (2.49) (0.13) MAX 0.310 (7.87) 13.00 (0.5118) MIN 0.220 (5.59) 20 11 12.60 (0.4961) PIN 1 110 20 11 0.060 (1.52) 7.60 (0.2992) 0.320 (8.13) 0.200 (5.08) 0.015 (0.38) 1.060 (26.92) MAX 7.40 (0.2913) MAX 0.290 (7.37) 0.150 (3.81) 10.65 (0.4193) MIN 1 10 10.00 (0.3937) 0.015 (0.38) 0.200 (5.08) 0.008 (0.20) 15 0.125 (3.18) 0 0.100 0.070 (1.78) SEATING PLANE 2.65 (0.1043) (2.54) 0.023 (0.58) 0.75 (0.0295) 0.030 (0.76) � 45� BSC 2.35 (0.0925) 0.014 (0.36) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR 8� REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 1.27 0.51 (0.0201) SEATING 0� 1.27 (0.0500) COPLANARITY 0.32 (0.0126) (0.0500) PLANE 0.33 (0.0130) 0.10 0.40 (0.0157) 0.23 (0.0091) BSC COMPLIANT TO JEDEC STANDARDS MS-013AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. E –17– AD7701 Revision History Location Page 3/03—Data Sheet changed from REV. D to REV. E. Updated Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 –18– REV. E –19– –20– PRINTED IN U.S.A. C01162–0–3/03(E)