ANALOG DEVICES AD7699

16-Bit, 8-Channel, 500 kSPS PulSAR ADC Data Sheet AD7699 FEATURES FUNCTIONAL BLOCK DIAGRAM 5V 0.5V TO 4.096V 0.5V TO VDD 16-bit resolution with no missing codes 0.1µF 10µF 8-channel multiplexer with choice of inputs REFIN REF VDD Unipolar single-ended Differential (GND sense) 1.8V BAND GAP VIO TO Pseudobipolar REF AD7699 VDD Throughput: 500 kSPS TEMP SENSOR INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) IN0 CNV Dynamic range: 93.3 dB IN1 SCK IN2 16-BIT SAR SPI SERIAL SINAD: 91.5 dB @ 20 kHz MUX IN3 INTERFACE ADC SDO THD: −97 dB @ 20 kHz IN4 ONE-POLE DIN IN5 Analog input range: 0 V to V with V up to VDD REF REF LPF IN6 SEQUENCER IN7 Multiple reference types COM Internal 4.096 V GND External buffered (up to 4.096 V) External (up to VDD) Figure 1. Internal temperature sensor Table 1. Multichannel 14-/16-Bit PulSAR® ADC Channel sequencer, selectable 1-pole filter, busy indicator Type Channels 250 kSPS 500 kSPS ADC Driver No pipeline delay, SAR architecture Single-supply 5 V operation with 14-Bit 8 AD7949 ADA4841-x 1.8 V to 5 V logic interface 16-Bit 4 AD7682 ADA4841-x Serial interface compatible with SPI, MICROWIRE, 16-Bit 8 AD7689 AD7699 ADA4841-x QSPI, and DSP Power dissipation GENERAL DESCRIPTION 26 mW @ 500 kSPS The AD7699 is an 8-channel, 16-bit, charge redistribution 5.2 μW @ 100 SPS successive approximation register (SAR) analog-to-digital Standby current: 50 nA converter (ADC) that operates from a single power supply, VDD. 20-lead 4 mm × 4 mm LFCSP package The AD7699 contains all components for use in a multichannel, APPLICATIONS low power data acquisition system, including a true 16-bit SAR Battery-powered equipment ADC with no missing codes; an 8-channel low crosstalk multip- Medical instruments: ECG/EKG lexer useful for configuring the inputs as single-ended (with or Mobile communications: GPS without ground sense), differential, or bipolar; an internal 4.096 V Personal digital assistants low drift reference and buffer; a temperature sensor; a selectable Power line monitoring one-pole filter; and a sequencer that is useful when channels are Data acquisition continuously scanned in order. Seismic data acquisition systems The AD7699 uses a simple serial port interface (SPI) for writing Instrumentation to the configuration register and receiving conversion results. Process control The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7699 is housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07354-001 AD7699 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference Output/Input .............................................. 18  Applications ....................................................................................... 1  Power Supply ............................................................................... 19  Functional Block Diagram .............................................................. 1  Supplying the ADC from the Reference .................................. 19  General Description ......................................................................... 1  Digital Interface .............................................................................. 20  Revision History ............................................................................... 2  Reading/Writing During Conversion, Fast Hosts .................. 20  Specif ica t ions ..................................................................................... 3  Reading/Writing During Acquisition, Any Speed Hosts ...... 20  Timing Specifications ....................................................................... 5  Reading/Writing Spanning Conversion, Any Speed Host .... 20  Absolute Maximum Ratings ............................................................ 6  Configuration Register, CFG .................................................... 20  ESD Caution .................................................................................. 6  General Timing Without a Busy Indicator ............................. 22  Pin Configuration and Function Descriptions ............................. 7  Read/Write Spanning Conversion Without a Busy Indicator ...................................................................................... 23  Typical Performance Characteristics ............................................. 8  General Timing With a Busy Indicator ................................... 24  Terminology .................................................................................... 12  Read/Write Spanning Conversion with a Busy Indicator ..... 25  Theory of Operation ...................................................................... 13  Application Hints ........................................................................... 26  Overview ...................................................................................... 13  Layout .......................................................................................... 26  Converter Operation .................................................................. 13  Evaluating AD7699 Performance ............................................. 26  Transfer Functions...................................................................... 14  Outline Dimensions ....................................................................... 27  Typical Connection Diagrams .................................................. 15  Ordering Guide .......................................................................... 27  Analog Inputs .............................................................................. 16  Driver Amplifier Choice ............................................................ 18  REVISION HISTORY 3/12—Rev. A to Rev. B Changes to Figure 28 ...................................................................... 15 Changes to Internal Reference/Temperature Sensor and External Reference and Internal Buffer Sections ....................................... 18 Changes to Bits[5:3] Function, Table 8 ........................................ 21 Updated Outline Dimensions ....................................................... 27 9/11—Rev. 0 to Rev. A Changed Internal Reference/Temperature Sensor Section to Internal Reference Section ............................................................ 18 Changes to Internal Reference Section, External Reference Section and Internal Buffer Section, and External Reference Section .. 18 Changes to Table 8 .......................................................................... 21 10/08—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7699 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range Unipolar mode 0 +V V REF Bipolar mode −V/2 +V/2 V REF REF Absolute Input Voltage Positive input, unipolar and bipolar modes −0.1 V + 0.1 V REF Negative or COM input, unipolar mode −0.1 +0.1 V Negative or COM input, bipolar mode VREF/2 − 0.1 VREF/2 VREF/2 + 0.1 V Analog Input CMRR fIN = 250 kHz 68 dB Leakage Current at 25°C Input Acquisition phase 1 nA 1 Impedance THROUGHPUT Conversion Rate 2 Full Bandwidth 0 500 kSPS 2 ¼ Bandwidth 0 125 kSPS Transient Response Full-scale step, full bandwidth 400 ns Full-scale step, ¼ bandwidth 1600 ns ACCURACY No Missing Codes 16 Bits 3 Integral Linearity Error −1.5 ±0.5 +1.5 LSB Differential Linearity Error −1 ±0.25 +1.5 LSB Transition Noise REF = VDD = 5 V 0.5 LSB 4 Gain Error All modes −10 ±1 +10 LSB Gain Error Match −3 ±1 +3 LSB Gain Error Temperature Drift ±0.3 ppm/°C 4 Offset Error All modes −10 ±1 +10 LSB Offset Error Match −3 ±1 +3 LSB Offset Error Temperature Drift ±0.3 ppm/°C Power Supply Sensitivity ±1.5 LSB VDD = 5 V ± 5% AC Accuracy 5 Dynamic Range 93.3 dB Signal-to-Noise fIN = 20 kHz, VREF = 5 V 92 92.5 dB fIN = 20 kHz, VREF = 4.096 V internal REF 89.5 91.5 dB SINAD f = 20 kHz, VREF = 5 V 90 91.5 dB IN f = 20 kHz, VREF = 5 V, −60 dB input 33.5 dB IN f = 20 kHz, VREF = 4.096 V internal REF 89 90.5 dB IN Total Harmonic Distortion fIN = 20 kHz −97 dB Spurious-Free Dynamic Range fIN = 20 kHz 112 dB Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s) −125 dB SAMPLING DYNAMICS −3 dB Input Bandwidth Full bandwidth 14 MHz ¼ bandwidth 3.6 MHz Aperture Delay VDD = 5 V 2.5 ns Rev. B | Page 3 of 28 AD7699 Data Sheet Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE REF Output Voltage @ 25°C 4.086 4.096 4.106 V 6 REFIN Output Voltage @ 25°C 2.3 V REF Output Current ±300 μA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 10 μF 5 ms EXTERNAL REFERENCE Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.2 V Current Drain 500 kSPS, REF = 5 V 100 μA TEMPERATURE SENSOR 7 Output Voltage @ 25°C 283 mV Temperature Sensitivity 1 mV/°C DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS 8 Data Format 9 Pipeline Delay VOL ISINK = +500 μA 0.4 V V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 4.5 5.5 V VIO Specified performance 1.8 VDD + 0.3 V 10, 11 Standby Current VDD and VIO = 5 V, @ 25°C 50 nA Power Dissipation VDD = 5 V, 100 kSPS throughput 5.2 μW VDD = 5 V, 500 kSPS throughput 26 29 mW VDD = 5 V, 500 kSPS throughput with internal reference 28 32 mW Energy per Conversion 52 nJ 12 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 See the Analog Inputs section. 2 The bandwidth is set with the configuration register. 3 LSB means least significant bit. With the 5 V input range, one LSB = 76.3 μV. 4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the reference. 5 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 6 This is the output from the internal band gap. 7 The output voltage is internal and present on a dedicated multiplexer input. 8 Unipolar mode: serial 16-bit straight binary. Bipolar mode: serial 16-bit twos complement. 9 Conversion results available immediately after completed conversion. 10 With all digital inputs forced to VIO or GND as required. 11 During acquisition phase. 12 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. B | Page 4 of 28 Data Sheet AD7699 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 1.6 μs CONV Acquisition Time t 400 ns ACQ Time Between Conversions tCYC 2 μs CNV Pulse Width tCNVH 10 ns Data Write/Read During Conversion tDATA 1.2 μs SCK Period t t + 2 ns SCK DSDO SCK Low Time t 11 ns SCKL SCK High Time t 11 ns SCKH SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 16 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 21 ns VIO Above 1.8 V 28 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 4.5 V 15 ns VIO Above 3 V 17 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns CNV High or Last SCK Falling Edge to SDO High Impedance tDIS 32 ns CNV Low to SCK Rising Edge t 10 ns CLSCK DIN Valid Setup Time from SCK Falling Edge t 5 ns SDIN DIN Valid Hold Time from SCK Falling Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. 500µA I OL 1.4V TOSDO C L 50pF 500µA I OH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V 2 2 0.8V OR 0.5V 0.8V OR 0.5V 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 28 07354-002 07354-003 AD7699 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational INx, COM GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA section of this specification is not implied. Exposure to absolute REF, REFIN GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V ESD CAUTION VDD to VIO ±7 V DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance (LFCSP) 47.6°C/W JA θ Thermal Impedance (LFCSP) 4.4°C/W JC 1 See the Analog Inputs section. Rev. B | Page 6 of 28 Data Sheet AD7699 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR VDD 1 15 VIO REF 2 14 SDO AD7699 REFIN 3 13 SCK GND 4 12 DIN TOP VIEW GND 5 11 CNV (Not to Scale) NOTES 1. THE EXPOSED PADDLE IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GND PLANE. Figure 4. Pin Configuration Table 5. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 20 VDD P Power Supply. Nominally 4.5 to 5.5 V and should be decoupled with 10 μF and 100 nF capacitors. 2 REF AI/O Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD – 0.5 V maximum) useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. 3 REFIN AI/O Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as previously described. 4, 5 GND P Power Supply Ground. 6 to 9 IN4 to IN7 AI Analog Input Channel 4, Analog Input Channel 5, Analog Input Channel 6, and Analog Input Channel 7. 10 COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V. 11 CNV DI Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. 12 DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. 14 SDO DO Serial Data Output. The conversion result is output on this pin and synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 16 to 19 IN0 to IN3 AI Analog Input Channel 0, Analog Input Channel 1, Analog Input Channel 2, and Analog Input Channel 3. 21 (EPAD) Exposed The exposed paddle is not connected internally. For increased reliability of the solder joints, it is Paddle recommended that the pad be soldered to the GND plane. (EPAD) 1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. B | Page 7 of 28 07354-004 IN4 6 20 VDD N5 19 IN3 I 7 IN6 8 18 IN2 IN7 9 17 IN1 COM 10 16 IN0 AD7699 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 5V, VREF = 5V, VIO = VDD, unless otherwise noted 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.5 –1.0 0 16,384 32,768 49,152 65,536 0 16,384 32,768 49,152 65,536 CODES CODES Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 250,000 250,000 σ = 0.51 LSB σ = 0.78 LSB 220,840 V = 5V V = 4.096V REF REF 200,000 200,000 191,013 150,000 150,000 100,000 100,000 50,000 50,000 38,420 31,411 26,926 13,341 00 3 10 0 0 0 0119 157 0 0 0 0 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX CODE IN HEX Figure 6. Histogram of a DC Input at Code Center Figure 9. Histogram of a DC Input at Code Center 0 0 V = 5V V = 4.096V REF REF f = 500kSPS f = 500kSPS S S –20 –20 f = 19.94kHz f = 19.94kHz IN IN SNR = 92.3dB SNR = 91.1dB –40 –40 SINAD = 91.5dB SINAD = 90.4dB THD = –98dB THD = –98dB SFDR = 100dB –60 –60 SFDR = 100dB SECOND HARMONIC = –111dB SECOND HARMONIC = –104dB THIRD HARMONIC = –101dB THIRD HARMONIC = –101dB –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 7. 20 kHz FFT, VREF = 5 V Figure 10. 20 kHz FFT, VREF = 4.096 V Rev. B | Page 8 of 28 AMPLITUDE (dB OF FULL SCALE) COUNTS (LSBS) 07354-006 07354-007 07354-005 AMPLITUDE (dB OF FULL SCALE) COUNTS (LSBS) 07354-009 07354-010 07354-008 Data Sheet AD7699 100 100 V = 5V V = 5V REF REF 95 95 –10dB –10dB 90 90 85 85 –0.5dB 80 80 –0.5dB 75 75 70 70 65 65 60 60 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. SNR vs. Frequency Figure 14. SINAD vs. Frequency 16 –60 V = 5V V = 5V REF REF –65 –10dB –70 15 –75 –0.5dB 14 –80 –10dB –85 –90 13 –0.5dB –95 12 –100 –105 11 –110 –115 10 –120 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. ENOB vs. Frequency Figure 12. THD vs. Frequency –80 115 96 f = 20kHz SFDR, V = 5V f = 20kHz IN REF IN SNR, V = 5V REF SINAD, V = 5V 94 REF SFDR, –85 110 V = 4.096V REF 92 –90 105 90 SNR, V = 4.096V REF THD, V = 5V THD, V = 4.096V SINAD, V = 4.096V REF REF REF –95 100 88 –100 95 86 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. SNR, SINAD vs.Temperature Figure 16. THD, SFDR vs. Temperature Rev. B | Page 9 of 28 SNR (dB) THD (dB) SNR, SINAD (dB) 07354-013 07354-012 07354-011 THD (dB) SINAD (dB) ENOB (Bits) 07354-015 07354-014 SFDR (dB) 07354-017 AD7699 Data Sheet 94 17 –80 110 f = 20kHz IN –85 105 SNR 92 16 SFDR 100 –90 SINAD 90 15 95 –95 THD ENOB 90 –100 88 14 –105 85 86 13 80 –110 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 17. SNR, SINAD, ENOB vs. Reference Voltage Figure 20. THD, SFDR vs. Reference Voltage 95 15.6 5500 180 f = 20kHz f = 500kSPS IN s V = 5V V , INT REF 94 15.5 DD REF 160 SNR 93 15.4 5250 140 92 15.3 SINAD 120 91 15.2 90 15.1 5000 100 ENOB 89 15.0 80 V , EXT REF DD 88 14.9 4750 60 87 14.8 VIO 40 86 14.7 4500 20 85 14.6 –10 –8–6 –4–2 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) INPUT LEVEL (dB) Figure 18. SNR, SINAD, and ENOB vs. Input Level Figure 21. Operating Currents vs. Temperature 3 5750 100 f = 500kSPS S 4.096V INTERNAL REF 5500 90 2 UNIPOLAR GAIN INTERNAL BUFFER, TEMP ON 5250 80 INTERNAL BUFFER, TEMP OFF 1 BIPOLAR GAIN 5000 70 0 4750 60 UNIPOLAR OFFSET 4500 50 –1 BIPOLAR OFFSET EXTERNAL REF, TEMP ON 4250 40 EXTERNAL REF, TEMP OFF –2 4000 30 VIO –3 3750 20 –55 –35 –15 5 25 45 65 85 105 125 4.5 5.0 5.5 TEMPERATURE (°C) VDD SUPPLY (V) Figure 19. Offset and Gain Errors vs. Temperature, Not Normalized Figure 22. Operating Currents vs. Supply Rev. B | Page 10 of 28 SNR (dB) SNR, SINAD (dB) ZERO ERROR, GAIN ERROR (LSB) 07354-020 ENOB (Bits) ENOB (Bits) 07354-016 07354-018 THD (dB) VDD CURRENT (µA) V CURRENT (µA) DD SFDR (dB) VIO CURRENT (µA) 07354-040 VIO CURRENT (µA) 07354-022 07354-019 Data Sheet AD7699 25 4.099 4.098 20 4.097 15 4.096 VDD = 5V, 85°C 4.095 10 4.094 VDD = 5V, 25°C 5 4.093 0 4.092 0 20 40 60 80 100 120 –55 –35 –15 5 25 45 65 85 105 125 SDO CAPACITIVE LOAD (pF) TEMPERATURE (°C) Figure 23. Internal Reference Output Voltage vs. Temperature, Three devices Figure 24. t Delay vs. SDO Capacitance Load and Supply DSDO Rev. B | Page 11 of 28 V (V) REF 07354-041 t DELAY (ns) DSDO 07354-021 AD7699 Data Sheet TERMINOLOGY Least Significant Bit (LSB) Signal-to-Noise Ratio (SNR) The LSB is the smallest increment that can be represented by a SNR is the ratio of the rms value of the actual input signal to the converter. For an analog-to-digital converter with N bits of rms sum of all other spectral components below the Nyquist resolution, the LSB expressed in volts is frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. V REF LSB (V)= N 2 Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to Integral Nonlinearity Error (INL) the rms sum of all other spectral components below the Nyquist INL refers to the deviation of each individual code from a line frequency, including harmonics but excluding dc. The value for drawn from negative full scale through positive full scale. The SINAD is expressed in decibels. point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB Total Harmonic Distortion (THD) beyond the last code transition. The deviation is measured from THD is the ratio of the rms sum of the first five harmonic the middle of each code to the true straight line (see Figure 26). components to the rms value of a full-scale input signal and is expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the Spurious-Free Dynamic Range (SFDR) maximum deviation from this ideal value. It is often specified in SFDR is the difference, in decibels, between the rms amplitude terms of resolution for which no missing codes are guaranteed. of the input signal and the peak spurious signal. Offset Error Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave For unipolar mode, the first transition should occur at a level input. It is related to SINAD by the formula ½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point. For bipolar ENOB = (SINAD − 1.76)/6.02 dB mode, the first transition should occur at a level ½ LSB above and is expressed in bits. V /2. The bipolar offset error is the deviation of the actual REF Channel-to-Channel Crosstalk transition from that point. Channel-to-channel crosstalk is a measure of the level of crosstalk Gain Error between any two adjacent channels. It is measured by applying a The last transition (from 111 … 10 to 111 … 11) should occur dc to the channel under test and applying a full-scale, 100 kHz for an analog voltage 1½ LSB below the nominal full scale. The sine wave signal to the adjacent channel(s). The crosstalk is the gain error is the deviation in LSB (or percentage of full-scale amount of signal that leaks into the test channel and is expressed range) of the actual level of the last transition from the ideal in decibels. level after the offset error is adjusted out. Closely related is the Reference Voltage Temperature Coefficient full-scale error (also in LSB or percentage of full-scale range), Reference voltage temperature coefficient is derived from the which includes the effects of the offset error. typical shift of output voltage at 25°C on a sample of parts at the Aperture Delay maximum and minimum reference output voltage (VREF) meas- Aperture delay is the measure of the acquisition performance. It ured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as is the time between the rising edge of the CNV input and the V (Max) –V (Min) REF REF 6 TCV (ppm/°C)= ×10 point at which the input signal is held for a conversion. REF V (25°C)× (T –T ) REF MAX MIN Transient Response where: Transient response is the time required for the ADC to accurately V (Max) = maximum V at T , T (25°C), or T . REF REF MIN MAX acquire its input after a full-scale step function is applied. V (Min) = minimum V at T , T (25°C), or T . REF REF MIN MAX Dynamic Range VREF (25°C) = VREF at 25°C. Dynamic range is the ratio of the rms value of the full scale to TMAX = +85°C. the total rms noise measured with the inputs shorted together. TMIN = –40°C. The value for dynamic range is expressed in decibels. Rev. B | Page 12 of 28 Data Sheet AD7699 THEORY OF OPERATION INx+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV INx– OR COM Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7699 is an 8-channel, 16-bit, charge redistribution The AD7699 is a successive approximation ADC based on a successive approximation register (SAR) analog-to-digital charge redistribution DAC. Figure 25 shows the simplified converter (ADC). It is capable of converting 500,000 samples schematic of the ADC. The capacitive DAC consists of two per second (500 kSPS) and power down between conversions. identical arrays of 16 binary-weighted capacitors, which are For example, when operating with an external reference at connected to the two comparator inputs. 1 kSPS, it consumes 52 μW typically, ideal for battery-powered During the acquisition phase, terminals of the array tied to the applications. comparator input are connected to GND via SW+ and SW−. All The AD7699 contains all of the components for use in a independent switches are connected to the analog inputs. multichannel, low power data acquisition system, including Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) • 16-bit SAR ADC with no missing codes inputs. When the acquisition phase is complete and the CNV • 8-channel, low crosstalk multiplexer input goes high, a conversion phase is initiated. When the • Internal low drift reference and buffer conversion phase begins, SW+ and SW− are opened first. The • Temperature sensor two capacitor arrays are then disconnected from the inputs and • Selectable one-pole filter connected to the GND input. Therefore, the differential voltage • Channel sequencer between the INx+ and INx− (or COM) inputs captured at the These components are configured through an SPI-compatible, end of the acquisition phase is applied to the comparator inputs, 14-bit register. Conversion results, also SPI compatible, can be causing the comparator to become unbalanced. By switching read after or during conversions with the option for reading each element of the capacitor array between GND and REF, the back the configuration. comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these The AD7699 provides the user with an on-chip track-and-hold switches, starting with the MSB, to bring the comparator back and does not exhibit pipeline delay or latency. into a balanced condition. After the completion of this process, The AD7699 is specified from 4.5 V to 5.5 V and can be interfaced the part returns to the acquisition phase, and the control logic to any 1.8 V to 5 V digital logic family. It is housed in a 20-lead, generates the ADC output code and a busy signal indicator. 4 mm × 4 mm LFCSP that combines space savings and allows Because the AD7699 has an on-board conversion clock, the flexible configurations and is also pin-for-pin compatible with serial clock, SCK, is not required for the conversion process. the 16-bit AD7682 and AD7689, and the 14-bit AD7949. Rev. B | Page 13 of 28 07354-023 AD7699 Data Sheet TRANSFER FUNCTIONS TWOS STRAIGHT COMPLEMENT BINARY With the inputs configured for unipolar range (single ended, 011...111 111...111 COM with ground sense, or paired differentially with INx− as 011...110 111...110 ground sense), the data output is straight binary. 011...101 111...101 With the inputs configured for bipolar range (COM = V /2 or REF paired differentially with INx− = V /2), the data outputs are REF twos complement. The ideal transfer characteristic for the AD7699 is shown in Figure 26 and for both unipolar and bipolar ranges with the 100...010 000...010 internal 4.096 V reference. 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function Table 6. Output Codes and Ideal Input Voltages 1 2 Unipolar Analog Input Digital Output Code Bipolar Analog Input Digital Output Code Description VREF = 4.096 V (Straight Binary Hex) VREF = 4.096 V (Twos Complement Hex) 3 3 FSR − 1 LSB 4.095938 V 0xFFFF 2.047938 V 0x7FFF Midscale + 1 LSB 2.048063 V 0x8001 62.5 μV 0x0001 Midscale 2.048 V 0x8000 0 V 0x0000 4 Midscale − 1 LSB 2.047938 V 0x7FFF −62.5 μV 0xFFFF −FSR + 1 LSB 62.5 μV 0x0001 −2.047938 V 0x8001 3 −FSR 0 V 0x0000 −2.048 V 0x8000 1 With COM or INx− = 0 V or all INx referenced to GND. 2 With COM or INx− = V /2. REF 3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − VGND). 4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below V ). GND Rev. B | Page 14 of 28 ADC CODE 07354-024 Data Sheet AD7699 TYPICAL CONNECTION DIAGRAMS 5V 1.8V TO VDD 100nF 2 100nF 100nF 10µF V+ REF REFIN VDD VIO 0V TO V REF 3 ADA4841-x IN0 V– V+ DIN MOSI IN[7:1] SCK AD7699 SCK SDO MISO 0V TO V REF CNV SS 3 ADA4841-x V– 0V OR COM V /2 REF GND NOTES 1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 27. Typical Application Diagram with Multiple Supplies 5V 1.8V TO VDD 100nF 100nF 100nF 2 10µF V+ REFIN VDD REF VIO 3 ADA4841-x IN0 V+ DIN MOSI IN[7:1] AD7699 SCK SCK SDO MISO 3 ADA4841-x CNV SS V p-p REF COM GND V /2 REF NOTES 1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 28. Typical Application Diagram Using Bipolar Input Rev. B | Page 15 of 28 07354-025 07354-026 AD7699 Data Sheet 70 Unipolar or Bipolar 65 Figure 27 shows an example of the recommended connection diagram for the AD7699 when multiple supplies are available. 60 Bipolar Single Supply 55 Figure 28 shows an example of a system with a bipolar input 50 using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the 45 amplifier/signal conditioning circuit is remotely located with 40 some common mode present. Note that for any input config- uration, the inputs, INx, are unipolar and always referenced to 35 GND (no negative voltages even in bipolar range). 30 1 10 100 1k 10k For this circuit, a rail-to-rail input/output amplifier can be used; FREQUENCY (kHz) however, the offset voltage vs. input common-mode range should Figure 30. Analog Input CMRR vs. Frequency be noted and taken into consideration (1 LSB = 62.5 μV with During the acquisition phase, the impedance of the analog inputs V = 4.096 V). Note that the conversion results are in twos REF can be modeled as a parallel combination of the capacitor, C , PIN complement format when using the bipolar input configuration. and the network formed by the series connection of R and C . IN IN Refer to the AN-581 Application Note, Biasing and Decoupling CPIN is primarily the pin capacitance. RIN is typically 400 Ω (8.8 kΩ Op Amps in Single Supply Applications, at www.analog.com for when the one-pole filter is active) and is a lumped component additional details about using single-supply amplifiers. made up of serial resistors and the on resistance of the switches. ANALOG INPUTS CIN is typically 27 pF and is mainly the ADC sampling capacitor. Input Structure Selectable Low-Pass Filter Figure 29 shows an equivalent circuit of the input structure of During the conversion phase, where the switches are opened, the AD7699. The two diodes, D1 and D2, provide ESD the input impedance is limited to CPIN. While the AD7699 is protection for the analog inputs, IN[7:0] and COM. Care must acquiring, RIN and CIN make a one-pole, low-pass filter that be taken to ensure that the analog input signal does not exceed reduces undesirable aliasing effects and limits the noise from the supply rails by more than 0.3 V because this causes the the driving circuitry. The low-pass filter can be programmed diodes to become forward-biased and to start conducting for the full bandwidth or ¼ of the bandwidth with CFG[6], as current. shown in Table 8. Note that the converter throughput must also be These diodes can handle a forward-biased current of 130 mA reduced by ¼ when using the filter. If the maximum throughput maximum. For instance, these conditions may eventually occur is used with the BW set to ¼, the acquisition time of the when the input buffer supplies are different from VDD. In such converter, tACQ, is violated, resulting in poor THD. a case, for example, an input buffer with a short circuit, the Input Configurations current limitation can be used to protect the part. Figure 31 shows the different methods for configuring the analog VDD inputs with the configuration register (CFG[12:10]). Refer to D1 INx+ C IN the Configuration Register, CFG section for more details. R IN OR INx– OR COM C PIN D2 GND Figure 29. Equivalent Analog Input Circuit This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or VREF ± 0.1 V). By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 30. Rev. B | Page 16 of 28 07354-027 CMRR (dB) 07354-028 Data Sheet AD7699 Sequencer CH0+ IN0 CH0+ IN0 CH1+ CH1+ The AD7699 includes a channel sequencer useful for scanning IN1 IN1 CH2+ channels in a IN0 to IN[7:0] fashion. Channels are scanned as IN2 CH2+ IN2 singles or pairs, with or without the temperature sensor, after CH3+ IN3 CH3+ IN3 CH4+ the last channel is sequenced. IN4 CH4+ IN4 CH5+ CH5+ IN5 IN5 The sequencer starts with IN0 and finishes with IN[7:0] set in CH6+ CH6+ IN6 IN6 CFG[9:7]. For paired channels, the channels are paired CH7+ CH7+ IN7 IN7 depending on the last channel set in CFG[9:7]. Note that the COM COM– COM channel pairs are always paired as IN (even) = INx+ and IN GND GND (odd) = INx− regardless of CFG[7]. A—8 CHANNELS, B—8 CHANNELS, To enable the sequencer, CFG[2:1] are written to for initializing SINGLE ENDED COMMON REFERENCE the sequencer. After CFG[13:0] are updated, DIN must be held low while reading data out (at least for Bit 13), or the CFG register CH0+ (–) IN0 CH0+ (–) IN0 begins updating again. CH0– (+) IN1 CH0– (+) IN1 While operating in a sequence, the CFG register can be changed CH1+ (–) IN2 CH1+ (–) IN2 by writing 01 to CFG[2:1]. However, if changing CFG11 (paired 2 CH1– (+) CH1– (+) IN3 IN3 or single channel) or CFG[9:7] (last channel in sequence), the CH2+ (–) CH2+ IN4 IN4 sequence reinitializes and converts IN0 (or IN1) after CFG is CH2– (+) IN5 CH3+ IN5 updated. CH3+ (–) IN6 CH4+ IN6 CH3– (+) IN7 CH5+ IN7 Examples COM COM– COM Bit[13], Bits[6:3], and Bit 0 are configured for the input and GND GND sequencer. C—4 CHANNELS, D—COMBINATION As a first example, scan all IN[7:0] referenced to COM = GND DIFFERENTIAL with the temperature sensor. Figure 31. Multiplexed Analog Input Configurations 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The analog inputs can be configured as CFG INCC INx BW REF SEQ RB • Figure 31A, single-ended referenced to system ground; 1 1 0 1 1 1 1 0 CFG[12:10] = 111 . 2 As a second example, scan three paired channels without the • Figure 31B, bipolar differential with a common reference temperature sensor and referenced to V /2. REF point; COM = VREF/2; CFG[12:10] = 0102. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unipolar differential with COM connected to a ground CFG INCC INx BW REF SEQ RB sense; CFG[12:10] = 1102. 1 1 0 0 X 1 0 X 1 1 • Figure 31C, bipolar differential pairs with INx− referenced 1 to VREF/2; CFG[12:10] = 00X2. X = don’t care. Unipolar differential pairs with INx− referenced to a Source Resistance ground sense; CFG[12:10] = 10X . 2 When the source impedance of the driving circuit is low, the In this configuration, the INx+ is identified by the channel AD7699 can be driven directly. Large source impedances signifi- in CFG[9:7]. For example, for IN0 = IN1+ and IN1 = cantly affect the ac performance, especially total harmonic IN1−, CFG[9:7] = 0002; for IN1 = IN1+ and IN0 = IN1−, distortion (THD). The dc performances are less sensitive to the CFG[9:7] = 0012. input impedance. The maximum source impedance depends on • Figure 31D, inputs configured in any of the above the amount of THD that can be tolerated. The THD degrades as a combinations (showing that the AD7699 can be configured function of the source impedance and the maximum input dynamically). frequency. Rev. B | Page 17 of 28 07354-029 AD7699 Data Sheet DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE OUTPUT/INPUT Although the AD7699 is easy to drive, the driver amplifier must The AD7699 allows the choice of a very low temperature drift meet the following requirements: internal voltage reference, an external reference, or an external buffered reference.  The noise generated by the driver amplifier must be kept The internal reference of the AD7699 provides excellent as low as possible to preserve the SNR and transition noise performance and can be used in almost all applications. There performance of the AD7699. Note that the AD7699 has a are five possible choices of voltage reference schemes briefly noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given described in Table 8 with more details in each of the following sections. system noise specification. The noise from the amplifier is filtered by the AD7699 analog input circuit low-pass filter Internal Reference/Temperature Sensor made by RIN and CIN or by an external filter, if one is used. The internal reference can be set for a 4.096 V output as Because the typical noise of the AD7699 is 35 μV rms (with detailed in Table 8. With the internal reference enabled, the VREF = 5 V), the SNR degradation due to the amplifier is band gap voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current     output of REFIN is limited, it can be used as a source if followed 35   SNR  20log LOSS by a suitable buffer, such as the AD8605.   π 2 2 35  f (Ne )   N 3dB Enabling the reference also enables the internal temperature 2   sensor, which measures the internal temperature of the AD7699 where: and is thus useful for performing a system calibration. For f is the input bandwidth in megahertz of the AD7699 −3dB applications requiring the use of the temperature sensor, the (14.7 MHz in full BW or 670 kHz in ¼ BW) or the cutoff internal reference must be active (internal buffer can be frequency of an input filter, if one is used. disabled in this case). Note that, when using the temperature N is the noise gain of the amplifier (for example, 1 in buffer sensor, the output is straight binary referenced from the configuration). AD7699 GND pin. eN is the equivalent input noise voltage of the op amp, in The internal reference is temperature-compensated to within nV/√Hz. 15 mV. The reference is trimmed to provide a typical drift of  For ac applications, the driver should have a THD perfor- 3 ppm/°C. mance commensurate with the AD7699. Figure 12 shows External Reference and Internal Buffer THD vs. frequency for the AD7699.  For multichannel, multiplexed applications on each input For improved drift performance, an external reference can be or input pair, the driver amplifier and the AD7699 analog used with the internal buffer. The external reference is connected to REFIN, and the output is produced on the REF pin. An input circuit must settle a full-scale step onto the capacitor external reference can be used with the internal buffer with or array at a 16-bit level (0.0015%). In amplifier data sheets, without the temperature sensor enabled. Refer to Table 8 for settling at 0.1% to 0.01% is more commonly specified. This register details. With the buffer enabled, the gain is unity and is may differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. limited to an input/output of 4.096 V. The internal reference buffer is useful in multiconverter applica- Table 7. Recommended Driver Amplifiers tions because a buffer is typically required in these applications. In Amplifier Typical Application addition, a low power reference can be used because the internal ADA4841-x Very low noise, small, and low power buffer provides the necessary performance to drive the SAR AD8655 5 V single supply, low noise architecture of the AD7699. AD8021 Very low noise and high frequency External Reference AD8022 Low noise and high frequency OP184 Low power, low noise, and low frequency In any of the five voltage reference schemes, an external refer- AD8605, AD8615 5 V single supply, low power ence can be connected directly on the REF pin because the output impedance of REF is >5 kΩ. To reduce power consumption, the reference and buffer can be powered down independently or together for the lowest power consumption. When only using the external reference (and optional reference buffer as shown in Figure 34), an internal buffer is disabled. Refer to Table 8 for register details. For improved drift performance, an external reference such as the ADR43x or ADR44x is recommended. Rev. B | Page 18 of 28 Data Sheet AD7699 75 Reference Decoupling 70 Whether using an internal or external reference, the AD7699 voltage reference output/input, REF, has a dynamic input 65 impedance and should therefore be driven by a low impedance 60 source with efficient decoupling between the REF and GND 55 pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected 50 to REF and GND with minimum parasitic inductance. A 10 μF 45 (X5R, 1206 size) ceramic chip capacitor is appropriate when using 40 the internal reference, the ADR43x/ADR44x external reference, 35 or a low impedance buffer such as the AD8031 or the AD8605. 30 The placement of the reference decoupling capacitor is also 1 10 100 1k 10k FREQUENCY (kHz) important to the performance of the AD7699, as explained in the Figure 32. PSRR vs. Frequency Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND should The AD7699 powers down automatically at the end of each also connect to the reference decoupling capacitor with the shortest conversion phase; therefore, the operating currents and power distance and to the analog ground plane with several vias. scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low battery- If desired, smaller reference decoupling capacitor values down powered applications. to 2.2 μF can be used with a minimal impact on performance, 10,000 especially on DNL. 1000 VDD = 5V, INTERNAL REF Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF 100 VDD = 5V, EXTERNAL REF and GND pins. 10 For applications that use multiple AD7699s or other PulSAR devices, it is more effective to use the internal reference buffer 1 to buffer the external reference voltage, thus reducing SAR VIO conversion crosstalk. 0.1 The voltage reference temperature coefficient (TC) directly 0.010 impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, 0.001 10 100 1k 10k 100k 1M a ±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. SAMPLING RATE (sps) Figure 33. Operating Currents vs. Sampling Rate POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7699 uses two power supply pins: an analog and digital For simplified applications, the AD7699, with its low operating core supply (VDD) and a digital input/output interface supply current, can be supplied directly using the reference circuit, as (VIO). VIO allows direct interface with any logic between 1.8 V shown in Figure 34. The reference line can be driven by and VDD. To reduce the supplies needed, the VIO and VDD pins • The system power supply directly can be tied together. The AD7699 is independent of power supply • A reference voltage with enough current output capability, sequencing between VIO and VDD. The only restriction is that such as the ADR43x/ADR44x CNV must be low when powering up the AD7699. Additionally, • A reference buffer, such as the AD8605, which can also it is very insensitive to power supply variations over a wide filter the system power supply, as shown in Figure 34 frequency range, as shown in Figure 32. 5V 5V 10Ω 5V 10kΩ 1µF 10µF 0.1µF 0.1µF AD8605 1µF 1 REF VDD VIO AD7699 1 OPTIONAL REFERENCE BUFFER AND FILTER. Figure 34. Example of an Application Circuit Rev. B | Page 19 of 28 OPERATING CURRENT (µA) PSSR (dB) 07354-030 07354-031 07354-032 AD7699 Data Sheet DIGITAL INTERFACE The SCK frequency required is calculated by The AD7699 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for Number _ SCK _ Edges f ≥ example, Blackfin® ADSP-BF53x, SHARC®, ADSP-219x, and SCK t DATA ADSP-218x. The time between tDATA and tCONV is a safe time when digital The interface uses the CNV, DIN, SCK, and SDO signals and activity should not occur, or sensitive bit decisions may be allows CNV, which initiates the conversion, to be independent corrupt. of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications. READING/WRITING DURING ACQUISITION, ANY SPEED HOSTS A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other When reading/writing after conversion, or during acquisition components, which are detailed in the Configuration Register, (n), conversion results are for the previous (n − 1) conversion, CFG section. and writing is for the (n + 1) acquisition. When CNV is low, reading/writing can occur during conversion, For the maximum throughput, the only time restriction is that acquisition, and spanning conversion (acquisition plus conver- the reading/writing take place during the tACQ (min) time. For sion), as detailed in the following sections. The CFG word is slow throughputs, the time restriction is dictated by throughput updated on the first 14 SCK rising edges, and conversion results required by the user, and the host is free to run at any speed. are output on the first 15 (or 16 if busy mode is selected) SCK Thus for slow hosts, data access must take place during the falling edges. If the CFG readback is enabled, an additional acquisition phase. 14 SCK falling edges are required to output the CFG word READING/WRITING SPANNING CONVERSION, ANY associated with the conversion results, with the CFG MSB SPEED HOST following the LSB of the conversion result. When reading/writing spanning conversion, the data access starts A discontinuous SCK is recommended because the part is at the current acquisition (n) and spans into the conversion (n). selected with CNV low, and SCK activity begins to write a new Conversion results are for the previous (n − 1) conversion, and configuration word and clock out data. writing the CFG register is for the next (n + 1) acquisition and Note that in the following sections, the timing diagrams indicate conversion. digital activity (SCK, CNV, DIN, SDO) during the conversion. Similar to reading/writing during conversion, reading/writing However, due to the possibility of performance degradation, should only occur up to tDATA. For the maximum throughput, digital activity should occur only prior to the safe data reading/ the only time restriction is that reading/writing take place writing time, t , because the AD7699 provides error correction DATA during the tACQ (min) + tDATA time. circuitry that can correct for an incorrect bit during this time. to t , there is no error correction and conversion For slow throughputs, the time restriction is dictated by the From tDATA CONV user’s required throughput, and the host is free to run at any results may be corrupted. The user should configure the AD7699 speed. Similar to reading/writing during acquisition, for slow and initiate the busy indicator (if desired) prior to tDATA. It is also hosts, the data access must take place during the acquisition possible to corrupt the sample by having SCK or DIN transitions phase with additional time into the conversion. near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns Note that data access spanning conversion requires the CNV to after the rising edge of CNV, using a discontinuous SCK whenever be driven high to initiate a new conversion, and data access is possible to avoid any potential performance degradation. not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method. READING/WRITING DURING CONVERSION, FAST HOSTS CONFIGURATION REGISTER, CFG When reading/writing during conversion (n), conversion The AD7699 uses a 14-bit configuration register (CFG[13:0]) as results are for the previous (n − 1) conversion, and writing the detailed in Table 8 for configuring the inputs, the channel to be CFG is for the next (n + 1) acquisition and conversion. converted, one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on After the CNV is brought high to initiate conversion, it must be DIN with 14 SCK rising edges. CFG update is edge dependent, brought low again to allow reading/writing during conversion. allowing for asynchronous or synchronous hosts. Reading/writing should only occur up to t and, because this DATA time is limited, the host must use a fast SCK. Rev. B | Page 20 of 28 Data Sheet AD7699 The register can be written to during conversion, during acquisi-  IN[7:0] unipolar referenced to GND, sequenced in order tion, or spanning acquisition/conversion and is updated at the  Full bandwidth for a one-pole filter end of conversion, t (maximum). There is always a one deep CONV  Internal reference/temperature sensor disabled, buffer delay when writing the CFG register. Note that at power-up, the enabled CFG register is undefined and two dummy conversions are  Enables the sequencer required to update the register. To preload the CFG register  No readback of the CFG register with a factory setting, hold DIN high for two conversions. Thus Table 8 summarizes the configuration register bit details. See CFG[13:0] = 0x3FFF. This sets the AD7699 for the following: the Theory of Operation section for more details. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG INCC INCC INCC INx INx INx BW REF REF REF SEQ SEQ RB Table 8. Configuration Register Description Bit(s) Name Description [13] CFG Configuration update. 0 = Keep current configuration settings. 1 = Overwrite contents of register. [12:10] INCC Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended, or temperature sensor. Refer to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function 1 0 0 X Bipolar differential pairs; INx− referenced to V /2 ± 0.1 V. REF 0 1 0 Bipolar; INx referenced to COM = VREF/2 ± 0.1 V. 0 1 1 Temperature sensor. 1 1 0 X Unipolar differential pairs; INx− referenced to GND ± 0.1 V. 1 1 0 Unipolar, IN0 to IN7 referenced to COM = GND ± 0.1 V (GND sense). 1 1 1 Unipolar, IN0 to IN7 referenced to GND. [9:7] INx Input channel selection in binary fashion. Bit 9 Bit 8 Bit 7 Channel 0 0 0 IN0 0 0 1 IN1 … … … … 1 1 1 IN7 [6] BW Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼. 1 = Full BW. [5:3] REF Reference/buffer selection. Selection of internal, external, and external buffered references, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section. Bit 5 Bit 4 Bit 3 Function 0 0 0 Not used 0 0 1 Internal reference, REF = 4.096 V output, temperature enabled. 0 1 0 External reference, temperature enabled. 0 1 1 External reference, internal buffer, temperature enabled. 1 1 0 External reference, temperature disabled. 1 1 1 External reference, internal buffer, temperature disabled. [2:1] SEQ Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Sequencer section. Bit 2 Bit 1 Function 0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature. 1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]). 0 RB Read back the CFG register. 0 = Read back current configuration at end of data. 1 = Do not read back contents of configuration. 1 X = don’t care. Rev. B | Page 21 of 28 AD7699 Data Sheet MSB of the current conversion. For detailed timing, refer to GENERAL TIMING WITHOUT A BUSY INDICATOR Figure 36 and Figure 37, which depict reading/writing spanning Figure 35 details the timing for all three modes: reading/writing conversion with all timing details, including setup, hold, and SCK. during conversion, after conversion, and spanning conversion. Note that the gating item for both CFG and data readback is at When CNV is brought low after EOC, SDO is driven from high the end of conversion (EOC). At the end of conversions (EOC), impedance to the MSB. Falling SCK edges clock out bits starting if CNV is high, the busy indicator is disabled. with MSB − 1. As detailed previously, the data access should occur up to safe The SCK can idle high or low depending on the clock polarity (CPOL) and clock phase (CPHA) settings if SPI is used. A simple data reading/writing time, tDATA. If the full CFG word was not solution is to use CPOL = CPHA = 0 as shown in Figure 35 with written to prior to EOC, it is discarded and the current SCK idling low. configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the START OF CONVERSION t CYC t CONV END OF CONVERSION (EOC) EOC EOC POWER t DATA UP ACQUISITION ACQUISITION ACQUISITION ACQUISITION PHASE CONVERSION (n – 2) CONVERSION (n – 1) CONVERSION (n) CONVERSION (n + 1) (n – 1) (n) (n + 1) (n + 2) CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) MSB MSB MSB MSB XXX DATA (n – 2) DATA (n – 1) DATA (n) SDO (n + 1) (n – 2) (n – 1) (n) 1 16/30 1 16/30 1 16/30 1 16/30 SCK CNV CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) DIN DATA DATA DATA (n) DATA (n + 1) SDO (n – 2) (n – 1) 1 16/30 1 16/30 1 16/30 1 SCK CNV DIN CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) DATA DATA DATA DATA DATA SDO DATA (n) DATA (n) (n – 2) (n – 2) (n – 1) (n – 1) (n + 1) 1 SCK 1 16/30 1 16/30 1 16/30 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 35. General Interface Timing for the AD7699 Without a Busy Indicator Rev. B | Page 22 of 28 READ/WRITE READ/WRITE READ/WRITE SPANNING CONVERT AFTER CONVERT DURING CONVERT 07354-033 Data Sheet AD7699 the CFG update. While CNV is low, both a CFG update and a READ/WRITE SPANNING CONVERSION WITHOUT data readback take place. The first 14 SCK rising edges are used A BUSY INDICATOR to update the CFG, and the first 15 SCK falling edges clock out This mode is used when the AD7699 is connected to any host the conversion results starting with MSB − 1. The restriction using an SPI, serial port, or FPGA. The connection diagram is for both configuring and reading is that they both must occur shown in Figure 36, and the corresponding timing is given in before the tDATA time of the next conversion elapses. All 14 bits Figure 37. For SPI, the host should use CPHA = CPOL = 0. of CFG[13:0] must be written, or they are ignored. In addition, Reading/writing spanning conversion is shown, which covers if the 16-bit conversion result is not read back before t elapses, DATA all three modes detailed in the Digital Interface section. For this it is lost. mode, the host must generate the data transfer based on the The SDO data is valid on both SCK edges. Although the rising conversion time. For an interrupt driven transfer, refer to the edge can be used to capture the data, a digital host using the next section, which uses a busy indicator. SCK falling edge allows a faster reading rate, provided it has an A rising edge on CNV initiates a conversion, forces SDO to th th acceptable hold time. After the 16 (or 30 ) SCK falling edge, or high impedance, and ignores data present on DIN. After a when CNV goes high (whichever occurs first), SDO returns to conversion is initiated, it continues until completion irrespective high impedance. of the state of CNV. CNV must be returned high before the safe If CFG readback is enabled, the CFG associated with the conver- data transfer time, t , and then held high beyond the conver- DATA sion result is read back MSB first following the LSB of the sion time, t , to avoid generation of the busy signal indicator. CONV conversion result. A total of 30 SCK falling edges is required to After the conversion is complete, the AD7699 enters the acquisi- return SDO to high impedance if this is enabled. tion phase and powers down. When the host brings CNV low after tCONV (max), the MSB is enabled on SDO. The host also must enable the MSB of CFG at this time (if necessary) to begin DIGITAL HOST AD7699 CNV SS MISO SDO MOSI DIN SCK SCK FOR SPI USE CPHA = 0, CPOL = 0. Figure 36. Connection Diagram for the AD7699 Without a Busy Indicator t CYC > t CONV t t CONV CONV t t DATA DATA t CNVH RETURN CNV HIGH RETURN CNV HIGH CNV FOR NO BUSY FOR NO BUSY t ACQ ACQUISITION (QUIET (QUIET ACQUISITION CONVERSION (n) CONVERSION (n – 1) ACQUISITION (n) (n + 1) (n – 1) TIME) TIME) t UPDATE (n + 1) SCK UPDATE (n) t SCKH SEE NOTE CFG/SDO CFG/SDO 16/ 16/ SCK 14 15 1 2 14 15 30 30 t t CLSCK SCKL t t SDIN HDIN CFG CFG CFG CFG DIN X X MSB – 1 X X LSB MSB LSB t t t HSDO t END CFG (n + 1) EN END CFG (n) EN BEGIN CFG (n + 1) EN t DSDO SEE NOTE SDO LSB MSB MSB – 1 LSB + 1 LSB LSB + 1 t END DATA (n – 1) t t END DATA (n – 2) t DIS DIS BEGIN DATA (n – 1) DIS DIS NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF. 15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. Figure 37. Serial Interface Timing for the AD7699 Without a Busy Indicator Rev. B | Page 23 of 28 07354-034 07354-035 AD7699 Data Sheet fully prior to EOC, the last bit clocked out remains. If this bit is GENERAL TIMING WITH A BUSY INDICATOR low, the busy signal indicator cannot be generated because the Figure 38 details the timing for all three modes: reading/writing digital output requires a high impedance, or a bit remaining high, during conversion, after conversion, and spanning conversion. to low transition for the interrupt input of the host. A good Note that the gating item for both CFG and data readback is at example of this occurs when an SPI host sends 16 SCKs because the end of conversion (EOC). As detailed previously, the data these are usually limited to 8-bit or 16-bit bursts, thus the LSB access should occur up to safe data reading/writing time, t . DATA remains. Because the transition noise of the AD7699 is 4 LSBs If the full CFG word is not written to prior to EOC, it is peak to peak (or greater), the LSB is low 50% of the time. For discarded and the current configuration remains. this interface, the SPI host needs to burst 24 SCKs, or a QSPI At the EOC, if CNV is low, the busy indicator is enabled. In interface can be used and programmed for 17 SCKs. addition, to generate the busy indicator properly, the host must The SCK can idle high or low depending on the CPOL and assert a minimum of 17 SCK falling edges to return SDO to CPHA settings if SPI is used. A simple solution is to use CPOL high impedance because the last bit of data on SDO remains = CPHA = 1 (not shown) with SCK idling high. active. Unlike the case detailed in the General Timing Without a Busy Indicator section, if the conversion result is not read out START OF CONVERSION t CYC t CONV END OF CONVERSION (EOC) EOC EOC POWER t DATA UP ACQUISITION ACQUISITION ACQUISITION ACQUISITION PHASE CONVERSION (n – 1) CONVERSION (n) CONVERSION (n + 1) CONVERSION (n – 2) (n –1) (n) (n + 1) (n + 2) CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) DATA DATA XXX SDO DATA (n) (n – 2) (n – 1) 1 17/31 1 17/31 1 17/31 1 17/31 SCK CNV DIN CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) DATA DATA SDO DATA (n) DATA (n + 1) (n – 2) (n – 1) 117/31 11 17/31 17/31 1 SCK CNV CFG (n + 1) CFG (n + 2) CFG (n) CFG (n + 3) DIN DATA DATA DATA SDO DATA (n – 2) DATA (n) DATA (n) DATA (n + 1) (n – 2) (n – 1) (n – 1) 1 SCK 17/31 1 17/31 1 17/31 1 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. A TOTAL OF 17 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 38. General Interface Timing for the AD7699 With a Busy Indicator Rev. B | Page 24 of 28 READ/WRITE READ/WRITE READ/WRITE SPANNING CONVERT AFTER CONVERT DURING CONVERT 07354-036 Data Sheet AD7699 update. While CNV is low, both a CFG update and a data READ/WRITE SPANNING CONVERSION WITH A readback take place. The first 14 SCK rising edges are used to BUSY INDICATOR update the CFG register, and the first 16 SCK falling edges clock This mode is used when the AD7699 is connected to any host out the conversion results starting with the MSB. The restriction using an SPI, serial port, or FPGA with an interrupt input. The for both configuring and reading is that they both occur before connection diagram is shown in Figure 39, and the the tDATA time elapses for the next conversion. All 14 bits of corresponding timing is given in Figure 40. For SPI, the host CFG[13:0] must be written or they are ignored. Also, if the 16-bit should use CPHA = CPOL = 1. Reading/writing spanning conversion result is not read back before tDATA elapses, it is lost. conversion is shown, which covers all three modes detailed in The SDO data is valid on both SCK edges. Although the rising the Digital Interface section. edge can be used to capture the data, a digital host using the A rising edge on CNV initiates a conversion, forces SDO to SCK falling edge allows a faster reading rate, provided it has an high impedance, and ignores data present on DIN. After a th acceptable hold time. After the optional 17 SCK falling edge, conversion is initiated, it continues until completion irrespec- SDO returns to high impedance. Note that, if the optional SCK tive of the state of CNV. CNV must be returned low before the falling edge is not used, the busy feature cannot be detected if safe data transfer time, tDATA, and then held low beyond the the LSB for the conversion is low. conversion time, tCONV, to generate the busy signal indicator. If CFG readback is enabled, the CFG register associated with When the conversion is complete, SDO transitions from high the conversion result (n − 1) is read back MSB first following impedance to low with a pull-up to VIO, which can be used to the LSB of the conversion result. A total of 31 SCK falling edges interrupt the host to begin data transfer. is required to return SDO to high impedance if this is enabled. After the conversion is complete, the AD7699 enters the acquisition phase and power-down. The host must enable the MSB of CFG at this time (if necessary) to begin the CFG VIO AD7699 DIGITAL HOST SDO MISO IRQ CNV SS MOSI DIN SCK SCK FOR SPI USE CPHA = 1, CPOL = 1. Figure 39. Connection Diagram for the AD7699 with a Busy Indicator t t CYC CONV t t t ACQ DATA DATA t CNVH CNV CONVERSION (QUIET (QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n – 1) TIME) TIME) (n + 1) t SCK UPDATE (n) UPDATE (n + 1) t SCKH SEE NOTE CFG/SDO CFG/SDO 17/ 17/ SCK 15 16 1 2 16 15 31 31 t t SCKL HDIN t SDIN CFG CFG DIN XX X X X X MSB MSB –1 t t BEIGN CFG (n + 1) HSDO t t END CFG (n) DIS EN END CFG (n + 1) DIS t DSDO LSB MSB LSB SDO LSB MSB LSB + 1 – 1 + 1 SEE NOTE END DATA (n – 2) BEGIN DATA (n – 1) END DATA (n – 1) t t t EN DIS EN NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF. 16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. Figure 40. Serial Interface Timing for the AD7699 with a Busy Indicator Rev. B | Page 25 of 28 07354-037 07354-038 AD7699 Data Sheet APPLICATION HINTS inductances. This is done by placing the reference decoupling LAYOUT ceramic capacitor close to, ideally right up against, the REF and The printed circuit board that houses the AD7699 should be GND pins and connecting them with wide, low impedance traces. designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the Finally, the power supplies, VDD and VIO, of the AD7699 should be decoupled with ceramic capacitors, typically 100 nF, AD7699, with all its analog signals on the left side and all its placed close to the AD7699 and connected using short, wide digital signals on the right side, eases this task. traces to provide low impedance paths and to reduce the effect Avoid running digital lines under the device because these couple of glitches on the power supply lines. noise onto the die unless a ground plane under the AD7699 is used as a shield. Fast switching signals, such as CNV or clocks, EVALUATING AD7699 PERFORMANCE should not run near analog signal paths. Crossover of digital Other recommended layouts for the AD7699 are outlined in the and analog signals should be avoided. documentation of the evaluation board for the AD7699 (EVAL- At least one ground plane should be used. It can be common or AD76MUXCBZ). The evaluation board package includes a fully split between the digital and analog sections. In the latter case, assembled and tested evaluation board, documentation, and the planes should be joined underneath the AD7699. software for controlling the board from a PC via the evaluation controller board, EVAL-CONTROL BRD3. The AD7699 voltage reference input, REF, has a dynamic input impedance and should be decoupled with minimal parasitic Rev. B | Page 26 of 28 Data Sheet AD7699 OUTLINE DIMENSIONS 4.10 0.60 MAX 4.00 SQ 3.90 0.60 MAX 16 20 15 1 PIN 1 0.50 2.65 3.75 EXPOSED INDICATOR BSC BSC SQ PAD 2.50 SQ (BOTTOM VIEW) 2.35 5 11 10 6 0.50 0.25 MIN TOP VIEW 0.40 0.30 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.30 SEATING 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 41. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Integral No Missing Temperature Package Ordering 1, 2 Model Nonlinearity Code Range Package Description Option Quantity AD7699BCPZ ±1.5 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_VQ CP-20-4 Tray, 490 AD7699BCPZRL7 ±1.5 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_VQ CP-20-4 Reel, 1500 EVAL-AD7699EDZ Evaluation Board EVAL-CONTROL BRD3Z Controller Board 1 Z = RoHS Compliant Part. 2 The EVAL-CONTROL BRD3Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in CB. Rev. B | Page 27 of 28 IN P 1 O INDICAT R 03-08-2012-B AD7699 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07354-0-3/12(B) Rev. B | Page 28 of 28