ANALOG DEVICES AD7694

® 16-Bit, 250 kSPS PulSAR ADC in MSOP AD7694 APPLICATION DIAGRAM FEATURES 1V TO VDD 2.5V TO 5V 16-bit resolution with no missing codes Throughput: 250 kSPS @ 5 V INL: ±4 LSB max REF VDD S/(N + D): 92 dB @ 20 kHz 0 TO V REF IN+ THD: –106 dB @ 20 kHz SCK AD7694 3-WIRE SPI SDO IN– Pseudo-differential analog input range: INTERFACE CNV GND 0 V to VREF with VREF up to VDD No pipeline delay Single-supply operation: 2.7 V or 5 V Figure 1. Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Supply Current: 540 μA @ 2.7 V/100 kSPS, 800 μA @ 5 V/100 kSPS Table 1. MSOP, LFCSP (QFN)/SOT-23, 16-Bit PulSAR ADC Standby current: 1 nA Type 100 kSPS 250 kSPS 500 kSPS 8-lead MSOP package True Differential AD7684 AD7687 AD7688 Improved second source to LTC1864 and LTC1864L Pseudo AD7683 AD7685 AD7686 Differential/Unipolar AD7694 APPLICATIONS Unipolar AD7680 Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control GENERAL DESCRIPTION The AD7694 is a 16-bit, charge redistribution, successive approximation, PulSAR analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V to 5.25 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input, IN+, between 0 V to REF with respect to a ground sense, IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7694 is housed in an 8-lead MSOP package with an operating temperature specified from −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 www.analog.com No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 05003-001 AD7694 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation.................................................................. 12 Applications....................................................................................... 1 Transfer Functions ..................................................................... 12 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 13 Application Diagram........................................................................ 1 Analog Input ............................................................................... 13 Revision History ............................................................................... 2 Driver Amplifier Choice ........................................................... 13 Specifications..................................................................................... 3 Voltage Reference Input ............................................................ 14 Timing Specifications....................................................................... 5 Power Supply............................................................................... 14 Absolute Maximum Ratings............................................................ 6 Supplying the ADC from the Reference.................................. 14 ESD Caution.................................................................................. 6 Digital Interface.......................................................................... 15 Pin Configuration and Function Descriptions............................. 7 Layout .......................................................................................... 15 Terminology ...................................................................................... 8 Evaluating the AD7694’s Performance.................................... 15 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 16 Application Information................................................................ 12 Ordering Guide .......................................................................... 16 Circuit Information.................................................................... 12 REVISION HISTORY 5/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Digital Interface Section............................................ 14 Changes to Figure 25...................................................................... 15 Changes to Evaluating the AD7694’s Performance Section...... 15 7/04—Revision 0: Initial Version Rev. A | Page 2 of 16 AD7694 SPECIFICATIONS VDD = 2.7 V to 5.25 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 2. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ANALOG INPUT Voltage Range IN+ − IN− 0 V 0 V V REF REF Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V IN− −0.1 +0.1 −0.1 +0.1 V Leakage Current at 25°C Acquisition phase 1 1 nA Input Impedance See the Analog Input section ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 +6 −4 +4 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 LSB 1 Gain Error , TMIN to TMAX ±2 ±30 ±2 ±15 LSB Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C 1 Offset Error , TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity ±0.05 ±0.05 LSB VDD = 5 V ± 5% THROUGHPUT Conversion Rate VDD = 4.75 V to 5.25 V 0 250 0 250 kSPS VDD = 2.7 V to 4.75 V 0 150 0 150 kSPS AC ACCURACY 2 Signal-to-Noise f = 20 kHz, V = 5 V 90 88 92 dB IN REF f = 20 kHz, V = 2.5 V 86 87 dB IN REF Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 dB Total Harmonic Distortion fIN = 20 kHz −100 −106 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 89 88 92 dB f = 20 kHz, V = 2.5 V 86 87 dB IN REF 1 See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference. 2 All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 3 of 16 AD7694 VDD = 2.7 V to 5.25 V; V = VDD; T = –40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 1 VDD V Load Current 250 kSPS, V − V = V /2 = 2.5 V 50 μA IN+ IN− REF SAMPLING DYNAMICS −3 dB Input Bandwidth 9 MHz DIGITAL INPUTS Logic Levels V VDD = 4.75 V 0.8 V IL VDD = 2.7 V 0.45 V V VDD = 5.25 V 3.15 V IH VDD = 3.3 V 1.9 V IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial, 16 bits straight binary Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK VOH ISOURCE = −500 μA VDD − 0.3 V POWER SUPPLIES VDD Specified performance 2.7 5.25 V Operating Current VDD VDD = 5 V, 100 kSPS throughput 0.8 1.2 mA VDD = 2.7 V, 100 kSPS throughput 540 960 μA 1, 2 Standby Current 1 50 nA VDD = 5 V, 25°C TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With all digital inputs forced to VDD or GND, as required. 2 During acquisition phase. Rev. A | Page 4 of 16 AD7694 TIMING SPECIFICATIONS VDD = 4.75 V to 5.25 V; TA = −40°C to +85°C, unless otherwise stated. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 3.2 μs CONV Time Between Conversions t 4 μs CYC SCK Period tSCK 50 ns SCK Low Time tSCKL 20 ns SCK High Time tSCKH 20 ns SCK Falling Edge to Data Remains Valid t 5 ns HSDO SCK Falling Edge to Data Valid Delay t 20 ns DSDO CNV Low to SDO, D15 MSB Valid t 60 ns EN CNV High to SDO High Impedance tDIS 60 ns VDD = 2.7 V to 4.75 V; T = −40°C to +85°C, unless otherwise stated. A Table 5. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 4.66 μs CONV Time Between Conversions t 6.66 μs CYC SCK Period t 125 ns SCK SCK Low Time tSCKL 50 ns SCK High Time tSCKH 50 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay t 50 ns DSDO CNV Low to SDO, D15 MSB Valid t 120 ns EN CNV High to SDO High Impedance t 120 ns DIS Rev. A | Page 5 of 16 AD7694 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Stresses above those listed under Absolute Maximum Ratings Analog Inputs may cause permanent damage to the device. This is a stress 1 1 IN+ , IN− GND − 0.3 V to VDD + 0.3 V rating only; functional operation of the device at these or any or ±130 mA other conditions above those indicated in the operational REF GND − 0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute Supply Voltages maximum rating conditions for extended periods may affect VDD to GND −0.3 V to +7 V device reliability. Digital Inputs to GND −0.3 V to VDD + 0.3 V Digital Outputs to GND −0.3 V to VDD + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance 200°C/W (MSOP-8) JA θ Thermal Impedance 44°C/W (MSOP-8) JC Lead Temperature Range Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Input section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500μAI OL TO SDO 1.4V C L 50pF 500μAI OH Figure 2. Load Circuit for Digital Interface Timing V IH V IL t t DELAY DELAY V V OH OH V V OL OL Figure 3. Voltage Reference Levels for Timing Rev. A | Page 6 of 16 05003-002 05003-003 AD7694 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 8 VDD AD7694 IN+ 2 7 SCK TOP VIEW IN– 3 6 SDO (Not to Scale) GND 4 5 CNV Figure 4. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions 1 Pin No. Mnemonic Type Function 1 REF AI Reference Input Voltage. The REF range is from 1 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a ceramic capacitor of a few μF. 2 IN+ AI Analog Input. It is referred to in IN−. The voltage range, that is, the difference between IN+ and IN−, which is 0 V to V . REF 3 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 4 GND P Power Supply Ground. 5 CNV DI Convert Input. On its leading edge, it initiates the conversions. It enables the SDO pin when low. 6 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 7 SCK DI Serial Data Clock Input. When CNV is low, the conversion result is shifted out by this clock. 8 VDD P Power Supply. 1 AI = analog input; DI = digital input; DO = digital output; and P = power. Rev. A | Page 7 of 16 05003-004 AD7694 TERMINOLOGY Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) ENOB is a measurement of the resolution with a sine wave Linearity error refers to the deviation of each individual code input. It is related to S/(N + D) by from a line drawn from negative full scale to positive full scale. The point used as negative full scale occurs ½ LSB before the ENOB = (S/[N + D]dB − 1.76)/6.02 first code transition. Positive full scale is defined as a level and is expressed in bits. 1 ½ LSB beyond the last code transition. The deviation is Total Harmonic Distortion (THD) measured from the middle of each code to the true straight line THD is the ratio of the rms sum of the first five harmonic (see Figure 19). components to the rms value of a full-scale input signal and is Differential Nonlinearity Error (DNL) expressed in dB. In an ideal ADC, code transitions are 1 LSB apart. DNL is the Signal-to-Noise Ratio (SNR) maximum deviation from this ideal value. It is often specified in SNR is the ratio of the rms value of the actual input signal to the terms of resolution for which no missing codes are guaranteed. rms sum of all other spectral components below the Nyquist Offset Error frequency, excluding harmonics and dc. The value for SNR is The first transition should occur at a level ½ LSB above analog expressed in dB. ground (38.1 μV for the 0 V to 5 V range). The offset error is Signal-to-(Noise + Distortion) Ratio (S/[N + D]) the deviation of the actual transition from that point. S/(N+D) is the ratio of the rms value of the actual input signal Gain Error to the rms sum of all other spectral components below the The last transition (from 111...10 to 111...11) should occur for Nyquist frequency, including harmonics but excluding dc. The an analog voltage 1 ½ LSB below the nominal full scale value for S/(N+D) is expressed in dB. (4.999886 V for the 0 V to 5 V range). The gain error is the Aperture Delay deviation of the actual level of the last transition from the ideal Aperture delay is a measure of the acquisition performance and level after the offset has been adjusted out. the time between the rising edge of the CNV input and the time Spurious-Free Dynamic Range (SFDR) the input signal is held for conversion. The difference, in decibels (dB), between the rms amplitude of Transient Response the input signal and the peak spurious signal. The time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. A | Page 8 of 16 AD7694 TYPICAL PERFORMANCE CHARACTERISTICS 4 2.0 POSITIVE INL = +0.68 LSB POSITIVE DNL = +0.59 LSB NEGATIVE INL = –1.14 LSB NEGATIVE DNL = –0.56 LSB 3 1.5 2 1.0 1 0.5 0 0 –1 –0.5 –2 –1.0 –3 –1.5 –4 –2.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 12000 8000 108568 VDD = REF = 2.5V VDD = REF = 5V 7000 65487 10000 6000 8000 5000 6000 4000 32418 28148 3000 4000 2000 2000 12500 1000 10003 2133 2808 00 1 0 0 0 00 27 50 10 0 0 0 251B 251C 251D 251E 251F 2520 2521 2522 2523 2524 2525 2526 24E0 24E1 24E2 24E3 24E4 24E5 24E6 24E7 24E8 CODE IN HEX CODE IN HEX Figure 6. Histogram of a DC Input at the Code Center Figure 9. Histogram of a DC Input at the Code Center 0 0 16384 POINT FFT 16384 POINT FFT VDD = REF = 5V VDD = REF = 2.5V –20 –20 f = 250kSPS f = 150kSPS S S f = 20.43kHz f = 20.43kHz IN IN –40 –40 SNR = 92.5dB SNR = 88.5dB THD = –109.9dB THD = –102.7dB SFDR = –111.0dB SFDR = –105.1dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 20 40 60 80 100 120 0 10 203040 506070 FREQUENCY (kHz) FREQUENCY (kHz) Figure 7. FFT Plot Figure 10. FFT Plot Rev. A | Page 9 of 16 AMPLITUDE (dB OF FULL SCALE) COUNTS INL (LSB) 05003-007 05003-006 05003-005 AMPLITUDE (dB OF FULL SCALE) COUNTS DNL (LSB) 05003-010 05003-009 05003-008 AD7694 100 17 1200 1000 f = 100kSPS S 95 16 800 SNR 90 15 600 400 ENOB S/[N+D] 85 14 200 80 13 0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V) SUPPLY (V) Figure 11. SNR, S/(N + D), and ENOB vs. Reference Voltage Figure 14. Operating Current vs. Supply 100 900 VDD = 5V, f = 100kSPS S 800 95 V = 5V, –10dB 700 REF VDD = 2.7V, f = 100kSPS S 90 600 V = 5V, –1dB REF 500 85 400 V = 2.5V, –1dB REF 80 300 200 75 100 70 0 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 12. S/[N + D] vs. Frequency Figure 15. Operating Current vs. Temperature 1000 –80 V = 2.5V, –1dB REF –85 750 –90 –95 500 V = 5V, –1dB REF –100 –105 250 –110 0 –115 –55 –35 –15 5 25 45 65 85 105 125 0 40 80 120 160 200 TEMPERATURE (°C) FREQUENCY (kHz) Figure 16. Power-Down Current vs. Temperature Figure 13. THD vs. Frequency Rev. A | Page 10 of 16 SNR, S/[N+D] (dB) THD (dB) S/[N+D] (dB) 05003-013 05003-012 ENOB (Bits) 05003-011 POWER-DOWN CURRENT (nA) OPERATING CURRENT (μA) OPERATING CURRENT (μA) 05003-016 05003-014 05003-015 AD7694 6 4 2 OFFSET ERROR 0 –2 GAIN ERROR –4 –6 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 17. Offset and Gain Error vs. Temperature Rev. A | Page 11 of 16 OFFSET ERROR, GAIN ERROR (LSB) 05003-017 AD7694 APPLICATION INFORMATION IN+ SWITCHES CONTROL MSB SW+ LSB 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV IN– Figure 18. ADC Simplified Schematic After the completion of this process, the part returns to the CIRCUIT INFORMATION acquisition phase and the control logic generates the ADC The AD7694 is a low power, single-supply, 16-bit ADC using a output code. successive approximation architecture. It is capable of con- Because the AD7694 has an on-board conversion clock, the verting 250,000 samples per second (250 kSPS) and powers serial clock, SCK, is not required for the conversion process. down between conversions. When operating at 100 SPS, for example, it typically consumes 4 μW, ideal for battery-powered TRANSFER FUNCTIONS applications. The ideal transfer function for the AD7694 is shown in The AD7694 provides the user with on-chip, track-and-hold Figure 19 and Table 8. and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. The AD7694 is specified from 2.7 V to 5.25 V. It is housed in an 111...111 111...110 8-lead MSOP. The AD7694 is an improved second source to 111...101 LTC1864 and LTC1864L. For even better performance, the AD7685 should be considered. CONVERTER OPERATION The AD7694 is a successive approximation ADC based on a charge redistribution DAC. Figure 18 shows the simplified 000...010 schematic of the ADC. The capacitive DAC consists of two 000...001 identical arrays of 16 binary weighted capacitors, which are 000...000 –FS –FS + 1 LSB +FS – 1 LSB connected to the two comparator inputs. –FS + 0.5 LSB +FS – 1.5 LSB During the acquisition phase, terminals of the array tied to the ANALOG INPUT comparator’s input are connected to GND via SW+ and SW−. Figure 19. ADC Ideal Transfer Function All independent switches are connected to the analog inputs. Table 8. Output Codes and Ideal Input Voltages Thus, the capacitor arrays are used as sampling capacitors and Analog Input Digital Output Code acquire the analog signal on the IN+ and IN− inputs. When the Description V = 5 V Hexadecimal REF acquisition phase is complete and the CNV input goes high, a 1 FSR – 1 LSB 4.999924 V FFFF conversion phase begins. When the conversion phase begins, Midscale + 1 LSB 2.500076 V 8001 SW+ and SW− are opened first. The two capacitor arrays are Midscale 2.5 V 8000 then disconnected from the inputs and connected to the GND Midscale – 1 LSB 2.499924 V 7FFF input. Thus, the differential voltage between the inputs, IN+ –FSR + 1 LSB 76.3 μV 0001 and IN−, captured at the end of the acquisition phase applies to 2 –FSR 0 V 0000 the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array 1 This is also the code for an overranged analog input (VIN+ – VIN– above between GND and REF, the comparator input varies by binary V – V ). REF GND 2 This is also the code for an underranged analog input (VIN+ – VIN– below VGND). weighted voltage steps (VREF/2, VREF/4 … VREF/65536). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. Rev. A | Page 12 of 16 ADC CODE (STRAIGHT BINARY) 05003-018 05003-019 AD7694 (NOTE 1) REF 2.7V TO 5.25V 2.2 TO 10μF 100nF (NOTE 2) REF VDD 33Ω IN+ 0 TO V REF SCK 2.7nF AD7694 (NOTE 3) SDO 3-WIRE INTERFACE IN– CNV (NOTE 4) GND NOTES 1. SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10μF CERAMIC CAPACITOR (X5R). REF 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 20. Typical Application Diagram the ADC sampling capacitor. During the conversion phase, TYPICAL CONNECTION DIAGRAM where the switches are opened, the input impedance is limited Figure 20 shows an example of the recommended application to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces diagram for the AD7694. undesirable aliasing effects and limits the noise. ANALOG INPUT When the source impedance of the driving circuit is low, the Figure 21 shows an equivalent circuit of the AD7694 input AD7694 can be driven directly. Large source impedances structure. The two diodes, D1 and D2, provide ESD protection significantly affect the ac performance, especially total for the analog inputs, IN+ and IN−. Care must be taken to harmonic distortion (THD). The dc performances are less ensure that the analog input signal never exceeds the supply sensitive to the input impedance. rails by more than 0.3 V, because this will cause these diodes to DRIVER AMPLIFIER CHOICE become forward-biased and start conducting current. However, Although the AD7694 is easy to drive, the driver amplifier these diodes can handle a forward-biased current of 130 mA needs to meet the following requirements: maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from • The noise generated by the driver amplifier needs to be VDD. In such a case, an input buffer with a short-circuit, kept as low as possible to preserve the SNR and transition current limitation can be used to protect the part. noise performance of the AD7694. Note that the AD7694 VDD has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier op D1 C IN R IN IN+ amp while preserving the same or better system perfor- OR IN– mance. The noise coming from the driver is filtered by the C PIN D2 AD7694 analog input circuit 1-pole, low-pass filter made GND by R1 and C2 or by the external filter, if one is used. Figure 21. Equivalent Analog Input Circuit • For ac applications, the driver needs to have a THD This analog input structure allows the sampling of the performance suitable to that of the AD7694. Figure 13 differential signal between IN+ and IN−. By using this gives the THD vs. frequency that the driver should exceed. differential input, small signals common to both inputs are • For multichannel, multiplexed applications, the driver rejected. For instance, by using IN− to sense a remote signal amplifier and the AD7694 analog input circuit must be ground, ground potential differences between the sensor and able to settle for a full-scale step of the capacitor array at a the local ADC ground are eliminated. During the acquisition 16-bit level (0.0015%). In the amplifier’s data sheet, settling phase, the impedance of the analog input IN+ can be modeled at 0.1% to 0.01% is more commonly specified. This could as a parallel combination of the capacitor CPIN and the network differ significantly from the settling time at a 16-bit level formed by the series connection of R and C . C is primarily IN IN PIN and should be verified prior to driver selection. the pin capacitance. R is typically 600 Ω and is a lumped IN component made up of some serial resistors and the on resistance of the switches. C is typically 30 pF and is mainly IN Rev. A | Page 13 of 16 05003-021 05003-020 AD7694 Table 9. Recommended Driver Amplifiers SUPPLYING THE ADC FROM THE REFERENCE Amplifier Typical Application For simplified applications, the AD7694, with its low operating AD8021 Very low noise and high frequency current, can be supplied directly using the reference circuit, as AD8022 Low noise and high frequency shown in Figure 23. The reference line can be driven by either OP184 Low power, low noise, and low frequency • The system power supply directly AD8605, AD8615 5 V single-supply and low power AD8519 Small, low power, and low frequency • A reference voltage with enough current output capability, AD8031 High frequency and low power such as the ADR43x • A reference buffer, such as the AD8031, that can also filter VOLTAGE REFERENCE INPUT the system power supply, as shown in Figure 23 The AD7694 voltage reference input, REF, has a dynamic input 5V OR 3V impedance and should therefore be driven by a low impedance 5V OR 3V source with efficient decoupling between the REF and GND 10Ω pins, as explained in the Layout section. 5V 10kΩ 2.2 OR 1μF TO AD8031 3V When REF is driven by a very low impedance source (for 10μF 1μF example, an unbuffered reference voltage like the low (NOTE 1) temperature drift ADR43x reference or a reference buffer using REF VDD the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. AD7694 If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, NOTES especially DNL. 1. OPTIONAL REFERENCE BUFFER AND FILTER. POWER SUPPLY Figure 23. Example of an Application Circuit The AD7694 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 22. This makes the part ideal for a low sampling rate (even a few Hz) and low battery- powered applications. 10,000 1,000 VDD = 5V 100 VDD = 2.7V 10 1 0.1 0.01 10 100 1k 10k 100k 1M SAMPLING RATE (SPS) Figure 22. Operating Current vs. Sampling Rate Rev. A | Page 14 of 16 OPERATING CURRENT (μA) 05003-022 05003-023 AD7694 t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 1 2 3 14 15 16 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 1 SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW. Figure 24. Serial Interface Timing Avoid running digital lines under the device because these DIGITAL INTERFACE couple noise onto the die, unless a ground plane under the The AD7694 is compatible with SPI, QSPI, digital hosts, and AD7694 is used as a shield. Fast switching signals, such as CNV DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. The or clocks, should never run near analog signal paths. Crossover connection diagram is shown in Figure 25 and the of digital and analog signals should be avoided. corresponding timing diagram is shown in Figure 24. At least one ground plane should be used. It could be common A rising edge on CNV initiates a conversion and forces SDO to or split between the digital and analog section. In such a case, it high impedance. When the conversion is complete, the AD7694 should be joined underneath the AD7694s. enters the acquisition phase and powers down. When CNV The AD7694 voltage reference input REF has a dynamic input goes low, the MSB is output onto SDO. The remaining data bits impedance and should be decoupled with minimal parasitic are clocked by SCK falling edges. The data is valid on both SCK inductances. That is done by placing the reference decoupling edges. ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low CONVERT impedance traces. CNV DIGITAL HOST Finally, the power supply, VDD, of the AD7694 should be SDO DATA IN AD7694 decoupled with a ceramic capacitor, typically 100 nF. This SCK capacitor should be placed close to the AD7694 and connected CLK using short and large traces to provide low impedance paths Figure 25. Connection Diagram and reduce the effect of glitches on the power supply lines. LAYOUT EVALUATING THE AD7694’S PERFORMANCE The printed circuit board that houses the AD7694 should be Other recommended layouts for the AD7694 are outlined in the designed so that the analog and digital sections are separated evaluation board for the AD7694 (EVAL-AD7694). The and confined to certain areas of the board. The pinout of the evaluation board package includes a fully assembled and tested AD7694 with all its analog signals on the left side and all its evaluation board, documentation, and software for controlling digital signals on the right side eases this task. the board from a PC via the EVAL-CONTROL BRD3. Rev. A | Page 15 of 16 05003-024 05003-025 AD7694 OUTLINE DIMENSIONS 3.00 BSC 8 5 4.90 3.00 BSC BSC 1 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.80 8° 0.60 0.38 0.23 0° 0.40 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 26. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions Shown in Millimeters ORDERING GUIDE Integral Package Package Transport Media, Model Nonlinearity Temperature Range Description Option Quantity Branding AD7694ARM ±6 LSB max –40°C to +85°C MSOP RM-8 Tube, 50 C2H AD7694ARMRL7 ±6 LSB max –40°C to +85°C MSOP RM-8 Reel, 1,000 C2H AD7694BRM ±4 LSB max –40°C to +85°C MSOP RM-8 Tube, 50 C2J AD7694BRMRL7 ±4 LSB max –40°C to +85°C MSOP RM-8 Reel, 1,000 C2J 1 EVAL-AD7694CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board 2 EVAL-CONTROL BRD3 Controller Board 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 2 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators. ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05003–0–5/05(A) Rev. A | Page 16 of 16