ANALOG DEVICES AD7693

® 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential ADC in MSOP/QFN AD7693 FEATURES APPLICATION DIAGRAM +2.5V TO +5V +5V 16-bit resolution with no missing codes Throughput: 500 kSPS INL/DNL: ±0.25 LSB typ, ±0.5 LSB max (±8 ppm of FSR) VIO +1.8V TO VDD Dynamic range: 96.5 dB REF VDD IN+ SDI SINAD: 96 dB @ 1 kHz 3- OR 4-WIRE SCK AD7693 ±10V, ±5V, ... INTERFACE SDO THD: −120 dB @ 1 kHz (SPI, DAISY CHAIN, CS) IN– GND CNV True differential analog input range: ±V REF ADA4941-1 0 V to V with V up to VDD on both inputs REF REF Figure 2. No pipeline delay Single-supply 5 V operation with Table 1. MSOP, QFN (LFCSP)/SOT-23 1.8 V/2.5 V/3 V/5 V logic interface 14-/16-/18-Bit PulSAR ADC Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible 400 kSPS Daisy-chain multiple ADCs, selectable busy indicator 100 250 to ADC Type kSPS kSPS 500 kSPS Driver Power dissipation: 40 nJ/conversion 18-Bit AD7691 AD7690 ADA4941-1 40 μW @ 5 V/1 kSPS ADA4841-x 4 mW @ 5 V/100 kSPS 16-Bit True AD7684 AD7687 AD7688 ADA4941-1 18 mW @ 5 V/500 kSPS Differential ADA4841-x AD7693 Standby current: 1 nA 16-Bit Pseudo AD7683 AD7685 AD7686 ADA4841-x 10-lead package: MSOP (MSOP-8 size) and Differential/ AD7680 AD7694 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Unipolar Pin-for-pin compatible with the 16-bit AD7687 and AD7688 14-Bit AD7940 AD7942 AD7946 ADA4841-x and the 18-bit AD7690 and AD7691 APPLICATIONS GENERAL DESCRIPTION Battery-powered equipment The AD7693 is a 16-bit, successive approximation analog-to- Data acquisitions digital converter (ADC) that operates from a single power supply, Seismic data acquisition systems VDD. It contains a low power, high speed, 16-bit sampling ADC DVMs with no missing codes, an internal conversion clock, and a Instrumentation versatile serial interface port. The reference voltage, VREF, is Medical instruments applied externally and can be set up to the supply voltage, VDD. On the CNV rising edge, it samples the voltage difference 1.0 POSITIVE INL = +0.17LSB NEGATIVE INL = –0.17LSB between the IN+ and IN− pins. The voltages on these pins 0.8 swing in opposite phase between 0 V and V about V /2. REF REF 0.6 Its power scales linearly with throughput. 0.4 Using the SDI input, the SPI-compatible serial interface also 0.2 features the ability to daisy-chain several ADCs on a single 0 3-wire bus and provides an optional busy indicator. It is compatible –0.2 with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply. –0.4 The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN –0.6 (LFCSP) with operation specified from −40°C to +85°C. –0.8 –1.0 0 16384 32768 49152 65536 CODE Figure 1. Integral Nonlinearity vs. Code Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 06394-001 06394-002 AD7693 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications....................................................................................... 1 Single-Ended-to-Differential Driver ....................................... 15 Application Diagram........................................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply............................................................................... 15 Revision History ............................................................................... 2 Supplying the ADC from the Reference.................................. 16 Specifications..................................................................................... 3 Digital Interface.......................................................................... 16 Timing Specifications....................................................................... 5 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Absolute Maximum Ratings............................................................ 6 CS Mode, 3-Wire with Busy Indicator .................................... 18 ESD Caution.................................................................................. 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 Pin Configurations and Function Descriptions ........................... 7 CS Mode, 4-Wire with Busy Indicator .................................... 20 Terminology ...................................................................................... 8 Chain Mode Without Busy Indicator ...................................... 21 Typical Performance Characteristics ............................................. 9 Chain Mode with Busy Indicator............................................. 22 Theory of Operation ...................................................................... 12 Application Hints ........................................................................... 23 Circuit Information.................................................................... 12 Layout .......................................................................................... 23 Converter Operation.................................................................. 12 Evaluating AD7693 Performance............................................. 23 Typical Connection Diagram ................................................... 13 Outline Dimensions....................................................................... 24 Analog Inputs.............................................................................. 14 Ordering Guide .......................................................................... 24 REVISION HISTORY 6/11—Rev. 0 to Rev. A Changes to Resolution Parameter and Common-Mode Input Range Parameter in Table 2............................................................. 3 Changes to Figure 6 and Table 6..................................................... 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 12/06—Revision 0: Initial Version Rev. A | Page 2 of 24 AD7693 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN+ − (IN−) −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V /2 – 0.1 V/2 V /2 + 0.1 V REF REF REF Analog Input CMRR fIN = 250 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA 1 Input Impedance THROUGHPUT Conversion Rate 0 500 kSPS Transient Response Full-scale step 400 ns ACCURACY No Missing Codes 16 Bits 2 Integral Linearity Error −0.5 ±0.25 +0.5 LSB Differential Linearity Error −0.5 ±0.25 +0.5 LSB Transition Noise REF = VDD = 5 V 0.35 LSB 3 Gain Error −20 ±0.5 +20 LSB Gain Error Temperature Drift ±0.3 ppm/°C 3 Zero Error −5 ±0.5 +5 LSB Zero Temperature Drift ±0.3 ppm/°C Power Supply Sensitivity ±1 ppm VDD = 5 V ± 5% 4 AC ACCURACY 5 Dynamic Range 96 96.5 dB Signal-to-Noise f = 1 kHz 95.5 96 dB IN fIN = 10 kHz 95.5 dB fIN = 100 kHz 93 dB f = 1 kHz, V = 2.5 V 93 dB IN REF Signal-to-(Noise + Distortion) f = 1 kHz 95.5 96 dB IN f = 10 kHz 95.5 dB IN fIN = 100 kHz 90 dB Total Harmonic Distortion fIN = 1 kHz −120 −108 dB fIN = 10 kHz −113 dB f = 100 kHz −92 dB IN Spurious-Free Dynamic Range f = 1 kHz 120 dB IN f = 10 kHz 114 dB IN fIN = 100 kHz 93.5 dB 6 Intermodulation Distortion 115 dB 1 See the Analog Inputs section. 2 LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV. 3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 With V = 5 V, unless otherwise noted. REF 5 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 6 f = 21.4 kHz and f = 18.9 kHz, with each tone at −7 dB below full scale. IN1 IN2 Rev. A | Page 3 of 24 AD7693 VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 3. Parameter Conditions/Comments Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 500 kSPS, REF = 5 V 100 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 9 MHz Aperture Delay VDD = 5V 2.5 ns DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 16 bits, twos complement 1 Pipeline Delay V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 4. 5 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 2, 3 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation 100 SPS throughput 5 μW 100 kSPS throughput 4 mW 500 kSPS throughput 18 21.5 mW Energy per Conversion 40 nJ 4 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 Conversion results available immediately after completed conversion. 2 With all digital inputs forced to VIO or GND as required. 3 During acquisition phase. 4 Contact an Analog Devices sales representative for the extended temperature range. Rev. A | Page 4 of 24 AD7693 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 0.5 1.6 μs CONV Acquisition Time t 400 ns ACQ Time Between Conversions tCYC 2.0 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid t 4 ns HSDO SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns t CNV or SDI Low to SDO D15 MSB Valid (CS Mode) EN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) t 15 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 10 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 4 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t DSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 1 See Figure 3 and Figure 4 for load conditions. Rev. A | Page 5 of 24 AD7693 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs rating only; functional operation of the device at these or any 1 1 IN+, IN− GND − 0.3 V to VDD + 0.3 V other conditions above those indicated in the operational or ±130 mA section of this specification is not implied. Exposure to absolute REF GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V ESD CAUTION Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance (MSOP-10) 200°C/W JA θ Thermal Impedance (MSOP-10) 44°C/W JC Lead Temperature Range JEDEC J-STD-20 1 See the Analog Inputs section. 500µA I OL TO SDO 1.4V C L 50pF 500µA I OH Figure 3. Load Circuit for Digital Interface Timing 70% VIO 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V 2 2 0.8V OR 0.5V 0.8V OR 0.5V 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Rev. A | Page 6 of 24 06394-003 06394-004 AD7693 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9SDI AD7693 IN+ 3 8SCK TOP VIEW IN– 4 (Not to Scale) 7SDO GND 5 6CNV REF 1 10 VIO VDD 2 9 SDI AD7693 NOTES IN+ 3 8 SCK TOP VIEW 1. THE EXPOSED PAD IS CONNECTED (Not to Scale) TO GND. THIS CONNECTION IS NOT IN– 4 7 SDO REQUIRED TO MEET THE ELECTRICAL GND 5 6 CNV PERFORMANCES. Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain or CS mode. In chain mode, the data should be read when CNV is high. In CS mode, the SDO pin is enabled when CNV is low. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD Exposed Pad. The exposed pad is connected to GND. This connection is not required to meet the electrical performances. The exposed pad is only on the 10-Lead QFN (LFCSP). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 24 06394-005 05793-006 AD7693 TERMINOLOGY Transient Response Least Significant Bit (LSB) Transient response is the time required for the ADC to accurately The LSB is the smallest increment that can be represented by a acquire its input after a full-scale step function is applied. converter. For a differential analog-to-digital converter with N bits of resolution, the LSB expressed in volts is Dynamic Range Dynamic range is the ratio of the rms value of the full scale to 2V REF LSB (V)= the total rms noise measured with the inputs shorted together. N 2 The value for dynamic range is expressed in decibels. Integral Nonlinearity Error (INL) Signal-to-Noise Ratio (SNR) INL refers to the deviation of each individual code from a line SNR is the ratio of the rms value of the actual input signal to the drawn from negative full scale through positive full scale. The rms sum of all other spectral components below the Nyquist point used as negative full scale occurs ½ LSB before the first frequency, excluding harmonics and dc. The value for SNR is code transition. Positive full scale is defined as a level 1½ LSB expressed in decibels. beyond the last code transition. The deviation is measured from Signal-to-(Noise + Distortion) Ratio (SINAD) the middle of each code to the true straight line (see Figure 26). SINAD is the ratio of the rms value of the actual input signal to Differential Nonlinearity Error (DNL) the rms sum of all other spectral components below the Nyquist In an ideal ADC, code transitions are 1 LSB apart. DNL is the frequency, including harmonics but excluding dc. The value for maximum deviation from this ideal value. It is often specified in SINAD is expressed in decibels. terms of resolution for which no missing codes are guaranteed. Total Harmonic Distortion (THD) Zero Error THD is the ratio of the rms sum of the first five harmonic Zero error is the difference between the ideal midscale voltage, components to the rms value of a full-scale input signal and is that is, 0 V, from the actual voltage producing the midscale expressed in decibels. output code, that is, 0 LSB. Spurious-Free Dynamic Range (SFDR) Gain Error SFDR is the difference, in decibels, between the rms amplitude The first transition (from 100 ... 00 to 100 ... 01) should occur at of the input signal and the peak spurious signal. a level ½ LSB above nominal negative full scale (−4.999847 V Effective Number of Bits (ENOB) for the ±5 V range). The last transition (from 011 … 10 to ENOB is a measurement of the resolution with a sine wave 011 … 11) should occur for an analog voltage 1½ LSB below the input. It is related to SINAD by the following formula: nominal full scale (+4.999771 V for the ±5 V range.) The gain error is the deviation of the difference between the actual level ENOB = (SINAD − 1.76)/6.02 dB of the last transition and the actual level of the first transition and is expressed in bits. from the difference between the ideal levels. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Rev. A | Page 8 of 24 AD7693 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = 25C. 1.0 1.0 POSITIVE DNL = +0.22LSB POSITIVE INL = +0.17LSB NEGATIVE DNL = –0.22LSB NEGATIVE INL = –0.17LSB 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 65536 0 16384 32768 49152 65536 16384 32768 49152 CODE CODE Figure 10. Differential Nonlinearity vs. Code Figure 7. Integral Nonlinearity vs. Code 300000 160000 258774 135054 140000 250000 126066 120000 200000 100000 150000 80000 60000 100000 40000 50000 20000 1905 441 00 0 0 00 0 00 0 0 67 8 9 ABC 7 89 A B C D CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Transition 0 100 –80 f = 500kSPS S f = 0.95kHz IN 99 –85 –20 SNR = 96.4dB THD = –121dB –90 98 –40 SFDR = 124dB SINAD = 96.4dB –95 97 –60 SNR 96 –100 –80 –105 95 –100 –110 94 –120 93 –115 –140 –120 92 THD –160 –125 91 –180 90 –130 02 20 40 60 80 100 120 140 160 18000 –10 –8 –6 –4 –2 0 INPUT LEVEL (dB) FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. SNR, THD vs. Input Level Rev. A | Page 9 of 24 COUNTS INL (LSB) AMPLITUDE (dB of Full Scale) 06394-009 06394-008 06394-007 SNR (dB) DNL (LSB) COUNTS THD (dB) 06394-011 06394-010 06394-012 AD7693 100 20.0 –80 130 99 19.5 –85 125 SFDR –90 120 98 19.0 97 18.5 –95 115 18.0 –100 110 96 SNR, SINAD –105 105 95 17.5 –110 94 17.0 100 16.5 –115 95 93 THD –120 90 92 16.0 ENOB –125 15.5 85 91 15.0 –130 80 90 2.0 2.53.0 3.54.04.5 5.0 5.5 2.0 2.53.0 3.54.0 4.55.0 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage –100 130 100 20.0 V = 5V DD 19.5 99 –105 125 98 19.0 SFDR 97 18.5 SNR, SINAD –110 120 18.0 96 17.5 –115 115 95 17.0 94 THD 110 –120 16.5 93 16.0 92 ENOB 105 –125 15.5 91 15.0 100 –130 90 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. SNR, SINAD, and ENOB vs. Temperature Figure 17. THD, SFDR vs. Temperature 100 –80 98 –85 V = –10dBFS V = –1dBFS IN IN 96 –90 94 –95 92 –100 V = –1dBFS IN 90 –105 V = –10dBFS IN 88 –110 86 –115 84 –120 82 –125 80 –130 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. SINAD vs. Frequency Figure 18. THD vs. Frequency Rev. A | Page 10 of 24 SNR, SINAD (dB) SNR, SINAD (dB) SNR, SINAD (dB) 06394-015 ENOB (Bits) ENOB (Bits) 06394-014 06394-013 THD (dB) THD (dB) THD (dB) SFDR (dB) SFDR (dB) 06394-018 06394-017 06394-016 AD7693 1000 1000 f = 100kSPS S 800 800 VDD 600 600 400 400 200 200 VIO VDD + VIO 0 0 4.50 4.75 5.00 5.25 5.50 –55 –35 –15 5 25 45 65 85 105 125 SUPPLY (V) TEMPERATURE (°C) Figure 19. Operating Currents vs. Supply Figure 22. Power-Down Currents vs. Temperature 1000 1.0 f = 100kSPS S VDD 800 0.5 600 ZERO ERROR 0 GAIN ERROR 400 –0.5 200 VIO 0 –1.0 –55 –35 –15 –5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. Operating Currents vs. Temperature Figure 23. Zero Error and Gain Error vs. Temperature 10k 25 1k 20 VDD 100 15 VDD = 5V, 85°C 10 VIO 10 1 VDD = 5V, 25°C 5 0.1 0.01 0 10 100 1k 10k 100k 1M 0 2040 6080 100 120 SDO CAPACITIVE LOAD (pF) SAMPLING RATE (SPS) Figure 24. t Delay vs. Capacitance Load and Supply Figure 21. Operating Currents vs. Sample Rate DSDO Rev. A | Page 11 of 24 OPERATING CURRENT (µA) OPERATING CURRENT (µA) OPERATING CURRENT (µA) 06394-021 06394-020 06394-019 ZERO, GAIN ERROR (LSB) POWER-DOWN CURRENT (nA) t DELAY (ns) DSDO 06394-022 06394-031 06394-023 AD7693 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV IN– Figure 25. ADC Simplified Schematic During the acquisition phase, terminals of the array tied to the CIRCUIT INFORMATION comparator’s input are connected to GND via SW+ and SW−. The AD7693 is a fast, low power, single-supply, precise, 16-bit All independent switches are connected to the analog inputs. ADC using a successive approximation architecture. Thus, the capacitor arrays are used as sampling capacitors and The AD7693 is capable of converting 500,000 samples per acquire the analog signal on the IN+ and IN− inputs. When the second (500 kSPS) and powers down between conversions. acquisition phase is complete and the CNV input goes high, a When operating at 1 kSPS, for example, it consumes 40 μW conversion phase is initiated. When the conversion phase typically, ideal for battery-powered applications. begins, SW+ and SW− are opened first. The two capacitor The AD7693 provides the user with an on-chip track-and-hold arrays are then disconnected from the inputs and connected to and does not exhibit pipeline delay or latency, making it ideal the GND input. Therefore, the differential voltage between the for multiple multiplexed channel applications. IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to The AD7693 is specified from 4.5 V to 5.5 V and can be become unbalanced. By switching each element of the capacitor interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines array between GND and REF, the comparator input varies by space savings and allows flexible configurations. binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/32,768). The control logic toggles these switches, starting with the MSB, It is pin-for-pin compatible with the 16-bit AD7687 and to bring the comparator back into a balanced condition. After AD7688 and with the 18-bit AD7690 and AD7691. the completion of this process, the part returns to the CONVERTER OPERATION acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. The AD7693 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified Because the AD7693 has an on-board conversion clock, the schematic of the ADC. The capacitive DAC consists of two serial clock, SCK, is not required for the conversion process. identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. Rev. A | Page 12 of 24 06394-024 AD7693 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Analog Input Digital Output The ideal transfer characteristic for the AD7693 is shown in Description V = 5 V Code (Hex) REF Figure 26 and Table 7. 1 FSR − 1 LSB +4.999847 V 0x7FFF Midscale + 1 LSB +152.6 μV 0x0001 Midscale 0 V 0x0000 Midscale − 1 LSB −152.6 μV 0xFFFF 011...111 −FSR + 1 LSB −4.999847 V 0x8001 011...110 2 −FSR −5 V 0x8000 011...101 1 This is also the code for an overranged analog input (V − V above V − V ). IN+ IN− REF GND 2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND). TYPICAL CONNECTION DIAGRAM 100...010 Figure 27 shows an example of the recommended connection 100...001 diagram for the AD7693 when multiple supplies are available. 100...000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function 1 V+ REF 5V 2 10µF 100nF V+ 1.8V TO VDD 100nF 33Ω REF VDD VIO 0TO V REF SDI IN+ 2.7nF 3 ADA4841-2 SCK V– 5 AD7693 3- OR 4-WIRE INTERFACE SDO 4 V+ IN– CNV GND 33Ω V TO 0 REF 2.7nF 3 ADA4841-2 V– 4 1 SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3 SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE. Figure 27. Typical Application Diagram with Multiple Supplies Rev. A | Page 13 of 24 ADC CODE (TWOS COMPLEMENT) 06394-025 06394-026 AD7693 harmonic distortion (THD). The dc performances are less ANALOG INPUTS sensitive to the input impedance. The maximum source Figure 28 shows an equivalent circuit of the input structure of impedance depends on the amount of THD that can be the AD7693. tolerated. The THD degrades as a function of the source The two diodes, D1 and D2, provide ESD protection for the impedance and the maximum input frequency. analog inputs, IN+ and IN−. Care must be taken to ensure that –80 the analog input signal does not exceed the supply rails by more VDD = 5V –85 than 0.3 V because this causes the diodes to become forward 250Ω –90 biased and to start conducting current. These diodes can handle –95 a forward-biased current of 130 mA maximum. For instance, 100Ω these conditions could eventually occur when the input buffer’s –100 50Ω (U1) supplies are different from VDD. In such a case, for –105 example, an input buffer with a short circuit, the current 33Ω –110 limitation can be used to protect the part. –115 VDD –120 D1 C IN R IN+ IN –125 OR IN– C –130 PIN D2 0 1020304050 6070 8090 GND FREQUENCY (kHz) Figure 30. THD vs. Analog Input Frequency and Source Resistance Figure 28. Equivalent Analog Input Circuit DRIVER AMPLIFIER CHOICE The analog input structure allows the sampling of the true Although the AD7693 is easy to drive, the driver amplifier must differential signal between IN+ and IN−. By using these meet the following requirements: differential inputs, signals common to both inputs are rejected. 100 • The noise generated by the driver amplifier needs to be VREF = 5V kept as low as possible to preserve the SNR and transition 95 noise performance of the AD7693. The noise coming from 90 the driver is filtered by the AD7693 analog input circuit’s 85 1-pole, low-pass filter made by R and C or by the IN IN 80 external filter, if one is used. Because the typical noise of 75 the AD7693 is 56 μV rms, the SNR degradation due to the amplifier is 70 65 ⎛ ⎞ ⎜ ⎟ 60 56 ⎜ ⎟ SNR = 20 log LOSS ⎜ ⎟ 55 π π 2 2 2 ⎜ ⎟ 56 + f (Ne ) + f (Ne ) ⎜ −3 dB N −3 dB N ⎟ 2 2 ⎝ ⎠ 50 1 10 100 1000 10000 where: FREQUENCY (kHz) f is the input bandwidth in megahertz of the AD7693 −3 dB Figure 29. Analog Input CMRR vs. Frequency (9 MHz) or the cutoff frequency of the input filter, if During the acquisition phase, the impedance of the analog one is used. inputs (IN+ and IN−) can be modeled as a parallel combination N is the noise gain of the amplifier (for example, 1 in of the capacitor, C , and the network formed by the series PIN buffer configuration). connection of RIN and CIN. CPIN is primarily the pin capacitance. eN is the equivalent input noise voltage of the op amp, RIN is typically 600 Ω and is a lumped component made up of in nV/√Hz. serial resistors and the on resistance of the switches. CIN is • For ac applications, the driver should have a THD typically 30 pF and is mainly the ADC sampling capacitor. performance commensurate with the AD7693. During the conversion phase, where the switches are opened, • For multichannel multiplexed applications, the driver the input impedance is limited to C . R and C make a 1-pole, PIN IN IN amplifier and the AD7693 analog input circuit must settle low-pass filter that reduces undesirable aliasing effects and for a full-scale step onto the capacitor array at a 16-bit level limits the noise. (0.0015%, 15 ppm). In the amplifier’s data sheet, settling at When the source impedance of the driving circuit is low, the 0.1% to 0.01% is more commonly specified. This could AD7693 can be driven directly. Large source impedances differ significantly from the settling time at a 16-bit level significantly affect the ac performance, especially total and should be verified prior to driver selection. Rev. A | Page 14 of 24 CMRR (dB) 06394-027 06394-028 THD (dB) 06394-047 AD7693 Table 8. Recommended Driver Amplifiers If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, Amplifier Typical Application 1206 size) ceramic chip capacitor is appropriate for optimum ADA4941-1 Very low noise, low power single to differential performance using low temperature drift ADR43x and ADR44x ADA4841-x Very low noise, small, and low power references. AD8655 5 V single supply, low noise AD8021 Very low noise and high frequency If desired, smaller reference decoupling capacitor values down AD8022 Low noise and high frequency to 2.2 μF can be used with a minimal impact on performance, OP184 Low power, low noise, and low frequency especially DNL. AD8605, AD8615 5 V single supply, low power Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the SINGLE-ENDED-TO-DIFFERENTIAL DRIVER REF and GND pins. For applications using a single-ended analog signal, either POWER SUPPLY bipolar or unipolar, the ADA4941-1 single-ended-to-differential The AD7693 uses two power supply pins: a core supply, VDD, driver allows for a differential input into the part. The and a digital input/output interface supply, VIO. VIO allows schematic is shown in Figure 31. direct interface with any logic between 1.8 V and VDD. To R1 and R2 set the attenuation ratio between the input range and reduce the supplies needed, the VIO and VDD pins can be tied the ADC range (VREF). R1, R2, and CF are chosen depending on together. The AD7693 is independent of power supply sequencing the desired input resistance, signal bandwidth, antialiasing and between VIO and VDD. Additionally, it is very insensitive to noise contribution. For example, for the ±10 V range with a 4 kΩ power supply variations over a wide frequency range, as shown impedance, R2 = 1 kΩ and R1 = 4 kΩ. in Figure 32. R3 and R4 set the common mode on the IN− input, and R5 and 100 VREF = 5V R6 set the common mode on the IN+ input of the ADC. The 95 common mode should be set close to VREF/2; however, if single 90 supply is desired, it can be set slightly above VREF/2 to provide 85 some headroom for the ADA4941-1 output stage. For example, 80 for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. 75 R5 R6 70 65 R3 R4 +5V REF 60 10µF +5.2V +5.2V 55 100nF 50 REF VDD 33Ω 1 10 100 1000 10000 IN+ 2.7nF FREQUENCY (kHz) AD7693 2.7nF Figure 32. PSRR vs. Frequency 100nF IN– 33Ω GND The AD7693 powers down automatically at the end of each ADA4941 conversion phase; therefore, the operating currents and power scale linearly with the sampling rate (refer to Figure 21). This makes the part ideal for low sampling rates (even of a few hertz) ±10V, ±5V, ... R1 R2 and low battery-powered applications. C F Figure 31. Single-Ended-to-Differential Driver Circuit VOLTAGE REFERENCE INPUT The AD7693 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. Rev. A | Page 15 of 24 06394-029 PSRR (dB) 06394-030 AD7693 prior to reading back the data. This configuration is described SUPPLYING THE ADC FROM THE REFERENCE in the Chain Mode with Busy Indicator section. For simplified applications, the AD7693, with its low operating The primary limitations of 3-wire chain mode are that all ADCs current, can be supplied directly using the reference circuit are simultaneously sampled and the user cannot randomly shown in Figure 33. The reference line can be driven by select an individual ADC for readback. This can be overcome • The system power supply directly only by increasing the number of wires (for example, one chip • A reference voltage with enough current output capability, select wire per ADC). To operate with this increased such as the ADR43x CS CS functionality, the part must be used in Mode. mode is separated into two categories (3-wire and 4-wire) whereby • A reference buffer, such as the AD8031, which can also CS flexibility is traded off for wiring complexity. In 4-wire filter the system power supply, as shown in Figure 33. mode, the user has independent control over the sampling 5V operation (via CNV) and the chip select operation (via SDI) for 5V each ADC. In CS 3-wire mode, SDI is unused (tied high) and 10Ω 5V 10kΩ CNV is used to both sample the input and chip select the part 10µF 1µF AD8031 1µF when needed. As with chain mode, the parts can optionally be 1 configured to provide a busy indication, but at the expense of one additional SCK when reading back the data. So in total REF VDD VIO CS there are four modes: 3-wire and 4-wire modes, each with AD7693 busy and without busy. 1 OPTIONAL REFERENCE BUFFER AND FILTER. There is no elaborate writing of configuration words into the Figure 33. Example of an Application Circuit part via the SDI pin. The mode in which the part operates is defined by ensuring a specific relationship between the CNV, DIGITAL INTERFACE CS SDI, and SCK inputs at key times. To select mode, ensure Generally, a user is interested in either minimizing the wiring that SDI is high at the rising edge of CNV; otherwise, chain complexity of a multichannel ADC system or communicating CS mode will be selected. Once in mode, selecting the part for with the parts via a specific interface standard. Although the readback before the conversion is complete (by bringing either ADC has only four digital pins (CNV, SCK, SDI, and SDO), it SDI or CNV low) instructs the part to provide a busy indicator, offers a significantly flexible serial interface, including a high-to-low impedance transition on SDO, to tell the user compatibility with SPI, QSPI, digital hosts, and DSPs (such as when the conversion has finished. If the part is selected after the Blackfin® ADSP-BF53x or ADSP-219x). By configuring the conversion has finished, SDO outputs the MSB when it is ADC into one of six modes, virtually any serial interface selected. In chain mode, the busy indicator, a low-to-high scenario can be accommodated. transition on SDO, is selected based on the state of SCK at the For wiring efficiency, the best way to configure a multichannel, rising edge of CNV. If SCK is high, the busy indicator is simultaneous-sampling system is to use the 3-wire chain mode. enabled; otherwise, the busy indicator is not enabled. This system is easily created by cascading multiple (M) ADCs The following sections provide specifics for each of the different into a shift register structure. The CNV and CLK pins are serial interface modes. Note that in the following sections, the common to all ADCs, and the SDO of one part feeds the SDI of timing diagrams indicate digital activity (SCK, CNV) during the next part in the chain. The 3-wire interface is simply the conversion. However, due to the possibility of performance CNV, SCK, and SDO of the last ADC in the chain. For a system degradation, digital activity should only occur during the first containing M- and N-bit converters, the user needs to provide quarter of the conversion phase because the AD7693 provides M × N SCK transitions to read back all of the data. This 3-wire error correction circuitry that can correct for an incorrect bit interface is also ideally suited for isolated applications. during this time. The user should initiate the busy indicator if Additional flexibility is provided by optionally configuring the desired during this time. It is also possible to corrupt the sample ADCs to provide a busy indication. Without a busy indication, by having SCK or SDI transitions near the sampling instant. the user must externally timeout the maximum ADC Therefore, it is recommended to keep the digital pins quiet for conversion time before commencing readback. This approximately 30 ns before and 10 ns after the rising edge of configuration is described in the Chain Mode Without Busy CNV. The exception is when the device is in the chain mode Indicator section. With the busy indication enabled, external with busy configuration, where SDI is tied to CNV, because this timer circuits are not required because the SDO at the end of scenario does not yield a corrupted sample. To this extent, it is the chain provides a low-to-high transition (that is, a start bit) recommended, to use a discontinuous SCK whenever possible to when all of the chain members have completed their avoid any potential performance degradation. conversions and are ready to transmit data. However, one additional SCK is required to flush the SDO busy indication Rev. A | Page 16 of 24 06394-032 AD7693 returned high before the minimum conversion time elapses and CS MODE, 3-WIRE WITHOUT BUSY INDICATOR then held high for the maximum possible conversion time to This mode is usually used when a single AD7693 is connected avoid the generation of the busy signal indicator. When the to an SPI-compatible digital host. The connection diagram is conversion is complete, the AD7693 enters the acquisition shown in Figure 34, and the corresponding timing is given in phase and powers down. When CNV goes low, the MSB is Figure 35. output onto SDO. The remaining data bits are clocked by With SDI tied to VIO, a rising edge on CNV initiates a subsequent SCK falling edges. The data is valid on both SCK conversion, selects the mode, and forces SDO to high CS edges. Although the rising edge can be used to capture the data, impedance. Once a conversion is initiated, it continues until a digital host using the SCK falling edge will allow a faster completion irrespective of the state of CNV. This could be reading rate, provided it has an acceptable hold time. After the th useful, for instance, to bring CNV low to select other SPI 16 SCK falling edge or when CNV goes high (whichever devices, such as analog multiplexers; however, CNV must be occurs first), SDO returns to high impedance. CONVERT DIGITAL HOST CNV VIO SDI SDO DATA IN AD7693 SCK CLK Figure 34. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 14 15 16 t t HSDO SCKH t t t DSDO EN DIS SDO D15 D14 D13 D1 D0 CS Figure 35. Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. A | Page 17 of 24 06394-033 06394-034 AD7693 impedance to low impedance. With a pull-up on the SDO line, CS MODE, 3-WIRE WITH BUSY INDICATOR this transition can be used as an interrupt signal to initiate the This mode is usually used when a single AD7693 is connected data reading controlled by the digital host. The AD7693 then to an SPI-compatible digital host having an interrupt input. enters the acquisition phase and powers down. The data bits are The connection diagram is shown in Figure 36, and the clocked out, MSB first, by subsequent SCK falling edges. The corresponding timing is given in Figure 37. data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling With SDI tied to VIO, a rising edge on CNV initiates a edge will allow a faster reading rate, provided it has an CS conversion, selects the mode, and forces SDO to high th acceptable hold time. After the optional 17 SCK falling edge or impedance. SDO is maintained in high impedance until the when CNV goes high (whichever occurs first), SDO returns to completion of the conversion irrespective of the state of CNV. high impedance. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV If multiple AD7693s are selected at the same time, the SDO must be returned low before the minimum conversion time output pin handles this contention without damage or induced elapses and then held low for the maximum possible conversion latch-up. Meanwhile, it is recommended to keep this contention time to guarantee the generation of the busy signal indicator. as short as possible to limit extra power dissipation. When the conversion is complete, SDO goes from high CONVERT VIO DIGITAL HOST CNV VIO SDI SDO DATA IN AD7693 SCK IRQ CLK Figure 36. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 12 3 15 16 17 t t HSDO SCKH t t DSDO DIS SDO D15 D14 D1 D0 CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Figure 37. Rev. A | Page 18 of 24 06394-035 06394-036 AD7693 time elapses and then held high for the maximum possible CS MODE, 4-WIRE WITHOUT BUSY INDICATOR conversion time to avoid the generation of the busy signal This mode is usually used when multiple AD7693s are indicator. When the conversion is complete, the AD7693 enters connected to an SPI-compatible digital host. the acquisition phase and powers down. Each ADC result can A connection diagram example using two AD7693s is shown in be read by bringing its SDI input low, which consequently Figure 38, and the corresponding timing is given in Figure 39. outputs the MSB onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK With SDI high, a rising edge on CNV initiates a conversion, edges. Although the rising edge can be used to capture the data, selects the mode, and forces SDO to high impedance. In this CS a digital host using the SCK falling edge will allow a faster mode, CNV must be held high during the conversion phase and reading rate, provided it has an acceptable hold time. After the the subsequent data readback. (If SDI and CNV are low, SDO is th 16 SCK falling edge or when SDI goes high (whichever occurs driven low.) Prior to the minimum conversion time, SDI can be first), SDO returns to high impedance and another AD7693 can used to select other SPI devices, such as analog multiplexers, be read. but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV CNV DIGITAL HOST SDI SDO SDI SDO AD7693 AD7693 SCK SCK DATA IN CLK CS Figure 38. Mode, 4-Wire Without Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 14 15 16 17 18 30 31 32 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 D16 D15 D1 D0 CS Figure 39. Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. A | Page 19 of 24 06394-037 06394-038 AD7693 but SDI must be returned low before the minimum conversion CS MODE, 4-WIRE WITH BUSY INDICATOR time elapses and then held low for the maximum possible This mode is usually used when a single AD7693 is connected conversion time to guarantee the generation of the busy signal to an SPI-compatible digital host with an interrupt input and it indicator. When the conversion is complete, SDO goes from is desired to keep CNV, which is used to sample the analog high impedance to low impedance. With a pull-up on the SDO input, independent of the signal used to select the data reading. line, this transition can be used as an interrupt signal to initiate This requirement is particularly important in applications the data readback controlled by the digital host. The AD7693 where low jitter on CNV is desired. then enters the acquisition phase and powers down. The data The connection diagram is shown in Figure 40, and the bits are clocked out, MSB first, by subsequent SCK falling edges. corresponding timing is given in Figure 41. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK With SDI high, a rising edge on CNV initiates a conversion, falling edge will allow a faster reading rate, provided it has an selects the CS mode, and forces SDO to high impedance. In this th acceptable hold time. After the optional 17 SCK falling edge, mode, CNV must be held high during the conversion phase and or when SDI goes high (whichever occurs first), SDO returns to the subsequent data readback. (If SDI and CNV are low, SDO is high impedance. driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, CS1 CONVERT VIO DIGITAL HOST CNV DATA IN SDI AD7693 SDO SCK IRQ CLK CS Figure 40. Mode, 4-Wire with Busy Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 15 16 17 t t HSDO SCKH t t DSDO DIS t EN D15 D14 D1 D0 SDO CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Figure 41. Rev. A | Page 20 of 24 06394-039 06394-040 AD7693 readback. When the conversion is complete, the MSB is output CHAIN MODE WITHOUT BUSY INDICATOR onto SDO and the AD7693 enters the acquisition phase and This mode can be used to daisy-chain multiple AD7693s on powers down. The remaining data bits stored in the internal a 3-wire serial interface. This feature is useful for reducing shift register are clocked by subsequent SCK falling edges. For component count and wiring connections, for example, in each ADC, SDI feeds the input of the internal shift register and isolated multiconverter applications or for systems with a is clocked by the SCK falling edge. Each ADC in the chain limited interfacing capacity. Data readback is analogous to outputs its data MSB first, and 16 × N clocks are required to clocking a shift register. read back the N ADCs. The data is valid on both SCK edges. A connection diagram example using two AD7693s is shown in Although the rising edge can be used to capture the data, a Figure 42, and the corresponding timing is given in Figure 43. digital host using the SCK falling edge will allow a faster reading rate and consequently more AD7693s in the chain, When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain provided the digital host has an acceptable hold time. The mode, and disables the busy indicator. In this mode, CNV is maximum conversion rate can be reduced due to the total held high during the conversion phase and the subsequent data readback time. CONVERT CNV CNV DIGITAL HOST AD7693 AD7693 SDI SDO SDI SDO DATA IN A B SCK SCK CLK Figure 42. Chain Mode Without Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 14 15 16 17 18 30 31 32 t t t HSCKCNV SSDISCK SCKH t t HSDISCK EN D 15 D 14 D 13 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 SDO B B B B B A A A A B Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing Rev. A | Page 21 of 24 06394-041 06394-042 AD7693 completed their conversions, the SDO pin of the ADC closest to CHAIN MODE WITH BUSY INDICATOR the digital host (see the AD7693 ADC labeled C in Figure 44) is This mode can also be used to daisy-chain multiple AD7693s driven high. This transition on SDO can be used as a busy on a 3-wire serial interface while providing a busy indicator. indicator to trigger the data readback controlled by the digital This feature is useful for reducing component count and wiring host. The AD7693 then enters the acquisition phase and powers connections, for example, in isolated multiconverter applications down. The data bits stored in the internal shift register are or for systems with a limited interfacing capacity. Data readback clocked out, MSB first, by subsequent SCK falling edges. For is analogous to clocking a shift register. each ADC, SDI feeds the input of the internal shift register and A connection diagram example using three AD7693s is shown is clocked by the SCK falling edge. Each ADC in the chain in Figure 44, and the corresponding timing is given in Figure 45. outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the capture the data, a digital host using the SCK falling edge allows chain mode, and enables the busy indicator feature. In this a faster reading rate and consequently more AD7693s in the mode, CNV is held high during the conversion phase and the chain, provided the digital host has an acceptable hold time. subsequent data readback. When all ADCs in the chain have CONVERT CNV CNV CNV DIGITAL HOST AD7693 AD7693 AD7693 SDI SDO SDI SDO SDI SDO DATA IN A B C SCK SCK SCK IRQ CLK Figure 44. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 415 16 17 18 19 31 32 33 34 35 47 48 49 t t HSCKCNV SSDISCK t SCKL t t DSDOSDI t HSDISCK EN SDO = SDI A B D 15 D 14 D 13 D 1 D 0 A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI B C D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 B B B B B A A A A t t DSDOSDI DSDOSDI SDO D 15 D 14 D 13 D1D0D D 15 D 14 D1D0D 15 14 D1D 0 C C C C C C B B B B A A A A Figure 45. Chain Mode with Busy Indicator Serial Interface Timing Rev. A | Page 22 of 24 06394-043 06394-044 AD7693 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7693 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7693, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7693 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7693s. Figure 46. Example Layout of the AD7693 (Top Layer) The AD7693 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7693 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7693 and connected using short, wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of a layout following these rules is shown in Figure 46 and Figure 47. EVALUATING AD7693 PERFORMANCE Other recommended layouts for the AD7693 are outlined Figure 47. Example Layout of the AD7693 (Bottom Layer) in the documentation of the evaluation board for the AD7693 (EVAL-AD7693CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. A | Page 23 of 24 06394-045 06394-046 AD7693 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 48.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE 1 Model Notes Temperature Range Package Description Package Option Branding Ordering Quantity AD7693BCPZRL −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4Y Reel, 5,000 AD7693BCPZRL7 −40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4Y Reel, 1,500 AD7693BRMZ −40°C to +85°C 10-Lead MSOP RM-10 C4Y Tube, 50 AD7693BRMZRL7 −40°C to +85°C 10-Lead MSOP RM-10 C4Y Reel, 1,000 2 EVAL-AD7693CBZ Evaluation Board 3 EVAL-CONTROL BRD2 Controller Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05793-0-6/11(A) Rev. A | Page 24 of 24 N 1 PI I IND CATOR (R 0.15) 091709-A 121009-A