ANALOG DEVICES AD7691

18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN Data Sheet AD7691 FEATURES APPLICATION DIAGRAM +0.5V TO VDD +2.5V TO +5V 18-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.75 LSB typical, ±1.5 LSB maximum (±6 ppm of FSR) VIO +1.8V TO VDD Dynamic range: 102 dB typical @ 250 kSPS REF VDD IN+ SDI Oversampled dynamic range: 125 dB @1 kSPS 3- OR 4-WIRE SCK ±10V, ±5V, ... INTERFACE SDO Noise-free code resolution: 20 bits @ 1 kSPS (SPI, DAISY CHAIN, CS) IN– GND CNV Effective resolution: 22.7 bits @ 1 kSPS ADA4941 SINAD: 101.5 dB typical @ 1 kHz AD7691 THD: −125 dB typical @ 1 kHz Figure 2. True differential analog input range: ±V REF 0 V to V with V up to VDD on both inputs REF REF Table 1. MSOP, QFN (LFCSP)/SOT-23 No pipeline delay 14-/16-/18-Bit PulSAR® ADC Single-supply 2.3 V to 5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface 100 250 400 kSPS to ≥1000 ADC Type kSPS kSPS 500 kSPS kSPS Driver Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible 18-Bit True AD7691 AD7690 AD7982 ADA4941-1 Ability to daisy-chain multiple ADCs Differential AD7984 ADA4841-x Optional busy indicator feature 16-Bit True AD7684 AD7687 AD7688 ADA4941-1 Power dissipation Differential AD7693 ADA4841-x 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4841-x Pseudo AD7683 AD7694 1.4 μW @ 2.5 V/100 SPS Differential Standby current: 1 nA 14-Bit AD7940 AD7942 AD7946 ADA4841-1 10-lead packages: MSOP (MSOP-8 size) and Pseudo 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Differential Pin-for-pin compatible with the18-bit AD7690 and 16-bit AD7693, AD7688, and AD7687 GENERAL DESCRIPTION APPLICATIONS The AD7691 is an 18-bit, charge redistribution, successive Battery-powered equipment approximation, analog-to-digital converter (ADC) that operates Data acquisitions from a single power supply, VDD, between 2.3 V and 5 V. It Seismic data acquisition systems contains a low power, high speed, 18-bit sampling ADC with no Instrumentation missing codes, an internal conversion clock, and a versatile Medical instruments serial interface port. On the CNV rising edge, it samples the 1.5 voltage difference between the IN+ and IN− pins. The voltages POSITIVE INL = 0.43LSB NEGATIVE INL = –0.62LSB on these pins swing in opposite phases between 0 V and REF. 1.0 The reference voltage, REF, is applied externally and can be set up to the supply voltage. 0.5 The part’s power scales linearly with throughput. The SPI-compatible serial interface also features the ability, 0 using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. It is compatible –0.5 with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply. –1.0 The AD7691 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. –1.5 0 65536 131072 196608 262144 CODE Figure 1. Integral Nonlinearity vs. Code, 5 V Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 06146-025 06146-001 AD7691 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Single-to-Differential Driver .................................................... 16 Application Diagram........................................................................ 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply............................................................................... 17 Revision History ............................................................................... 2 Supplying the ADC from the Reference.................................. 17 Specifications..................................................................................... 3 Digital Interface.......................................................................... 17 Timing Specifications .................................................................. 5 CS Mode, 3-Wire Without Busy Indicator ............................. 18 Absolute Maximum Ratings............................................................ 7 CS Mode, 3-Wire with Busy Indicator .................................... 19 Thermal Resistance ...................................................................... 7 CS Mode, 4-Wire Without Busy Indicator ............................. 20 ESD Caution.................................................................................. 7 CS Mode, 4-Wire with Busy Indicator .................................... 21 Pin Configurations and Function Descriptions ........................... 8 Chain Mode Without Busy Indicator ...................................... 22 Typical Performance Characteristics ............................................. 9 Chain Mode with Busy Indicator............................................. 23 Terminology .................................................................................... 13 Application Hints ........................................................................... 24 Theory of Operation ...................................................................... 14 Layout .......................................................................................... 24 Circuit Information.................................................................... 14 Evaluating the AD7691 Performance ...................................... 24 Converter Operation.................................................................. 14 Outline Dimensions....................................................................... 25 Typical Connection Diagram ................................................... 15 Ordering Guide .......................................................................... 25 Analog Inputs.............................................................................. 15 REVISION HISTORY 3/12—Rev. B to Rev. C Change to Table 9 ........................................................................... 14 Changes to Ordering Guide .......................................................... 25 7/11—Rev. A to Rev. B Changes to Common-Mode Input Range Min Parameter ......... 3 Added EPAD Note to Figure 6 and Table 8................................... 8 Updated Outline Dimensions ....................................................... 25 11/07—Rev. 0 to Rev. A Deleted QFN Package in Development References .......Universal Changes to Features, Applications, Figure 1 and Figure 2 .......... 1 Changes to Accuracy, Table 2.......................................................... 3 Changes to Power Dissipation, Table 3.......................................... 4 Added Thermal Resistance Section ............................................... 7 Changes to Figure 22...................................................................... 11 Changes to Format ......................................................................... 12 Changes to Terminology Section.................................................. 13 Changes to Format and Figure 29 ................................................ 15 Inserted Figure 31........................................................................... 15 Changes to Format ......................................................................... 17 Changes to Figure 44...................................................................... 22 Changes to Figure 46...................................................................... 23 Updated QFN Outline Dimensions ............................................. 25 Changes to Ordering Guide .......................................................... 25 7/06—Revision 0: Initial Version Rev. C | Page 2 of 28 Data Sheet AD7691 SPECIFICATIONS VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range, V IN+ − (IN−) −V +V V IN REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V /2 − 0.1 V/2 V /2 + 0.1 V REF REF REF Analog Input CMRR fIN = 250 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA 1 Input Impedance THROUGHPUT Conversion Rate VDD = 4.5 V to 5.25 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 180 kSPS Transient Response Full-scale step 1.8 μs ACCURACY No Missing Codes 18 Bits 2 Integral Linearity Error −1.5 ±0.75 +1.5 LSB 2 Differential Linearity Error −1 ±0.5 +1.25 LSB 2 Transition Noise REF = VDD = 5 V 0.75 LSB 3 2 Gain Error VDD = 4.5 V to 5.25 V −40 ±2 +40 LSB 2 VDD = 2.3 V to 4.5 V −80 ±2 +80 LSB Gain Error Temperature Drift ±0.3 ppm/°C 3 Zero Error VDD = 4.5 V to 5.25 V −0.8 ±0.1 +0.8 mV VDD = 2.3 V to 4.5 V −3.5 ±0.7 +3.5 mV Zero Temperature Drift ±0.3 ppm/°C 2 Power Supply Sensitivity ±0.25 LSB VDD = 5 V ± 5% 4 AC ACCURACY Dynamic Range VREF = 5 V 101 102 dB 5 Oversampled Dynamic Range fIN = 1 kSPS 125 dB Signal-to-Noise f = 1 kHz, V = 5 V 100 101.5 dB IN REF f = 1 kHz, V = 2.5 V 95 96.5 dB IN REF Spurious-Free Dynamic Range fIN = 1 kHz, VREF = 5 V −125 dB Total Harmonic Distortion fIN = 1 kHz, VREF = 5 V −118 dB Signal-to-(Noise + Distortion) fIN = 1 kHz, VREF = 5 V 100 101.5 dB f = 1 kHz, V = 2.5 V 95 96.5 dB IN REF 6 Intermodulation Distortion 115 dB 1 See the Analog Inputs section. 2 LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 μV. 3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 All ac accuracy specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 5 Dynamic range obtained by oversampling the ADC running at a throughput f of 250 kSPS, followed by postdigital filtering with an output word rate f . S O 6 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale. Rev. C | Page 3 of 28 AD7691 Data Sheet VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 3. Parameter Conditions/Comments Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 60 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 18-bit, twos complement 1 Pipeline Delay VOL ISINK = +500 μA 0.4 V V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.25 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 2, 3 Standby Current VDD and VIO = 5 V, TA = 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 μW VDD = 2.5 V, 100 kSPS throughput 1.35 mW VDD = 2.5 V, 180 kSPS throughput 2.4 mW VDD = 5 V, 100 kSPS throughput 4.24 5 mW VDD = 5 V, 250 kSPS throughput 10.6 12.5 mW Energy per Conversion 50 nJ/sample 4 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 Conversion results are available immediately after completed conversion. 2 With all digital inputs forced to VIO or GND as required. 3 During acquisition phase. 4 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. C | Page 4 of 28 Data Sheet AD7691 TIMING SPECIFICATIONS 1 VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 0.5 2.2 μs CONV Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) t 15 ns SCK SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time t 7 ns SCKL SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 10 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 1 See Figure 3 and Figure 4 for load conditions. Rev. C | Page 5 of 28 AD7691 Data Sheet 1 VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 5. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 3.7 μs Acquisition Time t 1.8 ns ACQ Time Between Conversions t 5.5 μs CYC CNV Pulse Width (CS Mode) t 10 ns CNVH SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time t 12 ns SCKL SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) t 30 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 8 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 10 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t 36 DSDOSDI 1 See Figure 3 and Figure 4 for load conditions. 70% VIO 500µA I OL 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V TO SDO 1.4V 2 2 0.8V OR 0.5V 0.8V OR 0.5V C L 50pF 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. 500µA I OH Figure 4. Voltage Levels for Timing Figure 3. Load Circuit for Digital Interface Timing Rev. C | Page 6 of 28 06146-002 06146-003 Data Sheet AD7691 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA 1 soldered in a circuit board for surface-mount packages. Analog Inputs (IN+, IN−) GND − 0.3 V to VDD + 0.3 V or ±130 mA Table 7. Thermal Resistance REF GND − 0.3 V to VDD + 0.3 V Package Type θ θ Unit JA JC Supply Voltages 10-Lead MSOP 200 44 °C/W VDD, VIO to GND −0.3 V to +7 V 10-Lead QFN (LFCSP) 43.4 6.5 °C/W VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Lead Temperature Range JEDEC J-STD-20 1 See the Analog Inputs section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 7 of 28 AD7691 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9SDI AD7691 IN+ 3 8SCK TOP VIEW IN– 4 (Not to Scale) 7SDO REF 1 10 VIO GND 5 6 CNV VDD 2 9 SDI AD7691 IN+ 3 8 SCK NOTES TOP VIEW 1. THE EXPOSED PAD IS NOT CONNECTED (Not to Scale) IN– 4 7 SDO INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT GND 5 6 CNV THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 8. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and V , REF centered about V /2 and must be driven 180° out of phase with IN−. REF 4 IN− AI Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and VREF, centered about VREF/2 and must be driven 180° out of phase with IN+. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, either chain or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the ground plane. 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 28 06146-004 06146-005 Data Sheet AD7691 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 POSITIVE DNL = 0.37LSB POSITIVE INL = 0.39LSB NEGATIVE DNL = –0.33LSB NEGATIVE INL = –0.73LSB 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 7. Integral Nonlinearity vs. Code 2.5 V Figure 10. Differential Nonlinearity vs. Code, 5 V 80k 45k VDD = REF = 5V VDD = REF = 2.5V 69769 σ = 0.76LSB σ = 1.42LSB 40k 38068 70k 35k 60k 30k 28179 50k 24411 25k 40k 20k 17460 28527 27770 30k 14362 15k 20k 10k 4055 10k 5k 2997 2904 2062 910 501 012 29 78 9 0 0 0 26 14 0 0 0 0 25 26 27 28 29 2A 2B 2C 2D 2E 2F 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center, 5 V Figure 11. Histogram of a DC Input at the Code Center, 2.5 V 0 0 32768 POINT FFT 32768 POINT FFT VDD = REF = 5V VDD = REF = 2.5V –20 –20 f = 250kSPS f = 180kSPS S S f = 2kHz f = 2kHz IN IN –40 –40 SNR = 101.4dB SNR = 96.4dB THD = –120.1dB THD = –120.3dB –60 2ND HARMONIC = –140.7dB –60 2ND HARMONIC = –132.5dB 3RD HARMONIC = –120.3dB 3RD HARMONIC = –121.2dB –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 80 90 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. 2 kHz FFT Plot, 5 V Figure 12. 2 kHz FFT Plot, 2.5 V Rev. C | Page 9 of 28 INL (LSB) AMPLITUDE (dB of Full Scale) COUNTS 06146-027 06146-028 06146-026 DNL (LSB) AMPLITUDE (dB of Full Scale) COUNTS 06146-030 06146-031 06146-029 AD7691 Data Sheet 104 18 –105 SNR 102 –110 100 17 SINAD 98 –115 THD ENOB 96 16 –120 94 92 –125 15 90 –130 88 SFDR 86 14 –135 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage 105 –90 V = 5V REF 100 –100 V = 2.5V REF 95 –110 90 V = 5V REF –120 85 V = 2.5V REF 80 –130 –55 –35 –15 5 25456585 105 125 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. SNR vs. Temperature Figure 17. THD vs. Temperature 105 –60 V = 5V, –10dB REF V = 5V, –1dB REF 100 –70 95 –80 V = 5V, –1dB REF V = 2.5V, –1dB REF 90 –90 V = 2.5V, –1dB REF V = 2.5V, –10dB REF 85 –100 80 –110 V = 2.5V, –10dB REF 75 –120 V = 5V, –10dB REF 70 –130 0 25 50 75 100 125 0 25 50 75 100 125 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. SINAD vs. Frequency Figure 18. THD vs. Frequency Rev. C | Page 10 of 28 SNR, SINAD (dB) SINAD (dB) SNR (dB) 06146-037 06146-033 ENOB (Bits) 06146-032 THD (dB) THD (dB) THD, SFDR (dB) 06146-038 06146-040 06146-039 Data Sheet AD7691 105 –90 6 SNR 5V GAIN ERROR 102 –95 4 99 SNR 2.5V –100 2 96 –105 93 –110 0 THD 5V 90 –115 –2 87 –120 –4 THD 2.5V 84 –125 OFFSET ERROR 81 –130 –6 –10 –8 –6 –4 –2 0 –55 –35 –15 5 25456585 105 125 INPUT LEVEL (dB) TEMPERATURE (°C) Figure 19. SNR, THD vs. Input Level Figure 22. Zero Error, Gain Error vs. Temperature 1000 1000 f =100kSPS VDD = 5V S 750 750 VDD = 2.5V 500 500 250 250 VDD + VIO VIO 0 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Power-Down Current vs. Temperature Figure 20. Operating Current vs. Temperature 25 1000 f =100kSPS S 20 750 VDD 15 VDD = 5V, 85°C 500 10 VDD = 5V, 25°C 250 5 VIO 0 0 0 2040 6080 100 120 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 SDO CAPACITIVE LOAD (pF) SUPPLY (V) Figure 24. tDSDO Delay vs. Capacitance Load and Supply Figure 21. Operating Current vs. Supply Rev. C | Page 11 of 28 SNR (dB) OPERATING CURRENT (µA) OPERATING CURRENT (µA) 06146-043 06146-042 THD (dB) 06146-041 POWER-DOWN CURRENT (nA) t DELAY (ns) DSDO OFFSET, GAIN ERROR (LSB) 06146-044 06146-034 06146-047 AD7691 Data Sheet 95 90 V = VDD = 5V REF 85 90 80 75 85 70 80 65 60 75 55 50 70 45 65 40 1 10 100 1000 10000 1 10 100 1000 10000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 25. PSSR vs. Frequency Figure 26. Analog Input CMRR vs. Frequency Rev. C | Page 12 of 28 PSRR (dB) 06146-035 CMRR (dB) 06146-036 Data Sheet AD7691 TERMINOLOGY Noise-Free Code Resolution Least Significant Bit (LSB) It is the number of bits beyond which it is impossible to resolve The least significant bit, or LSB, is the smallest increment that individual codes distinctly. It is calculated as can be represented by a converter. For an analog-to-digital N Noise-Free Code Resolution = log2(2 /Peak-to-Peak Noise) converter with N bits of resolution, the LSB expressed in volts is and is expressed in bits. V INpp LSB(V)= N Effective Resolution 2 It is calculated as Integral Nonlinearity Error (INL) N Effective Resolution = log (2 /RMS Input Noise) 2 INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The and is expressed in bits. point used as negative full scale occurs ½ LSB before the first Total Harmonic Distortion (THD) code transition. Positive full scale is defined as a level 1½ LSB THD is the ratio of the rms sum of the first five harmonic beyond the last code transition. The deviation is measured from components to the rms value of a full-scale input signal and is the middle of each code to the true straight line (see Figure 28). expressed in decibels. Differential Nonlinearity Error (DNL) Dynamic Range In an ideal ADC, code transitions are 1 LSB apart. DNL is the Dynamic range is the ratio of the rms value of the full scale to maximum deviation from this ideal value. It is often specified in the total rms noise measured with the inputs shorted together. terms of resolution for which no missing codes are guaranteed. The value for dynamic range is expressed in decibels. Zero Error Signal-to-Noise Ratio (SNR) Zero error is the difference between the ideal midscale voltage, SNR is the ratio of the rms value of the actual input signal to the that is, 0 V, from the actual voltage producing the midscale rms sum of all other spectral components below the Nyquist output code, that is, 0 LSB. frequency, excluding harmonics and dc. The value for SNR is Gain Error expressed in decibels. The first transition (from 100 . . . 00 to 100 . . . 01) should occur Signal-to-(Noise + Distortion) Ratio (SINAD) at a level ½ LSB above nominal negative full scale (−4.999981 V SINAD is the ratio of the rms value of the actual input signal to for the ±5 V range). The last transition (from 011 … 10 to the rms sum of all other spectral components below the Nyquist 011 … 11) should occur for an analog voltage 1½ LSB below the frequency, including harmonics but excluding dc. The value for nominal full scale (+4.999943 V for the ±5 V range). The gain SINAD is expressed in decibels. error is the deviation in LSBs (or % of full-scale range) of the Aperture Delay difference between the actual level of the last transition and the Aperture delay is the measure of the acquisition performance. It actual level of the first transition from the difference between is the time between the rising edge of the CNV input and when the ideal levels. The closely related full-scale error, which is the input signal is held for a conversion. expressed also in LSBs or % of full-scale range, includes the contribution from the zero error. Transient Response Transient response is the time required for the ADC to acquire Spurious-Free Dynamic Range (SFDR) its input accurately after a full-scale step function is applied. SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINAD − 1.76)/6.02 dB and is expressed in bits. Rev. C | Page 13 of 28 AD7691 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 131,072C 65,536C 4C 2C C C MSB LSB SW– CNV IN– Figure 27. ADC Simplified Schematic The control logic toggles these switches, starting with the MSB, CIRCUIT INFORMATION to bring the comparator back into a balanced condition. After The AD7691 is a fast, low power, single-supply, precise, 18-bit the completion of this process, the part returns to the ADC using a successive approximation architecture. acquisition phase, and the control logic generates the ADC The part is capable of converting 250,000 samples per second output code and a busy signal indicator. (250 kSPS) and powers down between conversions. When Because the AD7691 has an on-board conversion clock, the operating at 1 kSPS, for example, it consumes 50 μW typically, serial clock, SCK, is not required for the conversion process. which is ideal for battery-powered applications. Transfer Functions The AD7691 provides the user with an on-chip track-and-hold The ideal transfer characteristic for the AD7691 is shown in and does not exhibit pipeline delay or latency, making it ideal Figure 28 and Table 9. for multiple multiplexed channel applications. The AD7691 is specified from 2.3 V to 5.25 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in 011...111 a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines 011...110 space savings and allows flexible configurations. 011...101 The part is pin-for-pin compatible with the 18-bit AD7690 as well as the 16-bit AD7687 and AD7688. CONVERTER OPERATION The AD7691 is a successive approximation ADC based on a 100...010 charge redistribution DAC. Figure 27 shows the simplified 100...001 schematic of the ADC. The capacitive DAC consists of two 100...000 –FSR identical arrays of 18 binary-weighted capacitors, which are –FSR + 1LSB +FSR – 1LSB connected to the two comparator inputs. –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT During the acquisition phase, terminals of the array tied to the Figure 28. ADC Ideal Transfer Function comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Table 9. Output Codes and Ideal Input Voltages Thus, the capacitor arrays are used as sampling capacitors and Analog Input Digital Output acquire the analog signal on the IN+ and IN− inputs. When the Description V = 5 V Code (Hex) REF acquisition phase is complete and the CNV input goes high, a 1 FSR − 1 LSB +4.999962 V 0x1FFFF conversion phase is initiated. When the conversion phase Midscale + 1 LSB +38.15 μV 0x00001 begins, SW+ and SW− are opened first. The two capacitor Midscale 0 V 0x00000 arrays are then disconnected from the inputs and connected to Midscale − 1 LSB −38.15 μV 0x3FFFF the GND input. Therefore, the differential voltage between the −FSR + 1 LSB −4.999962 V 0x20001 inputs IN+ and IN− captured at the end of the acquisition phase 2 −FSR −5 V 0x20000 is applied to the comparator inputs, causing the comparator to 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). become unbalanced. By switching each element of the capacitor 2 This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144). Rev. C | Page 14 of 28 ADC CODE (TWOS COMPLEMENT) 06146-024 06146-006 Data Sheet AD7691 TYPICAL CONNECTION DIAGRAM Figure 29 shows an example of the recommended connection diagram for the AD7691 when multiple supplies are available. 1 V+ REF 5V 2 10µF 100nF V+ 1.8V TO VDD 100nF 15Ω REF VDD VIO 0 TO V REF SDI IN+ 2.7nF 3 ADA4841-2 SCK V– 5 AD7691 3- OR 4-WIRE INTERFACE SDO 4 V+ IN– CNV GND 15Ω V TO 0 REF 2.7nF 3 ADA4841-2 V– 4 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3 SEE TABLE 9 FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE. Figure 29. Typical Application Diagram with Multiple Supplies During the conversion phase, where the switches are opened, ANALOG INPUTS the input impedance is limited to C . R and C make a PIN IN IN Figure 30 shows an equivalent circuit of the input structure of 1-pole, low-pass filter that reduces undesirable aliasing effects the AD7691. and limits noise. The two diodes, D1 and D2, provide ESD protection for the When the source impedance of the driving circuit is low, the analog inputs, IN+ and IN−. Care must be taken to ensure that AD7691 can be driven directly. Large source impedances the analog input signal does not exceed the supply rails by more significantly affect the ac performance, especially total harmonic than 0.3 V because this causes the diodes to become forward distortion (THD). The dc performances are less sensitive to biased and start conducting current. These diodes can handle a the input impedance. The maximum source impedance forward-biased current of 130 mA maximum. For instance, depends on the amount of THD that can be tolerated. these conditions could eventually occur if the input buffer (U1) supplies are different from VDD. In such a case (for example, an The THD degrades as a function of the source impedance and input buffer with a short circuit), the current limitation can be the maximum input frequency as shown in Figure 31. used to protect the part. –80 V = VDD 5V REF VDD –85 –90 D1 C IN R IN+ IN OR IN– –95 250Ω C PIN D2 –100 100Ω GND –105 33Ω –110 Figure 30. Equivalent Analog Input Circuit 15Ω 50Ω –115 The analog input structure allows the sampling of the true –120 differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. –125 –130 During the acquisition phase, the impedance of the analog 09 10 20 30 40 50 60 70 800 inputs (IN+ and IN−) can be modeled as a parallel combination FREQUENCY (kHz) of the capacitor, CPIN, and the network formed by the series Figure 31. THD vs. Analog Input Frequency and Source Resistance connection of RIN and CIN. CPIN is primarily the pin capacitance. R is typically 3 kΩ and is a lumped component composed of IN serial resistors and the on resistance of the switches. C is IN typically 30 pF and is mainly the ADC sampling capacitor. Rev. C | Page 15 of 28 06146-007 THD (dB) 06146-008 06146-009 AD7691 Data Sheet DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER Although the AD7691 is easy to drive, the driver amplifier must For applications using a single-ended analog signal, either meet the following requirements: bipolar or unipolar, the ADA4941-1 single-ended-to-differential driver allows for a differential input into the part. The schematic The noise generated by the driver amplifier needs to be kept as is shown in Figure 32. low as possible to preserve the SNR and transition noise R5 R6 performance of the AD7691. The noise coming from the driver is filtered by the AD7691 analog input circuit’s R3 R4 +5V REF 1-pole, low-pass filter made by RIN and CIN or by the 10µF external filter, if one is used. The SNR degradation due to +5.2V +5.2V the amplifier is as follows: 100nF 15Ω REF VDD IN+ SNRLOSS = 2.7nF AD7691 2.7nF ⎛ ⎞ 100nF IN– ⎜ ⎟ 15Ω GND V ⎜ NADC ⎟ 20 log ⎜ ⎟ ADA4941 π π 2 2 2 ⎜ V + f (Ne ) + f (Ne ) ⎟ NADC N+ N− −3 dB −3 dB 2 2 ⎝ ⎠ ±10V, ±5V, ... where: R1 R2 VNADC is the noise of the ADC, in μV, given by the following: C F Figure 32. Single-Ended-to-Differential Driver Circuit V INpp R1 and R2 set the attenuation ratio between the input range and 2 2 V = NADC SNR the ADC range (VREF). R1, R2, and CF are chosen depending on 20 10 the desired input resistance, signal bandwidth, antialiasing, and f is the input bandwidth, in MHz, of the AD7691 (2 MHz) −3 dB noise contribution. For example, for the ±10 V range with a 4 kΩ or the cutoff frequency of the input filter, if one is used. impedance, R2 = 1 kΩ and R1 = 4 kΩ. N is the noise gain of the amplifier (for example, 1 in R3 and R4 set the common mode on the IN− input, and R5 and buffer configuration). R6 set the common mode on the IN+ input of the ADC. The eN+ and eN− are the equivalent input noise voltage densities common mode should be set close to V /2; however, if single REF of the op amps connected to IN+ and IN−, in nV/√Hz. supply is desired, it can be set slightly above VREF/2 to provide This approximation can be used when the resistances around some headroom for the ADA4941-1 output stage. For example, the amplifier are small. If larger resistances are used, their for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = noise contributions should also be root-sum-squared. 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. For ac applications, the driver should have a THD performance VOLTAGE REFERENCE INPUT commensurate with the AD7691. The AD7691 voltage reference input, REF, has a dynamic input For multichannel multiplexed applications, the driver amplifier impedance and should therefore be driven by a low impedance and the AD7691 analog input circuit must settle for a full- source with efficient decoupling between the REF and GND scale step onto the capacitor array at an 18-bit level pins, as explained in the Layout section. (0.0004%, 4 ppm). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This may When REF is driven by a very low impedance source, for differ significantly from the settling time at an 18-bit level example, a reference buffer using the AD8031 or the AD8605, a and should be verified prior to driver selection. 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. Table 10. Recommended Driver Amplifiers If an unbuffered reference voltage is used, the decoupling value Amplifier Typical Application depends on the reference used. For instance, a 22 μF (X5R, ADA4941-1 Very low noise, low power single-ended-to- 1206 size) ceramic chip capacitor is appropriate for optimum differential performance using a low temperature drift ADR43x reference. ADA4841-x Very low noise, small, and low power AD8655 5 V single supply, low noise If desired, smaller reference decoupling capacitor values as low AD8021 Very low noise and high frequency as 2.2 μF can be used with a minimal impact on performance, AD8022 Low noise and high frequency especially DNL. OP184 Low power, low noise, and low frequency Regardless, there is no need for an additional lower value AD8605, AD8615 5 V single supply, low power ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. Rev. C | Page 16 of 28 06146-010 Data Sheet AD7691 POWER SUPPLY 5V 5V The AD7691 uses two power supply pins: a core supply (VDD) and 10Ω 5V 10kΩ a digital input/output interface supply (VIO). VIO allows direct 10µF 1µF AD8031 interface with any logic between 1.8 V and VDD. To reduce the 1µF supplies needed, the VIO and VDD pins can be tied together. The 1 AD7691 is independent of power supply sequencing between VIO REF VDD VIO and VDD. Additionally, it is very insensitive to power supply AD7691 variations over a wide frequency range, as shown in Figure 25. The AD7691 powers down automatically at the end of each 1 OPTIONAL REFERENCE BUFFER AND FILTER. conversion phase, and therefore, the power scales linearly with Figure 34. Example of an Application Circuit the sampling rate. This makes the part ideal for low sampling DIGITAL INTERFACE rate (as low as a few hertz) and low battery-powered applications. Though the AD7691 has a reduced number of pins, it offers flexibility in its serial interface modes. 1000 CS When in mode, the AD7691 is compatible with SPI, QSPI, VDD = 5V digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. In this mode, the AD7691 can use either a 3-wire 10 or 4-wire interface. A 3-wire interface using the CNV, SCK, and VIO SDO signals minimizes wiring connections and is useful, for instance, in isolated applications. A 4-wire interface using the 0.1 SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. 0.001 10 100 1k 10k 100k 1M When in chain mode, the AD7691 provides a daisy-chain SAMPLING RATE (SPS) feature using the SDI input for cascading multiple ADCs on a Figure 33. Operating Current vs. Sample Rate single data line similar to a shift register. SUPPLYING THE ADC FROM THE REFERENCE The mode in which the part operates depends on the SDI level For simplified applications, the AD7691, with its low operating when the CNV rising edge occurs. The CS mode is selected if current, can be supplied directly using the reference circuit SDI is high, and the chain mode is selected if SDI is low. The shown in Figure 34. The reference line can be driven by SDI hold time is such that when SDI and CNV are connected The system power supply directly. together, the chain mode is selected. A reference voltage with enough current output capability, such In either mode, the AD7691 offers the option of forcing a start as the ADR43x. bit in front of the data bits. This start bit can be used as a busy A reference buffer, such as the AD8031, which can also filter the signal indicator to interrupt the digital host and trigger the data system power supply, as shown in Figure 34. reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. The busy indicator feature is enabled CS In the mode if CNV or SDI is low when the ADC conversion ends (see Figure 38 and Figure 42). In the chain mode if SCK is high during the CNV rising edge (see Figure 46). Rev. C | Page 17 of 28 OPERATING CURRENT (µA) 06146-045 06146-046 AD7691 Data Sheet edges. The data is valid on both SCK edges. Although the rising CS MODE, 3-WIRE WITHOUT BUSY INDICATOR edge can be used to capture the data, a digital host using the This mode is usually used when a single AD7691 is connected SCK falling edge can allow a faster reading rate, provided it has to an SPI-compatible digital host. The connection diagram is th an acceptable hold time. After the 18 SCK falling edge, or shown in Figure 35, and the corresponding timing is given in when CNV goes high, whichever occurs first, SDO returns to Figure 36. high impedance. With SDI tied to VIO, a rising edge on CNV initiates a CS CONVERT conversion, selects the mode, and forces SDO to high impedance. Once a conversion is initiated, it continues until DIGITAL HOST CNV completion irrespective of the state of CNV. This can be useful, VIO for instance, to bring CNV low to select other SPI devices, such DATA IN SDI SDO AD7691 as analog multiplexers, but CNV must be returned high before SCK the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation CLK of the busy signal indicator. When the conversion is complete, the AD7691 enters the acquisition phase and powers down. Figure 35. 3-Wire CS Mode Without Busy Indicator Connection Diagram (SDI High) When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 16 17 18 t t HSDO SCKH t t t EN DSDO DIS SDO D17 D16 D15 D1 D0 Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High) Rev. C | Page 18 of 28 06146-012 06146-011 Data Sheet AD7691 The data is valid on both SCK edges. Although the rising edge CS MODE, 3-WIRE WITH BUSY INDICATOR can be used to capture the data, a digital host using the SCK This mode is usually used when a single AD7691 is connected falling edge can allow a faster reading rate, provided it has an to an SPI-compatible digital host having an interrupt input. th acceptable hold time. After the optional 19 SCK falling edge, The connection diagram is shown in Figure 37, and the or when CNV goes high, whichever occurs first, SDO returns to corresponding timing is given in Figure 38. high impedance. With SDI tied to VIO, a rising edge on CNV initiates a If multiple AD7691s are selected at the same time, the SDO CS conversion, selects the mode, and forces SDO to high output pin handles this contention without damage or induced impedance. SDO is maintained in high impedance until the latch-up. Meanwhile, it is recommended to keep this contention completion of the conversion irrespective of the state of CNV. as short as possible to limit extra power dissipation. Prior to the minimum conversion time, CNV can be used to CONVERT select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time VIO DIGITAL HOST CNV elapses and then held low for the maximum possible conversion VIO 47kΩ time to guarantee the generation of the busy signal indicator. SDI SDO DATA IN AD7691 When the conversion is complete, SDO goes from high SCK IRQ impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the CLK data reading controlled by the digital host. The AD7691 then enters the acquisition phase and powers down. The data bits Figure 37. 3-Wire CS Mode with Busy Indicator Connection Diagram (SDI High) are clocked out, MSB first, by subsequent SCK falling edges. SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 17 18 19 t t HSDO SCKH t t DSDO DIS SDO D17 D16 D1 D0 Figure 38. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High) Rev. C | Page 19 of 28 06146-014 06146-013 AD7691 Data Sheet time elapses and then held high for the maximum possible CS MODE, 4-WIRE WITHOUT BUSY INDICATOR conversion time to avoid the generation of the busy signal This mode is usually used when multiple AD7691s are indicator. When the conversion is complete, the AD7691 enters connected to an SPI-compatible digital host. the acquisition phase and powers down. Each ADC result can A connection diagram example using two AD7691s is shown in be read by bringing its SDI input low, which consequently Figure 39, and the corresponding timing is given in Figure 40. outputs the MSB onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK With SDI high, a rising edge on CNV initiates a conversion, edges. Although the rising edge can be used to capture the data, CS selects the mode, and forces SDO to high impedance. In this a digital host using the SCK falling edge allows a faster reading mode, CNV must be held high during the conversion phase and th rate, provided it has an acceptable hold time. After the 18 SCK the subsequent data readback. (If SDI and CNV are low, SDO is falling edge, or when SDI goes high, whichever occurs first, SDO driven low.) Prior to the minimum conversion time, SDI can be returns to high impedance and another AD7691 can be read. used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI SDO SDI SDO AD7691 AD7691 SCK SCK DATA IN CLK Figure 39. 4-Wire CS Mode Without Busy Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI (CS1) t HSDICNV SDI (CS2) t SCK t SCKL SCK 12 3 16 17 18 19 20 34 35 36 t t HSDO SCKH t t t DSDO DIS EN SDO D17 D16 D15 D1 D0 D17 D16 D1 D0 Figure 40. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing Rev. C | Page 20 of 28 06146-015 06146-016 Data Sheet AD7691 line, this transition can be used as an interrupt signal to initiate CS MODE, 4-WIRE WITH BUSY INDICATOR the data readback controlled by the digital host. The AD7691 This mode is normally used when a single AD7691 is connected then enters the acquisition phase and powers down. The data to an SPI-compatible digital host with an interrupt input, and it bits are clocked out, MSB first, by subsequent SCK falling edges. is desired to keep CNV, which is used to sample the analog The data is valid on both SCK edges. Although the rising edge input, independent of the signal used to select the data reading. can be used to capture the data, a digital host using the SCK This requirement is particularly important in applications falling edge can allow a faster reading rate, provided it has an where low jitter on CNV is desired. th acceptable hold time. After the optional 19 SCK falling edge, The connection diagram is shown in Figure 41, and the or SDI going high, whichever occurs first, SDO returns to high corresponding timing is given in Figure 42. impedance. With SDI high, a rising edge on CNV initiates a conversion, CS1 selects the CS mode, and forces SDO to high impedance. In this CONVERT mode, CNV must be held high during the conversion phase and VIO DIGITAL HOST CNV the subsequent data readback. (If SDI and CNV are low, SDO is 47kΩ driven low.) Prior to the minimum conversion time, SDI can be SDI SDO DATA IN AD7691 used to select other SPI devices, such as analog multiplexers, SCK IRQ but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible CLK conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from Figure 41. 4-Wire CS Mode with Busy Indicator Connection Diagram high impedance to low impedance. With a pull-up on the SDO t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 171819 t t HSDO SCKH t t DSDO DIS t EN SDO D17 D16 D1 D0 Figure 42. 4-Wire CS Mode with Busy Indicator Serial Interface Timing Rev. C | Page 21 of 28 06146-018 06146-017 AD7691 Data Sheet readback. When the conversion is complete, the MSB is output CHAIN MODE WITHOUT BUSY INDICATOR onto SDO and the AD7691 enters the acquisition phase and This mode can be used to daisy-chain multiple AD7691s on powers down. The remaining data bits stored in the internal a 3-wire serial interface. This feature is useful for reducing shift register are clocked by subsequent SCK falling edges. For component count and wiring connections, for example, in each ADC, SDI feeds the input of the internal shift register and isolated multiconverter applications or for systems with a is clocked by the SCK falling edge. Each ADC in the chain limited interfacing capacity. Data readback is analogous to outputs its data MSB first, and 18 × N clocks are required to clocking a shift register. read back the N ADCs. The data is valid on both SCK edges. A connection diagram example using two AD7691s is shown in Although the rising edge can be used to capture the data, a Figure 43, and the corresponding timing is given in Figure 44. digital host using the SCK falling edge can allow a faster reading When SDI and CNV are low, SDO is driven low. With SCK low, rate and, consequently, more AD7691s in the chain, provided a rising edge on CNV initiates a conversion, selects the chain the digital host has an acceptable hold time. The maximum mode, and disables the busy indicator. In this mode, CNV is conversion rate may be reduced due to the total readback time. held high during the conversion phase and the subsequent data CONVERT CNV CNV DIGITAL HOST AD7691 AD7691 SDI SDO SDI SDO DATA IN A B SCK SCK CLK Figure 43. Chain Mode Without Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 12 3 16 17 18 19 20 34 35 36 t t t HSCKCNV SSDISCK SCKH t t HSDISCK EN D 17 D 16 D 15 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 SDO B B B B B A A A A B Figure 44. Chain Mode Without Busy Indicator Serial Interface Timing Rev. C | Page 22 of 28 06146-019 06146-020 Data Sheet AD7691 completed their conversions, the SDO pin of the ADC closest to CHAIN MODE WITH BUSY INDICATOR the digital host (see the AD7691 ADC labeled C in Figure 45) is This mode can also be used to daisy-chain multiple AD7691s driven high. This transition on SDO can be used as a busy on a 3-wire serial interface while providing a busy indicator. indicator to trigger the data readback controlled by the digital This feature is useful for reducing component count and wiring host. The AD7691 then enters the acquisition phase and powers connections, for example, in isolated multiconverter applications down. The data bits stored in the internal shift register are or for systems with a limited interfacing capacity. Data readback clocked out, MSB first, by subsequent SCK falling edges. For is analogous to clocking a shift register. each ADC, SDI feeds the input of the internal shift register and A connection diagram example using three AD7691s is shown is clocked by the SCK falling edge. Each ADC in the chain in Figure 45, and the corresponding timing is given in Figure 46. outputs its data MSB first, and 18 × N + 1 clocks are required to When SDI and CNV are low, SDO is driven low. With SCK readback the N ADCs. Although the rising edge can be used to high, a rising edge on CNV initiates a conversion, selects the capture the data, a digital host using the SCK falling edge allows chain mode, and enables the busy indicator feature. In this a faster reading rate and, consequently, more AD7691s in the mode, CNV is held high during the conversion phase and the chain, provided the digital host has an acceptable hold time. subsequent data readback. When all ADCs in the chain have CONVERT CNV CNV CNV DIGITAL HOST AD7691 AD7691 AD7691 DATA IN SDI SDO SDI SDO SDI SDO A B C SCK SCK SCK IRQ CLK Figure 45. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 417 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t EN HSDISCK SDO = SDI D 17 D 16 D 15 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI B C D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 B B B B B A A A A t t DSDOSDI DSDOSDI SDO D 17 D 16 D 15 D1D0D D 17 D 16 D1D0D 17 16 D1D 0 C C C C C C B B B B A A A A Figure 46. Chain Mode with Busy Indicator Serial Interface Timing Rev. C | Page 23 of 28 06146-021 06146-022 AD7691 Data Sheet APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7691 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7691, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because this couples noise onto the die unless a ground plane under the AD7691 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7691. Figure 47. Example Layout of the AD7691 (Top Layer) The AD7691 voltage reference input, REF, has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies, VDD and VIO, of the AD7691 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7691 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example layout following these rules is shown in Figure 47 and Figure 48. EVALUATING THE AD7691 PERFORMANCE Other recommended layouts for the AD7691 are outlined Figure 48. Example Layout of the AD7691 (Bottom Layer) in the documentation of the evaluation board for the AD7691 (EVAL-AD7691CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3Z. Rev. C | Page 24 of 28 06146-048 06146-023 Data Sheet AD7691 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding Ordering Quantity AD7691BCPZRL –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4E Reel, 5,000 AD7691BCPZRL7 –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4E Reel, 1,500 AD7691BRMZ –40°C to +85°C 10-Lead MSOP RM-10 C4E Tube, 50 AD7691BRMZ-RL7 –40°C to +85°C 10-Lead MSOP RM-10 C4E Reel, 1,000 EVAL-AD7691SDZ Evaluation Board EVAL-SDP-CB1Z Controller Board 1 Z = RoHS Compliant Part. Rev. C | Page 25 of 28 PIN 1 INDICATOR (R 0.15) 091709-A 121009-A AD7691 Data Sheet NOTES Rev. C | Page 26 of 28 Data Sheet AD7691 NOTES Rev. C | Page 27 of 28 AD7691 Data Sheet NOTES ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06146-0-3/12(C) Rev. C | Page 28 of 28