ANALOG DEVICES AD7690

® 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN AD7690 FEATURES APPLICATION EXAMPLE +2.5V TO +5V +5V 18-bit resolution with no missing codes Throughput: 400 kSPS INL: ±0.75 LSB typ, ±1.5 LSB max (±6 ppm of FSR) Dynamic range: 102 dB @ 400 kSPS VIO +1.8V TO VDD REF VDD IN+ SDI Oversampled dynamic range: 125 dB @ 1 kSPS 3- OR 4-WIRE SCK ±10V, ±5V, ... INTERFACE Noise-free code resolution: 20 bits @ 1 kSPS SDO (SPI, DAISY CHAIN, CS) IN– GND CNV Effective resolution: 22.7 bits @ 1 kSPS ADA4941-1 SINAD: 101.5 dB @ 1 kHz AD7690 THD: −125 dB @ 1 kHz Figure 2. True differential analog input range: ±VREF 0 V to V with V up to VDD on both inputs REF REF Table 1. MSOP, QFN (LFCSP)/SOT-23 No pipeline delay 14-/16-/18-Bit PulSAR ADC Single-supply 5 V operation with 400 kSPS 1.8 V/2.5 V/3 V/5 V logic interface 100 250 to 1000 ADC Serial interface, SPI®/QSPI™/MICROWIRE™/DSP compatible Type kSPS kSPS 500 kSPS kSPS Driver Daisy-chain multiple ADCs and busy indicator 18-Bit True AD7691 AD7690 AD7982 ADA4941 Differential AD7982 ADA4841 Power dissipation 16-Bit True AD7684 AD7687 AD7688 ADA4941 4.25 μW @ 100 SPS Differential AD7693 ADA4841 4.25 mW @ 100 kSPS 16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841 Standby current: 1 nA Differential AD7683 AD7694 10-lead package: MSOP (MSOP-8 size) and 14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841 Differential 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Pin-for-pin compatible with QFN/MSOP PulSAR ADCs GENERAL DESCRIPTION APPLICATIONS The AD7690 is an 18-bit, successive approximation, analog-to- Battery-powered equipment digital converter (ADC) that operates from a single power supply, Data acquisition VDD. It contains a low power, high speed, 18-bit sampling ADC Seismic data acquisition systems with no missing codes, an internal conversion clock, and a DVMs versatile serial interface port. On the CNV rising edge, it Instrumentation samples the voltage difference between the IN+ and IN− pins. Medical instruments The voltages on these pins swing in opposite phase between 0 V 1.5 and REF. The reference voltage, REF, is applied externally and POSITIVE INL = +0.42LSB NEGATIVE INL = –0.6LSB can be set up to the supply voltage. 1.0 The power of the AD7690 scales linearly with the throughput. 0.5 The SPI-compatible serial interface also features the ability, 0 using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible –0.5 with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply. –1.0 The AD7690 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. –1.5 0 65536 131072 196608 262144 CODE Figure 1. Integral Nonlinearity vs. Code Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 05792-025 05792-001 AD7690 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications ....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Example ........................................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply ............................................................................... 16 Revision History ............................................................................... 2 Supplying the ADC from the Reference .................................. 16 Specif ica t ions ..................................................................................... 3 Digital Interface .......................................................................... 16 Timing Specifications ....................................................................... 5 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Absolute Maximum Ratings ............................................................ 6 CS Mode, 3-Wire With Busy Indicator ................................... 18 ESD Caution .................................................................................. 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 Pin Configurations and Function Descriptions ........................... 7 CS Mode, 4-Wire With Busy Indicator ................................... 20 Terminology ...................................................................................... 8 Chain Mode Without Busy Indicator ...................................... 21 Typical Performance Characteristics ............................................. 9 Chain Mode with Busy Indicator ............................................. 22 Theory of Operation ...................................................................... 12 Application Hints ........................................................................... 23 Circuit Information .................................................................... 12 Layout .......................................................................................... 23 Converter Operation .................................................................. 12 Evaluating the AD7690’s Performance .................................... 23 Typical Connection Diagram ................................................... 13 Outline Dimensions ....................................................................... 24 Analog Inputs .............................................................................. 14 Ordering Guide .......................................................................... 24 REVISION HISTORY 7/11—Rev. A to Rev. B Change to Conversion Time: Changes to Common-Mode Input Range Min Parameter ......... 3 CNV Rising Edge to Data Available in Table 4 ........................ 5 Added EPAD Note to Figure 6 and Table 6 ................................... 7 Change to Acquisition Time in Table 4 .......................................... 5 Updated Outline Dimensions ....................................................... 24 Changes to Figure 12 ......................................................................... 9 Changes to Ordering Guide .......................................................... 24 Change to Figure 22 Caption ........................................................ 11 Changes to Circuit Information Section ..................................... 12 3/07—Rev. 0 to Rev. A Change to Table 7 ........................................................................... 13 Removed Endnote Regarding QFN Package .................. Universal Change to Endnote 1 of Figure 26 ................................................ 13 Changes to Features .......................................................................... 1 Added Figure 29 ............................................................................. 14 Changes to Table 1 ............................................................................ 1 Changes to Driver Amplifier Choice Section ............................. 14 Changes to Figure 2 .......................................................................... 1 Change to Evaluating the AD7690’s Performance Section ....... 23 Changes to Gain Error in Table 2 ................................................... 3 Updated Outline Dimensions ....................................................... 24 Change to Gain Error Temperature Drift in Table 2 ................... 3 Changes to Ordering Guide .......................................................... 24 Change to Zero Temperature Drift in Table 2 .............................. 3 Changes to Power Dissipation in Table 3 ...................................... 4 4/06—Revision 0: Initial Version Rev. B | Page 2 of 24 AD7690 SPECIFICATIONS VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range IN+ to IN− −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− V /2 − 0.1 V/2 V /2 + 0.1 V REF REF REF Analog Input CMRR fIN = 250 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA 1 Input Impedance THROUGHPUT Conversion Rate 0 400 kSPS Transient Response Full-scale step 400 ns ACCURACY No Missing Codes 18 Bits 2 Integral Linearity Error −1.5 ±0.75 +1.5 LSB Differential Linearity Error −1 ±0.5 +1.25 LSB Transition Noise REF = VDD = 5 V 0.75 LSB 3 Gain Error −40 ±2 +40 LSB Gain Error Temperature Drift ±0.3 ppm/°C 3 Zero Error −0.8 +0.8 mV Zero Temperature Drift ±0.3 ppm/°C Power Supply Sensitivity ±0.25 LSB VDD = 5 V ± 5% AC ACCURACY 4 Dynamic Range V = 5 V 101 102 dB REF 5 Oversampled Dynamic Range f = 1 kSPS 125 dB IN Signal-to-Noise fIN = 1 kHz, VREF = 5 V 100 101.5 dB fIN = 1 kHz, VREF = 2.5 V 94.5 96 dB Spurious-Free Dynamic Range fIN = 1 kHz, VREF = 5 V −125 dB Total Harmonic Distortion f = 1 kHz, V = 5 V −125 dB IN REF Signal-to-(Noise + Distortion) f = 1 kHz, V = 5 V 100 101.5 dB IN REF 6 Intermodulation Distortion 115 dB 1 See the Analog Inputs section. 2 LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 μV. 3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 5 Dynamic range obtained by oversampling the ADC running at a throughput f of 400 kSPS, followed by postdigital filtering with an output word rate f . S O 6 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale. Rev. B | Page 3 of 24 AD7690 VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 400 kSPS, REF = 5 V 100 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 9 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 18 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 4.75 5.25 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 1, 2 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V, 100 SPS throughput 4.25 μW VDD = 5 V, 100 kSPS throughput 4.25 5 mW VDD = 5 V, 400 kSPS throughput 17 20 mW Energy per Conversion 50 nJ/sample 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. B | Page 4 of 24 AD7690 TIMING SPECIFICATIONS VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 0.5 2.1 μs CONV Acquisition Time t 400 ns ACQ Time Between Conversions tCYC 2.5 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time t 7 ns SCKL SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid t 4 ns HSDO SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns t CNV or SDI Low to SDO D17 MSB Valid (CS Mode) EN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) t 15 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 10 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with BUSY Indicator) t DSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 1 See Figure 3 and Figure 4 for load conditions. 70% VIO 500μAI OL 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V TO SDO 1.4V 2 2 C 0.8V OR 0.5V 0.8V OR 0.5V L 50pF NOTES: 1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 500μAI OH 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. B | Page 5 of 24 02968-002 02968-003 AD7690 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs rating only; functional operation of the device at these or any 1 1 IN+, IN− GND − 0.3 V to VDD + 0.3 V other conditions above those indicated in the operational or ±130 mA section of this specification is not implied. Exposure to absolute REF GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V ESD CAUTION Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance 200°C/W JA (10-Lead MSOP) θ Thermal Impedance 44°C/W JC (10-Lead MSOP) Lead Temperature Range JEDEC J-STD-20 1 See the Analog Inputs section. Rev. B | Page 6 of 24 AD7690 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9SDI AD7690 IN+ 3 8SCK TOP VIEW IN– 4 (Not to Scale) 7SDO REF 1 10 VIO GND 5 6CNV VDD 2 9 SDI AD7690 IN+ 3 8 SCK TOP VIEW NOTES (Not to Scale) 1. THE EXPOSED PAD IS NOT CONNECTED IN– 4 7 SDO INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT GND 5 6 CNV THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the ground plane. 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. B | Page 7 of 24 05792-004 05792-005 AD7690 TERMINOLOGY Integral Nonlinearity Error (INL) Effective Resolution INL refers to the deviation of each individual code from a line Effective resolution is calculated as drawn from negative full scale through positive full scale. The N Effective Resolution = log2(2 /RMS Input Noise) point used as negative full scale occurs ½ LSB before the first and is expressed in bits. code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from Total Harmonic Distortion (THD) the middle of each code to the true straight line (see Figure 25). THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is Differential Nonlinearity Error (DNL) expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in Dynamic Range terms of resolution for which no missing codes are guaranteed. Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. Zero Error The value for dynamic range is expressed in decibels. Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale Signal-to-Noise Ratio (SNR) output code, that is, 0 LSB. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that is less than the Gain Error Nyquist frequency, excluding harmonics and dc. The value of The first transition (from 100 ... 00 to 100 ... 01) should occur at SNR is expressed in decibels. a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to Signal-to-(Noise + Distortion) Ratio (SINAD) 011 … 11) should occur for an analog voltage 1½ LSB below the SINAD is the ratio of the rms value of the actual input signal to nominal full scale (+4.999943 V for the ±5 V range). The gain the rms sum of all other spectral components below the Nyquist error is the deviation of the difference between the actual level frequency, including harmonics but excluding dc. The value for of the last transition and the actual level of the first transition SINAD is expressed in decibels. from the difference between the ideal levels. Aperture Delay Spurious-Free Dynamic Range (SFDR) Aperture delay is the measure of the acquisition performance. It SFDR is the difference, in decibels, between the rms amplitude is the time between the rising edge of the CNV input and when of the input signal and the peak spurious signal. the input signal is held for a conversion. Effective Number of Bits (ENOB) Transient Response ENOB is a measurement of the resolution with a sine wave Transient response is the time required for the ADC to accurately input. It is related to SINAD by the following formula: acquire its input after a full-scale step function is applied. ENOB = (SINAD − 1.76)/6.02 dB and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as: N Noise-Free Code Resolution = log (2 /Peak-to-Peak Noise) 2 and is expressed in bits. Rev. B | Page 8 of 24 AD7690 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.5 POSITIVE INL = +0.42LSB NEGATIVE INL = –0.6LSB 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 80k 60k VDD = REF = 5V VDD = REF = 5V 53936 52500 67198 70k 50k 60k 40k 50k 40k 30k 31666 30k 27546 20k 20k 12623 11212 10k 10k 2614 1991 533 39 18 00 2 263 30 0 0 0 0 0 0 0 55 57 58 59 5A 5B 5C 5D 5E 5F 60 31 32 33 34 35 36 37 38 39 3A 3B 3C CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Transition 105 –110 0 f = 400kSPS S 104 –112 f = 1.99kHz IN –20 SNR = 101.4dB THD = –122dB 103 –114 –40 SFDR = 130dB SINAD = 101.3dB 102 –116 –60 SNR 101 –118 –80 100 –120 –100 99 –122 –120 98 –124 –140 97 –126 THD –160 96 –128 95 –130 –180 –10 –8 –6 –4 –2 0 02 20 40 60 80 100 120 140 160 18000 INPUT LEVEL (dB) FREQUENCY (kHz) Figure 9. Fast Fourier Transform Plot Figure 12. SNR, THD vs. Input Level Rev. B | Page 9 of 24 INL (LSB) AMPLITUDE (dB of Full Scale) COUNTS 05792-026 05792-037 05792-025 SNR (dB) DNL (LSB) COUNTS 05792-039 05792-027 THD (dB) 05792-047 AD7690 104 20 –100 135 SNR 102 19 –105 130 SFDR SINAD 100 18 –110 125 98 17 –115 120 ENOB 96 16 –120 115 94 15 THD 92 14 –125 110 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage 103 –90 V = 5V V = 5V REF REF 102 101 –100 100 99 –110 98 97 –120 96 95 –130 –55 –35 –15 5 25456585 105 125 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. SNR vs. Temperature Figure 17. THD vs. Temperature 105 –60 V = 5V, –10dB 100 REF –70 95 V = 5V, –1dB –80 REF 90 –90 85 V = 5V, –1dB REF –100 80 –110 V = 5V, –10dB REF 75 –120 70 65 –130 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. SINAD vs. Frequency Figure 18. THD vs. Frequency Rev. B | Page 10 of 24 SNR, SINAD (dB) SINAD (dB) SNR (dB) 05792-043 05792-030 ENOB (Bits) 05792-029 THD (dB) THD (dB) THD (dB) 05792-044 05792-032 SFDR (dB) 05792-031 AD7690 1000 6 f = 100kSPS S VDD GAIN ERROR 4 750 2 500 0 –2 250 –4 ZERO ERROR VIO 0 –6 4.50 4.75 5.00 5.25 5.50 –55 –35 –15 5 25456585 105 125 SUPPLY (V) TEMPERATURE (°C) Figure 19. Operating Current vs. Supply Figure 22. Zero and Gain Error vs. Temperature 1000 25 20 750 15 VDD = 5V, 85°C 500 10 VDD = 5V, 25°C 250 5 VDD + VIO 0 0 –55 –35 –15 5 25 45 65 85 105 125 0 2040 6080 100 120 TEMPERATURE (°C) SDO CAPACITIVE LOAD (pF) Figure 20. Power-Down Current vs. Temperature Figure 23. t Delay vs. Capacitance Load and Supply DSDO 1000 f = 100kSPS S VDD 750 500 250 VIO –6 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) Figure 21. Operating Current vs. Temperature Rev. B | Page 11 of 24 POWER-DOWN CURRENT (nA) OPERATING CURRENT (µA) VDD OPERATING CURRENT (µA) 05792-042 05792-041 05792-033 t DELAY (ns) DSDO ZERO, GAIN ERROR (LSB) 05792-040 05792-034 AD7690 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 131,072C 65,536C 4C 2C C C MSB LSB SW– CNV IN– Figure 24. ADC Simplified Schematic CONVERTER OPERATION CIRCUIT INFORMATION The AD7690 is a successive approximation ADC based on a The AD7690 is a fast, low power, single-supply, precise, 18-bit charge redistribution DAC. Figure 24 shows the simplified ADC using a successive approximation architecture. schematic of the ADC. The capacitive DAC consists of two The AD7690 is capable of converting 400,000 samples per identical arrays of 18 binary-weighted capacitors, which are second (400 kSPS) and powers down between conversions. connected to the two comparator inputs. When operating at 1 kSPS, for example, it consumes 50 μW During the acquisition phase, terminals of the array tied to the typically, ideal for battery-powered applications. comparator’s input are connected to GND via SW+ and SW−. The AD7690 provides the user with an on-chip track-and-hold All independent switches are connected to the analog inputs. and does not exhibit pipeline delay or latency, making it ideal Thus, the capacitor arrays are used as sampling capacitors and for multiple multiplexed channel applications. acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a The AD7690 is specified from 4.75 V to 5.25 V and can be conversion phase is initiated. When the conversion phase interfaced to any 1.8 V to 5 V digital logic family. It is housed in begins, SW+ and SW− are opened first. The two capacitor a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that allows arrays are then disconnected from the inputs and connected to space savings and flexible configurations. the GND input. Therefore, the differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase It is pin-for-pin compatible with the 18-bit AD7691 and AD7982 is applied to the comparator inputs, causing the comparator to and the 16-bit AD7687, AD7688, and AD7693. become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (V /2, V /4 ... V /262,144). REF REF REF The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7690 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 12 of 24 05792-006 AD7690 Transfer Functions Table 7. Output Codes and Ideal Input Voltages The ideal transfer characteristic for the AD7690 is shown in Analog Input Digital Output Figure 25 and Table 7. Description V = 5 V Code (Hex) REF 1 FSR − 1 LSB +4.999962 V 0x1FFFF Midscale + 1 LSB +38.15 μV 0x00001 Midscale 0 V 0x00000 011...111 Midscale − 1 LSB −38.15 μV 0x3FFFF 011...110 011...101 −FSR + 1 LSB −4.999962 V 0x20001 2 −FSR −5 V 0x20000 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND TYPICAL CONNECTION DIAGRAM 100...010 100...001 Figure 26 shows an example of the recommended connection 100...000 diagram for the AD7690 when multiple supplies are available. –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function 1 V+ 5V REF 2 10µF 100nF V+ 1.8V TO VDD 100nF 15Ω REF VDD VIO 0 TO V REF SDI IN+ 2.7nF 3 ADA4841-2 SCK V– 5 AD7690 3- OR 4-WIRE INTERFACE SDO 4 V+ IN– CNV GND 15Ω V TO 0 REF 2.7nF 3 ADA4841-2 V– 4 1 SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3 SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE. Figure 26. Typical Application Diagram with Multiple Supplies Rev. B | Page 13 of 24 ADC CODE (TWOS COMPLEMENT) 05792-007 05792-008 AD7690 ANALOG INPUTS When the source impedance of the driving circuit is low, the AD7690 can be driven directly. Large source impedances Figure 27 shows an equivalent circuit of the input structure of significantly affect the ac performance, especially total the AD7690. harmonic distortion (THD). The dc performances are less The two diodes, D1 and D2, provide ESD protection for the sensitive to the input impedance. The maximum source analog inputs, IN+ and IN−. Care must be taken to ensure that impedance depends on the amount of THD that can be the analog input signal does not exceed the supply rails by more tolerated. The THD degrades as a function of the source than 0.3 V because this causes the diodes to become forward impedance and the maximum input frequency. biased and start conducting current. These diodes can handle a –80 V = VDD 5V REF forward-biased current of 130 mA maximum. For instance, these –85 conditions could eventually occur when the input buffer’s (U1) –90 supplies are different from VDD. In such a case (for example, an –95 input buffer with a short circuit), the current limitation can be 250Ω used to protect the part. –100 100Ω VDD –105 33Ω –110 D1 C IN 15Ω R IN IN+ 50Ω –115 OR IN– C PIN D2 –120 GND –125 –130 Figure 27. Equivalent Analog Input Circuit 09 10 20 30 40 50 60 70 800 FREQUENCY (kHz) The analog input structure allows the sampling of the true Figure 29. THD vs. Analog Input Frequency and Source Resistance differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. DRIVER AMPLIFIER CHOICE 90 Although the AD7690 is easy to drive, the driver amplifier must V = VDD = 5V REF meet the following requirements: 85 80 • The noise generated by the driver amplifier must be kept 75 as low as possible to preserve the SNR and transition noise 70 performance of the AD7690. The noise from the driver is filtered by the AD7690 analog input circuit’s 1-pole, low- 65 pass filter made by RIN and CIN or by the external filter, 60 if one is used. Because the typical noise of the AD7690 is 55 28 μV rms, the SNR degradation due to the amplifier is 50 ⎛ ⎞ 45 ⎜ ⎟ 28 ⎜ ⎟ 40 SNR = 20 log LOSS ⎜ ⎟ 1 10 100 1000 10000 π π 2 2 2 ⎜ ⎟ 28 + f (Ne ) + f (Ne ) ⎜ −3dB N+ −3dB N− ⎟ FREQUENCY (kHz) 2 2 ⎝ ⎠ Figure 28. Analog Input CMRR vs. Frequency where: During the acquisition phase, the impedance of the analog f is the input bandwidth in megahertz of the AD7690 −3 dB inputs (IN+ and IN−) can be modeled as a parallel combination (9 MHz) or the cutoff frequency of the input filter, if one is of the capacitor, CPIN, and the network formed by the series used. connection of RIN and CIN. CPIN is primarily the pin capacitance. N is the noise gain of the amplifier (for example, 1 in RIN is typically 600 Ω and is a lumped component composed buffer configuration). of serial resistors and the on resistance of the switches. C is IN eN+ and eN− are the equivalent input noise voltage densities typically 30 pF and is mainly the ADC sampling capacitor. of the op amps connected to IN+ and IN−, in nV/√Hz. This approximation can be used when the resistances During the conversion phase, where the switches are opened, around the amplifiers are small. If larger resistances are the input impedance is limited to C . R and C make a 1- PIN IN IN used, their noise contributions should also be root pole, low-pass filter that reduces undesirable aliasing effects and summed squared. limits the noise. Rev. B | Page 14 of 24 CMRR (dB) 05792-009 05792-036 THD (dB) 05792-047 AD7690 R5 R6 • For ac applications, the driver should have a THD performance commensurate with the AD7690. R3 R4 +5V REF 10µF • For multichannel multiplexed applications, the driver +5.2V +5.2V amplifier and the AD7690 analog input circuit must settle 100nF for a full-scale step onto the capacitor array at an 18-bit 15Ω REF VDD IN+ level (0.0004%, 4 ppm). In the amplifier’s data sheet, settling 2.7nF AD7690 at 0.1% to 0.01% is more commonly specified. This may 2.7nF 100nF IN– differ significantly from the settling time at an 18-bit level 15Ω GND and should be verified prior to driver selection. ADA4941 Table 8. Recommended Driver Amplifiers ±10V, ±5V, ... Amplifier Typical Application R1 R2 ADA4941-1 Very low noise, low power single to differential C F ADA4841-x Very low noise, small, and low power Figure 30. Single-Ended-to-Differential Driver Circuit AD8655 5 V single supply, low noise AD8021 Very low noise and high frequency VOLTAGE REFERENCE INPUT AD8022 Low noise and high frequency The AD7690 voltage reference input, REF, has a dynamic input OP184 Low power, low noise, and low frequency impedance and should therefore be driven by a low impedance AD8605, AD8615 5 V single supply, low power source with efficient decoupling between the REF and GND pins, as explained in the Layout section. SINGLE-TO-DIFFERENTIAL DRIVER When REF is driven by a very low impedance source (for For applications using a single-ended analog signal, either bipolar example, a reference buffer using the AD8031 or the AD8605), or unipolar, the ADA4941-1 single-ended-to-differential driver a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate allows for a differential input into the part. The schematic is for optimum performance. shown in Figure 30. If an unbuffered reference voltage is used, the decoupling value R1 and R2 set the attenuation ratio between the input range and depends on the reference used. For instance, a 22 μF (X5R, the ADC range (VREF). R1, R2, and CF are chosen depending on 1206 size) ceramic chip capacitor is appropriate for optimum the desired input resistance, signal bandwidth, antialiasing, and performance using a low temperature drift ADR43x reference. noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. If desired, a reference-decoupling capacitor with a value as small as 2.2 μF can be used with a minimal impact on performance, R3 and R4 set the common mode on the IN− input, and R5 and especially DNL. R6 set the common mode on the IN+ input of the ADC. The common mode should be set close to V /2; however, if single REF Regardless, there is no need for an additional lower value supply is desired, it can be set slightly above VREF/2 to provide ceramic decoupling capacitor (for example, 100 nF) between the some headroom for the ADA4941-1 output stage. For example, REF and GND pins. for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. Rev. B | Page 15 of 24 05792-010 AD7690 5V POWER SUPPLY 5V The AD7690 uses two power supply pins: a core supply, VDD, and 10Ω 5V 10kΩ a digital input/output interface supply, VIO. VIO allows a direct 10µF 1µF AD8031 interface with any logic between 1.8 V and VDD. To reduce the 1µF 1 number of supplies needed, the VIO and VDD pins can be tied together. The AD7690 is independent of power supply sequencing REF VDD VIO between VIO and VDD. Additionally, it is very insensitive to power AD7690 supply variations over a wide frequency range, as shown in Figure 31. 1 95 OPTIONAL REFERENCE BUFFER AND FILTER. Figure 33. Example of Application Circuit 90 DIGITAL INTERFACE 85 Though the AD7690 has a reduced number of pins, it offers flexibility in its serial interface modes. 80 CS When in mode, the AD7690 is compatible with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or 75 ADSP-219x. In this mode, the AD7690 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and 70 SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, 65 1 10 100 1000 10000 SCK, and SDO signals allows CNV, which initiates the conversions, FREQUENCY (kHz) to be independent of the readback timing (SDI). This is useful Figure 31. PSRR vs. Frequency in low jitter sampling or simultaneous sampling applications. The AD7690 powers down automatically at the end of each When in chain mode, the AD7690 provides a daisy-chain conversion phase and, therefore, the power scales linearly with feature using the SDI input for cascading multiple ADCs on a the sampling rate. This makes the part ideal for low sampling single data line similar to a shift register. rates (even of a few hertz) and low battery-powered applications. The mode in which the part operates depends on the SDI level 10000 when the CNV rising edge occurs. The CS mode is selected if 1000 SDI is high, and the chain mode is selected if SDI is low. The VDD = 5V SDI hold time is such that when SDI and CNV are connected 100 together, the chain mode is selected. 10 In either mode, the AD7690 offers the option of forcing a start VIO bit in front of the data bits. This start bit can be used as a busy 1 signal indicator to interrupt the digital host and trigger the data 0.1 reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. 0.01 The busy indicator feature is enabled 0.001 10 100 1k 10k 100k 1M CS • In mode if CNV or SDI is low when the ADC conversion SAMPLING RATE (SPS) ends (see Figure 37 and Figure 41). Figure 32. Operating Current vs. Sample Rate • In chain mode if SCK is high during the CNV rising edge (see Figure 45). SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7690, with its low operating current, can be supplied directly using the reference circuit shown in Figure 33. The reference line can be driven by • The system power supply directly. • A reference voltage with enough current output capability, such as the ADR43x. • A reference buffer, such as the AD8031, which can also filter the system power supply, as shown in Figure 33. Rev. B | Page 16 of 24 PSRR (dB) OPERATING CURRENT (µA) 05792-045 05792-035 05792-046 AD7690 high for the maximum possible conversion time to avoid the CS MODE, 3-WIRE WITHOUT BUSY INDICATOR generation of the busy signal indicator. When the conversion is This mode is usually used when a single AD7690 is connected complete, the AD7690 enters the acquisition phase and powers to an SPI-compatible digital host. The connection diagram is down. When CNV goes low, the MSB is output onto SDO. The shown in Figure 34, and the corresponding timing is given in remaining data bits are clocked by subsequent SCK falling Figure 35. edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the With SDI tied to VIO, a rising edge on CNV initiates a SCK falling edge allows a faster reading rate, provided it has an CS conversion, selects the mode, and forces SDO to high th acceptable hold time. After the 18 SCK falling edge or when impedance. Once a conversion is initiated, it continues until CNV goes high (whichever occurs first), SDO returns to high completion irrespective of the state of CNV. This can be useful, impedance. for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held CONVERT DIGITAL HOST CNV VIO SDI SDO DATA IN AD7690 SCK CLK CS Figure 34. 3-Wire Mode Without Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 16 17 18 t t HSDO SCKH t t t EN DSDO DIS D17 D16 D15 D1 D0 SDO Figure 35. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 17 of 24 05792-011 05792-012 AD7690 impedance to low impedance. With a pull-up on the SDO line, CS MODE, 3-WIRE WITH BUSY INDICATOR this transition can be used as an interrupt signal to initiate the This mode is usually used when a single AD7690 is connected data reading controlled by the digital host. The AD7690 then to an SPI-compatible digital host having an interrupt input. enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The The connection diagram is shown in Figure 36, and the data is valid on both SCK edges. Although the rising edge can corresponding timing is given in Figure 37. be used to capture the data, a digital host using the SCK falling With SDI tied to VIO, a rising edge on CNV initiates a edge allows a faster reading rate, provided it has an acceptable th CS hold time. After the optional 19 SCK falling edge or when conversion, selects the mode, and forces SDO to high CNV goes high (whichever occurs first), SDO returns to high impedance. SDO is maintained in high impedance until the impedance. completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to If multiple AD7690s are selected at the same time, the SDO select other SPI devices, such as analog multiplexers, but CNV output pin handles this contention without damage or induced must be returned low before the minimum conversion time latch-up. Meanwhile, it is recommended to keep this contention elapses and then held low for the maximum possible conversion as short as possible to limit extra power dissipation. time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI SDO DATA IN AD7690 SCK IRQ CLK Figure 36. 3-Wire CS Mode with Busy Indicator Connection Diagram (SDI High) SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 123 17 18 19 t t HSDO SCKH t t DSDO DIS SDO D17 D16 D1 D0 CS Mode with Busy Indicator Serial Interface Timing (SDI High) Figure 37. 3-Wire Rev. B | Page 18 of 24 05792-013 05792-014 AD7690 but SDI must be returned high before the minimum conversion CS MODE, 4-WIRE WITHOUT BUSY INDICATOR time elapses and then held high for the maximum possible This mode is usually used when multiple AD7690s are connected conversion time to avoid the generation of the busy signal to an SPI-compatible digital host. indicator. When the conversion is complete, the AD7690 enters the acquisition phase and powers down. Each ADC result can A connection diagram example using two AD7690s is shown in be read by bringing its SDI input low, which consequently Figure 38, and the corresponding timing is given in Figure 39. outputs the MSB onto SDO. The remaining data bits are clocked With SDI high, a rising edge on CNV initiates a conversion, by subsequent SCK falling edges. The data is valid on both SCK CS edges. Although the rising edge can be used to capture the data, selects the mode, and forces SDO to high impedance. In this a digital host using the SCK falling edge allows a faster reading mode, CNV must be held high during the conversion phase and th rate, provided it has an acceptable hold time. After the 18 SCK the subsequent data readback. (If SDI and CNV are low, SDO is falling edge or when SDI goes high (whichever occurs first), SDO driven low.) Prior to the minimum conversion time, SDI can be returns to high impedance and another AD7690 can be read. used to select other SPI devices, such as analog multiplexers, CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI AD7690 SDO SDI AD7690 SDO SCK SCK DATA IN CLK CS Figure 38. 4-Wire Mode Without Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 16 17 18 19 20 34 35 36 t t HSDO SCKH t t t EN DSDO DIS SDO D17 D16 D15 D1 D0 D17 D16 D1 D0 CS Figure 39. 4-Wire Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 19 of 24 05792-015 05792-016 AD7690 used to select other SPI devices, such as analog multiplexers, CS MODE, 4-WIRE WITH BUSY INDICATOR but SDI must be returned low before the minimum conversion This mode is usually used when a single AD7690 is connected time elapses and then held low for the maximum possible to an SPI-compatible digital host, which has an interrupt input, conversion time to guarantee the generation of the busy signal and it is desired to keep CNV, which is used to sample the analog indicator. When the conversion is complete, SDO goes from input, independent of the signal used to select the data reading. high impedance to low impedance. With a pull-up on the SDO This independence is particularly important in applications where line, this transition can be used as an interrupt signal to initiate low jitter on CNV is desired. the data readback controlled by the digital host. The AD7690 then enters the acquisition phase and powers down. The data The connection diagram is shown in Figure 40, and the bits are clocked out, MSB first, by subsequent SCK falling edges. corresponding timing is given in Figure 41. The data is valid on both SCK edges. Although the rising edge With SDI high, a rising edge on CNV initiates a conversion, can be used to capture the data, a digital host using the SCK selects the CS mode, and forces SDO to high impedance. In this falling edge allows a faster reading rate, provided it has an th acceptable hold time. After the optional 19 SCK falling edge or mode, CNV must be held high during the conversion phase and SDI going high (whichever occurs first), SDO returns to high the subsequent data readback. (If SDI and CNV are low, SDO is impedance. driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ SDI SDO DATA IN AD7690 SCK IRQ CLK Figure 40. 4-Wire CS Mode with Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 171819 t t HSDO SCKH t t DSDO DIS t EN SDO D17 D16 D1 D0 Figure 41. 4-Wire CS Mode with Busy Indicator Serial Interface Timing Rev. B | Page 20 of 24 05792-017 05792-018 AD7690 held high during the conversion phase and the subsequent data CHAIN MODE WITHOUT BUSY INDICATOR readback. When the conversion is complete, the MSB is output This mode can be used to daisy-chain multiple AD7690s on onto SDO and the AD7690 enters the acquisition phase and a 3-wire serial interface. This feature is useful for reducing powers down. The remaining data bits stored in the internal component count and wiring connections, for example, in shift register are clocked by subsequent SCK falling edges. For isolated multiconverter applications or for systems with a each ADC, SDI feeds the input of the internal shift register and limited interfacing capacity. Data readback is analogous to is clocked by the SCK falling edge. Each ADC in the chain clocking a shift register. outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. A connection diagram example using two AD7690s is shown in Although the rising edge can be used to capture the data, a Figure 42, and the corresponding timing is given in Figure 43. digital host using the SCK falling edge allows a faster reading When SDI and CNV are low, SDO is driven low. With SCK low, rate and consequently more AD7690s in the chain, provided the a rising edge on CNV initiates a conversion, selects the chain digital host has an acceptable hold time. The maximum conversion mode, and disables the busy indicator. In this mode, CNV is rate may be reduced due to the total readback time. CONVERT CNV CNV DIGITAL HOST AD7690 AD7690 SDI SDO SDI SDO DATA IN A B SCK SCK CLK Figure 42. Chain Mode Without Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 12 3 16 17 18 19 20 34 35 36 t t t HSCKCNV SSDISCK SCKH t t EN HSDISCK D 17 D 16 D 15 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 SDO B B B B B A A A A B Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 21 of 24 05792-019 05792-020 AD7690 subsequent data readback. When all ADCs in the chain have CHAIN MODE WITH BUSY INDICATOR completed their conversions, the SDO pin of the ADC closest to This mode can also be used to daisy-chain multiple AD7690s the digital host (see the AD7690 ADC labeled C in Figure 44) is on a 3-wire serial interface while providing a busy indicator. driven high. This transition on SDO can be used as a busy This feature is useful for reducing component count and wiring indicator to trigger the data readback controlled by the digital connections, for example, in isolated multiconverter applications host. The AD7690 then enters the acquisition phase and powers or for systems with a limited interfacing capacity. Data readback down. The data bits stored in the internal shift register are is analogous to clocking a shift register. clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and A connection diagram example using three AD7690s is shown is clocked by the SCK falling edge. Each ADC in the chain in Figure 44, and the corresponding timing is given in Figure 45. outputs its data MSB first, and 18 × N + 1 clocks are required to When SDI and CNV are low, SDO is driven low. With SCK read back the N ADCs. Although the rising edge can be used to high, a rising edge on CNV initiates a conversion, selects the capture the data, a digital host using the SCK falling edge allows chain mode, and enables the busy indicator feature. In this a faster reading rate and consequently more AD7690s in the mode, CNV is held high during the conversion phase and the chain, provided the digital host has an acceptable hold time. CONVERT CNV CNV CNV DIGITAL HOST AD7690 AD7690 AD7690 SDI SDO SDI SDO SDI SDO DATA IN A B C SCK SCK SCK IRQ CLK Figure 44. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 417 18 19 20 21 35 36 37 38 39 53 54 55 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t HSDISCK EN SDO = SDI D 17 D 16 D 15 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 17 D 16 D 15 D1D0D 17 D 16 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 17 D 16 D 15 D1D0D D 17 D 16 D1D0D 17 16 D1D 0 C C C C C B B B B A A A A Figure 45. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 22 of 24 05792-021 05792-022 AD7690 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7690 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7690, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7690 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, Figure 46. Example Layout of the AD7690 (Top Layer) the planes should be joined underneath the AD7690s. The AD7690 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the AD7690 VDD and VIO power supplies should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7690 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of a layout following these rules is shown in Figure 46 and Figure 47. EVALUATING THE AD7690’S PERFORMANCE Figure 47. Example Layout of the AD7690 (Bottom Layer) Other recommended layouts for the AD7690 are outlined in the documentation of the evaluation board (EVAL- AD7690CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. B | Page 23 of 24 05792-024 05792-023 AD7690 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA Figure 48.10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00SQ 0.50BSC 2.90 6 10 PIN1INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOPVIEW BOTTOMVIEW FORPROPERCONNECTIONOF 0.80 THEEXPOSEDPAD,REFERTO 0.05MAX 0.75 THEPINCONFIGURATIONAND 0.02NOM 0.70 FUNCTIONDESCRIPTIONS SECTIONOFTHISDATASHEET. SEATING 0.30 PLANE 0.20REF 0.25 0.20 Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE 1 Model Notes Temperature Range Package Description Package Option Branding Ordering Quantity AD7690BCPZRL –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4C Reel, 5,000 AD7690BCPZRL7 –40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 C4C Reel, 1,000 AD7690BRMZ –40°C to +85°C 10-Lead MSOP RM-10 C4C Tube, 50 AD7690BRMZ-RL7 –40°C to +85°C 10-Lead MSOP RM-10 C4C Reel, 1,000 2 EVAL-AD7690CBZ Evaluation Board 3 EVAL-CONTROL BRD2 Controller Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05792-0-7/11(B) Rev. B | Page 24 of 24 PIN1 INDICATOR (R0.15) 091709-A 121009-A