ANALOG DEVICES AD7687

16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™ Differential ADC in MSOP/QFN Data Sheet AD7687 FEATURES APPLICATION DIAGRAM 0.5V TO 5V 2.5 TO 5V 16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR) VREF Dynamic range: 96.5 dB VIO 1.8V TO VDD REF VDD 0 S/(N + D): 95.5 dB @ 20 kHz SDI IN+ SCK AD7687 3- OR 4-WIRE INTERFACE THD: −118 dB @ 20 kHz IN– (SPI, DAISY CHAIN, CS) SDO True differential analog input range VREF GND CNV ±VREF 0 0 V to V with V up to VDD on both inputs REF REF No pipeline delay Figure 2. Single-supply 2.3 V to 5.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Type 100 kSPS 250 kSPS 500 kSPS Daisy-chain multiple ADCs and BUSY indicator True Differential AD7684 AD7687 AD7688 Power dissipation Pseudo AD7683 AD7685 AD7686 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS, and Differential/Unipolar AD7694 1.4 μW @ 2.5 V/100 SPS Standby current: 1 nA Unipolar AD7680 10-lead MSOP (MSOP-8 size) and 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) GENERAL DESCRIPTION Pin-for-pin compatible with AD7685, AD7686, and AD7688 The AD7687 is a 16-bit, charge redistribution, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It APPLICATIONS contains a low power, high speed, 16-bit sampling ADC with no Battery-powered equipment missing codes, an internal conversion clock, and a versatile Data acquisitions serial interface port. The part also contains a low noise, wide Instrumentation bandwidth, short aperture delay track-and-hold circuit. On the Medical instruments CNV rising edge, it samples the voltage difference between IN+ Process controls and IN− pins. The voltages on these pins usually swing in 1.5 POSITIVE INL = +0.32LSB opposite phase between 0 V to REF. The reference voltage, REF, NEGATIVE INL = –0.41LSB is applied externally and can be set up to the supply voltage. 1.0 Its power scales linearly with throughput. 0.5 The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 0 3-wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate –0.5 supply VIO. The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN –1.0 (LFCSP) with operation specified from −40°C to +85°C. –1.5 0 16384 32768 49152 65535 CODE Figure 1. Integral Nonlinearity vs. Code Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 02972-001 02972-002 AD7687 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Driver Amplifier Choice ........................................................... 16  Applications....................................................................................... 1  Single-to-Differential Driver .................................................... 16  Application Diagram........................................................................ 1  Voltage Reference Input ............................................................ 16  General Description ......................................................................... 1  Power Supply............................................................................... 16  Revision History ............................................................................... 2  Supplying the ADC from the Reference.................................. 17  Specifications..................................................................................... 3  Digital Interface.......................................................................... 17  Timing Specifications....................................................................... 5  CS MODE 3-Wire, No BUSY Indicator .................................. 18  Absolute Maximum Ratings............................................................ 7  CS Mode 3-Wire with BUSY Indicator ................................... 19  Thermal Resistance ...................................................................... 7  CS Mode 4-Wire, No BUSY Indicator..................................... 20  ESD Caution.................................................................................. 7  CS Mode 4-Wire with BUSY Indicator ................................... 21  Pin Configurations and Function Descriptions ........................... 8  Chain Mode, No BUSY Indicator ............................................ 22  Terminology ...................................................................................... 9  Chain Mode with BUSY Indicator........................................... 23  Typical Performance Characteristics ........................................... 10  Application Hints ........................................................................... 24  Circuit Information.................................................................... 13  Layout .......................................................................................... 24  Converter Operation.................................................................. 13  Evaluating the AD7687’s Performance.................................... 24  Typical Connection Diagram ................................................... 14  Outline Dimensions....................................................................... 25  Analog Input ............................................................................... 15  Ordering Guide .......................................................................... 26  REVISION HISTORY 8/11—Rev. A to Rev. B Changes to Table 7............................................................................ 7 Changes to Ordering Guide .......................................................... 26 2/11—Rev. 0 to Rev. A Deleted QFN in Development Note............................ Throughout Changes to Table 6............................................................................ 7 Added Thermal Resistance Section and Table 7 .......................... 7 Changes to Figure 6 and Table 8..................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 4/05—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7687 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range IN+ − IN− −V +V V REF REF Absolute Input Voltage IN+, IN− −0.1 V + 0.1 V REF Common-Mode Input Range IN+, IN− 0 V/2 V /2 + 0.1 V REF REF Analog Input CMRR fIN = 250 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section ACCURACY No Missing Codes 16 Bits 1 Differential Linearity Error −1 ±0.4 +1 LSB Integral Linearity Error −1.5 ±0.4 +1.5 LSB Transition Noise REF = VDD = 5 V 0.35 LSB 2 Gain Error , TMIN to TMAX ±2 ±6 LSB Gain Error Temperature Drift ±0.3 ppm/°C 2 Offset Error , TMIN to TMAX VDD = 4.5 V to 5.5 V ±0.1 ±1.6 mV VDD = 2.3 V to 4.5 V ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ppm/°C Power Supply Sensitivity ±0.05 LSB VDD = 5 V ± 5% THROUGHPUT Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 kSPS Transient Response Full-scale step 1.8 μs AC ACCURACY 3 Dynamic Range VREF = 5 V 95.8 96.5 dB Signal-to-Noise fIN = 20 kHz, VREF = 5 V 94 95.5 dB f = 20 kHz, V = 2.5 V 92 92.5 dB IN REF Spurious-Free Dynamic Range f = 20 kHz −118 dB IN Total Harmonic Distortion f = 20 kHz −118 dB IN Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 94 95.5 dB fIN = 20 kHz, VREF = 5 V, −60 dB input 36.5 dB fIN = 20 kHz, VREF = 2.5 V 92 92.5 dB 4 Intermodulation Distortion 115 dB 1 LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV. 2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 f = 21.4 kHz, f = 18.9 kHz, each tone at −7 dB below full-scale. IN1 IN2 Rev. B | Page 3 of 28 AD7687 Data Sheet VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V = VDD, T = –40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 16-bits twos complement Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 1, 2 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 μW VDD = 2.5 V, 100 kSPS throughput 1.35 mW VDD = 2.5 V, 200 kSPS throughput 2.7 mW VDD = 5 V, 100 kSPS throughput 4 5.5 mW VDD = 5 V, 250 kSPS throughput 12.5 mW 3 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact sales for extended temperature range. Rev. B | Page 4 of 28 Data Sheet AD7687 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 0.5 2.2 μs CONV Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) t 15 ns SCK SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time t 7 ns SCKL SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS t 15 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 5 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with BUSY indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns Rev. B | Page 5 of 28 AD7687 Data Sheet −40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 5. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs Acquisition Time t 1.8 μs ACQ Time Between Conversions t 5 μs CYC t 10 ns CNV Pulse Width ( CS Mode ) CNVH SCK Period ( CS Mode ) tSCK 25 ns SCK Period ( Chain Mode ) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay t DSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 8 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 5 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with BUSY indicator) tDSDOSDI 36 ns Rev. B | Page 6 of 28 Data Sheet AD7687 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 6. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational IN+ , IN− GND − 0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute or ±130 mA maximum rating conditions for extended periods may affect REF GND − 0.3 V to VDD + 0.3 V device reliability. Supply Voltages VDD, VIO to GND −0.3 V to +7 V THERMAL RESISTANCE VDD to VIO ±7 V θ is specified for the worst-case conditions, that is, a device JA Digital Inputs to GND −0.3 V to VIO + 0.3 V soldered in a circuit board for surface-mount packages. Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Table 7. Thermal Resistance Junction Temperature 150°C Package Type θ θ Unit JA JC Lead Temperature Range JEDEC J-STD-20 10-Lead QFN (LFCSP) 84 2.96 °C/W 1 10-Lead MSOP 200 44 °C/W See the Analog Input section. ESD CAUTION 500μAI OL 1.4V TO SDO C L 50pF 500μAI OH Figure 3. Load Circuit for Digital Interface Timing 70% VIO 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V 2 2 0.8V OR 0.5V 0.8V OR 0.5V 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Rev. B | Page 7 of 28 02972-003 02972-004 AD7687 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO REF 1 10 VIO VDD 2 9 SDI AD7687 VDD 2 9SDI AD7687 IN+ 3 8 SCK TOP VIEW IN+ 3 8SCK TOP VIEW (Not to Scale) IN– 4 7 SDO (Not to Scale) IN– 4 7SDO GND 5 6 CNV GND 5 6 CNV NOTES 1. FOR THE LFCSP PACKAGE ONLY, THE EXPOSED PADDLE MUST BE CONNECTED TO GND. Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 8. Pin Function Descriptions 1 Pin No. Mnemonic Type Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and CS CS selects the interface mode, chain or . In mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD N/A For the LFCSP package only, the exposed paddle must be connected to GND. 1 AI = Analog Input, DI = Digital Input, DO = Digital Output, P = Power, and N/A = not applicable. Rev. B | Page 8 of 28 02972-005 02972-006 Data Sheet AD7687 TERMINOLOGY Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) ENOB is a measurement of the resolution with a sine wave It refers to the deviation of each individual code from a line input. It is related to S/(N+D) by the following formula drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first ENOB = (S/[N + D]dB − 1.76)/6.02 code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from Total Harmonic Distortion (THD) the middle of each code to the true straight line (Figure 26). THD is the ratio of the rms sum of the first five harmonic Differential Nonlinearity Error (DNL) components to the rms value of a full-scale input signal and is In an ideal ADC, code transitions are 1 LSB apart. DNL is the expressed in dB. maximum deviation from this ideal value. It is often specified in Dynamic Range terms of resolution for which no missing codes are guaranteed. It is the ratio of the rms value of the full scale to the total rms Zero Error noise measured with the inputs shorted together. The value for It is the difference between the ideal midscale voltage, that is, 0 dynamic range is expressed in dB. V, from the actual voltage producing the midscale output code, Signal-to-Noise Ratio (SNR) that is, 0 LSB. SNR is the ratio of the rms value of the actual input signal to the Gain Error rms sum of all other spectral components below the Nyquist The first transition (from 100 . . . 00 to 100 . . . 01) should occur frequency, excluding harmonics and dc. The value for SNR is at a level ½ LSB above nominal negative full scale (−4.999924 V expressed in dB. for the ±5 V range). The last transition (from 011…10 to Signal-to-(Noise + Distortion) Ratio (S/[N+D]) 011…11) should occur for an analog voltage 1½ LSB below the S/(N+D) is the ratio of the rms value of the actual input signal nominal full scale (+4.999771 V for the ±5 V range.) The gain to the rms sum of all other spectral components below the error is the deviation of the difference between the actual level Nyquist frequency, including harmonics but excluding dc. The of the last transition and the actual level of the first transition value for S/(N+D) is expressed in dB. from the difference between the ideal levels. Aperture Delay Spurious-Free Dynamic Range (SFDR) Aperture delay is the measure of the acquisition performance. It SFDR is the difference, in decibels (dB), between the rms is the time between the rising edge of the CNV input and when amplitude of the input signal and the peak spurious signal. the input signal is held for a conversion. Transient Response It is the time required for the ADC to accurately acquire its input after a full-scale step function was applied. Rev. B | Page 9 of 28 AD7687 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.5 POSITIVE INL = +0.32LSB POSITIVE DNL = +0.27LSB NEGATIVE INL = –0.41LSB NEGATIVE DNL = –0.24LSB 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 16384 32768 49152 65535 0 16384 32768 49152 65535 CODE CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 300000 250000 VDD = REF = 5V VDD = REF = 2.5V 258680 200403 250000 200000 200000 150000 150000 100000 100000 50000 50000 30721 29918 0 0 1049 1391 0 0 0 060 18 00 0 0 41 42 43 44 45 46 47 44 45 46 47 48 49 4A 4B 4C CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Center 0 0 8192 POINT FFT 32768 POINT FFT VDD = REF = 5V VDD = REF = 2.5V –20 –20 F = 250KSPS F = 250KSPS S S F = 2.1kHz F = 2kHz IN IN –40 –40 SNR = 95.5dB SNR = 92.8dB THD = –118.3dB THD = –115.9dB –60 –60 2nd HARM = –130dB 2nd HARM = –124dB 3rd HARM = –122.7dB 3rd HARM = –119dB –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 20 40 60 80 100 120 0 20 40 60 80 100 120 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. FFT Plot Rev. B | Page 10 of 28 COUNTS INL (LSB) AMPLITUDE (dB of Full Scale) 02972-001 02972-008 02972-007 COUNTS DNL (LSB) AMPLITUDE (dB of Full Scale) 02972-009 02972-011 02972-010 Data Sheet AD7687 100 17.0 –100 –105 SNR 95 16.0 S/[N + D] –110 ENOB 90 15.0 –115 THD SFDR –120 14.0 85 –125 70 13.0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 –130 REFERENCE VOLTAGE (V) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 REFERENCE VOLTAGE (V) Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage 100 –60 VREF = 5V, –10dB 95 –70 VREF = 2.5V, –10dB 90 –80 VREF = 5V, –1dB VREF = 2.5V, –1dB VREF = 2.5V, –1dB 85 –90 VREF = 5V, –1dB 80 –100 VREF = 2.5V, –10dB 75 –110 VREF = 5V, –10dB 70 –120 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. S/(N + D) vs. Frequency Figure 17. THD vs. Frequency 100 –90 VREF = 5V 95 –100 VREF = 2.5V VREF = 5V 90 –110 VREF = 2.5V 85 –120 80 –130 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. SNR vs. Temperature Figure 18. THD vs. Temperature Rev. B | Page 11 of 28 S/(N + D) (dB) SNR, S/(N + D) (dB) SNR (dB) ENOB (Bits) 02972-014 02972-013 02972-012 THD (dB) THD (dB) THD, SFDR (dB) 02972-017 02972-016 02972-015 AD7687 Data Sheet 100 1000 f = 100kSPS S 99 VDD = 5V 98 750 97 VDD = 2.5V VREF = 5V 96 500 95 94 VREF = 2.5V 93 250 92 91 VIO 0 90 –55 –35 –15 5 25 45 65 85 105 125 –10 –8–6–4–2 0 TEMPERATURE (°C) INPUT LEVEL (dB) Figure 19. SNR vs. Input Level Figure 22. Operating Currents vs. Temperature 1000 6 f = 100kSPS S VDD 4 750 GAIN ERROR 2 500 0 –2 OFFSET ERROR 250 –4 VIO 0 –6 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 –55 –35 –15 5 25 45 65 85 105 125 SUPPLY (V) TEMPERATURE (°C) Figure 20. Operating Currents vs. Supply Figure 23. Offset and Gain Error vs. Temperature 1000 25 20 VDD = 2.5V, 85°C 750 15 500 VDD = 2.5V, 25°C 10 VDD = 5V, 85°C 250 VDD = 5V, 25°C 5 VDD = 3.3V, 85°C VDD + VIO VDD = 3.3V, 25°C 0 0 –55 –35 –15 5 25 45 65 85 105 125 0 204060 80 100 120 TEMPERATURE (°C) SDO CAPACITIVE LOAD (pF) Figure 24. t Delay vs. Capacitance Load and Supply DSDO Figure 21. Power-Down Currents vs. Temperature Rev. B | Page 12 of 28 POWER-DOWN CURRENT (nA) OPERATING CURRENT (μA) SNR (dB) 02972-020 02972-019 02972-018 T DELAY (ns) OPERATING CURRENT (μA) OFFSET, GAIN ERROR (LSB) DSDO 02972-023 02972-022 02972-021 Data Sheet AD7687 IN+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV IN– Figure 25. ADC Simplified Schematic CONVERTER OPERATION CIRCUIT INFORMATION The AD7687 is a successive approximation ADC based on a The AD7687 is a fast, low power, single-supply, precise 16-bit charge redistribution DAC. Figure 25 shows the simplified ADC using a successive approximation architecture. schematic of the ADC. The capacitive DAC consists of two The AD7687 is capable of converting 250,000 samples per identical arrays of 16 binary weighted capacitors, which are second (250 kSPS) and powers down between conversions. connected to the two comparator inputs. When operating at 100 SPS, for example, it typically consumes During the acquisition phase, terminals of the array tied to the 1.35 μW, which is ideal for battery-powered applications. comparator’s input are connected to GND via SW+ and SW−. The AD7687 provides the user with an on-chip track-and-hold All independent switches are connected to the analog inputs. and does not exhibit any pipeline delay or latency, making it Thus, the capacitor arrays are used as sampling capacitors and ideal for multiple multiplexed channel applications. acquire the analog signal on the IN+ and IN− inputs. When the The AD7687 is specified from 2.3 V to 5.5 V and can be acquisition phase is complete and the CNV input goes high, a interfaced to any of the 1.8 V to 5 V digital logic family. It is conversion phase is initiated. When the conversion phase housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that begins, SW+ and SW− are opened first. The two capacitor combines space savings and allows flexible configurations. arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the It is pin-for-pin-compatible with the AD7685, AD7686, and inputs IN+ and IN− captured at the end of the acquisition phase AD7688. is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (V /2, V /4 . . . V /65536). REF REF REF The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7687 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 13 of 28 02972-024 AD7687 Data Sheet Transfer Functions TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7687 is shown in Figure 27 shows an example of the recommended connection Figure 26 and Table 9. diagram for the AD7687 when multiple supplies are available. 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB +FSR – 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function Table 9. Output Codes and Ideal Input Voltages Analog Input Description VREF = 5 V Digital Output Code Hexa 1 FSR – 1 LSB +4.999847 V 7FFF Midscale + 1 LSB +152.6 μV 0001 Midscale 0 V 0000 Midscale – 1 LSB −152.6 μV FFFF –FSR + 1 LSB −4.999847 V 8001 2 –FSR −5 V 8000 1 This is also the code for an overranged analog input (VIN+ − VIN− above V − V ). REF GND 2 This is also the code for an underranged analog input (VIN+ − VIN− below −V + V ). REF GND 1 ≥7V REF 5V 2 10μF 100nF ≥7V 1.8V TO VDD 100nF 33Ω REF VDD VIO 0 TO VREF SDI IN+ 3 2.7nF SCK ≤–2V 5 3- OR 4-WIRE INTERFACE AD7687 SDO 4 ≥7V IN– CNV GND 33Ω VREF TO 0 3 2.7nF ≤–2V 4 1 SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10μF CERAMIC CAPACITOR (X5R). REF 3 SEE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 27. Typical Application Diagram with Multiple Supplies Rev. B | Page 14 of 28 ADC CODE (TWOS COMPLEMENT) 02972-025 02972-026 Data Sheet AD7687 During the acquisition phase, the impedance of the analog ANALOG INPUT inputs (IN+ or IN−) can be modeled as a parallel combination Figure 28 shows an equivalent circuit of the input structure of of capacitor, C , and the network formed by the series PIN the AD7687. connection of RIN and CIN. CPIN is primarily the pin capacitance. The two diodes, D1 and D2, provide ESD protection for the RIN is typically 3 kΩ and is a lumped component made up of analog inputs IN+ and IN−. Care must be taken to ensure that some serial resistors and the on resistance of the switches. CIN is the analog input signal never exceeds the supply rails by more typically 30 pF and is mainly the ADC sampling capacitor. than 0.3 V because this causes these diodes to begin to forward- During the conversion phase, where the switches are opened, bias and start conducting current. These diodes can handle a the input impedance is limited to C . R and C make a PIN IN IN forward-biased current of 130 mA maximum. For instance, 1-pole, low-pass filter that reduces undesirable aliasing effects these conditions could eventually occur when the input buffer’s and limits the noise. (U1) supplies are different from VDD. In such a case, an input When the source impedance of the driving circuit is low, the buffer with a short-circuit current limitation can be used to AD7687 can be driven directly. Large source impedances protect the part. significantly affect the ac performance, especially total VDD harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source D1 C IN R IN+ IN impedance depends on the amount of THD that can be OR IN– tolerated. The THD degrades as a function of the source C PIN D2 impedance and the maximum input frequency, as shown in GND Figure 30. –60 Figure 28. Equivalent Analog Input Circuit The analog input structure allows the sampling of the true –70 differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected, –80 as shown in Figure 29, which represents the typical CMRR over frequency. –90 90 R = 250Ω S VDD = 5V –100 80 R = 100Ω S VDD = 2.5V –110 R = 50Ω 70 S R = 33Ω S –120 0 25 50 75 100 FREQUENCY (kHz) 60 Figure 30. THD vs. Analog Input Frequency and Source Resistance 50 40 1 10 100 1000 FREQUENCY (kHz) Figure 29. Analog Input CMRR vs. Frequency Rev. B | Page 15 of 28 CMRR (dB) 02972-027 02972-028 THD (dB) 02972-029 AD7687 Data Sheet DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER Although the AD7687 is easy to drive, the driver amplifier For applications using a single-ended analog signal, either needs to meet the following requirements: bipolar or unipolar, a single-ended-to-differential driver allows for a differential input into the part (see Figure 31 for • The noise generated by the driver amplifier needs to be the schematic). When provided a single-ended input signal, kept as low as possible in order to preserve the SNR and this configuration produces a differential ±V with midscale REF transition noise performance of the AD7687. Note that at V /2. REF the AD7687 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system perform- 590Ω ANALOG INPUT (±10V,±5V, ..) ance. The noise coming from the driver is filtered by the U1 AD7687 analog input circuit 1-pole, low-pass filter made VREF VREF by RIN and CIN or by the external filter, if one is used. 100nF 10μF Because the typical noise of the AD7687 is 53 μV rms, 590Ω the SNR degradation due to the amplifier is REF IN+ 590Ω ⎛ ⎞ AD7687 ⎜ ⎟ 53 ⎜ ⎟ SNR = 20log LOSS IN– π U2 10kΩ 2 2 ⎜ ⎟ 53 + f () 2Ne ⎜ ⎟ VREF N −3dB ⎝ 2 ⎠ 10kΩ 100nF where: Figure 31. Single-Ended-to-Differential Driver Circuit f is the input bandwidth in MHz of the AD7687 –3dB VOLTAGE REFERENCE INPUT (2 MHz) or the cutoff frequency of the input filter, if one is used. The AD7687 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance N is the noise gain of the amplifier (for example, +1 in source with efficient decoupling between the REF and GND buffer configuration). pins, as explained in the Layout section. e is the equivalent input noise voltage of the op amp, N When REF is driven by a very low impedance source, for in nV/√Hz. example, a reference buffer using the AD8031 or the AD8605, a • For ac applications, the driver should have a THD 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for performance commensurate with the AD7687. Figure 17 optimum performance. shows the THD vs. frequency that the driver should If an unbuffered reference voltage is used, the decoupling value exceed. depends on the reference used. For instance, a 22 μF (X5R, • For multichannel multiplexed applications, the driver 1206 size) ceramic chip capacitor is appropriate for optimum amplifier and the AD7687 analog input circuit must settle a performance using a low temperature drift ADR43x reference. full-scale step onto the capacitor array at a 16-bit level If desired, smaller reference decoupling capacitor values down (0.0015%, 15 ppm). In the amplifier’s data sheet, settling at to 2.2 μF can be used with a minimal impact on performance, 0.1% to 0.01% is more commonly specified. This could especially DNL. differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the Table 10. Recommended Driver Amplifiers. REF and GND pins. Amplifier Typical Application POWER SUPPLY AD8021 Very low noise and high frequency AD8022 Low noise and high frequency The AD7687 is specified over a wide operating range of 2.3 V to OP184 Low power, low noise, and low frequency 5.5 V. Unlike other low voltage converters, it has a low enough AD8605, AD8615 5 V single-supply, low power noise to design a 16-bit resolution system with low supply and AD8519 Small, low power and low frequency respectable performance. It uses two power supply pins: a core AD8031 High frequency and low power supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7687 is independent of power supply sequencing between VIO and VDD. Additionally, it is very Rev. B | Page 16 of 28 02972-030 Data Sheet AD7687 insensitive to power supply variations over a wide frequency 5V 5V range, as shown in Figure 32, which represents PSRR over frequency. 10Ω 5V 10kΩ 100 10μF 1μF AD8031 1μF 95 1 VDD = 5V 90 REF VDD VIO 85 AD7687 80 75 1 OPTIONAL REFERENCE BUFFER AND FILTER. VDD = 2.5V 70 Figure 34. Example of Application Circuit 65 DIGITAL INTERFACE 60 Though the AD7687 has a reduced number of pins, it offers 55 flexibility in its serial interface modes. 50 The AD7687, when in CS mode, is compatible with SPI, QSPI, 1 10 100 1000 10000 FREQUENCY (kHz) digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or Figure 32. PSRR vs. Frequency ADSP-219x. This interface can use either 3-wire or 4-wire. A 3- wire interface using the CNV, SCK, and SDO signals minimizes The AD7687 powers down automatically at the end of each wiring connections useful, for instance, in isolated applications. conversion phase and, therefore, the power scales linearly with A 4-wire interface using the SDI, CNV, SCK, and SDO signals the sampling rate, as shown in Figure 33. This makes the part allows CNV, which initiates the conversions, to be independent ideal for low sampling rate (even a few Hz) and low battery- of the readback timing (SDI). This is useful in low jitter powered applications. sampling or simultaneous sampling applications. The AD7687, when in chain mode, provides a daisy chain 1000 feature using the SDI input for cascading multiple ADCs on a VDD = 5V single data line similar to a shift register. VDD = 2.5V The mode in which the part operates depends on the SDI level CS 10 when the CNV rising edge occurs. The mode is selected if SDI is high and the chain mode is selected if SDI is low. The VIO SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. 0.1 In either mode, the AD7687 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and 0.001 trigger the data reading. Otherwise, without a BUSY indicator, 10 100 1000 10000 100000 1000000 the user must time out the maximum conversion time prior to SAMPLING RATE (SPS) readback. Figure 33. Operating Currents vs. Sampling Rate The BUSY indicator feature is enabled as: SUPPLYING THE ADC FROM THE REFERENCE CS • In the mode, if CNV or SDI is low when the ADC For simplified applications, the AD7687, with its low operating conversion ends (Figure 38 and Figure 42). current, can be supplied directly using the reference circuit shown in Figure 34. The reference line can be driven by either: • In the chain mode, if SCK is high during the CNV rising edge (Figure 46). • The system power supply directly • A reference voltage with enough current output capability, such as the ADR43x • A reference buffer, such as the AD8031, which can also filter the system power supply, as shown in Figure 34 Rev. B | Page 17 of 28 OPERATING CURRENT (μA) PSRR (dB) 02972-032 02972-031 02972-033 AD7687 Data Sheet to capture the data, a digital host using the SCK falling edge CS MODE 3-WIRE, NO BUSY INDICATOR allows a faster reading rate provided it has an acceptable hold This mode is usually used when a single AD7687 is connected time. After the 16th SCK falling edge or when CNV goes high, to an SPI-compatible digital host. The connection diagram is whichever is earlier, SDO returns to high impedance. shown in Figure 35 and the corresponding timing is given in Figure 36. CONVERT With SDI tied to VIO, a rising edge on CNV initiates a CS conversion, selects the mode, and forces SDO to high DIGITAL HOST CNV impedance. Once a conversion is initiated, it continues to VIO completion irrespective of the state of CNV. For instance, it SDI AD7687 SDO DATA IN could be useful to bring CNV low to select other SPI devices, SCK such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the CLK maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7687 CS Figure 35. Mode 3-Wire, No BUSY Indicator enters the acquisition phase and powers down. When CNV Connection Diagram (SDI High) goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 14 15 16 t t HSDO SCKH t t t DSDO EN DIS SDO D15 D14 D13 D1 D0 CS Figure 36. Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 02972-035 02972-034 Data Sheet AD7687 a digital host using the SCK falling edge allows a faster reading CS MODE 3-WIRE WITH BUSY INDICATOR rate provided it has an acceptable hold time. After the optional This mode is usually used when a single AD7687 is connected 17th SCK falling edge, or when CNV goes high, whichever is to an SPI-compatible digital host having an interrupt input. earlier, SDO returns to high impedance. The connection diagram is shown in Figure 37 and the If multiple AD7687s are selected at the same time, the SDO corresponding timing is given in Figure 38. output pin handles this contention without damage or induced With SDI tied to VIO, a rising edge on CNV initiates a latch-up. Meanwhile, it is recommended to keep this contention CS conversion, selects the mode, and forces SDO to high as short as possible to limit extra power dissipation. impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. CONVERT Prior to the minimum conversion time, CNV could be used to VIO select other SPI devices, such as analog multiplexers, but CNV DIGITAL HOST CNV must be returned low before the minimum conversion time and VIO 47kΩ held low until the maximum conversion time to guarantee the SDI SDO DATA IN AD7687 generation of the BUSY signal indicator. When the conversion SCK IRQ is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an CLK interrupt signal to initiate the data reading controlled by the digital host. The AD7687 then enters the acquisition phase and CS Figure 37. Mode 3-Wire with BUSY Indicator powers down. The data bits are then clocked out, MSB first, by Connection Diagram (SDI High) subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 12 3 15 16 17 t t HSDO SCKH t t DSDO DIS SDO D15 D14 D1 D0 CS Figure 38. Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 19 of 28 02972-037 02972-036 AD7687 Data Sheet time and held high until the maximum conversion time to CS MODE 4-WIRE, NO BUSY INDICATOR avoid the generation of the BUSY signal indicator. When the This mode is usually used when multiple AD7687s are conversion is complete, the AD7687 enters the acquisition connected to an SPI-compatible digital host. phase and powers down. Each ADC result can be read by A connection diagram example using two AD7687s is shown in bringing low its SDI input, which consequently outputs the Figure 39 and the corresponding timing is given in Figure 40. MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK With SDI high, a rising edge on CNV initiates a conversion, edges. Although the rising edge can be used to capture the data, CS selects the mode, and forces SDO to high impedance. In this a digital host using the SCK falling edge allows a faster reading mode, CNV must be held high during the conversion phase and rate provided it has an acceptable hold time. After the 16th SCK the subsequent data readback (if SDI and CNV are low, SDO is falling edge, or when SDI goes high, whichever is earlier, SDO driven low). Prior to the minimum conversion time, SDI could returns to high impedance and another AD7687 can be read. be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI AD7687 SDO SDI AD7687 SDO SCK SCK DATA IN CLK CS Figure 39. Mode 4-Wire, No BUSY Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 14 15 16 17 18 30 31 32 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 D15 D14 D1 D0 CS Figure 40. Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev. B | Page 20 of 28 02972-038 02972-039 Data Sheet AD7687 as an interrupt signal to initiate the data readback controlled by CS MODE 4-WIRE WITH BUSY INDICATOR the digital host. The AD7687 then enters the acquisition phase This mode is usually used when a single AD7687 is connected and powers down. The data bits are then clocked out, MSB first, to an SPI-compatible digital host, which has an interrupt input, by subsequent SCK falling edges. The data is valid on both SCK and it is desired to keep CNV, which is used to sample the edges. Although the rising edge can be used to capture the data, analog input, independent of the signal used to select the data a digital host using the SCK falling edge allows a faster reading reading. This requirement is particularly important in rate provided it has an acceptable hold time. After the optional applications where low jitter on CNV is desired. 17th SCK falling edge, or SDI going high, whichever is earlier, The connection diagram is shown in Figure 41 and the the SDO returns to high impedance. corresponding timing is given in Figure 42. CS1 With SDI high, a rising edge on CNV initiates a conversion, CONVERT selects the CS mode, and forces SDO to high impedance. In this VIO mode, CNV must be held high during the conversion phase and DIGITAL HOST CNV the subsequent data readback (if SDI and CNV are low, SDO is 47kΩ driven low). Prior to the minimum conversion time, SDI could SDI AD7687 SDO DATA IN be used to select other SPI devices, such as analog multiplexers, SCK but SDI must be returned low before the minimum conversion IRQ time and held low until the maximum conversion time to CLK guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to CS Figure 41. Mode 4-Wire with BUSY Indicator Connection Diagram low. With a pull-up on the SDO line, this transition can be used t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 12 3 15 16 17 t t HSDO SCKH t t DSDO DIS t EN SDO D15 D14 D1 D0 CS Figure 42. Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev. B | Page 21 of 28 02972-041 02972-040 AD7687 Data Sheet onto SDO and the AD7687 enters the acquisition phase and CHAIN MODE, NO BUSY INDICATOR powers down. The remaining data bits stored in the internal This mode can be used to daisy chain multiple AD7687s on a 3- shift register are then clocked by subsequent SCK falling edges. wire serial interface. This feature is useful for reducing For each ADC, SDI feeds the input of the internal shift register component count and wiring connections, for example, in and is clocked by the SCK falling edge. Each ADC in the chain isolated multiconverter applications or for systems with a outputs its data MSB first, and 16 × N clocks are required to limited interfacing capacity. Data readback is analogous to readback the N ADCs. The data is valid on both SCK edges. clocking a shift register. Although the rising edge can be used to capture the data, a A connection diagram example using two AD7687s is shown in digital host using the SCK falling edge allows a faster reading Figure 43 and the corresponding timing is given in Figure 44. rate and, consequently more AD7687s in the chain, provided the digital host has an acceptable hold time. The maximum When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain conversion rate may be reduced due to the total readback time. mode, and disables the BUSY indicator. In this mode, CNV is For instance, with a 3 ns digital host set-up time and 3 V held high during the conversion phase and the subsequent data interface, up to eight AD7687s running at a conversion rate of readback. When the conversion is complete, the MSB is output 220 kSPS can be daisy-chained on a 3-wire port. CONVERT CNV CNV DIGITAL HOST SDI AD7687 SDO SDI AD7687 SDO DATA IN A B SCK SCK CLK Figure 43. Chain Mode, No BUSY Indicator Connection Diagram SDI = 0 A t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 14 15 16 17 18 30 31 32 t t t HSCKCNV SSDISCK SCKH t t HSDISC EN D 15 D 14 D 13 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 SDO B B B B B A A A A B Figure 44. Chain Mode, No BUSY Indicator Serial Interface Timing Rev. B | Page 22 of 28 02972-042 02972-043 Data Sheet AD7687 Figure 45) SDO is driven high. This transition on SDO can be CHAIN MODE WITH BUSY INDICATOR used as a BUSY indicator to trigger the data readback controlled This mode can also be used to daisy-chain multiple AD7687s by the digital host. The AD7687 then enters the acquisition on a 3-wire serial interface while providing a BUSY indicator. phase and powers down. The data bits stored in the internal This feature is useful for reducing component count and wiring shift register are then clocked out, MSB first, by subsequent connections, for example, in isolated multiconverter SCK falling edges. For each ADC, SDI feeds the input of the applications or for systems with a limited interfacing capacity. internal shift register and is clocked by the SCK falling edge. Data readback is analogous to clocking a shift register. Each ADC in the chain outputs its data MSB first, and 16 × N + A connection diagram example using three AD7687s is shown 1 clocks are required to readback the N ADCs. Although the in Figure 45 and the corresponding timing is given in Figure 46. rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the consequently more AD7687s in the chain, provided the digital chain mode, and enables the BUSY indicator feature. In this host has an acceptable hold time. For instance, with a 3 ns mode, CNV is held high during the conversion phase and the digital host setup time and 3 V interface, up to eight AD7687s subsequent data readback. When all ADCs in the chain have running at a conversion rate of 220 kSPS can be daisy-chained completed their conversions, the near-end ADC (ADC C in to a single 3-wire port. CONVERT DIGITAL HOST CNV CNV CNV SDI AD7687 SDO SDI AD7687 SDO SDI AD7687 SDO DATA IN A B C SCK SCK SCK IRQ CLK Figure 45. Chain Mode with BUSY Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 123 415 16 17 18 19 31 32 33 34 35 47 48 49 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t EN HSDISC SDO = SDI A B D 15 D 14 D 13 D 1 D 0 A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 15 D 14 D 13 D1D0D D 15 D 14 D1D0D 15 14 D1D 0 C C C C C B B B B A A A A Figure 46. Chain Mode with BUSY Indicator Serial Interface Timing Rev. B | Page 23 of 28 02972-044 02972-045 AD7687 Data Sheet APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7687 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7687, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7687 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7687s. Figure 47. Example of Layout of the AD7687 (Top Layer) The AD7687 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connecting it with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7687 should be decoupled with ceramic capacitors (typically 100 nF) placed close to the AD7687 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of layout following these rules is shown in Figure 47 and Figure 48. EVALUATING THE AD7687’S PERFORMANCE Other recommended layouts for the AD7687 are outlined Figure 48. Example of Layout of the AD7687 (Bottom Layer) in the documentation of the evaluation board for the AD7687 (EVAL-AD7687). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. B | Page 24 of 28 02972-047 02972-046 Data Sheet AD7687 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. B | Page 25 of 28 PIN 1 INDICATOR (R 0.15) 091709-A 121009-A AD7687 Data Sheet ORDERING GUIDE Integral Transport Media, Package Package 1, 2, 3 Model Nonlinearity Temperature Range Quantity Description Option Branding AD7687BRMZ ±1.5 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C3Q AD7687BRMZRL7 ±1.5 LSB max –40°C to +85°C Reel, 1,000 10-Lead MSOP RM-10 C3Q AD7687BCPZRL ±1.5 LSB max –40°C to +85°C Reel, 5,000 10-Lead QFN (LFCSP_WD) CP-10-9 #C03 AD7687BCPZRL7 ±1.5 LSB max –40°C to +85°C Reel, 1,500 10-Lead QFN (LFCSP_WD) CP-10-9 #C03 EVAL-AD7687CBZ Evaluation Board EVAL-CONTROL BRD2Z Controller Board EVAL-CONTROL BRD3Z Controller Board 1 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked. 2 The EVAL-AD7687CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 The EVAL-CONTROL BRD2 and EVAL-CONTROL BRD3 allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. B | Page 26 of 28 Data Sheet AD7687 NOTES Rev. B | Page 27 of 28 AD7687 Data Sheet NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02972-0-8/11(B) Rev. B | Page 28 of 28