ANALOG DEVICES AD7686

16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN AD7686 FEATURES FUNCTIONAL BLOCK DIAGRAM 0.5V TO 5V 5V 16-bit resolution with no missing codes Throughput: 500 kSPS INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR) SINAD: 92.5 dB @ 20 kHz VIO 1.8V TO VDD REF VDD 0TO VREF SDI THD: −110 dB @ 20 kHz IN+ SCK AD7686 3- OR 4-WIRE INTERFACE Pseudo differential analog input range IN– (SPI, DAISY CHAIN, CS) SDO 0 V to V with V up to VDD REF REF GND CNV No pipeline delay Single-supply 5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Figure 2. Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs and busy indicator Table 1. MSOP, QFN (LFCSP)/SOT-23 Power dissipation 14-/16-/18-Bit PulSAR ADC 3.75 μW @ 5 V/100 SPS 400 kSPS 100 250 to 1000 ADC 3.75 mW @ 5 V/100 kSPS Type kSPS kSPS 500 kSPS kSPS Driver Standby current: 1 nA 18-Bit True AD7691 AD7690 AD7982 ADA4941 10-lead MSOP (MSOP-8 size) and Differential AD7982 ADA4841 3 mm × 3 mm, 10-lead QFN (LFCSP) (SOT-23 size) 16-Bit True AD7684 AD7687 AD7688 ADA4941 Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs Differential AD7693 ADA4841 16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841 APPLICATIONS Differential AD7683 AD7694 Battery-powered equipment 14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841 Data acquisitions Differential Instrumentation Medical instruments GENERAL DESCRIPTION Process controls The AD7686 is a 16-bit, charge redistribution, successive 2.0 approximation, analog-to-digital converter (ADC) that operates POSITIVE INL = +0.52LSB from a single 5 V power supply, VDD. It contains a low power, NEGATIVE INL = –0.38LSB 1.5 high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. 1.0 The part also contains a low noise, wide bandwidth, short 0.5 aperture delay track-and-hold circuit. On the CNV rising edge, the AD7686 samples an analog input IN+ between 0 V to REF 0 with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage. –0.5 Power dissipation scales linearly with throughput. –1.0 The SPI-compatible serial interface also features the ability, –1.5 using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus or provides an optional busy indicator. This device is –2.0 0 16384 32768 49152 65535 compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate CODE supply VIO. Figure 1. Integral Nonlinearity vs. Code The AD7686 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 02969-007 02969-002 AD7686 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 15 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 15 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 15 General Description ......................................................................... 1 Supplying the ADC from the Reference.................................. 16 Revision History ............................................................................... 2 Digital Interface.......................................................................... 16 Specifications..................................................................................... 3 CS MODE 3-Wire, No Busy Indicator .................................... 17 Timing Specifications....................................................................... 5 CS Mode 3-Wire with Busy Indicator ..................................... 18 Absolute Maximum Ratings............................................................ 6 CS Mode 4-Wire, No Busy Indicator....................................... 19 ESD Caution.................................................................................. 6 CS Mode 4-Wire with Busy Indicator ..................................... 20 Pin Configurations and Function Descriptions ........................... 7 Chain Mode, No Busy Indicator .............................................. 21 Terminology ...................................................................................... 8 Chain Mode with Busy Indicator............................................. 22 Typical Performance Characteristics ............................................. 9 Application Hints ........................................................................... 23 Theory of Operation ...................................................................... 12 Layout .......................................................................................... 23 Circuit Information.................................................................... 12 Evaluating Performance ............................................................ 23 Converter Operation.................................................................. 12 True 16-Bit Isolated Application Example.............................. 24 Typical Connection Diagram ................................................... 13 Outline Dimensions ....................................................................... 25 Analog Input ............................................................................... 14 Ordering Guide .......................................................................... 26 REVISION HISTORY 3/07—Rev. A to Rev. B 4/06—Rev. 0 to Rev. A Changes to Features and Table 1 .................................................... 1 Updated Format..................................................................Universal Changes to Table 3............................................................................ 4 Updated Outline Dimensions....................................................... 25 Moved Figure 3 and Figure 4 to Page............................................. 5 Changes to Ordering Guide .......................................................... 26 Changes to Figure 13 and Figure 15............................................. 10 4/05—Revision 0: Initial Version Changes to Figure 26...................................................................... 13 Changes to Table 8.......................................................................... 15 Changes to Figure 31...................................................................... 16 Changes to Figure 42...................................................................... 21 Changes to Figure 44...................................................................... 22 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 Rev. B | Page 2 of 28 AD7686 SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. B Grade C Grade Parameter Conditions Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ANALOG INPUT Voltage Range IN+ − IN− 0 V 0 V V REF REF Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V IN− −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR fIN = 200 kHz 65 65 dB Leakage Current @ 25°C Acquisition phase 1 1 nA Input Impedance See the Analog Input See the Analog Input section section ACCURACY No Missing Codes 16 16 Bits 1 Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB 1 Integral Linearity Error −3 ±1 +3 −2 ±0.6 +2 LSB 1 Transition Noise REF = VDD = 5 V 0.5 0.45 LSB 2 1 Gain Error , T to T ±2 ±8 ±2 ±6 LSB MIN MAX Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C 2 Offset Error , T to T ±0.1 ±1.6 ±0.1 ±1.6 mV MIN MAX Offset Temperature Drift ±0.3 ±0.3 ppm/°C 1 Power Supply Sensitivity ±0.05 ±0.05 LSB VDD = 5 V ± 5% THROUGHPUT Conversion Rate 0 500 0 500 kSPS Transient Response Full-scale step 400 400 ns AC ACCURACY 3 Signal-to-Noise Ratio fIN = 20 kHz, VREF = 5 V 89 92 91 92.7 dB 2 fIN = 20 kHz, VREF = 2.5 V 87.5 88 dB 2 Spurious-Free Dynamic Range f = 20 kHz −106 −110 dB IN 2 Total Harmonic Distortion f = 20 kHz −106 −110 dB IN 2 Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 5 V 89 92 91 92.5 dB 2 fIN = 20 kHz, VREF = 5 V, −60 dB input 32 33.5 dB 4 2 Intermodulation Distortion −110 −115 dB 1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV. 2 See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 f = 21.4 kHz, f = 18.9 kHz, each tone at −7 dB below full scale. IN1 IN2 Rev. B | Page 3 of 28 AD7686 VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V = VDD, T = –40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 500 kSPS, REF = 5 V 100 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 9 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V –0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 16 bits straight binary Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 4.5 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 1, 2 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V, 100 SPS throughput 3.75 μW VDD = 5 V, 100 kSPS throughput 3.75 4.3 mW VDD = 5 V, 500 kSPS throughput 15 21.5 mW 3 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact sales for extended temperature range. Rev. B | Page 4 of 28 AD7686 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 0.5 1.6 μs CONV Acquisition Time tACQ 400 ns Time Between Conversions tCYC 2 μs CNV Pulse Width ( CS Mode) tCNVH 10 ns SCK Period (CS Mode) t 15 ns SCK SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time t 7 ns SCKL SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t 5 ns HSCKCNV SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 70% VIO 500µA I OL 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V TO SDO 1.4V 2 2 0.8V OR 0.5V 0.8V OR 0.5V C L 50pF 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. 500µA I OH Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. B | Page 5 of 28 02969-003 02969-004 AD7686 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational IN+ , IN− GND − 0.3 V to VDD + 0.3 V or ±130 mA section of this specification is not implied. Exposure to absolute REF GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V ESD CAUTION Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance 200°C/W (MSOP-10) JA θ Thermal Impedance 44°C/W (MSOP-10) JC Lead Temperature JEDEC J-STD-20 1 See the Analog Input section. Rev. B | Page 6 of 28 AD7686 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO REF 1 10 VIO VDD 2 9SDI AD7686 VDD 2 9 SDI IN+ 3 AD7686 8SCK TOP VIEW IN+ 3 8 SCK TOP VIEW IN– 4 7SDO (Not to Scale) (Not to Scale) IN– 4 7 SDO GND 5 6CNV GND 5 6 CNV Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to V . REF 4 IN− AI Analog Input Ground Sense. It is connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is completed, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. B | Page 7 of 28 02969-005 02969-006 AD7686 TERMINOLOGY Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) ENOB is a measurement of the resolution with a sine wave INL refers to the deviation of each individual code from a line input. It is related to SINAD by drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first ENOB = (SINADdB − 1.76)/6.02 code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from Total Harmonic Distortion (THD) the middle of each code to the true straight line (see Figure 25). THD is the ratio of the rms sum of the first five harmonic Differential Nonlinearity Error (DNL) components to the rms value of a full-scale input signal and is In an ideal ADC, code transitions are 1 LSB apart. DNL is the expressed in dB. maximum deviation from this ideal value. It is often specified in Signal-to-Noise Ratio (SNR) terms of resolution for which no missing codes are guaranteed. SNR is the ratio of the rms value of the actual input signal to the Offset Error rms sum of all other spectral components below the Nyquist The first transition should occur at a level ½ LSB above analog frequency, excluding harmonics and dc. The value for SNR is ground (38.1 μV for the 0 V to 5 V range). The offset error is expressed in dB. the deviation of the actual transition from that point. Signal-to-(Noise + Distortion), SINAD Gain Error SINAD is the ratio of the rms value of the actual input signal to The last transition (from 111 . . . 10 to 111 . . . 11) should occur the rms sum of all other spectral components below the Nyquist for an analog voltage 1½ LSB below the nominal full scale frequency, including harmonics but excluding dc. The value for (4.999886 V for the 0 V to 5 V range). The gain error is the SINAD is expressed in dB. deviation of the actual level of the last transition from the ideal Aperture Delay level after the offset is adjusted out. It is the measure of the acquisition performance and is the time Spurious-Free Dynamic Range (SFDR) between the rising edge of the CNV input and when the input SFDR is the difference, in decibels (dB), between the rms signal is held for a conversion. amplitude of the input signal and the peak spurious signal. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 8 of 28 AD7686 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 POSITIVE INL = +0.52LSB POSITIVE DNL = +0.35LSB NEGATIVE INL = –0.38LSB NEGATIVE DNL = –0.36LSB 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 16384 32768 49152 65535 0 16384 32768 49152 65535 CODE CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 250000 160000 VDD = REF = 5V VDD = REF = 5V 140000 133575 202719 124164 200000 120000 100000 150000 80000 100000 60000 40000 50000 30770 27583 20000 00 26 22 00 0 0 1703 1678 0 0 0 0 8026 8027 8028 8029 802A 802B 802C 802D 802E 8024 8025 8026 8027 8028 8029 802A 802B CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Transition 0 95 –105 8192 POINT FFT VDD = REF = 5V –20 f = 500kSPS S f = 19.99kHz IN 94 –108 –40 SNR = 92.8dB THD = –108.7dB THD –60 SECOND HARMONIC = –110.1dB THIRD HARMONIC = –119.2dB 93 –111 –80 SNR –100 92 –114 –120 –140 91 –117 –160 –180 90 –120 0 20 40 60 80 100 120 140 160 180 200 220 240 –10 –8–6–4–2 0 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 9. FFT Plot Figure 12. SNR and THD vs. Input Level Rev. B | Page 9 of 28 COUNTS INL (LSB) AMPLITUDE (dB OF FULL SCALE) 02969-009 02969-007 02969-008 SNR (dB) COUNTS DNL (LSB) 02969-010 02969-011 THD (dB) 02969-012 AD7686 100 17.0 –90 –95 95 16.0 –100 THD SNR –105 SINAD SFDR 90 15.0 –110 ENOB –115 14.0 –120 85 –125 70 13.0 –130 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage 100 –90 VREF = 5V VREF = 5V 95 –100 90 –110 85 –120 80 –130 –55 –35 –15 5 25456585 105 125 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. SNR vs. Temperature Figure 17. THD vs. Temperature 100 –60 95 –70 VREF = 5V, –10dB 90 –80 VREF = 5V, –1dB 85 VREF = 5V, –1dB –90 80 –100 75 –110 VREF = 5V, –10dB 70 –120 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. SINAD vs. Frequency Figure 18. THD vs. Frequency Rev. B | Page 10 of 28 SNR, SINAD (dB) SINAD (dB) SNR (dB) 02969-015 02969-014 ENOB (Bits) 02969-013 THD (dB) THD (dB) THD, SFDR (dB) 02969-018 02969-017 02969-016 AD7686 1000 4 f = 100kSPS S 3 VDD 750 2 OFFSET ERROR 1 500 –0 GAIN ERROR –1 250 –2 –3 VIO 0 –4 4.50 4.75 5.00 5.25 5.50 –55 –35 –15 5 25 45 65 85 105 125 SUPPLY (V) TEMPERATURE (°C) Figure 19. Operating Currents vs. Supply Figure 22. Offset and Gain Error vs. Temperature 1000 25 20 750 15 500 VDD = 5V, 85°C 10 VDD = 5V, 25°C 250 5 VDD + VIO 0 0 –55 –35 –15 5 25 45 65 85 105 125 0 2040 6080 100 120 TEMPERATURE (°C) SDO CAPACITIVE LOAD (pF) Figure 20. Power-Down Currents vs. Temperature Figure 23. tDSDO Delay vs. Capacitance Load and Supply 1000 f = 100kSPS S VDD = 5V 750 500 250 VIO 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 21. Operating Currents vs. Temperature Rev. B | Page 11 of 28 OPERATING CURRENTS (µA) POWER-DOWN CURRENTS (nA) OPERATING CURRENTS (µA) 02969-021 02969-020 02969-019 T DELAY (ns) OFFSET, GAIN ERROR (LSB) DSDO 02969-023 02969-022 AD7686 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV IN– Figure 24. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7686 is a fast, low power, single-supply, precise 16-bit The AD7686 is a successive approximation ADC based on a ADC using a successive approximation architecture. charge redistribution DAC. Figure 24 shows a simplified schematic of the ADC. The capacitive DAC consists of two The AD7686 is capable of converting 500,000 samples per identical arrays of 16 binary weighted capacitors, which are second (500 kSPS) and powers down between conversions. connected to two comparator inputs. For example, when operating at 100 SPS, the device consumes 3.75 μW typically, which is ideal for battery-powered During the acquisition phase, terminals of the array tied to the applications. comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. The AD7686 provides the user with on-chip, track-and-hold Therefore, the capacitor arrays are used as sampling capacitors and does not exhibit any pipeline delay or latency, making it and acquire the analog signal on the IN+ and IN− inputs. When ideal for multiple, multiplexed channel applications. the acquisition phase is complete and the CNV input goes high, The AD7686 is specified from 4.5 V to 5.5 V and can be a conversion phase initiates. When the conversion phase begins, interfaced to any of the 1.8 V to 5 V digital logic family. It is SW+ and SW− are opened first. housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that The two capacitor arrays are then disconnected from the inputs combines space savings and allows flexible configurations. and connected to the GND input. Therefore, the differential This device is pin-for-pin-compatible with the AD7685, voltage between the inputs IN+ and IN−, captured at the end of AD7687, and AD7688. the acquisition phase, is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a busy signal indicator. Because the AD7686 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 12 of 28 02969-024 AD7686 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Analog Input Digital Output Code The ideal transfer characteristic for the AD7686 is shown in Description V = 5 V Hexadecimal REF Figure 25 and Table 7. 1 FSR – 1 LSB 4.999924 V FFFF Midscale + 1 LSB 2.500076 V 8001 Midscale 2.5 V 8000 111...111 Midscale – 1 LSB 2.499924 V 7FFF 111...110 111...101 –FSR + 1 LSB 76.3 μV 0001 2 –FSR 0 V 0000 TYPICAL CONNECTION DIAGRAM Figure 26 shows an example of the recommended connection diagram for the AD7686 when multiple supplies are available. 000...010 000...001 1 000...000 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). –FSR 2 –FSR + 1 LSB This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND +FSR – 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function 1 ≥7V REF 5V 2 10µF 100nF 1.8V TO VDD ≥7V 100nF REF VDD VIO 33Ω SDI IN+ 0 TO VREF SCK 5 3 3- OR 4-WIRE INTERFACE 2.7nF AD7686 SDO ≤–2V IN– CNV 4 GND 1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3 SEE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5 SEE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE. Figure 26. Typical Application Diagram with Multiple Supplies Rev. B | Page 13 of 28 ADC CODE (STRAIGHT BINARY) 02969-025 02969-026 AD7686 During the acquisition phase, the impedance of the analog ANALOG INPUT inputs (IN+ or IN−) can be modeled as a parallel combination Figure 27 shows an equivalent circuit of the input structure of capacitor, C , and the network formed by the series PIN of the AD7686. The two diodes, D1 and D2, provide ESD connection of RIN and CIN. CPIN is primarily the pin capacitance. protection for the analog inputs IN+ and IN−. Care must be RIN is typically 600 Ω and is a lumped component made up of taken to ensure that the analog input signal never exceeds the some serial resistors and the on resistance of the switches. CIN is supply rails by more than 0.3 V because this causes these typically 30 pF and is mainly the ADC sampling capacitor. diodes to begin to forward-bias and start conducting current. During the conversion phase, where the switches are opened, These diodes can handle a forward-biased current of 130 mA the input impedance is limited to C . R and C make a PIN IN IN maximum. For instance, these conditions could eventually 1-pole, low-pass filter that reduces undesirable aliasing effects occur when the input buffer’s (U1) supplies are different from and limits the noise. VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. When the source impedance of the driving circuit is low, the AD7686 can be driven directly. Large source impedances VDD significantly affect the ac performance, especially THD. The dc D1 C IN R IN performances are less sensitive to the input impedance. The IN+ OR IN– maximum source impedance depends on the amount of THD C PIN D2 that can be tolerated. The THD degrades as a function of the GND source impedance and the maximum input frequency, as shown in Figure 29. Figure 27. Equivalent Analog Input Circuit –80 The analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this –85 differential input, small signals common to both inputs are rejected, as shown in Figure 28, which represents the typical –90 CMRR over frequency. For instance, by using IN− to sense a remote signal ground, ground potential differences between –95 the sensor and the local ADC ground are eliminated. R = 250Ω S 80 –100 –105 R = 100Ω S 70 R = 50Ω S R = 33Ω S –110 VDD = 5V 025 50 75 100 FREQUENCY (kHz) 60 Figure 29. THD vs. Analog Input Frequency and Source Resistance 50 40 1 10 100 1000 10000 FREQUENCY (kHz) Figure 28. Analog Input CMRR vs. Frequency Rev. B | Page 14 of 28 CMRR (dB) 02969-028 02969-027 THD (dB) 02969-030 AD7686 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Although the AD7686 is easy to drive, the driver amplifier The AD7686 voltage reference input, REF, has a dynamic input should meet the following requirements: impedance and should, therefore, be driven by a low impedance source with efficient decoupling between the REF and GND • The noise generated by the driver amplifier needs to be pins, as explained in the Layout section. kept as low as possible to preserve the SNR and transition When REF is driven by a very low impedance source, such as a noise performance of the AD7686. Note that the AD7686 reference buffer using the AD8031 or the AD8605, a 10 μF has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. to meet a given system noise specification. The noise coming from the amplifier is filtered by the AD7686 analog If an unbuffered reference voltage is used, the decoupling value input circuit 1-pole, low-pass filter made by RIN and CIN or depends on the reference used. For instance, a 22 μF (X5R, by the external filter, if one is used. Because the typical 1206 size) ceramic chip capacitor is appropriate for optimum noise of the AD7686 is 37 μV rms, the SNR degradation performance using a low temperature drift ADR43x reference. due to the amplifier is If desired, smaller reference decoupling capacitor values down ⎛ ⎞ to 2.2 μF can be used with a minimal impact on performance, ⎜ ⎟ 37 especially DNL. ⎜ ⎟ SNR = 20log LOSS ⎜ ⎟ π 2 2 Regardless, there is no need for an additional lower value 37 + f (Ne ) ⎜ ⎟ −3dB N 2 ⎝ ⎠ ceramic decoupling capacitor, such as 100 nF, between the REF and GND pins. where: POWER SUPPLY f is the input bandwidth in MHz of the AD7686 –3dB (9 MHz) or the cutoff frequency of the input filter, if The AD7686 is specified at 4.5 V to 5.5 V. The device uses two one is used. power supply pins: a core supply VDD and a digital input/ output interface supply VIO. VIO allows direct interface with N is the noise gain of the amplifier (for example, 1 in buffer any logic between 1.8 V and VDD. To reduce the supplies configuration). needed, the VIO and VDD can be tied together. e is the equivalent input noise voltage of the op amp, N The AD7686 is independent of power supply sequencing in nV/√Hz. between VIO and VDD. Additionally, it is very insensitive to • For ac applications, the driver should have a THD power supply variations over a wide frequency range, as shown performance commensurate with the AD7686. Figure 18 in Figure 30, which represents PSRR over frequency. shows the THD vs. frequency that the driver should exceed. 110 • For multichannel multiplexed applications, the driver 100 amplifier and the AD7686 analog input circuit must settle a 90 full-scale step onto the capacitor array at a 16-bit level (0.0015%). In the data sheet for the amplifier, settling at 80 VDD = 5V 0.1% to 0.01% is more commonly specified. This could 70 differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. 60 Table 8. Recommended Driver Amplifiers 50 Amplifier Typical Application 40 ADA4841-x Very low noise and low power AD8605, AD8615 5 V single-supply, low power 30 1 10 100 1000 10000 AD8655 5 V single-supply, low power FREQUENCY (kHz) OP184 Low power, low noise, and low frequency Figure 30. PSRR vs. Frequency AD8021 Very low noise and high frequency AD8022 Very low noise and high frequency AD8519 Small, low power and low frequency AD8031 High frequency and low power Rev. B | Page 15 of 28 PSRR (dB) 02969-031 AD7686 The AD7686 powers down automatically at the end of each DIGITAL INTERFACE conversion phase and, therefore, the power scales linearly with Though the AD7686 has a reduced number of pins, it offers the sampling rate, as shown in Figure 31. This makes the part flexibility in its serial interface modes. ideal for low sampling rates (even a few Hz) and low battery- CS The AD7686, when in mode, is compatible with SPI, QSPI, powered applications. digital hosts, and DSPs, such as Blackfin® ADSP-BF53x or 10000 ADSP-219x. This interface can use either 3-wire or 4-wire. A 1000 3-wire interface using the CNV, SCK, and SDO signals VDD = 5V minimizes wiring connections useful, for instance, in isolated 100 applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be 10 VIO independent of the readback timing (SDI). This is useful in low 1 jitter sampling or simultaneous sampling applications. The AD7686, when in chain mode, provides a daisy-chain 0.1 feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. 0.01 The mode in which the part operates depends on the SDI level 0.001 10 100 1000 10000 100000 1000000 when the CNV rising edge occurs. The CS mode is selected if SAMPLING RATE (SPS) SDI is high, and the chain mode is selected if SDI is low. The Figure 31. Operating Currents vs. Sampling Rate SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7686, with its low operating In either mode, the AD7686 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be current, can be supplied directly using the reference circuit shown in Figure 32. The reference line can be driven by either: used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, • The system power supply directly. the user must timeout the maximum conversion time prior to • A reference voltage with enough current output capability, readback. such as the ADR43x. The busy indicator feature is enabled as follows: • A reference buffer, such as the AD8031, which can also CS • In mode, if CNV or SDI is low when the ADC conversion filter the system power supply, as shown in Figure 32. ends (see Figure 36 and Figure 40). 5V • In chain mode, if SCK is high during the CNV rising edge 5V (see Figure 44). 10Ω 5V 10kΩ 10µF 1µF AD8031 1µF 1 REF VDD VIO AD7686 1 OPTIONAL REFERENCE BUFFER AND FILTER. Figure 32. Example of Application Circuit Rev. B | Page 16 of 28 OPERATING CURRENTS (µA) 02969-033 02969-032 AD7686 The data is valid on both SCK edges. Although the rising edge CS MODE 3-WIRE, NO BUSY INDICATOR can be used to capture the data, a digital host using the SCK This mode is most often used when a single AD7686 is falling edge allows a faster reading rate provided it has an connected to an SPI-compatible digital host. The connection acceptable hold time. After the 16th SCK falling edge, or when diagram is shown in Figure 33, and the corresponding timing is CNV goes high, whichever occurs first, SDO returns to high provided in Figure 34. impedance. With SDI tied to VIO, a rising edge on CNV initiates a CS conversion, selects the mode, and forces SDO to high CONVERT impedance. Once a conversion is initiated, it continues to DIGITAL HOST CNV completion irrespective of the state of CNV. For instance, it VIO could be useful to bring CNV low to select other SPI devices, SDI AD7686 SDO DATA IN such as analog multiplexers. However, CNV must be returned SCK high before the minimum conversion time and held high until the maximum conversion time to avoid generating the busy CLK signal indicator. When the conversion is complete, the AD7686 enters the acquisition phase and powers down. When CNV CS Figure 33. Mode 3-Wire, No Busy Indicator Connection Diagram (SDI High) goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 12 3 14 15 16 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 Figure 34. CS Mode 3-Wire, No Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 17 of 28 02969-035 02969-034 AD7686 Although the rising edge can be used to capture the data, a CS MODE 3-WIRE WITH BUSY INDICATOR digital host using the SCK falling edge allows a faster reading This mode is generally used when a single AD7686 is connected rate, provided it has an acceptable hold time. After the optional to an SPI-compatible digital host having an interrupt input. The 17th SCK falling edge or when CNV goes high, whichever connection diagram is shown in Figure 35, and the correspond- occurs first, SDO returns to high impedance. ing timing is provided in Figure 36. If multiple AD7686s are selected at the same time, the SDO With SDI tied to VIO, a rising edge on CNV initiates a output pin handles this connection without damage or induced CS conversion, selects the mode, and forces SDO to high latch-up. Meanwhile, it is recommended to keep this connection as impedance. SDO is maintained in high impedance until the short as possible to limit extra power dissipation. completion of the conversion, irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to CONVERT select other SPI devices, such as analog multiplexers. However, VIO DIGITAL HOST CNV must be returned low before the minimum conversion CNV VIO 47kΩ time and held low until the maximum conversion time to SDI SDO DATA IN AD7686 guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. SCK IRQ With a pull-up on the SDO line, this transition can be used as CLK an interrupt signal to initiate the data reading controlled by the digital host. The AD7686 then enters the acquisition phase and Figure 35. CS Mode 3-Wire with Busy Indicator powers down. The data bits are then clocked out, MSB first, by Connection Diagram (SDI High) subsequent SCK falling edges. The data is valid on both SCK edges. SDI = 1 t CYC t CNVH CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 15 16 17 t t HSDO SCKH t t DSDO DIS SDO D15 D14 D1 D0 CS Figure 36. Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 02969-037 02969-036 AD7686 avoid the generation of the busy signal indicator. When the CS MODE 4-WIRE, NO BUSY INDICATOR conversion is complete, the AD7686 enters the acquisition This mode is generally used when multiple AD7686s are phase and powers down. Each ADC result can be read by connected to an SPI-compatible digital host. A connection bringing its SDI input low, which consequently outputs the MSB diagram example using two AD7686 devices is shown in onto SDO. The remaining data bits are then clocked by Figure 37, and the corresponding timing is given in Figure 38. subsequent SCK falling edges. The data is valid on both SCK With SDI high, a rising edge on CNV initiates a conversion, edges. Although the rising edge can be used to capture the data, CS selects the mode, and forces SDO to high impedance. In this a digital host using the SCK falling edge allows a faster reading mode, CNV must be held high during the conversion phase and rate, provided it has an acceptable hold time. After the 16th the subsequent data readback (if SDI and CNV are low, SDO is SCK falling edge or when SDI goes high, whichever occurs first, driven low). Prior to the minimum conversion time, SDI could SDO returns to high impedance and another AD7686 can be used to select other SPI devices, such as analog multiplexers. be read. but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI SDO SDI SDO AD7686 AD7686 SCK SCK DATA IN CLK Figure 37. CS Mode 4-Wire, No Busy Indicator Connection Diagram t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 14 15 16 17 18 30 31 32 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 D15 D14 D1 D0 CS Figure 38. Mode 4-Wire, No Busy Indicator Serial Interface Timing Rev. B | Page 19 of 28 02969-038 02969-039 AD7686 With a pull-up on the SDO line, this transition can be used as CS MODE 4-WIRE WITH BUSY INDICATOR an interrupt signal to initiate the data readback controlled by This mode is usually used when a single AD7686 is connected the digital host. The AD7686 then enters the acquisition phase to an SPI-compatible digital host, which has an interrupt input, and powers down. The data bits are then clocked out, MSB first, and when it is desired to keep CNV, which is used to sample the by subsequent SCK falling edges. The data is valid on both SCK analog input, independent of the signal used to select the data edges. Although the rising edge can be used to capture the data, reading. This requirement is particularly important in applications a digital host using the SCK falling edge allows a faster reading where low jitter on CNV is desired. The connection diagram is rate, provided it has an acceptable hold time. After the optional shown in Figure 39, and the corresponding timing is provided 17th SCK falling edge or SDI going high, whichever occurs first, in Figure 40. the SDO returns to high impedance. With SDI high, a rising edge on CNV initiates a conversion, CS1 selects the CS mode, and forces SDO to high impedance. In this CONVERT mode, CNV must be held high during the conversion phase and VIO the subsequent data readback (if SDI and CNV are low, SDO is DIGITAL HOST CNV driven low). Prior to the minimum conversion time, SDI can be 47kΩ SDI SDO DATA IN AD7686 used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion SCK IRQ time and held low until the maximum conversion time to CLK guarantee the generation of the busy signal indicator. When conversion is complete, SDO goes from high impedance to low. Figure 39. CS Mode 4-Wire with Busy Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 151617 t t HSDO SCKH t t DSDO DIS t EN SDO D15 D14 D1 D0 CS Figure 40. Mode 4-Wire with Busy Indicator Serial Interface Timing Rev. B | Page 20 of 28 02969-041 02969-040 AD7686 When the conversion is complete, the MSB is output onto SDO, CHAIN MODE, NO BUSY INDICATOR and the AD7686 enters the acquisition phase and powers down. This mode can be used to daisy-chain multiple AD7686s on a The remaining data bits stored in the internal shift register are 3-wire serial interface. This feature is useful for reducing then clocked by subsequent SCK falling edges. For each ADC, component count and wiring connections, for example, in SDI feeds the input of the internal shift register and is clocked isolated multiconverter applications or for systems with a by the SCK falling edge. Each ADC in the chain outputs its data limited interfacing capacity. Data readback is analogous to MSB first, and 16 × N clocks are required to read back the N clocking a shift register. ADCs. The data is valid on both SCK edges. Although the rising A connection diagram example using two AD7686s is shown in edge can be used to capture the data, a digital host using the Figure 41, and the corresponding timing is given in Figure 42. SCK falling edge allows a faster reading rate and, consequently, more AD7686s in the chain, provided the digital host has an When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain acceptable hold time. The maximum conversion rate can be mode, and disables the busy indicator. In this mode, CNV is reduced due to the total readback time. For instance, with a 3 ns held high during the conversion phase and the subsequent data digital host setup time and 3 V interface, up to four AD7686s readback. running at a conversion rate of 360 kSPS can be daisy-chained on a 3-wire port. CONVERT CNV CNV DIGITAL HOST SDI SDO SDI SDO DATA IN AD7686 AD7686 A B SCK SCK CLK Figure 41. Chain Mode, No Busy Indicator Connection Diagram SDI = 0 A t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 14 15 16 17 18 303132 t t t HSCKCNV SSDISCK SCKH t t HSDISCK EN D 15 D 14 D 13 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 SDO B B B B B A A A A B Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing Rev. B | Page 21 of 28 02969-042 02969-043 AD7686 This transition on SDO can be used as a busy indicator to CHAIN MODE WITH BUSY INDICATOR trigger the data readback controlled by the digital host. The This mode can be used to daisy-chain multiple AD7686s AD7686 then enters the acquisition phase and powers down. on a 3-wire serial interface while providing a busy indicator. The data bits stored in the internal shift register are then This feature is useful for reducing component count and clocked out, MSB first, by subsequent SCK falling edges. For wiring connections, for example, in isolated multiconverter each ADC, SDI feeds the input of the internal shift register and applications or for systems with a limited interfacing capacity. is clocked by the SCK falling edge. Each ADC in the chain Data readback is analogous to clocking a shift register. A outputs its data MSB first, and 16 × N + 1 clocks are required to connection diagram example using three AD7686s is shown in readback the N ADCs. Figure 43, and the corresponding timing is given in Figure 44. Although the rising edge can be used to capture the data, a When SDI and CNV are low, SDO is driven low. With SCK digital host using the SCK falling edge allows a faster reading high, a rising edge on CNV initiates a conversion, selects the rate and, consequently, more AD7686s in the chain, provided chain mode, and enables the busy indicator feature. In this the digital host has an acceptable hold time. For instance, mode, CNV is held high during the conversion phase and the with a 3 ns digital host setup time and 3 V interface, up to four subsequent data readback. When all ADCs in the chain have AD7686s running at a conversion rate of 360 kSPS can be daisy completed their conversions, the nearend ADC (ADC C in chained to a single 3-wire port. Figure 43) SDO is driven high. CONVERT CNV CNV CNV DIGITAL HOST DATA IN SDI AD7686 SDO SDI AD7686 SDO SDI AD7686 SDO A B C SCK SCK SCK IRQ CLK Figure 43. Chain Mode with Busy Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 415 16 17 18 19 31 32 33 34 35 47 48 49 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t EN HSDISCK SDO = SDI A B D 15 D 14 D 13 D 1 D 0 A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI B C D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 B B B B B A A A A t t DSDOSDI DSDOSDI SDO D 15 D 14 D 13 D1D0D D 15 D 14 D1D0D 15 14 D1D 0 C C C C C C B B B B A A A A Figure 44. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 22 of 28 02969-044 02969-045 AD7686 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7686 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7686, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because doing so couples noise onto the die, unless a ground plane under the AD7686 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the devices. Figure 45. Example of Layout of the AD7686 (Top Layer) The AD7686 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connecting it with wide, low impedance traces. Finally, the AD7686 power supplies VDD and VIO should be decoupled with ceramic capacitors (typically 100 nF) placed close to the AD7686 and connected using short and wide traces. This provides low impedance paths and reduces the effect of glitches on the power supply lines. Examples of layouts that follow these rules are shown in Figure 45 and Figure 46. EVALUATING PERFORMANCE Other recommended layouts for the AD7686 are outlined in the documentation of the evaluation board (EVAL-AD7686CB). Figure 46. Example of Layout of the AD7686 (Bottom Layer) The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the universal evaluation control board (EVAL-CONTROL BRD3). Rev. B | Page 23 of 28 02969-047 02969-046 AD7686 This skew is the channel-to-channel matching propagation TRUE 16-BIT ISOLATED APPLICATION EXAMPLE delay of the digital isolator (t ). This allows running the PSKCD In applications where high accuracy and isolation are required, serial interface at the maximum speed of the digital isolator such as power monitoring, motor control, and some medical (45 Mbps for the ADuM1402C), which would have been equipment, the circuit shown in Figure 47, using the AD7686 otherwise limited by the cascade of the propagation delays of and the ADuM1402C digital isolator, provides a compact and the digital isolator. For instance, four AD7686 devices running high performance solution. at 330 kSPS can be chained together. Multiple AD7686 devices are daisy-chained to reduce the The complete analog chain runs on a single 5 V supply using number of signals to isolate. Note that the SCKOUT, which is a the ADR391 low dropout reference voltage and the rail-to-rail readback of the AD7686 clock, has a very short skew with the CMOS AD8618 amplifier while offering true bipolar input range. DATA signal. 5V V , V V , V 2.7V TO 5V DD1 E1 DD2 E2 100nF 100nF GND GND 5V REF 5V 1 2 V V 10µF 100nF IA OA DATA 4kΩ 1kΩ ±10V INPUT V V 5V IB OB REF VDD VIO SDO SCKOUT SCK IN+ AD7686 CNV V V OC IC 2V REF SCKIN IN– GND SDI 1/4 AD8618 V V OD ID CONVERT 5V REF 5V 10µF 100nF ADuM1402C 4kΩ 1kΩ ±10V INPUT 5V REF VDD VIO SDO SCK IN+ AD7686 CNV 2V REF SDI IN– GND 1/4 AD8618 5V REF 5V 10µF 100nF 1kΩ 4kΩ ±10V INPUT 5V REF VDD VIO SDO SCK 1kΩ 1kΩ IN+ AD7686 CNV 2V REF 5V IN– GND SDI 1/4 AD8618 5V REF 5V REF 5V ADR391 1kΩ 10µF 100nF 5V IN OUT 2V REF 4kΩ 1kΩ ±10V INPUT GND 4kΩ 5V REF VDD VIO SDO SCK 10μF 100nF IN+ AD7686 CNV 2V REF IN– GND SDI 1/4 AD8618 Figure 47. A True 16-Bit Isolated Simultaneous Sampling Acquisition System Rev. B | Page 24 of 28 02969-048 AD7686 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.40 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters INDEX AREA 3.00 PIN 1 BSC SQ INDICATOR 1 10 1.50 BSC SQ 0.50 2.48 EXPOSED BSC 2.38 PAD TOP VIEW (BOT TOM VIEW) 2.23 6 5 0.50 1.74 0.40 1.64 0.80 MAX PADDLE CONNECTED TO GND. 0.30 0.80 1.49 0.55 TYP THIS CONNECTION IS NOT 0.75 REQUIRED TO MEET THE 0.05 MAX SIDE VIEW 0.70 ELECTRICAL PERFORMANCES 0.02 NOM SEATING 0.30 0.20 REF PLANE 0.23 0.18 Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. B | Page 25 of 28 022207-A AD7686 ORDERING GUIDE Integral Ordering Model Nonlinearity Temperature Range Quantity Package Description Package Option Branding 1 AD7686BCPZRL ±3 LSB max –40°C to +85°C Reel, 5000 10-Lead QFN (LFCSP_WD) CP-10-9 C02# 1 AD7686BCPZRL7 ±3 LSB max –40°C to +85°C Reel, 1500 10-Lead QFN (LFCSP_WD) CP-10-9 C02# AD7686BRM ±3 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C02 AD7686BRMRL7 ±3 LSB max –40°C to +85°C Reel, 1000 10-Lead MSOP RM-10 C02 1 AD7686BRMZ ±3 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C3N 1 AD7686BRMZRL7 ±3 LSB max –40°C to +85°C Reel, 1000 10-Lead MSOP RM-10 C3N 1 AD7686CCPZRL ±2 LSB max –40°C to +85°C Reel, 5000 10-Lead QFN (LFCSP_WD) CP-10-9 C2G# 1 AD7686CCPZRL7 ±2 LSB max –40°C to +85°C Reel, 1500 10-Lead QFN (LFCSP_WD) CP-10-9 C2G# AD7686CRM ±2 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C2G AD7686CRMRL7 ±2 LSB max –40°C to +85°C Reel, 1000 10-Lead MSOP RM-10 C2G 1 AD7686CRMZ ±2 LSB max –40°C to +85°C Tube, 50 10-Lead MSOP RM-10 C3P 1 AD7686CRMZRL7 ±2 LSB max –40°C to +85°C Reel, 1000 10-Lead MSOP RM-10 C3P 2 EVAL-AD7686CB Evaluation Board 1, 2 EVAL-AD7686CBZ Evaluation Board 3 EVAL-CONTROL BRD2 Controller Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = RoHS Compliant Part, # denotes RoHS Compliant product may be top or bottom marked. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. B | Page 26 of 28 AD7686 NOTES Rev. B | Page 27 of 28 AD7686 NOTES ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02969-0-3/07(B) Rev. B | Page 28 of 28