ANALOG DEVICES AD7685

16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN AD7685 FEATURES APPLICATION DIAGRAM 0.5V TO VDD 2.5V TO 5V 16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR) SINAD: 93.5 dB @ 20 kHz VIO 1.8V TO VDD REF VDD 0 TO VREF SDI THD: −110 dB @ 20 kHz IN+ SCK AD7685 3- OR 4-WIRE INTERFACE Pseudo differential analog input range IN– (SPI, DAISY CHAIN, CS) SDO 0 V to V with V up to VDD REF REF GND CNV No pipeline delay Single-supply operation 2.3 V to 5.5 V with 1.8 V to 5 V logic interface Figure 2. Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs, BUSY indicator Table 1. MSOP, QFN (LFCSP)/SOT-23 Power dissipation 14-/16-/18-Bit PulSAR ADC 1.4 μW @ 2.5 V/100 SPS 400 kSPS 100 250 to 1000 ADC 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS Type kSPS kSPS 500 kSPS kSPS Driver Standby current: 1 nA 18-Bit True AD7691 AD7690 AD7982 ADA4941 10-lead package: MSOP (MSOP-8 size) and Differential AD7982 ADA4841 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) 16-Bit True AD7684 AD7687 AD7688 ADA4941 Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs Differential AD7693 ADA4841 16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841 APPLICATIONS Differential AD7683 AD7694 14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841 Battery-powered equipment Differential Medical instruments Mobile communications GENERAL DESCRIPTION Personal digital assistants (PDAs) Data acquisition The AD7685 is a 16-bit, charge redistribution successive Instrumentation approximation, analog-to-digital converter (ADC) that operates Process controls from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no 2.0 POSITIVE INL = +0.33LSB missing codes, an internal conversion clock, and a versatile serial NEGATIVE INL = –0.50LSB 1.5 interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising 1.0 edge, it samples an analog input IN+ between 0 V to REF with 0.5 respect to a ground sense IN−. The reference voltage, REF, is 0 applied externally and can be set up to the supply voltage. Power dissipation scales linearly with throughput. –0.5 The SPI-compatible serial interface also features the ability, –1.0 using the SDI input, to daisy chain several ADCs on a single –1.5 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the –2.0 0 16384 32768 49152 65536 separate supply VIO. CODE The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN Figure 1. Integral Nonlinearity vs. Code. (LFCSP) with operation specified from −40°C to +85°C. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 02968-005 02968-001 AD7685 TABLE OF CONTENTS Features .............................................................................................. 1  Driver Amplifier Choice ........................................................... 16  Applications....................................................................................... 1  Voltage Reference Input ............................................................ 16  Application Diagram........................................................................ 1  Power Supply............................................................................... 16  General Description ......................................................................... 1  Supplying the ADC from the Reference.................................. 17  Revision History ............................................................................... 2  Digital Interface.......................................................................... 17  Specifications..................................................................................... 3  CS Mode 3-Wire, No BUSY Indicator..................................... 18  Timing Specifications....................................................................... 5  CS Mode 3-Wire with BUSY Indicator ................................... 19  Absolute Maximum Ratings............................................................ 7  CS Mode 4-Wire, No BUSY Indicator..................................... 20  ESD Caution.................................................................................. 7  CS Mode 4-Wire with BUSY Indicator ................................... 21  Pin Configuration and Function Descriptions............................. 8  Chain Mode, No BUSY Indicator ............................................ 22  Terminology ...................................................................................... 9  Chain Mode with BUSY Indicator........................................... 23  Typical Performance Characteristics ........................................... 10  Application Hints ........................................................................... 24  Theory of Operation ...................................................................... 13  Layout .......................................................................................... 24  Circuit Information.................................................................... 13  Evaluating the Performance of the AD7685............................... 24  Converter Operation.................................................................. 13  True 16-Bit Isolated Application Example.............................. 25  Typical Connection Diagram ................................................... 14  Outline Dimensions....................................................................... 26  Analog Inputs.............................................................................. 15  Ordering Guide .......................................................................... 27  REVISION HISTORY 12/04—Rev. 0 to Rev. A 8/11—Rev. B to Rev. C Changes to Figure 6 and Table 7..................................................... 8 Changes to Specifications.................................................................3 Updated Outline Dimensions ....................................................... 26 Changes to Figure 17 Captions..................................................... 11 Changes to Ordering Guide .......................................................... 27 Changes to Power Supply Section ................................................ 17 Changes to Digital Interface Section ........................................... 18 3/07—Rev. A to Rev. B Changes to CS Mode 4-Wire No Busy Indicator Section ......... 21 Changes to Features and Table 1 .................................................... 1 Changes to CS Mode 4-Wire with Busy Indicator Section....... 22 Changes to Table 3............................................................................ 4 Changes to Chain Mode, No Busy Indicator Section................ 23 Moved Figure 3 and Figure 4 to Page............................................. 6 Changes to Chain Mode with Busy Indicator Section .............. 24 Inserted Figure 6; Renumbered Sequentially................................ 8 Added True 16-Bit Isolated Application Example Section ....... 26 Changes to Figure 13 and Figure 14............................................. 11 Added Figure 47 ............................................................................. 26 Changes to Figure 27...................................................................... 14 Changes to Ordering Guide .......................................................... 28 Changes to Table 9.......................................................................... 16 Changes to Figure 32...................................................................... 17 4/04—Revision 0: Initial Revision Changes to Figure 43...................................................................... 22 Changes to Figure 45...................................................................... 23 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 Rev. C | Page 2 of 28 AD7685 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. A Grade B Grade C Grade Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 16 16 16 Bits ANALOG INPUT Voltage Range IN+ − IN− 0 VREF 0 VREF 0 VREF V Absolute Input Voltage IN+ −0.1 VDD + −0.1 VDD + −0.1 VDD + V 0.1 0.1 0.1 IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR f = 250 kHz 65 65 65 dB IN Leakage Current at 25°C Acquisition phase 1 1 1 nA Input Impedance See the See the See the Analog Inputs section Analog Inputs section Analog Inputs section ACCURACY No Missing Codes 15 16 16 Bits 1 Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB 2 Gain Error , T to T ±2 ±30 ±2 ±30 ±2 ±15 LSB MIN MAX Gain Error Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C 2 Offset Error , TMIN to TMAX VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB THROUGHPUT Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS Transient Response Full-scale step 1.8 1.8 1.8 μs AC ACCURACY 3 Signal-to-Noise Ratio fIN = 20 kHz, 90 90 92 91.5 93.5 dB V = 5 V REF fIN = 20 kHz, 86 86 88 87.5 88.5 dB V = 2.5 V REF Spurious-Free Dynamic f = 20 kHz −100 −106 −110 dB IN Range Total Harmonic Distortion f = 20 kHz −100 −106 −110 dB IN Signal-to-(Noise + Distortion) fIN = 20 kHz, 89 90 92 91.5 93.5 dB V = 5 V REF f = 20 kHz, 32 33.5 dB IN VREF = 5 V, −60 dB input fIN = 20 kHz, 86 85.5 87.5 87 88.5 dB VREF = 2.5 V 4 Intermodulation Distortion −110 −115 dB 1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV. 2 See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 f = 21.4 kHz, f = 18.9 kHz, each tone at −7 dB below full scale. IN1 IN2 Rev. C | Page 3 of 28 AD7685 VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V = VDD, T = –40°C to +85°C, unless otherwise noted. REF A Table 3. Parameter Conditions Min Typ Max Unit REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 μA SAMPLING DYNAMICS −3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns DIGITAL INPUTS Logic Levels V –0.3 0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS Data Format Serial 16 bits straight binary Pipeline Delay Conversion results available immediately after completed conversion V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V 1, 2 Standby Current VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 μW VDD = 2.5 V, 100 kSPS throughput 1.35 2.4 mW VDD = 2.5 V, 200 kSPS throughput 2.7 4.8 mW VDD = 5 V, 100 kSPS throughput 4 6 mW VDD = 5 V, 250 kSPS throughput 10 15 mW 3 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With all digital inputs forced to VIO or GND as required. 2 During acquisition phase. 3 Contact sales for extended temperature range. Rev. C | Page 4 of 28 AD7685 TIMING SPECIFICATIONS −40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. 1 Table 4. VDD = 4.5 V to 5.5 V Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge To Data Available t 0.5 2.2 μs CONV Acquisition Time t 1.8 μs ACQ Time Between Conversions tCYC 4 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) t SCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time t 7 ns SCKH SCK Falling Edge to Data Remains Valid t 5 ns HSDO SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns t CNV or SDI Low to SDO D15 MSB Valid (CS Mode) EN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) t 15 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 3 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t DSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns 1 See Figure 3 and Figure 4 for load conditions. Rev. C | Page 5 of 28 AD7685 −40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. 1 Table 5. VDD = 2.3V to 4.5 V Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs Acquisition Time t 1.8 μs ACQ Time Between Conversions t 5 μs CYC CNV Pulse Width (CS Mode) t 10 ns CNVH SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time t 12 ns SCKL SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t 25 ns DIS SDI Valid Setup Time from CNV Rising Edge (CS Mode) t 30 ns SSDICNV SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t 5 ns SSDISCK SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t 4 ns HSDISCK SDI High to SDO High (Chain Mode with Busy Indicator) t 36 ns DSDOSDI 1 See Figure 3 and Figure 4 for load conditions. 70% VIO 500µA I OL 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V TO SDO 1.4V 2 2 0.8V OR 0.5V 0.8V OR 0.5V C L 50pF NOTES 1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 500µA I 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. OH Figure 4. Voltage Levels for Timing Figure 3. Load Circuit for Digital Interface Timing Rev. C | Page 6 of 28 02968-002 02968-003 AD7685 ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational IN+ , IN− , REF GND − 0.3 V to VDD + 0.3 V or ±130 mA section of this specification is not implied. Exposure to absolute Supply Voltages maximum rating conditions for extended periods may affect VDD, VIO to GND −0.3 V to +7 V device reliability. VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V ESD CAUTION Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θ Thermal Impedance 44°C/W (MSOP-10) JC Lead Temperature Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 See the Analog Inputs section. Rev. C | Page 7 of 28 AD7685 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9SDI AD7685 IN+ 3 8SCK TOP VIEW (Not to Scale) IN– 4 7SDO REF 1 10 VIO GND 5 6CNV VDD 2 9 SDI AD7685 IN+ 3 8 SCK TOP VIEW NOTES (Not to Scale) IN– 4 7 SDO 1. EXPOSED PAD CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET GND 5 6 CNV THE ELECTRICAL PERFORMANCES. Figure 5. 10-Lead MSOP Pin Configuration Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Table 7. Pin Function Descriptions 1 Pin No Mnemonic Type Description 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to V . REF 4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD Exposed Pad. Exposed pad connected to GND. This connection is not required to meet the electrical performances. 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 28 02968-004 02968-005 AD7685 TERMINOLOGY Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) ENOB is a measurement of the resolution with a sine wave INL refers to the deviation of each individual code from a line input. It is related to SINAD by drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first ENOB = (SINADdB − 1.76)/6.02 code transition. Positive full scale is defined as a level 1½ LSB and is expressed in bits. beyond the last code transition. The deviation is measured from Total Harmonic Distortion (THD) the middle of each code to the true straight line (see Figure 26). THD is the ratio of the rms sum of the first five harmonic Differential Nonlinearity Error (DNL) components to the rms value of a full-scale input signal and is In an ideal ADC, code transitions are 1 LSB apart. DNL is the expressed in dB. maximum deviation from this ideal value. It is often specified in Signal-to-Noise Ratio (SNR) terms of resolution for which no missing codes are guaranteed. SNR is the ratio of the rms value of the actual input signal to the Offset Error rms sum of all other spectral components below the Nyquist The first transition should occur at a level ½ LSB above analog frequency, excluding harmonics and dc. The value for SNR is ground (38.1 μV for the 0 V to 5 V range). The offset error is expressed in dB. the deviation of the actual transition from that point. Signal-to-(Noise + Distortion), SINAD Gain Error SINAD is the ratio of the rms value of the actual input signal to The last transition (from 111 . . . 10 to 111 . . . 11) should the rms sum of all other spectral components below the Nyquist occur for an analog voltage 1½ LSB below the nominal full frequency, including harmonics but excluding dc. The value for scale (4.999886 V for the 0 V to 5 V range). The gain error is the SINAD is expressed in dB. deviation of the actual level of the last transition from the ideal Aperture Delay level after the offset is adjusted out. Aperture delay is a measure of the acquisition performance and Spurious-Free Dynamic Range (SFDR) is the time between the rising edge of the CNV input and when The difference, in decibels (dB), between the rms amplitude of the input signal is held for a conversion. the input signal and the peak spurious signal. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. C | Page 9 of 28 AD7685 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 POSITIVE INL = +0.33LSB POSITIVE DNL = +0.21LSB NEGATIVE INL = –0.50LSB NEGATIVE DNL = –0.30LSB 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 250000 140000 VDD = REF = 5V VDD = REF = 2.5V 125055 204292 120000 200000 100000 150000 80000 60966 59082 60000 100000 40000 50000 29041 27755 20000 8667 6956 00 12 20 00 02 213 179 0 0 0 0 80E5 80E6 80E7 80E8 80E9 80EA 80EB 80EC 80ED 804E 804F 8050 8051 8052 8053 8054 8055 8056 8057 8058 CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Center 0 0 8192 POINT FFT 16384 POINT FFT VDD = REF = 5V VDD = REF = 2.5V –20 –20 f = 250kSPS S f = 250kSPS S f = 20.45kHz IN f = 20.45kHz –40 IN –40 SNR = 93.3dB SNR = 88.8dB THD = –111.6dB THD = –103.5dB –60 SFDR = –113.7dB –60 SFDR = –104.5dB SECOND HARMONIC = –113.7dB SECOND HARMONIC = –112.4dB THIRD HARMONIC = –117.6dB –80 –80 THIRD HARMONIC = –105.4dB –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 20406080 100 120 0 204060 80 100 120 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. FFT Plot Rev. C | Page 10 of 28 COUNTS AMPLITUDE (dB OF FULL SCALE) INL (LSB) 02968-007 02968-047 02968-006 COUNTS AMPLITUDE (dB OF FULL SCALE) DNL (LSB) 02968-010 02968-008 02968-009 AD7685 100 –90 17 –95 SNR 95 16 –100 –105 SINAD 90 15 –110 THD ENOB –115 SFDR 85 14 –120 –125 80 13 –130 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD, SFDR vs. Reference Voltage 100 –60 95 –70 V = 5V, –10dB REF V = 5V, –1dB REF 90 –80 V = 5V, –1dB REF V = 2.5V, –1dB REF 85 –90 V = 2.5V, –1dB REF 80 –100 V = 5V, –10dB REF 75 –110 70 –120 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. SINAD vs. Frequency Figure 17. THD vs. Frequency 100 –90 95 V = 5V REF –100 V = 2.5V 90 REF V = 2.5V REF 85 –110 V = 5V REF 80 –120 75 70 –130 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. SNR vs. Temperature Figure 18. THD vs. Temperature Rev. C | Page 11 of 28 SINAD (dB) SNR (dB) SINAD (dB) 02968-013 02968-012 ENOB (Bits) 02968-011 THD (dB) THD (dB) THD, SFDR (dB) 02968-016 02968-015 02968-014 AD7685 95 1000 –105 f = 100kSPS S VDD = 5V 94 750 SNR –110 93 VDD = 2.5V 500 92 THD –115 250 91 VIO 90 –120 0 –10 –8 –6 –4 –2 0 –55 –35 –15 5 25 45 65 85 105 125 INPUT LEVEL (dB) TEMPERATURE (°C) Figure 19. SNR and THD vs. Input Level Figure 22. Operating Currents vs. Temperature 6 1000 5 f = 100kSPS S 4 3 750 VDD 2 1 OFFSET ERROR 0 500 –1 –2 GAIN ERROR –3 250 –4 –5 VIO –6 0 –55 –35 –15 5 25 45 65 85 105 125 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TEMPERATURE (°C) SUPPLY (V) Figure 23. Offset and Gain Error vs. Temperature Figure 20. Operating Currents vs. Supply 25 1000 VDD = 2.5V, 85°C 20 750 15 VDD = 2.5V, 25°C 500 10 VDD = 5V, 85°C 250 VDD = 5V, 25°C 5 VDD = 3.3V, 85°C VDD = 3.3V, 25°C VDD + VIO 0 0 020 40 60 80 100 120 –55 –35 –15 5 25 45 65 85 105 125 SDO CAPACITIVE LOAD (pF) TEMPERATURE (°C) Figure 24. tDSDO Delay vs. Capacitance Load and Supply Figure 21. Power-Down Currents vs. Temperature Rev. C | Page 12 of 28 SNR REFERENCE TO FULL SCALE (dB) POWER-DOWN CURRENTS (nA) OPERATING CURRENTS (µA) 02968-019 02968-018 THD (dB) 02968-017 t DELAY (ns) OFFSET, GAIN ERROR (LSB) OPERATING CURRENTS (µA) DSDO 02968-022 02968-021 02968-020 AD7685 THEORY OF OPERATION IN+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV IN– Figure 25. ADC Simplified Schematic CONVERTER OPERATION CIRCUIT INFORMATION The AD7685 is a successive approximation ADC based on a The AD7685 is a fast, low power, single-supply, precise 16-bit charge redistribution DAC. Figure 25 shows the simplified ADC using a successive approximation architecture. schematic of the ADC. The capacitive DAC consists of two The AD7685 is capable of converting 250,000 samples per identical arrays of 16 binary weighted capacitors, which are second (250 kSPS) and powers down between conversions. connected to the two comparator inputs. When operating at 100 SPS, for example, it consumes typically During the acquisition phase, terminals of the array tied to the 1.35 μW with a 2.5 V supply, ideal for battery-powered comparator’s input are connected to GND via SW+ and SW−. applications. All independent switches are connected to the analog inputs. The AD7685 provides the user with on-chip, track-and-hold Therefore, the capacitor arrays are used as sampling capacitors and does not exhibit any pipeline delay or latency, making it and acquire the analog signal on the IN+ and IN− inputs. When ideal for multiple multiplexed channel applications. the acquisition phase is complete and the CNV input goes high, The AD7685 is specified from 2.3 V to 5.5 V and can be a conversion phase is initiated. When the conversion phase interfaced to any 1.8 V to 5 V digital logic family. It is housed in begins, SW+ and SW− are opened first. The two capacitor a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines arrays are then disconnected from the inputs and connected to space savings and allows flexible configurations. the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase It is pin-for-pin-compatible with the AD7686, AD7687, and is applied to the comparator inputs, causing the comparator to AD7688. become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part powers down and returns to the acquisition phase, and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7685 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. C | Page 13 of 28 02968-023 AD7685 Transfer Functions TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7685 is shown in Figure 27 shows an example of the recommended connection Figure 26 and Table 8. diagram for the AD7685 when multiple supplies are available. 111...111 111...110 111...101 000...010 000...001 000...000 –FS –FS + 1 LSB +FS – 1 LSB –FS + 0.5 LSB +FS – 1.5 LSB ANALOG INPUT Figure 26. ADC Ideal Transfer Function 1 ≥7V REF 5V 2 10µF 100nF 1.8V TO VDD ≥7V 100nF REF VDD VIO 33Ω SDI IN+ 0 TO VREF SCK 5 3 3- OR 4-WIRE INTERFACE 2.7nF AD7685 SDO ≤–2V IN– CNV 4 GND NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 27. Typical Application Diagram with Multiple Supplies Table 8. Output Codes and Ideal Input Voltages Description Analog Input V = 5 V Digital Output Code Hexa REF 1 FSR – 1 LSB 4.999924 V FFFF Midscale + 1 LSB 2.500076 V 8001 Midscale 2.5 V 8000 Midscale – 1 LSB 2.499924 V 7FFF –FSR + 1 LSB 76.3 μV 0001 2 –FSR 0 V 0000 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (V − V below V ). IN+ IN− GND Rev. C | Page 14 of 28 ADC CODE (STRAIGHT BINARY) 02968-024 02968-025 AD7685 During the acquisition phase, the impedance of the analog ANALOG INPUTS inputs (IN+ or IN−) can be modeled as a parallel combination Figure 28 shows an equivalent circuit of the input structure of of capacitor C and the network formed by the series connection PIN the AD7685. of RIN and CIN. CPIN is primarily the pin capacitance. RIN is The two diodes, D1 and D2, provide ESD protection for the typically 3 kΩ and is a lumped component made up of some analog inputs IN+ and IN−. Care must be taken to ensure that serial resistors and the on resistance of the switches. CIN is the analog input signal never exceeds the supply rails by more typically 30 pF and is mainly the ADC sampling capacitor. than 0.3 V because this will cause these diodes to begin to During the conversion phase, where the switches are opened, forward-bias and start conducting current. These diodes can the input impedance is limited to C . R and C make a PIN IN IN handle a forward-biased current of 130 mA maximum. For 1-pole, low-pass filter that reduces undesirable aliasing effects instance, these conditions could eventually occur when the and limits the noise. input buffer’s (U1) supplies are different from VDD. In such a When the source impedance of the driving circuit is low, the case, an input buffer with a short-circuit current limitation can AD7685 can be driven directly. Large source impedances be used to protect the part. significantly affect the ac performance, especially THD. The dc VDD performances are less sensitive to the input impedance. The D1 maximum source impedance depends on the amount of THD C IN R IN+ IN OR IN– that can be tolerated. The THD degrades as a function of the C PIN D2 source impedance and the maximum input frequency, as shown GND in Figure 30. –60 Figure 28. Equivalent Analog Input Circuit This analog input structure allows the sampling of the –70 differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are –80 rejected, as shown in Figure 29, which represents the typical CMRR over frequency. For instance, by using IN− to sense a –90 remote signal ground, ground potential differences between R = 250Ω S –100 the sensor and the local ADC ground are eliminated. R = 100Ω S 80 R = 50Ω –110 S R = 33Ω S –120 70 V = 5V 0 255075 100 DD FREQUENCY (kHz) Figure 30. THD vs. Analog Input Frequency and Source Resistance V = 2.5V DD 60 50 40 1 10 100 1000 10000 FREQUENCY (kHz) Figure 29. Analog Input CMRR vs. Frequency Rev. C | Page 15 of 28 CMRR (dB) 02968-027 02968-026 THD (dB) 02968-028 AD7685 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Although the AD7685 is easy to drive, the driver amplifier The AD7685 voltage reference input, REF, has a dynamic input needs to meet the following requirements: impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND • The noise generated by the driver amplifier needs to be kept pins, as explained in the Layout section. as low as possible to preserve the SNR and transition noise When REF is driven by a very low impedance source, for performance of the AD7685. Note that the AD7685 has a example, a reference buffer using the AD8031 or the AD8605, a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. system noise specification. The noise coming from the amplifier is filtered by the AD7685 analog input circuit low- If an unbuffered reference voltage is used, the decoupling value pass filter made by RIN and CIN or by an external filter, if one depends on the reference used. For instance, a 22 μF (X5R, is used. Because the typical noise of the AD7685 is 35 μV 1206 size) ceramic chip capacitor is appropriate for optimum rms, the SNR degradation due to the amplifier is performance using a low temperature drift ADR43x reference. ⎛ ⎞ If desired, smaller reference decoupling capacitor values down ⎜ ⎟ 35 to 2.2 μF can be used with a minimal impact on performance, ⎜ ⎟ SNR = 20log LOSS ⎜ ⎟ especially DNL. π 2 2 ⎜ 35 + f (Ne ) ⎟ N −3dB 2 ⎝ ⎠ POWER SUPPLY where: The AD7685 is specified over a wide operating range from f is the input bandwidth in MHz of the AD7685 –3dB 2.3 V to 5.5 V. It has, unlike other low voltage converters, a (2 MHz) or the cutoff frequency of the input filter, if one is noise low enough to design a 16-bit resolution system with low used. supply and respectable performance. It uses two power supply N is the noise gain of the amplifier (for example, 1 in buffer pins: a core supply VDD and a digital input/output interface configuration). supply VIO. VIO allows direct interface with any logic between eN is the equivalent input noise voltage of the op amp, in 1.8 V and VDD. To reduce the number of supplies needed, the nV/√Hz. VIO and VDD can be tied together. The AD7685 is independent of power supply sequencing between VIO and VDD. Additionally, • For ac applications, the driver should have a THD it is very insensitive to power supply variations over a wide performance commensurate with the AD7685. Figure 17 frequency range, as shown in Figure 31, which represents PSRR shows the AD7685’s THD vs. frequency. over frequency. • For multichannel, multiplexed applications, the driver 110 amplifier and the AD7685 analog input circuit must settle a 100 full-scale step onto the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 90 0.01% is more commonly specified. This could differ VDD = 5V 80 significantly from the settling time at a 16-bit level and should be verified prior to driver selection. 70 VDD = 2.5V Table 9. Recommended Driver Amplifiers 60 Amplifier Typical Application 50 ADA4841-x Very low noise and low power 40 AD8605, AD8615 5 V single-supply, low power AD8655 5 V single-supply, low power 30 1 10 100 1000 10000 OP184 Low power, low noise, and low frequency FREQUENCY (kHz) AD8021 Very low noise and high frequency Figure 31. PSRR vs. Frequency AD8022 Very low noise and high frequency AD8519 Small, low power and low frequency AD8031 High frequency and low power Rev. C | Page 16 of 28 PSRR (dB) 02968-029 AD7685 The AD7685 powers down automatically at the end of each DIGITAL INTERFACE conversion phase and, therefore, the power scales linearly with Though the AD7685 has a reduced number of pins, it offers the sampling rate, as shown in Figure 32. This makes the part substantial flexibility in its serial interface modes. ideal for low sampling rate (even a few Hz) and low battery- The AD7685, when in CS mode, is compatible with SPI, QSPI, powered applications. digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or 10000 ADSP-219x. This interface can use either 3-wire or 4-wire. A 1000 3-wire interface using the CNV, SCK, and SDO signals minimizes VDD = 5V VDD = 2.5V wiring connections, useful, for instance, in isolated applications. 100 A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent 10 of the readback timing (SDI). This is useful in low jitter 1 sampling or simultaneous sampling applications. VIO The AD7685, when in chain mode, provides a daisy-chain 0.1 feature using the SDI input for cascading multiple ADCs on a 0.01 single data line similar to a shift register. The mode in which the part operates depends on the SDI level 0.001 10 100 1000 10000 100000 1000000 when the CNV rising edge occurs. The CS mode is selected if SAMPLING RATE (SPS) SDI is high and the chain mode is selected if SDI is low. The Figure 32. Operating Currents vs. Sampling Rate SDI hold time is such that when SDI and CNV are connected SUPPLYING THE ADC FROM THE REFERENCE together, the chain mode is always selected. For simplified applications, the AD7685, with its low operating In either the CS mode or the chain mode, the AD7685 offers the current, can be supplied directly using the reference circuit, as flexibility to optionally force a start bit in front of the data bits. shown in Figure 33. The reference line can be driven by either: This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. • The system power supply directly. Otherwise, without a BUSY indicator, the user must time out • A reference voltage with enough current output capability, the maximum conversion time prior to readback. such as the ADR43x. The BUSY indicator feature is enabled as follows: • A reference buffer, such as the AD8031, that can also filter CS • In the mode, if CNV or SDI is low when the ADC the system power supply, as shown in Figure 33. conversion ends (see Figure 37 and Figure 41). • In the chain mode, if SCK is high during the CNV rising edge (see Figure 45). 5V 5V 10Ω 5V 10kΩ 10µF 1µF AD8031 1µF 1 REF VDD VIO AD7685 1 OPTIONAL REFERENCE BUFFER AND FILTER. Figure 33. Example of Application Circuit Rev. C | Page 17 of 28 OPERATING CURRENTS (µA) 02968-031 02968-030 AD7685 valid on both SCK edges. Although the rising edge can be used CS MODE 3-WIRE, NO BUSY INDICATOR to capture the data, a digital host using the SCK falling edge will This mode is usually used when a single AD7685 is connected allow a faster reading rate provided it has an acceptable hold to an SPI-compatible digital host. time. After the 16th SCK falling edge or when CNV goes high, The connection diagram is shown in Figure 34, and the whichever is earlier, SDO returns to high impedance. corresponding timing is given in Figure 35. CONVERT With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the mode, and forces SDO to high CS DIGITAL HOST CNV VIO impedance. Once a conversion is initiated, it will continue to DATA IN SDI AD7685 SDO completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, SCK such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the CLK maximum conversion time to avoid the generation of the BUSY Figure 34. CS Mode 3-Wire, No BUSY Indicator signal indicator. When conversion is completed, the AD7685 Connection Diagram (SDI High) enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is SDI = 1 t CYC t CNVH CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 14 15 16 t t HSDO SCKH t t t DSDO EN DIS SDO D15 D14 D13 D1 D0 Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev. C | Page 18 of 28 02968-033 02968-032 AD7685 powers down. The data bits are then clocked out, MSB first, by CS MODE 3-WIRE WITH BUSY INDICATOR subsequent SCK falling edges. The data is valid on both SCK This mode is usually used when a single AD7685 is connected edges. Although the rising edge can be used to capture the data, to an SPI-compatible digital host having an interrupt input. a digital host using the SCK falling edge will allow a faster reading The connection diagram is shown in Figure 36, and the rate provided it has an acceptable hold time. After the optional corresponding timing is given in Figure 37. 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the mode, and forces SDO to high CS CONVERT impedance. SDO is maintained in high impedance until the VIO completion of the conversion irrespective of the state of CNV. DIGITAL HOST CNV Prior to the minimum conversion time, CNV could be used to VIO 47kΩ SDI AD7685 SDO DATA IN select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and SCK IRQ held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion CLK is complete, SDO goes from high impedance to low. With a CS Figure 36. Mode 3-Wire with BUSY Indicator pull-up on the SDO line, this transition can be used as an Connection Diagram (SDI High) interrupt signal to initiate the data reading controlled by the digital host. The AD7685 then enters the acquisition phase and SDI = 1 t CYC t CNVH CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SCK t SCKL SCK 1 2 3 15 16 17 t t HSDO SCKH t t DSDO DIS SDO D15 D14 D1 D0 CS Figure 37. Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev. C | Page 19 of 28 02968-035 02968-034 AD7685 conversion is complete, the AD7685 enters the acquisition CS MODE 4-WIRE, NO BUSY INDICATOR phase and powers down. Each ADC result can be read by This mode is usually used when multiple AD7685s are bringing low its SDI input, which consequently outputs the connected to an SPI-compatible digital host. MSB onto SDO. The remaining data bits are then clocked by A connection diagram example using two AD7685s is shown in subsequent SCK falling edges. The data is valid on both SCK Figure 38, and the corresponding timing is given in Figure 39. edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster With SDI high, a rising edge on CNV initiates a conversion, reading rate, provided it has an acceptable hold time. After the selects the mode, and forces SDO to high impedance. In this CS 16th SCK falling edge, or when SDI goes high, whichever is mode, CNV must be held high during the conversion phase and earlier, SDO returns to high impedance and another AD7685 the subsequent data readback (if SDI and CNV are low, SDO is can be read. driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, If multiple AD7685s are selected at the same time, the SDO but SDI must be returned high before the minimum conversion output pin handles this contention without damage or induced time and held high until the maximum conversion time to latch-up. Meanwhile, it is recommended to keep this contention avoid the generation of the BUSY signal indicator. When the as short as possible to limit extra power dissipation. CS2 CS1 CONVERT DIGITAL HOST CNV CNV SDI AD7685 SDO SDI AD7685 SDO SCK SCK DATA IN CLK Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram t CYC CNV t t CONV ACQ ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI(CS1) t HSDICNV SDI(CS2) t SCK t SCKL SCK 12 3 14 15 16 17 18 30 31 32 t t HSDO SCKH t t t EN DSDO DIS SDO D15 D14 D13 D1 D0 D15 D14 D1 D0 CS Figure 39. Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev. C | Page 20 of 28 02968-036 02968-037 AD7685 as an interrupt signal to initiate the data readback controlled by CS MODE 4-WIRE WITH BUSY INDICATOR the digital host. The AD7685 then enters the acquisition phase This mode is usually used when a single AD7685 is connected and powers down. The data bits are then clocked out, MSB first, to an SPI-compatible digital host, which has an interrupt input, by subsequent SCK falling edges. The data is valid on both SCK and it is desired to keep CNV, which is used to sample the edges. Although the rising edge can be used to capture the data, analog input, independent of the signal used to select the data a digital host using the SCK falling edge will allow a faster reading. This requirement is particularly important in reading rate provided it has an acceptable hold time. After the applications where low jitter on CNV is desired. optional 17th SCK falling edge, or SDI going high, whichever is The connection diagram is shown in Figure 40, and the earlier, the SDO returns to high impedance. corresponding timing is given in Figure 41. CS1 With SDI high, a rising edge on CNV initiates a conversion, CONVERT selects the CS mode, and forces SDO to high impedance. In this VIO DIGITAL HOST CNV mode, CNV must be held high during the conversion phase and 47kΩ the subsequent data readback (if SDI and CNV are low, SDO is SDI SDO DATA IN AD7685 driven low). Prior to the minimum conversion time, SDI could SCK IRQ be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion CLK time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When Figure 40. CS Mode 4-Wire with BUSY Indicator Connection Diagram the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SSDICNV SDI t SCK t HSDICNV t SCKL SCK 1 2 3 151617 t t HSDO SCKH t t DSDO DIS t EN SDO D15 D14 D1 D0 CS Figure 41. Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev. C | Page 21 of 28 02968-039 02968-038 AD7685 AD7685 enters the acquisition phase and powers down. The CHAIN MODE, NO BUSY INDICATOR remaining data bits stored in the internal shift register are then This mode can be used to daisy-chain multiple AD7685s on a clocked by subsequent SCK falling edges. For each ADC, SDI 3-wire serial interface. This feature is useful for reducing feeds the input of the internal shift register and is clocked by the component count and wiring connections, for example, in SCK falling edge. Each ADC in the chain outputs its data MSB isolated multiconverter applications or for systems with a first, and 16 × N clocks are required to readback the N ADCs. limited interfacing capacity. Data readback is analogous to The data is valid on both SCK edges. Although the rising edge clocking a shift register. can be used to capture the data, a digital host using the SCK A connection diagram example using two AD7685s is shown in falling edge will allow a faster reading rate and, consequently, Figure 42, and the corresponding timing is given in Figure 43. more AD7685s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion and selects the reduced due to the total readback time. For instance, with a 5 ns chain mode. In this mode, CNV is held high during the digital host setup time and 3 V interface, up to eight AD7685s conversion phase and the subsequent data readback. When the running at a conversion rate of 220 kSPS can be daisy-chained conversion is complete, the MSB is output onto SDO and the on a 3-wire port. CONVERT CNV CNV DIGITAL HOST SDI AD7685 SDO SDI AD7685 SDO DATA IN A B SCK SCK CLK Figure 42. Chain Mode Connection Diagram SDI = 0 A t CYC CNV t t ACQ CONV ACQUISITION CONVERSION ACQUISITION t SCK t SCKL t SSCKCNV SCK 1 2 3 14 15 16 17 18 303132 t t t HSCKCNV SSDISCK SCKH t t EN HSDISCK D 15 D 14 D 13 D 1 D 0 SDO = SDI A A A A A A B t HSDO t DSDO D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 SDO B B B B B A A A A B Figure 43. Chain Mode Serial Interface Timing Rev. C | Page 22 of 28 02968-040 02968-041 AD7685 Figure 44) SDO is driven high. This transition on SDO can be CHAIN MODE WITH BUSY INDICATOR used as a BUSY indicator to trigger the data readback controlled This mode can also be used to daisy chain multiple AD7685s on by the digital host. The AD7685 then enters the acquisition a 3-wire serial interface while providing a BUSY indicator. This phase and powers down. The data bits stored in the internal feature is useful for reducing component count and wiring shift register are then clocked out, MSB first, by subsequent connections, for example, in isolated multiconverter applications or SCK falling edges. For each ADC, SDI feeds the input of the for systems with a limited interfacing capacity. Data readback is internal shift register and is clocked by the SCK falling edge. analogous to clocking a shift register. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 A connection diagram example using three AD7685s is shown clocks are required to readback the N ADCs. Although the in Figure 44, and the corresponding timing is given in Figure 45. rising edge can be used to capture the data, a digital host also using the SCK falling edge allows a faster reading rate and, When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the consequently, more AD7685s in the chain, provided the digital chain mode, and enables the BUSY indicator feature. In this host has an acceptable hold time. For instance, with a 5 ns mode, CNV is held high during the conversion phase and the digital host setup time and 3 V interface, up to eight AD7685s subsequent data readback. When all ADCs in the chain have running at a conversion rate of 220 kSPS can be daisy-chained completed their conversions, the near-end ADC (ADC C in to a single 3-wire port. CONVERT CNV CNV CNV DIGITAL HOST SDI SDO SDI SDO SDI SDO DATA IN AD7685 AD7685 AD7685 A B C SCK SCK SCK IRQ CLK Figure 44. Chain Mode with BUSY Indicator Connection Diagram t CYC CNV = SDI A t CONV t ACQ ACQUISITION CONVERSION ACQUISITION t SCK t SSCKCNV t SCKH SCK 12 3 415 16 17 18 19 31 32 33 34 35 47 48 49 t t HSCKCNV SSDISCK t t SCKL DSDOSDI t t EN HSDISCK SDO = SDI D 15 D 14 D 13 D 1 D 0 A B A A A A A t HSDO t DSDOSDI t DSDO t DSDOSDI SDO = SDI D 15 D 14 D 13 D1D0D 15 D 14 D 1 D 0 B C B B B B B A A A A t t DSDOSDI DSDOSDI SDO C D 15 D 14 D 13 D1D0D D 15 D 14 D1D0D 15 14 D1D 0 C C C C C B B B B A A A A Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing Rev. C | Page 23 of 28 02968-042 02968-043 AD7685 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7685 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7685 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7685 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided At least one ground plane should be used. It could be common or split between the digital and analog section. In the latter case, the planes should be joined underneath the AD7685. Figure 46. Example of Layout of the AD7685 (Top Layer) The AD7685 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connected with wide, low impedance traces. Finally, the power supplies VDD and VIO should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7685 and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example layout following these rules is shown in Figure 46 and Figure 47. EVALUATING THE PERFORMANCE OF THE AD7685 Other recommended layouts for the AD7690 are outlined in Figure 47. Example of Layout of the AD7685 (Bottom Layer) the documentation of the evaluation board (EVAL-AD7685CB). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the universal evaluation control board (EVAL-CONTROL BRD3). Rev. C | Page 24 of 28 02968-045 02968-044 AD7685 Multiple AD7685s are daisy-chained to reduce the number of TRUE 16-BIT ISOLATED APPLICATION EXAMPLE signals to isolate. Note that the SCKOUT, which is a readback of In applications where high accuracy and isolation are required, the AD7685’s clock, has a very short skew with the DATA for example, power monitoring, motor control, and some signal. This skew is the channel-to-channel matching medical equipment, the circuit given in Figure 48, using the propagation delay of the digital isolator (tPSKCD). This allows AD7685 and the ADuM1402C digital isolator, provides a running the serial interface at the maximum speed of the digital compact and high performance solution. isolator (45 Mbps for the ADuM1402C), which would have been otherwise limited by the cascade of the propagation delays of the digital isolator. The complete analog chain runs on a 5 V single supply using the ADR391 low dropout reference voltage and the rail-to-rail CMOS AD8618 amplifier while offering true bipolar input range. 5V REF 5V 5V V , V V , V 2.7V TO 5V DD1 E1 DD2 E2 10µF 100nF 100nF 100nF 4kΩ 1kΩ GND GND ±10V INPUT 1 2 V V 5V REF VDD VIO IA OA SDO DATA SCK IN+ AD7685 CNV V V IB OB 2V REF SCKOUT SDI IN– GND 1/4 AD8618 V V OC IC SCKIN 5V REF 5V V V 10µF 100nF OD ID CONVERT 4kΩ 1kΩ ±10V INPUT 5V REF VDD VIO SDO ADuM1402C SCK IN+ AD7685 CNV 2V REF SDI IN– GND 1/4 AD8618 5V REF 5V 10µF 100nF 4kΩ 1kΩ ±10V INPUT 5V REF VDD VIO SDO SCK 1kΩ 1kΩ IN+ AD7685 CNV 2V REF SDI 5V IN– GND 1/4 AD8618 5V REF 5V REF 5V ADR391 10µF 100nF 1kΩ 5V IN OUT 2V REF 4kΩ 1kΩ GND ±10V INPUT 4kΩ 5V REF VDD VIO SDO SCK 10µF 100nF IN+ AD7685 CNV 2V REF SDI IN– GND 1/4 AD8618 Figure 48. A True 16-Bit Isolated Simultaneous Sampling Acquisition System Rev. C | Page 25 of 28 02968-046 AD7685 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49.10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 0.50 BSC 2.90 6 10 PIN 1 INDEX EXPOSED 1.74 PAD AREA 1.64 0.50 1.49 0.40 0.30 5 1 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.05 MAX 0.75 THE PIN CONFIGURATION AND 0.02 NOM 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.25 0.20 Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. C | Page 26 of 28 PIN 1 INDICATOR (R 0.15) 091709-A 121009-A AD7685 ORDERING GUIDE Integral No Missing Temperature Package Package Ordering 1 Model Notes Nonlinearity Code Range Description Option Branding Quantity AD7685ACPZRL ±6 LSB max 15 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C4H Reel, (LFCSP_WD) 5,000 AD7685ACPZRL7 ±6 LSB max 15 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C4H Reel, (LFCSP_WD) 1,500 AD7685ARMZ ±6 LSB max 15 Bits –40°C to +85°C 10-Lead MSOP RM-10 C4H Tube, 50 AD7685ARMZRL7 ±6 LSB max 15 Bits –40°C to +85°C 10-Lead MSOP RM-10 C4H Reel, 1,000 AD7685BCPZRL ±3 LSB max 16 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C3D Reel, (LFCSP_WD) 5,000 AD7685BCPZRL7 ±3 LSB max 16 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C3D Reel, (LFCSP_WD) 1,500 AD7685BRMZ ±3 LSB max 16 Bits –40°C to +85°C 10-Lead MSOP RM-10 C3D Tube, 50 AD7685BRMZRL7 ±3 LSB max 16 Bits –40°C to +85°C 10-Lead MSOP RM-10 C3D Reel, 1,000 AD7685CCPZRL ±2 LSB max 16 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C4J Reel, (LFCSP_WD) 5,000 AD7685CCPZRL7 ±2 LSB max 16 Bits –40°C to +85°C 10-Lead QFN CP-10-9 C4J Reel, (LFCSP_WD) 1,500 AD7685CRMZ ±2 LSB max 16 Bits –40°C to +85°C 10-Lead MSOP RM-10 C4J Tube, 50 AD7685CRMZRL7 ±2 LSB max 16 Bits –40°C to +85°C 10-Lead MSOP RM-10 C4J Reel, 1,000 2 EVAL-AD7685CBZ Evaluation Board 3 EVAL-CONTROL BRD2Z Controller Board 3 EVAL-CONTROL BRD3Z Controller Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. C | Page 27 of 28 AD7685 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02968-0-8/11(C) Rev. C | Page 28 of 28