ANALOG DEVICES AD7683

16-Bit, 100 kSPS, Single-Ended PulSAR ADC in MSOP/QFN AD7683 FEATURES APPLICATION DIAGRAM 0.5V TO VDD 2.7V TO 5.5V 16-bit resolution with no missing codes Throughput: 100 kSPS INL: ±1 LSB typical, ±3 LSB maximum REF VDD 0V TO V REF Pseudo differential analog input range +IN DCLOCK 0 V to V with V up to VDD 3-WIRE SPI REF REF AD7683 D –IN OUT INTERFACE Single-supply operation: 2.7 V to 5.5 V CS GND Serial interface SPI/QSPI/MICROWIRE/DSP compatible Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V, Figure 1. 150 μW @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead packages: Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit MSOP PulSAR ADC 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) 400 kSPS Improved second source to ADS8320 and ADS8325 100 250 to ≥1000 ADC Type kSPS kSPS 500 kSPS kSPS Driver 18-Bit True AD7691 AD7690 AD7982 ADA4941 APPLICATIONS Differential ADA4841 AD7984 Battery-powered equipment 16-Bit True AD7684 AD7687 AD7688 ADA4941 Differential AD7693 ADA4841 Data acquisition 16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841 Instrumentation Differential AD7683 AD7694 Medical instruments 14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841 Process control Differential GENERAL DESCRIPTION CS track-and-hold circuit. On the falling edge, it samples an The AD7683 is a 16-bit, charge redistribution, successive analog input, +IN, between 0 V to REF with respect to a ground approximation, PulSAR® analog-to-digital converter (ADC) sense, –IN. The reference voltage, REF, is applied externally and that operates from a single power supply, VDD, between 2.7 V can be set up to the supply voltage. Its power scales linearly with and 5.5 V. It contains a low power, high speed, 16-bit sampling throughput. ADC with no missing codes (B grade), an internal conversion The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN clock, and a serial, SPI-compatible interface port. The part also (LFCSP) package, with an operating temperature specified from contains a low noise, wide bandwidth, short aperture delay, −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 04301-001 AD7683 TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Information .................................................................... 12  Applications ....................................................................................... 1  Converter Operation .................................................................. 12  Application Diagram ........................................................................ 1  Transfer Functions ..................................................................... 12  General Description ......................................................................... 1  Typical Connection Diagram ................................................... 13  Revision History ............................................................................... 2  Analog Input ............................................................................... 13  Specif ica t ions ..................................................................................... 3  Driver Amplifier Choice ........................................................... 13  Timing Specifications .................................................................. 5  Voltage Reference Input ............................................................ 14  Absolute Maximum Ratings ............................................................ 6  Power Supply ............................................................................... 14  Thermal Resistance ...................................................................... 6  Digital Interface .......................................................................... 14  ESD Caution .................................................................................. 6  Layout .......................................................................................... 14  Pin Configuration and Function Descriptions ............................. 7  Evaluating the AD7683 Performance ...................................... 14  Terminology ...................................................................................... 8  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 9  Ordering Guide .......................................................................... 16  Applications Information ............................................................... 12  REVISION HISTORY 2/08—Rev. 0 to Rev. A Change to Title .................................................................................. 1 Moved Figure 3, Figure 4, and Figure 5 ......................................... 5 Changes to Figure 4 .......................................................................... 5 Moved Figure 17 and Figure 18 .................................................... 11 Changes to Figure 22 ...................................................................... 13 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 9/04—Initial Version: Revision 0 Rev. A | Page 2 of 16 AD7683 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 2. AD7683 All Grades Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range +IN − (–IN) 0 VREF V Absolute Input Voltage +IN −0.1 VDD + 0.1 V −IN −0.1 0.1 V Analog Input CMRR f = 100 kHz 65 dB IN Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section THROUGHPUT SPEED Complete Cycle 10 μs Throughput Rate 0 100 kSPS DCLOCK Frequency 0 2.9 MHz REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 100 kSPS, V − V = V /2 = 2.5 V 50 μA +IN −IN REF DIGITAL INPUTS Logic Levels V −0.3 0.3 × VDD V IL V 0.7 × VDD VDD + 0.3 V IH I −1 +1 μA IL IIH −1 +1 μA Input Capacitance 5 pF DIGITAL OUTPUTS Data Format Serial, 16 bits straight binary VOH ISOURCE = −500 μA VDD − 0.3 V V I = +500 μA 0.4 V OL SINK POWER SUPPLIES VDD Specified performance 2.7 5.5 V 1 VDD Range 2.0 5.5 V Operating Current 100 kSPS throughput VDD VDD = 5 V 800 μA VDD = 2.7 V 560 μA 2, 3 Standby Current VDD = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V 4 6 mW VDD = 2.7 V 1.5 mW 2 VDD = 2.7 V, 10 kSPS throughput 150 μW TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 See the Typical Performance Characteristics section for more information. 2 With all digital inputs forced to VDD or GND, as required. 3 During acquisition phase. Rev. A | Page 3 of 16 AD7683 VDD = 5 V; V = VDD; T = –40°C to +85°C, unless otherwise noted. REF A Table 3. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.5 0.5 LSB 1 Gain Error , T to T ±2 ±24 ±2 ±15 LSB MIN MAX Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C 1 Offset Error , TMIN to TMAX ±0.7 ±1.6 ±0.4 ±1.6 mV Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity ±0.05 ±0.05 LSB VDD = 5 V ± 5% AC ACCURACY 2 Signal-to-Noise f = 1 kHz 90 88 91 dB IN Spurious-Free Dynamic Range f = 1 kHz −100 −108 dB IN Total Harmonic Distortion f = 1 kHz −100 −106 dB IN Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits 1 See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. VDD = 2.7 V; VREF = 2.5V; TA = –40°C to +85°C, unless otherwise noted. Table 4. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.85 0.85 LSB 1 Gain Error , TMIN to TMAX ±2 ±30 ±2 ±15 LSB Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C 1 Offset Error , TMIN to TMAX ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity ±0.05 ±0.05 LSB VDD = 2.7 V ±5% AC ACCURACY 2 Signal-to-Noise f = 1 kHz 85 86 dB IN Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB Total Harmonic Distortion fIN = 1 kHz −94 −98 dB Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB Effective Number of Bits f = 1 kHz 13.8 14 Bits IN 1 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 4 of 16 AD7683 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter Symbol Min Typ Max Unit Throughput Rate t 100 kHz CYC CS Falling to DCLOCK Low tCSD 0 μs CS Falling to DCLOCK Rising tSUCS 20 ns DCLOCK Falling to Data Remains Valid tHDO 5 16 ns CS Rising Edge to D High Impedance t 14 100 ns OUT DIS DCLOCK Falling to Data Valid t 16 50 ns EN Acquisition Time tACQ 400 ns DOUT Fall Time tF 11 25 ns DOUT Rise Time tR 11 25 ns Timing and Circuit Diagrams t CYC COMPLETE CYCLE CS t t SUCS ACQ POWER DOWN 145 DCLOCK t t t t CSD EN HDO DIS HIGH-Z HIGH-Z D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 D 0 OUT (MSB) (LSB) NOTES 1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. D GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING. OUT Figure 2. Serial Interface Timing 500µA I OL TO D 1.4V OUT C L 100pF 500µA I OH Figure 3. Load Circuit for Digital Interface Timing 2V 0.8V t t EN EN 2V 2V 0.8V 0.8V Figure 4. Voltage Reference Levels for Timing 90% D OUT 10% t t R F Figure 5. DOUT Rise and Fall Timing Rev. A | Page 5 of 16 04301-003 04301-004 04301-006 04301-002 AD7683 ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational +IN , –IN GND − 0.3 V to VDD + 0.3 V or ±130 mA section of this specification is not implied. Exposure to absolute REF GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD to GND −0.3 V to +6 V THERMAL RESISTANCE Digital Inputs to GND −0.3 V to VDD + 0.3 V Digital Outputs to GND −0.3 V to VDD + 0.3 V Table 7. Thermal Resistance Storage Temperature Range −65°C to +150°C Package Type θ θ Unit JA JC Junction Temperature 150°C 8-Lead MSOP 200 44 °C/W Lead Temperature Range JEDEC J-STD-20 Vapor Phase (60 sec) 215°C ESD CAUTION Infrared (15 sec) 220°C 1 See the Analog Input section. Rev. A | Page 6 of 16 AD7683 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 8 VDD AD7683 +IN 2 7 DCLOCK TOP VIEW –IN 3 6 D OUT (Not to Scale) GND 4 5 CS Figure 6. 8-Lead MSOP and QFN (LFCSP) Pin Configuration Table 8. Pin Function Descriptions 1 Pin No. Mnemonic Type Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. 2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to V . REF 3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. 4 GND P Power Supply Ground. 5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables D . When high, D is high impedance. OUT OUT 6 D DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. OUT 7 DCLOCK DI Serial Data Clock Input. 8 VDD P Power Supply. 1 AI = analog input; DI = digital input; DO = digital output; and P = power. Rev. A | Page 7 of 16 04301-005 AD7683 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio (SINAD) Integral Nonlinearity Error (INL) SINAD is the ratio of the rms value of the actual input signal to Linearity error refers to the deviation of each individual code the rms sum of all other spectral components below the Nyquist from a line drawn from negative full scale through positive frequency, including harmonics but excluding dc. The value for full scale. The point used as negative full scale occurs ½ LSB SINAD is expressed in dB. before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation Effective Number of Bits (ENOB) is measured from the middle of each code to the true straight ENOB is a measurement of the resolution with a sine wave line (see Figure 21). input. It is related to SINAD (as represented by S/(N+D)) by the following formula and is expressed in bits: Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the ENOB=(S /[N+D] −1.76)/ 6.02 dB maximum deviation from this ideal value. It is often specified in Total Harmonic Distortion (THD) terms of resolution for which no missing codes are guaranteed. THD is the ratio of the rms sum of the first five harmonic Offset Error components to the rms value of a full-scale input signal and is The first transition should occur at a level ½ LSB above analog expressed in dB. ground (38.1 μV for the 0 V to 5 V range). The offset error is Signal-to-Noise Ratio (SNR) the deviation of the actual transition from that point. SNR is the ratio of the rms value of the actual input signal to Gain Error the rms sum of all other spectral components below the Nyquist The last transition (from 111...10 to 111...11) should occur for frequency, excluding harmonics and dc. The value for SNR is an analog voltage 1½ LSB below the nominal full scale expressed in dB. (4.999886 V for the 0 V to 5 V range). The gain error is the Aperture Delay deviation of the actual level of the last transition from the ideal Aperture delay is a measure of the acquisition performance and level after the offset has been adjusted out. is the time between the falling edge of the input and when CS Spurious-Free Dynamic Range (SFDR) the input signal is held for a conversion. The difference, in decibels (dB), between the rms amplitude of Transient Response the input signal and the peak spurious signal. Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. A | Page 8 of 16 AD7683 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 POSITIVE INL = +0.43LSB POSITIVE DNL = +0.43LSB NEGATIVE INL = –0.97LSB NEGATIVE DNL = –0.41LSB 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 7000 120000 62564 VDD = REF = 2.5V VDD = REF = 5V 102287 6000 100000 5000 80000 4000 35528 60000 3000 25440 40000 2000 15152 20000 13619 1000 4604 8 2755 001 50 130 00 00 6 0 0 0 0 79FD 79FE 79FF 7A007A017A027A037A047A057A06 7A077A08 7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16 CODE IN HEX CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center Figure 11. Histogram of a DC Input at the Code Center 0 0 16384 POINT FFT 16384 POINT FFT VDD = REF = 5V VDD = REF = 2.5V –20 –20 f = 100kSPS f = 100kSPS S S f = 20.43kHz f = 20.43kHz IN IN –40 –40 SNR = 92.7dB SNR = 88.7dB THD = –105.7dB THD = –102.6dB –60 SFDR = –106.4dB –60 SFDR = –104.6dB –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 102030 40 50 0 102030 4050 FREQUENCY (kHz) FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. FFT Plot Rev. A | Page 9 of 16 AMPLITUDE (dB OF FULL SCALE) COUNTS INL (LSB) 04301-012 04301-008 04301-009 COUNTS AMPLITUDE (dB OF FULL SCALE) DNL (LSB) 04301-011 04301-007 04301-010 AD7683 100 17 –80 –85 V 2.5V = –1dB REF 95 16 SNR –90 –95 90 15 SINAD V 5V = –1dB REF ENOB –100 85 14 –105 80 13 –110 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 40 80 120 160 200 REFERENCE VOLTAGE (V) FREQUENCY (kHz) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD vs. Frequency 100 1200 f = 100kSPS S 95 1000 V = 5V, –10dB REF 90 800 V = 5V, –1dB REF 85 600 V = 2.5V, –1dB REF 80 400 75 200 70 0 0 50 100 150 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) SUPPLY (V) Figure 14. SINAD vs. Frequency Figure 16. Operating Current vs. Supply Rev. A | Page 10 of 16 SNR, SINAD (dB) SINAD (dB) 04301-014 04301-013 ENOB (Bits) OPERATING CURRENT (µA) THD (dB) 04301-015 04301-017 AD7683 900 6 VDD = 5V, f = 100kSPS S 5 800 4 700 3 600 2 OFFSET ERROR VDD = 2.7V, f = 100kSPS S 1 500 0 400 –1 300 –2 GAIN ERROR –3 200 –4 100 –5 0 –6 –55 –34 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Operating Current vs. Temperature Figure 19. Offset and Gain Error vs. Temperature 1000 750 500 250 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 18. Power-Down Current vs. Temperature Rev. A | Page 11 of 16 POWER-DOWN CURRENT (nA) OPERATING CURRENT (µA) 04301-019 04301-018 OFFSET, GAIN ERROR (LSB) 04301-016 AD7683 APPLICATIONS INFORMATION +IN SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV –IN Figure 20. ADC Simplified Schematic array between GND and REF, the comparator input varies by CIRCUIT INFORMATION binary-weighted voltage steps (V /2, V /4...V /65,536). REF REF REF The AD7683 is a low power, single-supply, 16-bit ADC using a The control logic toggles these switches, starting with the MSB, successive approximation architecture. to bring the comparator back into a balanced condition. After The AD7683 is capable of converting 100,000 samples per the completion of this process, the part returns to the acquisition second (100 kSPS) and powers down between conversions. phase and the control logic generates the ADC output code. When operating at 10 kSPS, for example, it consumes typi- TRANSFER FUNCTIONS cally 150 μW with a 2.7 V supply, ideal for battery-powered The ideal transfer function for the AD7683 is shown in Figure 21 applications. and Table 9. The AD7683 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. 111...111 The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an 111...110 111...101 8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package. The AD7683 is an improved second source to the ADS8320 and ADS8325. For even better performance, consider the AD7685. CONVERTER OPERATION The AD7683 is a successive approximation ADC based on a 000...010 charge redistribution DAC. Figure 20 shows the simplified 000...001 schematic of the ADC. The capacitive DAC consists of two 000...000 –FS –FS + 1 LSB +FS – 1 LSB identical arrays of 16 binary-weighted capacitors that connect –FS + 0.5 LSB +FS – 1.5 LSB to the two comparator inputs. ANALOG INPUT During the acquisition phase, terminals of the array tied to the Figure 21. ADC Ideal Transfer Function comparator’s input are connected to GND via SW+ and SW−. Table 9. Output Codes and Ideal Input Voltages All independent switches are connected to the analog inputs. Analog Input Digital Output Code Thus, the capacitor arrays are used as sampling capacitors and Description VREF = 5 V Hexadecimal acquire the analog signal on the +IN and −IN inputs. When the 1 FSR – 1 LSB 4.999924 V FFFF acquisition phase is complete and the CS input goes low, a con- Midscale + 1 LSB 2.500076 V 8001 version phase is initiated. When the conversion phase begins, Midscale 2.5 V 8000 SW+ and SW− are opened first. The two capacitor arrays are Midscale – 1 LSB 2.499924 V 7FFF then disconnected from the inputs and connected to the GND –FSR + 1 LSB 76.3 μV 0001 input. Therefore, the differential voltage between the inputs, 2 –FSR 0 V 0000 +IN and −IN, captured at the end of the acquisition phase is 1 applied to the comparator inputs, causing the comparator to This is also the code for an overranged analog input (V+IN – V–IN above V – V ). REF GND become unbalanced. By switching each element of the capacitor 2 This is also the code for an underranged analog input (V+IN – V–IN below VGND). Rev. A | Page 12 of 16 ADC CODE (STRAIGHT BINARY) 04301-020 04301-021 AD7683 (NOTE 1) REF 2.7V TO 5.25V C REF 100nF 2.2µF TO 10µF (NOTE 2) REF VDD 33Ω +IN 0V TO V REF DCLOCK 2.7nF AD7683 (NOTE 3) D 3-WIRE INTERFACE OUT –IN CS (NOTE 4) GND NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 22. Typical Application Diagram pass filter that reduces undesirable aliasing effects and limits TYPICAL CONNECTION DIAGRAM the noise. Figure 22 shows an example of the recommended application When the source impedance of the driving circuit is low, the diagram for the AD7683. AD7683 can be driven directly. Large source impedances signi- ANALOG INPUT ficantly affect the ac performance, especially THD. The dc Figure 23 shows an equivalent circuit of the input structure of performances are less sensitive to the input impedance. the AD7683. The two diodes, D1 and D2, provide ESD protec- DRIVER AMPLIFIER CHOICE tion for the analog inputs, +IN and −IN. Care must be taken to Although the AD7683 is easy to drive, the driver amplifier ensure that the analog input signal never exceeds the supply rails needs to meet the following requirements: by more than 0.3 V because this causes these diodes to become forward-biased and start conducting current. However, these • The noise generated by the driver amplifier needs to be diodes can handle a forward-biased current of 130 mA maximum. kept as low as possible to preserve the SNR and transition For instance, these conditions can eventually occur when the noise performance of the AD7683. Note that the AD7683 input buffer (U1) supplies are different from VDD. In such a has a noise figure much lower than most other 16-bit case, use an input buffer with a short-circuit current limitation ADCs and, therefore, can be driven by a noisier op amp to protect the part. while preserving the same or better system performance. VDD The noise coming from the driver is filtered by the AD7683 analog input circuit, 1-pole, low-pass filter made by R IN D1 C IN R +IN IN and C or by the external filter, if one is used. IN OR –IN C PIN D2 • For ac applications, the driver needs to have a THD GND performance suitable to that of the AD7683. Figure 15 shows the THD vs. frequency that the driver should Figure 23. Equivalent Analog Input Circuit exceed. This analog input structure allows the sampling of the differen- • For multichannel multiplexed applications, the driver tial signal between +IN and −IN. By using this differential input, amplifier and the AD7683 analog input circuit must be small signals common to both inputs are rejected. For instance, able to settle for a full-scale step of the capacitor array at a by using −IN to sense a remote signal ground, ground potential 16-bit level (0.0015%). In the amplifier data sheet, settling differences between the sensor and the local ADC ground are at 0.1% to 0.01% is more commonly specified. This could eliminated. During the acquisition phase, the impedance of the differ significantly from the settling time at a 16-bit level analog input, +IN, can be modeled as a parallel combination of and should be verified prior to driver selection. Capacitor CPIN and the network formed by the series connection of R and C . C is primarily the pin capacitance. R is typically Table 10. Recommended Driver Amplifiers IN IN PIN IN 600 Ω and is a lumped component consisting of some serial Amplifier Typical Application resistors and the on resistance of the switches. C is typically IN ADA4841 Very low noise and low power 30 pF and is mainly the ADC sampling capacitor. During the OP184 Low power, low noise, and low frequency conversion phase, when the switches are opened, the input AD8605, AD8615 5 V single-supply, low power impedance is limited to CPIN. RIN and CIN make a 1-pole, low- AD8519 Low power and low frequency AD8031 High frequency and low power Rev. A | Page 13 of 16 04301-023 04301-022 AD7683 DCLOCK falling edges. The data is valid on both DCLOCK VOLTAGE REFERENCE INPUT edges. Although the rising edge can be used to capture the data, The AD7683 voltage reference input, REF, has a dynamic input a digital host also using the DCLOCK falling edge allows a impedance. Therefore, it should be driven by a low impedance faster reading rate, provided it has an acceptable hold time. source with efficient decoupling between the REF and GND pins, as explained in the Layout section. CONVERT When REF is driven by a very low impedance source (such as DIGITAL HOST CS an unbuffered reference voltage like the low temperature drift AD7683 DATA IN ADR43x reference or a reference buffer using the AD8031 or D OUT DCLOCK the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is CLK appropriate for optimum performance. Figure 25. Connection Diagram If desired, smaller reference decoupling capacitors with values as low as 2.2 μF can be used with a minimal impact on perfor- LAYOUT mance, especially DNL. Design the PCB that houses the AD7683 so that the analog and POWER SUPPLY digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7683, with all its The AD7683 powers down automatically at the end of each analog signals on the left side and all its digital signals on the conversion phase and, therefore, the power scales linearly with right side, eases this task. the sampling rate, as shown in Figure 24. This makes the part ideal for low sampling rates (even of a few Hz) and low battery- Avoid running digital lines under the device because these powered applications. couple noise onto the die, unless a ground plane under the 1000 CS AD7683 is used as a shield. Fast switching signals, such as or clocks, should never run near analog signal paths. Avoid VDD = 5V crossover of digital and analog signals. 100 Use at least one ground plane. It can be common or split between VDD = 2.7V the digital and analog sections. In such a case, it should be joined 10 underneath the AD7683. The AD7683 voltage reference input (REF) has a dynamic input 1 impedance and should be decoupled with minimal parasitic inductances. Accomplish this by placing the reference decoupling 0.1 ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low 0.01 impedance traces. 10 100 1k 10k 100k SAMPLING RATE (SPS) Finally, decouple the power supply, VDD, of the AD7683 with a Figure 24. Operating Current vs. Sampling Rate ceramic capacitor, typically 100 nF, placed close to the AD7683. Connect it using short and large traces to provide low impedance DIGITAL INTERFACE paths and reduce the effect of glitches on the power supply lines. The AD7683 is compatible with SPI®, QSPI™, digital hosts, MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF53x EVALUATING THE AD7683 PERFORMANCE or ADSP-219x). The connection diagram is shown in Figure 25 Other recommended layouts for the AD7683 are outlined in the and the corresponding timing is given in Figure 2. evaluation board for the AD7683 (EVAL-AD7683CBZ). The CS A falling edge on initiates a conversion and the data transfer. evaluation board package includes a fully assembled and tested After the fifth DCLOCK falling edge, D is enabled and forced evaluation board, documentation, and software for controlling OUT the board from a PC via the EVAL-CONTROL BRD3Z. low. The data bits are then clocked, MSB first, by subsequent Rev. A | Page 14 of 16 OPERATING CURRENT (µA) 04301-024 04301-025 AD7683 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.38 0.60 0.23 0° 0.00 0.22 0.40 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 26. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions Shown in millimeters 0.35 3.00 0.30 0.65 BSC BSC SQ 0.25 5 8 PIN 1 INDEX 1.74 * EXPOSED AREA PAD 1.64 (BOTTOM VIEW) 1.49 0.50 0.40 4 1 0.30 TOP VIEW 2.48 2.38 0.80 MAX 2.23 0.80 0.55 NOM 0.05 MAX 0.75 * PADDLE CONNECTED TO GND. 0.02 NOM 0.70 THIS CONNECTION IS NOT REQUIRED TO MEET THE SEATING ELECTRICAL PERFORMANCES. PLANE 0.20 REF Figure 27. 8-Terminal Quad Flat No Lead Package (QFN) [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-3) Dimensions Shown in millimeters Rev. A | Page 15 of 16 PIN 1 INDICATOR (R 0.19) 022808-B AD7683 ORDERING GUIDE Integral Temperature Package Package Ordering Model Nonlinearity Range Description Option Branding Quantity 1 AD7683ACPZRL ±6 LSB max –40°C to +85°C QFN [LFCSP_WD] CP-8-3 C4G Reel, 5,000 1 AD7683ACPZRL7 ±6 LSB max –40°C to +85°C QFN [LFCSP_WD] CP-8-3 C4G Reel, 1,500 AD7683ARM ±6 LSB max –40°C to +85°C MSOP RM-8 C1L Tube, 50 AD7683ARMRL7 ±6 LSB max –40°C to +85°C MSOP RM-8 C1L Reel, 1,000 1 AD7683ARMZ ±6 LSB max –40°C to +85°C MSOP RM-8 C4G Tube, 50 1 AD7683ARMZRL7 ±6 LSB max –40°C to +85°C MSOP RM-8 C4G Reel, 1,000 1 AD7683BCPZRL ±3 LSB max –40°C to +85°C QFN [LFCSP_WD] CP-8-3 C38 Reel, 5,000 1 AD7683BCPZRL7 ±3 LSB max –40°C to +85°C QFN [LFCSP_WD] CP-8-3 C38 Reel, 1,500 AD7683BRM ±3 LSB max –40°C to +85°C MSOP RM-8 C1C Tube, 50 AD7683BRMRL7 ±3 LSB max –40°C to +85°C MSOP RM-8 C1C Reel, 1,000 1 AD7683BRMZ ±3 LSB max –40°C to +85°C MSOP RM-8 C38 Tube, 50 1 AD7683BRMZRL7 ±3 LSB max –40°C to +85°C MSOP RM-8 C38 Reel, 1,000 1 EVAL-AD7683CBZ Evaluation Board 1, 2 EVAL-CONTROL BRD3Z Controller Board 1 Z= RoHS Compliant Part. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04301-0-2/08(A) Rev. A | Page 16 of 16