ANALOG DEVICES AD7682

16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC Data Sheet AD7682/AD7689 FEATURES FUNCTIONAL BLOCK DIAGRAM 2.3V TO 5.5V 0.5V TO VDD – 0.5V 0.5V TO VDD 16-bit resolution with no missing codes 0.1µF 10µF 4-channel (AD7682)/8-channel (AD7689) multiplexer with REFIN REF VDD choice of inputs Unipolar single-ended 1.8V BAND GAP VIO TO Differential (GND sense) REF AD7689 VDD Pseudobipolar TEMP SENSOR Throughput: 250 kSPS IN0 CNV INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) IN1 SCK IN2 16-BIT SAR SPI SERIAL Dynamic range: 93.8 dB MUX IN3 INTERFACE ADC SDO SINAD: 92.5 dB at 20 kHz IN4 ONE-POLE DIN IN5 THD: −100 dB at 20 kHz LPF IN6 SEQUENCER IN7 Analog input range: 0 V to V with V up to VDD REF REF COM Multiple reference types GND Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V) Figure 1. External (up to VDD) Table 1. Multichannel 14-/16-Bit PulSAR® ADC Internal temperature sensor (TEMP) Type Channels 250 kSPS 500 kSPS ADC Driver Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture 14-Bit 8 AD7949 ADA4841-x Single-supply 2.3 V to 5.5 V operation with 16-Bit 4 AD7682 ADA4841-x 1.8 V to 5.5 V logic interface 16-Bit 8 AD7689 AD7699 ADA4841-x Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP GENERAL DESCRIPTION Power dissipation The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge 3.5 mW @ 2.5 V/200 kSPS redistribution successive approximation register (SAR) analog- 12.5 mW @ 5 V/250 kSPS to-digital converters (ADCs) that operate from a single power Standby current: 50 nA supply, VDD. Low cost grade available The AD7682/AD7689 contain all components for use in a 20-lead 4 mm × 4 mm LFCSP package multichannel, low power data acquisition system, including a APPLICATIONS true 16-bit SAR ADC with no missing codes; a 4-channel Multichannel system monitoring (AD7682) or 8-channel (AD7689), low crosstalk multiplexer Battery-powered equipment that is useful for configuring the inputs as single-ended (with or Medical instruments: ECG/EKG without ground sense), differential, or bipolar; an internal low Mobile communications: GPS drift reference (selectable 2.5 V or 4.096 V) and buffer; a Power line monitoring temperature sensor; a selectable one-pole filter; and a sequencer Data acquisition that is useful when channels are continuously scanned in order. Seismic data acquisition systems The AD7682/AD7689 use a simple SPI interface for writing to Instrumentation the configuration register and receiving conversion results. The Process control SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7682/AD7689 are housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07353-001 AD7682/AD7689 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Voltage Reference Output/Input .............................................. 21  Applications....................................................................................... 1  Power Supply............................................................................... 23  Functional Block Diagram .............................................................. 1  Supplying the ADC from the Reference.................................. 23  General Description ......................................................................... 1  Digital Interface .............................................................................. 24  Revision History ............................................................................... 2  Reading/Writing During Conversion, Fast Hosts.................. 24  Specifications..................................................................................... 4  Reading/Writing After Conversion, Any Speed Hosts.......... 24  Timing Specifications .................................................................. 7  Reading/Writing Spanning Conversion, Any Speed Host.... 24  Absolute Maximum Ratings............................................................ 9  Configuration Register, CFG .................................................... 24  ESD Caution.................................................................................. 9  General Timing Without a Busy Indicator ............................. 26  Pin Configurations and Function Descriptions ......................... 10  General Timing with a Busy Indicator .................................... 27  Typical Performance Characteristics ........................................... 12  Channel Sequencer .................................................................... 28  Terminology .................................................................................... 15  Read/Write Spanning Conversion Without a Busy Indicator ....................................................................................................... 29  Theory of Operation ...................................................................... 16  Read/Write Spanning Conversion with a Busy Indicator..... 30  Overview...................................................................................... 16  Application Hints ........................................................................... 31  Converter Operation.................................................................. 16  Layout .......................................................................................... 31  Transfer Functions...................................................................... 17  Evaluating AD7682/AD7689 Performance ............................ 31  Typical Connection Diagrams.................................................. 18  Outline Dimensions....................................................................... 32  Analog Inputs.............................................................................. 19  Ordering Guide .......................................................................... 32  Driver Amplifier Choice............................................................ 21  REVISION HISTORY 4/12—Rev. C to Rev. D 3/09—Rev. 0 to Rev. A Changes to Figure 27...................................................................... 18 Changes to Features Section, Applications Section, and Changed Internal Reference Section to Internal Figure 1 ...............................................................................................1 Reference/Temperature Sensor Section....................................... 21 Added Table 2; Renumbered Sequentially .....................................3 Changes to Internal Reference/Temperature Sensor Section ... 21 Changed VREF to V .....................................................................4 REF Changed External Reference/Temperature Sensor Section to Changes to Table 3.............................................................................5 External Reference Section............................................................ 22 Changes to Table 4.............................................................................6 Changes to External Reference and Internal Buffer Section and Changes to Table 5.............................................................................7 External Reference Section............................................................ 22 Deleted Endnote 2 in Table 6...........................................................8 Changes to REF Bit, Function Column, Table 10 ...................... 25 Changes to Figure 4, Figure 5, and Table 7 ....................................9 Updated Outline Dimensions ....................................................... 32 Changes to Figure 6, Figure 9, and Figure 10 ............................. 11 Changes to Figure 22...................................................................... 13 9/11—Rev. B to Rev. C Changes to Overview Section and Converter Operation Changes to Internal Reference Section........................................ 21 Section.............................................................................................. 15 Changes to the External Reference and Internal Buffer Changes to Table 8.......................................................................... 16 Section.............................................................................................. 22 Changes to Figure 26 and Figure 27............................................. 17 Changes to the External Reference/Temperature Sensor Changes to Bipolar Single Supply Section and Analog Inputs Section.............................................................................................. 22 Section.............................................................................................. 18 Changes to Table 10, REF Bit Description .................................. 25 Changes to Internal Reference/Temperature Sensor Section... 20 Added Figure 31; Renumbered Sequentially .............................. 20 6/09—Rev. A to Rev. B Changes to External Reference and Internal Buffer Section and Changes Table 6 ................................................................................ 8 External Reference Section ........................................................... 21 Changes to Figure 37...................................................................... 25 Added Figure 32 and Figure 33 .................................................... 21 Changes to Figure 38...................................................................... 26 Changes to Power Supply Section ................................................ 22 Rev. D | Page 2 of 32 Data Sheet AD7682/AD7689 Changes to Digital Interface Section, Reading/Writing After Changes to Read/Write Spanning Conversion Without a Busy Conversion, Any Speed Hosts Section, and Configuration Indicator Section and Figure 41 ....................................................28 Register, CFG Section .....................................................................23 Changes to Read/Write Spanning Conversion with a Busy Indicator and Figure 43 ..................................................................29 Changes to Table 10 ........................................................................24 Added General Timing Without a Busy Indicator Section and Changes to Evaluating AD7682/AD7689 Performance Figure 37 ...........................................................................................25 Section ..............................................................................................30 Added General Timing With a Busy Indicator Section and Added Exposed Pad Notation to Outline Dimensions..............31 Figure 38 ...........................................................................................26 Changes to Ordering Guide...........................................................31 Added Channel Sequencer Section and Figure 39 .....................27 5/08—Revision 0: Initial Version Rev. D | Page 3 of 32 AD7682/AD7689 Data Sheet SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2. AD7689A AD7682B/AD7689B Parameter Conditions/Comments Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ANALOG INPUT Voltage Range Unipolar mode 0 +VREF 0 +VREF V Bipolar mode −V/2 +V/2 −V/2 +V/2 REF REF REF REF Absolute Input Voltage Positive input, unipolar −0.1 V + 0.1 −0.1 V + 0.1 V REF REF and bipolar modes Negative or COM input, −0.1 +0.1 −0.1 +0.1 V unipolar mode Negative or COM input, VREF/2 − 0.1 VREF/2 VREF/2 + 0.1 VREF/2 − 0. VREF/2 VREF/2 + 0.1 V bipolar mode 1 Analog Input CMRR fIN = 250 kHz 68 68 dB Leakage Current at 25°C Acquisition phase 1 1 nA 1 Input Impedance THROUGHPUT Conversion Rate 2 Full Bandwidth VDD = 4.5 V to 5.5 V 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 kSPS 2 ¼ Bandwidth VDD = 4.5 V to 5.5 V 0 62.5 0 62.5 kSPS VDD = 2.3 V to 4.5 V 0 50 0 50 kSPS Transient Response Full-scale step, 1.8 1.8 μs full bandwidth Full-scale step, 14.5 14.5 μs ¼ bandwidth ACCURACY No Missing Codes 15 16 Bits 3 Integral Linearity Error −4 +4 −1.5 ±0.4 +1.5 LSB Differential Linearity Error −1 ±0.25 +1.5 LSB Transition Noise REF = VDD = 5 V 0.6 0.5 LSB 4 Gain Error −32 +32 −8 ±1 +8 LSB Gain Error Match ±2 −4 ±0.5 +4 LSB Gain Error Temperature Drift ±1 ±1 ppm/°C 4 VDD = 4.5 V to 5.5 V −32 +32 −8 ±1 +8 LSB Offset Error VDD = 2.3 V to 4.5 V ±32 ±5 LSB Offset Error Match ±2 −4 ±0.5 +4 LSB Offset Error Temperature Drift ±1 ±1 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±1.5 ±1.5 LSB 5 AC ACCURACY 6 Dynamic Range 90.5 93.8 dB Signal-to-Noise fIN = 20 kHz, VREF = 5 V 90 92.5 93.5 dB f = 20 kHz, V = 4.096 V, 89 91 92.3 dB IN REF internal REF f = 20 kHz, V = 2.5 V, 86 87.5 88.8 dB IN REF internal REF SINAD fIN = 20 kHz, VREF = 5 V 89 91 92.5 dB f = 20 kHz, V = 5 V, 30.5 33.5 dB IN REF −60 dB input fIN = 20 kHz, VREF = 4.096 V 88 90 91 dB internal REF fIN = 20 kHz, VREF = 2.5 V 86 87 88.4 dB internal REF Rev. D | Page 4 of 32 Data Sheet AD7682/AD7689 AD7689A AD7682B/AD7689B Parameter Conditions/Comments Min Typ Max Min Typ Max Unit Total Harmonic Distortion f = 20 kHz −97 −100 dB IN (THD) Spurious-Free Dynamic fIN = 20 kHz 105 110 dB Range Channel-to-Channel Crosstalk fIN = 100 kHz on −120 −125 dB adjacent channel(s) SAMPLING DYNAMICS −3 dB Input Bandwidth Full bandwidth 1.7 1.7 MHz ¼ Bandwidth 0.425 0.425 MHz Aperture Delay VDD = 5 V 2.5 2.5 ns 1 See the Analog Inputs section. 2 The bandwidth is set in the configuration register. 3 LSB means least significant bit. With the 5 V input range, one LSB is 76.3 μV. 4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. D | Page 5 of 32 AD7682/AD7689 Data Sheet VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V = VDD, all specifications T to T , unless otherwise noted. REF MIN MAX Table 3. All Models/Grades Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE REF Output Voltage 2.5 V, @ 25°C 2.490 2.500 2.510 V 4.096 V, @ 25°C 4.086 4.096 4.106 V 1 REFIN Output Voltage 2.5 V, @ 25°C 1.2 V 4.096 V, @ 25°C 2.3 V REF Output Current ±300 μA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C = 10 μF 5 ms REF EXTERNAL REFERENCE Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.5 V 2 Current Drain 250 kSPS, REF = 5 V 50 μA TEMPERATURE SENSOR 3 Output Voltage @ 25°C 283 mV Temperature Sensitivity 1 mV/°C DIGITAL INPUTS Logic Levels VIL −0.3 +0.3 × VIO V VIH 0.7 × VIO VIO + 0.3 V IIL −1 +1 μA I −1 +1 μA IH DIGITAL OUTPUTS 4 Data Format 5 Pipeline Delay V I = +500 μA 0.4 V OL SINK V I = −500 μA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 1.8 VDD + 0.3 V 6, 7 Standby Current VDD and VIO = 5 V, @ 25°C 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.7 μW VDD = 2.5 V, 200 kSPS throughput 3.5 mW VDD = 5 V, 250 kSPS throughput 12.5 18 mW VDD = 5 V, 250 kSPS throughput with internal reference 15.5 21 mW Energy per Conversion VDD = 5V 60 nJ 8 TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 This is the output from the internal band gap. 2 This is an average current and scales with throughput. 3 The output voltage is internal and present on a dedicated multiplexer input. 4 Unipolar mode: serial 16-bit straight binary. Bipolar mode: serial 16-bit twos complement. 5 Conversion results available immediately after completed conversion. 6 With all digital inputs forced to VIO or GND as required. 7 During acquisition phase. 8 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. D | Page 6 of 32 Data Sheet AD7682/AD7689 TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 2.2 μs CONV Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 4.0 μs Data Write/Read During Conversion tDATA 1.2 μs CNV Pulse Width t 10 ns CNVH SCK Period t t + 2 ns SCK DSDO SCK Low Time tSCKL 11 ns SCK High Time tSCKH 11 ns SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay t DSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns CNV High or Last SCK Falling Edge to SDO High Impedance t 32 ns DIS CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge t 5 ns HDIN 1 See Figure 2 and Figure 3 for load conditions. Rev. D | Page 7 of 32 AD7682/AD7689 Data Sheet VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T to T , unless otherwise noted. MIN MAX Table 5. 1 Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 3.2 μs Acquisition Time t 1.8 μs ACQ Time Between Conversions t 5 μs CYC Data Write/Read During Conversion t 1.2 μs DATA CNV Pulse Width tCNVH 10 ns SCK Period tSCK tDSDO + 2 ns SCK Low Time tSCKL 12 ns SCK High Time t 12 ns SCKH SCK Falling Edge to Data Remains Valid t 5 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV Low to SDO D15 MSB Valid t EN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns CNV High or Last SCK Falling Edge to SDO High Impedance t 50 ns DIS CNV Low to SCK Rising Edge t 10 ns CLSCK DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. I 500µA OL TOSDO 1.4V C L 50pF 500µA I OH Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO t t DELAY DELAY 1 1 2V OR VIO – 0.5V 2V OR VIO – 0.5V 2 2 0.8V OR 0.5V 0.8V OR 0.5V 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Levels for Timing Rev. D | Page 8 of 32 07353-002 07353-003 Data Sheet AD7682/AD7689 ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Analog Inputs 1 1 other conditions above those indicated in the operational INx, COM GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA section of this specification is not implied. Exposure to absolute REF, REFIN GND − 0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Supply Voltages device reliability. VDD, VIO to GND −0.3 V to +7 V ESD CAUTION VIO to VDD −0.3 V to VDD + 0.3 V DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance (LFCSP) 47.6°C/W JA θ Thermal Impedance (LFCSP) 4.4°C/W JC 1 See the Analog Inputs section. Rev. D | Page 9 of 32 AD7682/AD7689 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR VDD 1 15 VIO PIN 1 REF 2 14 SDO INDICATOR VDD 1 15 VIO AD7682 REFIN 3 13 SCK REF 2 14 SDO AD7689 GND 4 12 DIN REFIN 3 13 SCK TOP VIEW GND 5 11 CNV GND 4 12 DIN (Not to Scale) TOP VIEW GND 5 11 CNV (Not to Scale) NOTES 1. NC = NO CONNECT. NOTES 2. THE EXPOSED PAD IS NOT CONNECTED 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM SOLDERED TO THE SYSTEM GROUND PLANE. GROUND PLANE. Figure 4. AD7682 Pin Configuration Figure 5. AD7689 Pin Configuration Table 7. Pin Function Descriptions AD7682 AD7689 1 Pin No. Mnemonic Mnemonic Type Description 1, 20 VDD VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.6 V. 2 REF REF AI/O Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the Reference Decoupling section. 3 REFIN REFIN AI/O Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description. 4, 5 GND GND P Power Supply Ground. 6 NC IN4 AI AD7682: no connection. AD7689: Analog Input Channel 4. 7 IN2 IN5 AI AD7682: Analog Input Channel 2. AD7689: Analog Input Channel 5. 8 NC IN6 AI AD7682: no connection. AD7689: Analog Input Channel 6. 9 IN3 IN7 AI AD7682: Analog Input Channel 3. AD7689: Analog Input Channel 7. 10 COM COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common- mode point of 0 V or V /2 V. REF 11 CNV CNV DI Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled. 12 DIN DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. Rev. D | Page 10 of 32 07353-004 07353-005 NC 6 20 VDD IN2 7 19 NC NC 8 18 IN1 IN3 9 17 NC 16 IN0 COM 10 IN4 6 20 VDD IN5 7 19 IN3 18 IN2 IN6 8 IN7 9 17 IN1 COM 10 16 IN0 Data Sheet AD7682/AD7689 AD7682 AD7689 1 Pin No. Mnemonic Mnemonic Type Description 14 SDO SDO DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 VIO VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 16 IN0 IN0 AI Analog Input Channel 0. 17 NC IN1 AI AD7682: no connection. AD7689: Analog Input Channel 1. 18 IN1 IN2 AI AD7682: Analog Input Channel 1. AD7689: Analog Input Channel 2. 19 NC IN3 AI AD7682: no connection. AD7689: Analog Input Channel 3. 21 Exposed Pad Exposed NC The exposed pad is not connected internally. For increased reliability of the solder joints, (EPAD) (EPAD) Pad (EPAD) it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, P = power, NC = no internal connection. Rev. D | Page 11 of 32 AD7682/AD7689 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted. 1.5 1.5 INL MAX = +0.34 LSB DNL MAX = +0.20 LSB INL MIN = –0.44 LSB DNL MIN = –0.22 LSB 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.5 –1.0 0 16,384 32,768 0 16,384 32,768 49,152 65,536 49,152 65,536 CODES CODES Figure 6. Integral Nonlinearity vs. Code, VREF = VDD = 5 V Figure 9. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 200k 160k σ = 0.78 σ = 0.50 V = VDD = 2.5V REF 180k = VDD = 5V V REF 135,207 140k 160k 120k 135,326 140k 124,689 100k 120k 100k 80k 63,257 80k 60k 51,778 60k 40k 40k 20k 20k 6649 4090 0 0 487 619 0 0 0 178 60 1 0 0 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 CODE IN HEX CODE IN HEX Figure 7. Histogram of a DC Input at Code Center Figure 10. Histogram of a DC Input at Code Center 0 0 V = VDD = 5V V = VDD = 2.5V REF REF –20 f = 250kSPS –20 f = 200kSPS S s f = 19.9kHz f = 19.9kHz IN IN SNR = 92.9dB SNR = 88.0dB –40 –40 SINAD = 92.4dB SINAD = 87.0dB THD = –102dB THD = –89dB –60 –60 SFDR = 103dB SFDR = 89dB SECOND HARMONIC = –111dB SECOND HARMONIC = –105dB –80 –80 THIRD HARMONIC = –104dB THIRD HARMONIC = –90dB –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 05 250 75 100 125 05 250 75 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 8. 20 kHz FFT, V = VDD = 5 V Figure 11. 20 kHz FFT, V = VDD = 2.5 V REF REF Rev. D | Page 12 of 32 AMPLITUDE (dB of Full-Scale) COUNTS INL (LSB) 07353-009 07353-008 07353-007 AMPLITUDE (dB of Full-Scale) DNL (LSB) COUNTS 07353-010 07353-006 07353-011 Data Sheet AD7682/AD7689 100 100 95 95 90 90 85 85 80 80 75 75 V = VDD = 5V, –0.5dB V = VDD = 5V, –0.5dB REF REF 70 70 V = VDD = 5V, –10dB V = VDD = 5V, –10dB REF REF V = VDD = 2.5V, –0.5dB V = VDD = 2.5V, –0.5dB REF REF 65 V = VDD = 2.5V, –10dB 65 V = VDD = 2.5V, –10dB REF REF 60 60 0 50 100 150 200 0 50 100 150 200 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. SNR vs. Frequency Figure 15. SINAD vs. Frequency 96 17.0 130 –60 SNR @ 2kHz 125 –65 SINAD @ 2kHz 94 16.5 SNR @ 20kHz 120 –70 SINAD @ 20kHz 92 16.0 SFDR = 2kHz 115 –75 ENOB @ 2kHz ENOB @ 20kHz 110 –80 90 15.5 105 –85 SFDR = 20kHz 88 15.0 100 –90 95 THD = 20kHz –95 86 14.5 90 –100 84 14.0 85 –105 THD = 2kHz 80 –110 82 13.5 75 –115 80 13.0 70 –120 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. SFDR and THD vs. Reference Voltage 96 –90 f = 20kHz IN f = 20kHz IN 94 V = VDD = 5V REF –95 92 V = VDD = 5V REF V = VDD = 2.5V REF 90 –100 88 V = VDD = 2.5V REF –105 86 84 –110 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. SNR vs. Temperature Figure 17. THD vs. Temperature Rev. D | Page 13 of 32 SNR, SINAD (dB) SNR (dB) SNR (dB) 07353-014 07353-041 ENOB (Bits) 07353-013 SFDR (dB) THD (dB) SINAD (dB) THD (dB) 07353-012 07353-017 07353-016 AD7682/AD7689 Data Sheet –60 3000 100 2.5V INTERNAL REF f = 200kSPS S 4.096V INTERNAL REF 2750 90 –70 INTERNAL BUFFER, TEMP ON INTERNAL BUFFER, TEMP OFF 2500 80 EXTERNAL REF, TEMP ON EXTERNAL REF, TEMP OFF –80 VIO 2250 70 –90 2000 60 1750 50 –100 1500 40 V = VDD = 5V, –0.5dB REF –110 V = VDD = 2.5V, –0.5dB REF 1250 30 V = VDD = 2.5V, –10dB REF V = VDD = 5V, –10dB REF –120 1000 20 0 50 100 150 200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) VDD SUPPLY (V) Figure 18. THD vs. Frequency Figure 21. Operating Currents vs. Supply 95 3000 180 f = 20kHz IN f = 200kSPS S 94 2750 160 V = VDD = 5V REF 93 VDD = 5V, INTERNAL 4.096V REF 2500 140 92 2250 120 91 VDD = 5V, EXTERNAL REF 90 2000 100 89 V = VDD = 2.5V REF 1750 80 88 1500 60 VDD = 2.5, EXTERNAL REF 87 1250 40 86 VIO 1000 20 85 –10 –8 –6 –4 –2 0 –55 –35 –15 5 25 45 65 85 105 125 INPUT LEVEL (dB) TEMPERATURE (°C) Figure 19. SNR vs. Input Level Figure 22. Operating Currents vs. Temperature 25 3 2 VDD = 2.5V, 85°C 20 1 15 VDD = 2.5V, 25°C 0 10 –1 VDD = 5V, 85°C UNIPOLAR ZERO VDD = 5V, 25°C 5 UNIPOLAR GAIN –2 VDD = 3.3V, 85°C BIPOLAR ZERO BIPOLAR GAIN VDD = 3.3V, 25°C –3 0 –55 –35 –15 5 25 45 65 85 105 125 0 204060 80 100 120 TEMPERATURE (°C) SDO CAPACITIVE LOAD (pF) Figure 20. Offset and Gain Errors vs. Temperature Figure 23. t Delay vs. SDO Capacitance Load and Supply DSDO Rev. D | Page 14 of 32 SNR (dB) THD (dB) OFFSET ERROR AND GAIN ERROR (LSB) 07353-020 07353-015 07353-018 VDD CURRENT (µA) VDD CURRENT (µA) t DELAY (ns) DSDO 07353-023 VIO CURRENT (µA) 07353-021 VIO CURRENT (µA) 07353-022 Data Sheet AD7682/AD7689 TERMINOLOGY Least Significant Bit (LSB) Signal-to-Noise Ratio (SNR) The LSB is the smallest increment that can be represented by a SNR is the ratio of the rms value of the actual input signal to the converter. For an analog-to-digital converter with N bits of rms sum of all other spectral components below the Nyquist resolution, the LSB expressed in volts is frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. V REF LSB (V)= N Signal-to-(Noise + Distortion) Ratio (SINAD) 2 SINAD is the ratio of the rms value of the actual input signal to Integral Nonlinearity Error (INL) the rms sum of all other spectral components below the Nyquist INL refers to the deviation of each individual code from a line frequency, including harmonics but excluding dc. The value for drawn from negative full scale through positive full scale. The SINAD is expressed in decibels. point used as negative full scale occurs ½ LSB before the first Total Harmonic Distortion (THD) code transition. Positive full scale is defined as a level 1½ LSB THD is the ratio of the rms sum of the first five harmonic beyond the last code transition. The deviation is measured from components to the rms value of a full-scale input signal and is the middle of each code to the true straight line (see Figure 25). expressed in decibels. Differential Nonlinearity Error (DNL) Spurious-Free Dynamic Range (SFDR) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in SFDR is the difference, in decibels, between the rms amplitude terms of resolution for which no missing codes are guaranteed. of the input signal and the peak spurious signal. Offset Error Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave The first transition should occur at a level ½ LSB above analog input. It is related to SINAD by the formula ground. The offset error is the deviation of the actual transition from that point. ENOB = (SINAD − 1.76)/6.02 dB Gain Error and is expressed in bits. The last transition (from 111 … 10 to 111 … 11) should occur Channel-to-Channel Crosstalk for an analog voltage 1½ LSB below the nominal full scale. The Channel-to-channel crosstalk is a measure of the level of crosstalk gain error is the deviation in LSB (or percentage of full-scale between any two adjacent channels. It is measured by applying a range) of the actual level of the last transition from the ideal dc to the channel under test and applying a full-scale, 100 kHz level after the offset error is adjusted out. Closely related is the sine wave signal to the adjacent channel(s). The crosstalk is the full-scale error (also in LSB or percentage of full-scale range), amount of signal that leaks into the test channel and is expressed which includes the effects of the offset error. in decibels. Aperture Delay Reference Voltage Temperature Coefficient Aperture delay is the measure of the acquisition performance. It Reference voltage temperature coefficient is derived from the is the time between the rising edge of the CNV input and the typical shift of output voltage at 25°C on a sample of parts at the point at which the input signal is held for a conversion. maximum and minimum reference output voltage (VREF) measured Transient Response at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as Transient response is the time required for the ADC to accurately V (Max)–V (Min) REF REF 6 acquire its input after a full-scale step function is applied. TCV (ppm/°C)= ×10 REF V (25°C)× (T –T ) REF MAX MIN Dynamic Range where: Dynamic range is the ratio of the rms value of the full scale to V (Max) = maximum V at T , T (25°C), or T . the total rms noise measured with the inputs shorted together. REF REF MIN MAX V (Min) = minimum V at T , T (25°C), or T . The value for dynamic range is expressed in decibels. REF REF MIN MAX VREF (25°C) = VREF at 25°C. TMAX = +85°C. TMIN = –40°C. Rev. D | Page 15 of 32 AD7682/AD7689 Data Sheet THEORY OF OPERATION INx+ SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV INx– OR COM Figure 24. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge The AD7682/AD7689 are successive approximation ADCs redistribution successive approximation register (SAR) analog- based on a charge redistribution DAC. Figure 24 shows the to-digital converters (ADCs). These devices are capable of simplified schematic of the ADC. The capacitive DAC consists converting 250,000 samples per second (250 kSPS) and power of two identical arrays of 16 binary-weighted capacitors, which down between conversions. For example, when operating with are connected to the two comparator inputs. an external reference at 1 kSPS, they consume 17 μW typically, During the acquisition phase, terminals of the array tied to the ideal for battery-powered applications. comparator input are connected to GND via SW+ and SW−. All The AD7682/AD7689 contain all of the components for use in a independent switches are connected to the analog inputs. multichannel, low power data acquisition system, including Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) • 16-bit SAR ADC with no missing codes inputs. When the acquisition phase is complete and the CNV • 4-channel/8-channel, low crosstalk multiplexer input goes high, a conversion phase is initiated. When the • Internal low drift reference and buffer conversion phase begins, SW+ and SW− are opened first. The • Temperature sensor two capacitor arrays are then disconnected from the inputs and • Selectable one-pole filter connected to the GND input. Therefore, the differential voltage • Channel sequencer between the INx+ and INx− (or COM) inputs captured at the These components are configured through an SPI-compatible, end of the acquisition phase is applied to the comparator inputs, 14-bit register. Conversion results, also SPI compatible, can be causing the comparator to become unbalanced. By switching read after or during conversions with the option for reading each element of the capacitor array between GND and REF, the back the configuration associated with the conversion. comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these The AD7682/AD7689 provide the user with an on-chip track- switches, starting with the MSB, to bring the comparator back and-hold and do not exhibit pipeline delay or latency. into a balanced condition. After the completion of this process, The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can the part returns to the acquisition phase, and the control logic be interfaced to any 1.8 V to 5 V digital logic family. They are generates the ADC output code and a busy signal indicator. housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space Because the AD7682/AD7689 have an on-board conversion savings and allows flexible configurations. They are pin-for-pin clock, the serial clock, SCK, is not required for the conversion compatible with the 16-bit AD7699 and 14-bit AD7949. process. Rev. D | Page 16 of 32 07353-026 Data Sheet AD7682/AD7689 TRANSFER FUNCTIONS TWOS STRAIGHT COMPLEMENT BINARY With the inputs configured for unipolar range (single-ended, 011...111 111...111 COM with ground sense, or paired differentially with INx− as 011...110 111...110 ground sense), the data output is straight binary. 011...101 111...101 With the inputs configured for bipolar range (COM = V /2 or REF paired differentially with INx− = V /2), the data outputs are REF twos complement. The ideal transfer characteristic for the AD7682/AD7689 is shown in Figure 25 and for both unipolar and bipolar ranges 100...010 000...010 with the internal 4.096 V reference. 100...001 000...001 100...000 000...000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function Table 8. Output Codes and Ideal Input Voltages 1 2 Unipolar Analog Input Digital Output Code Bipolar Analog Input Digital Output Code Description VREF = 4.096 V (Straight Binary Hex) VREF = 4.096 V (Twos Complement Hex) 3 3 FSR − 1 LSB 4.095938 V 0xFFFF 2.047938 V 0x7FFF Midscale + 1 LSB 2.048063 V 0x8001 62.5 μV 0x0001 Midscale 2.048 V 0x8000 0 V 0x0000 Midscale − 1 LSB 2.047938 V 0x7FFF −62.5 μV 0xFFFF −FSR + 1 LSB 62.5 μV 0x0001 −2.047938 V 0x8001 4 4 −FSR 0 V 0x0000 −2.048 V 0x8000 1 With COM or INx− = 0 V or all INx referenced to GND. 2 With COM or INx− = VREF /2. 3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V − GND). REF 4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND). Rev. D | Page 17 of 32 ADC CODE 07353-027 AD7682/AD7689 Data Sheet TYPICAL CONNECTION DIAGRAMS 5V 1.8V TO VDD 100nF 2 100nF 100nF 10µF V+ REF REFIN VDD VIO 0V TO V REF 3 ADA4841-x IN0 V– AD7689 V+ DIN MOSI IN[7:1] SCK SCK SDO MISO 0V TO V REF CNV SS 3 ADA4841-x V– 0V OR COM V /2 REF GND NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 26. Typical Application Diagram with Multiple Supplies +5V 1.8V TO VDD 100nF 2 10µF 100nF 100nF V+ REF REFIN VDD VIO 3 ADA4841-x V– IN0 AD7689 DIN MOSI IN[7:1] SCK V+ SCK SDO MISO 3 ADA4841-x V– CNV SS V p-p REF COM GND V /2 REF NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION. 2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA. Figure 27. Typical Application Diagram Using Bipolar Input Rev. D | Page 18 of 32 07353-028 07353-029 Data Sheet AD7682/AD7689 70 Unipolar or Bipolar 65 Figure 26 shows an example of the recommended connection diagram for the AD7682/AD7689 when multiple supplies are 60 available. 55 Bipolar Single Supply 50 Figure 27 shows an example of a system with a bipolar input using single supplies with the internal reference (optional 45 different VIO supply). This circuit is also useful when the 40 amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input config- 35 uration, the INx inputs are unipolar and are always referenced 30 to GND (no negative voltages even in bipolar range). 1 10 100 1k 10k FREQUENCY (kHz) For this circuit, a rail-to-rail input/output amplifier can be used; Figure 29. Analog Input CMRR vs. Frequency however, the offset voltage vs. input common-mode range should During the acquisition phase, the impedance of the analog inputs be noted and taken into consideration (1 LSB = 62.5 μV with can be modeled as a parallel combination of the capacitor, C , PIN VREF = 4.096 V). Note that the conversion results are in twos and the network formed by the series connection of R and C . IN IN complement format when using the bipolar input configuration. CPIN is primarily the pin capacitance. RIN is typically 2.2 kΩ and Refer to the AN-581 Application Note, Biasing and Decoupling is a lumped component composed of serial resistors and the on Op Amps in Single Supply Applications, for additional details resistance of the switches. CIN is typically 27 pF and is mainly about using single-supply amplifiers. the ADC sampling capacitor. ANALOG INPUTS Selectable Low-Pass Filter Input Structure During the conversion phase, where the switches are opened, Figure 28 shows an equivalent circuit of the input structure of the input impedance is limited to CPIN. While the AD7682/ the AD7682/AD7689. The two diodes, D1 and D2, provide ESD AD7689 are acquiring, RIN and CIN make a one-pole, low-pass protection for the analog inputs, IN[7:0] and COM. Care must filter that reduces undesirable aliasing effects and limits the be taken to ensure that the analog input signal does not exceed noise from the driving circuitry. The low-pass filter can be pro- the supply rails by more than 0.3 V because this causes the grammed for the full bandwidth or ¼ of the bandwidth with diodes to become forward biased and to start conducting CFG[6], as shown in Table 10. This setting changes R to 19 kΩ. IN current. Note that the converter throughput must also be reduced by ¼ These diodes can handle a forward-biased current of 130 mA when using the filter. If the maximum throughput is used with the maximum. For instance, these conditions may eventually occur bandwidth (BW) set to ¼, the converter acquisition time, tACQ, is when the input buffer supplies are different from VDD. In such violated, resulting in increased THD. a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part. VDD D1 INx+ C IN R IN OR INx– OR COM C PIN D2 GND Figure 28. Equivalent Analog Input Circuit This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or VREF ± 0.1 V). By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 29. Rev. D | Page 19 of 32 07353-030 CMRR (dB) 07353-031 AD7682/AD7689 Data Sheet Input Configurations CH0+ IN0 CH0+ IN0 Figure 30 shows the different methods for configuring the analog CH1+ CH1+ IN1 IN1 inputs with the configuration register, CFG[12:10]. Refer to the CH2+ IN2 CH2+ IN2 Configuration Register, CFG, section for more details. CH3+ IN3 CH3+ IN3 CH4+ IN4 CH4+ IN4 The analog inputs can be configured as CH5+ CH5+ IN5 IN5 • Figure 30A, single-ended referenced to system ground; CH6+ CH6+ IN6 IN6 CFG[12:10] = 111 . 2 CH7+ CH7+ IN7 IN7 In this configuration, all inputs (IN[7:0]) have a range of COM COM– COM GND to V . REF GND GND • Figure 30B, bipolar differential with a common reference A—8 CHANNELS, B—8 CHANNELS, point; COM = V /2; CFG[12:10] = 010 . REF 2 SINGLE ENDED COMMON REFERNCE Unipolar differential with COM connected to a ground sense; CFG[12:10] = 1102. CH0+ (–) IN0 CH0+ (–) IN0 In this configuration, all inputs IN[7:0] have a range of CH0– (+) IN1 CH0– (+) IN1 GND to VREF. CH1+ (–) IN2 CH1+ (–) IN2 • Figure 30C, bipolar differential pairs with the negative CH1– (+) CH1– (+) IN3 IN3 input channel referenced to VREF/2; CFG[12:10] = 00X2. CH2+ (–) CH2+ IN4 IN4 Unipolar differential pairs with the negative input channel CH2– (+) IN5 CH3+ IN5 referenced to a ground sense; CFG[12:10] = 10X . 2 CH3+ (–) IN6 CH4+ IN6 In these configurations, the positive input channels have CH3– (+) IN7 CH5+ IN7 the range of GND to VREF. The negative input channels are COM COM– COM a sense referred to VREF/2 for bipolar pairs, or GND for GND GND unipolar pairs. The positive channel is configured with CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 C—4 CHANNELS, D—COMBINATION DIFFERENTIAL are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 Figure 30. Multiplexed Analog Input Configurations are used, as indicated by the channels with parentheses in Figure 30C. For example, for IN0/IN1 pairs with the Sequencer . For IN4/IN5 positive channel on IN0, CFG[9:7] = 0002 The AD7682/AD7689 include a channel sequencer useful for pairs with the positive channel on IN5, CFG[9:7] = 1012. scanning channels in a repeated fashion. Refer to the Channel Note that for the sequencer, detailed in the Channel Sequencer section for further details of the sequencer operation. Sequencer section, the positive channels are always IN0, Source Resistance IN2, IN4, and IN6. When the source impedance of the driving circuit is low, the • Figure 30D, inputs configured in any of the preceding AD7682/AD7689 can be driven directly. Large source imped- combinations (showing that the AD7682/AD7689 can be ances significantly affect the ac performance, especially THD. configured dynamically). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Rev. D | Page 20 of 32 07353-032 Data Sheet AD7682/AD7689 DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE OUTPUT/INPUT Although the AD7682/AD7689 are easy to drive, the driver The AD7682/AD7689 allow the choice of a very low temper- amplifier must meet the following requirements: ature drift internal voltage reference, an external reference, or an external buffered reference. • The noise generated by the driver amplifier must be kept as The internal reference of the AD7682/AD7689 provide excel- low as possible to preserve the SNR and transition noise lent performance and can be used in almost all applications. performance of the AD7682/AD7689. Note that the AD7682/ There are six possible choices of voltage reference schemes AD7689have a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier briefly described in Table 10, with more details in each of the following sections. amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7682/AD7689 Internal Reference/Temperature Sensor analog input circuit low-pass filter made by RIN and CIN or The precision internal reference, suitable for most applications, by an external filter, if one is used. Because the typical noise can be set for either a 2.5 V or a 4.096 V output, as detailed in of the AD7682/AD7689 is 35 μV rms (with VREF = 5 V), the Table 10. With the internal reference enabled, the band gap SNR degradation due to the amplifier is voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN ⎛ ⎞ ⎜ ⎟ is limited, it can be used as a source if followed by a suitable 35 ⎜ ⎟ SNR = 20 log LOSS buffer, such as the AD8605. Note that the voltage of REFIN ⎜ ⎟ π 2 2 ⎜ 35 f (Ne ) ⎟ + changes depending on the 2.5 V or 4.096 V internal reference. ⎜ −3dB N ⎟ 2 ⎝ ⎠ Enabling the reference also enables the internal temperature sensor, where: which measures the internal temperature of the AD7682/AD7689, f is the input bandwidth in megahertz of the AD7682/ –3dB and is thus useful for performing a system calibration. For AD7689 (1.7 MHz in full BW or 425 kHz in ¼ BW) or the applications requiring the use of the temperature sensor, the cutoff frequency of an input filter, if one is used. internal reference must be active (internal buffer can be disabled in N is the noise gain of the amplifier (for example, 1 in buffer this case). Note that, when using the temperature sensor, the output configuration). is straight binary referenced from the AD7682/AD7689 GND pin. e is the equivalent input noise voltage of the op amp, in N The internal reference is temperature-compensated to within nV/√Hz. 10 mV. The reference is trimmed to provide a typical drift of • For ac applications, the driver should have a THD perfor- ±10 ppm/°C. mance commensurate with the AD7682/AD7689. Figure 18 Connect the AD7682/AD7689 as shown in Figure 31 for either shows THD vs. frequency for the AD7682/AD7689. a 2.5 V or 4.096 V internal reference. • For multichannel, multiplexed applications on each input 10µF or input pair, the driver amplifier and the AD7682/AD7689 100nF analog input circuit must settle a full-scale step onto the REF REFIN capacitor array at a 16-bit level (0.0015%). In amplifier data AD7682/ sheets, settling at 0.1% to 0.01% is more commonly AD7689 TEMP specified. This may differ significantly from the settling GND time at a 16-bit level and should be verified prior to driver selection. Figure 31. 2.5 V or 4.096 V Internal Reference Connection Table 9. Recommended Driver Amplifiers Amplifier Typical Application ADA4841-x Very low noise, small, and low power AD8655 5 V single supply, low noise AD8021 Very low noise and high frequency AD8022 Low noise and high frequency OP184 Low power, low noise, and low frequency AD8605, AD8615 5 V single supply, low power Rev. D | Page 21 of 32 07353-049 AD7682/AD7689 Data Sheet External Reference and Internal Buffer Reference Decoupling For improved drift performance, an external reference can be Whether using an internal or external reference, the AD7682/ used with the internal buffer, as shown in Figure 32. The AD7689 voltage reference output/input, REF, has a dynamic external source is connected to REFIN, the input to the on-chip input impedance and should therefore be driven by a low unity gain buffer, and the output is produced on the REF pin. impedance source with efficient decoupling between the REF An external reference can be used with the internal buffer with and GND pins. This decoupling depends on the choice of the or without the temperature sensor enabled. Refer to Table 10 for voltage reference but usually consists of a low ESR capacitor register details. With the buffer enabled, the gain is unity and connected to REF and GND with minimum parasitic inductance. is limited to an input/output of VDD = −0.2 V; however, the A 10 μF (X5R, 1206 size) ceramic chip capacitor is appropriate maximum voltage allowable must be ≤(VDD − 0.5 V). when using the internal reference, the ADR43x/ADR44x external reference, or a low impedance buffer such as the The internal reference buffer is useful in multiconverter appli- AD8031 or the AD8605. cations because a buffer is typically required in these applications. In addition, a low power reference can be used because the The placement of the reference decoupling capacitor is also impor- internal buffer provides the necessary performance to drive the tant to the performance of the AD7682/AD7689, as explained in SAR architecture of the AD7682/AD7689. the Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND REF SOURCE ≤ (VDD – 0.5V) should also connect to the reference decoupling capacitor with 10µF the shortest distance and to the analog ground plane with 100nF several vias. REF REFIN If desired, smaller reference decoupling capacitor values down AD7682/ to 2.2 μF can be used with a minimal impact on performance, AD7689 TEMP especially on DNL. GND Regardless, there is no need for an additional lower value ceramic Figure 32. External Reference Using Internal Buffer decoupling capacitor (for example, 100 nF) between the REF External Reference and GND pins. In any of the six voltage reference schemes, an external reference For applications that use multiple AD7682/AD7689 devices or can be connected directly on the REF pin as shown in Figure 33 other PulSAR devices, it is more effective to use the internal because the output impedance of REF is >5 kΩ. To reduce power reference buffer to buffer the external reference voltage, thus consumption, the reference and buffer should be powered down. reducing SAR conversion crosstalk. Refer to Table 10 for register details. For improved drift The voltage reference temperature coefficient (TC) directly performance, an external reference such as the ADR43x or impacts full scale; therefore, in applications where full-scale ADR44x is recommended. accuracy matters, care must be taken with the TC. For instance, REF SOURCE 0.5V < REF < (VDD + 0.3V) a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. 10µF NO CONNECTION REQUIRED REF REFIN AD7682/ AD7689 TEMP GND Figure 33.External Reference Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows: 4.096 SNR = 20 log LOSS 5 Rev. D | Page 22 of 32 07353-047 Data Sheet AD7682/AD7689 POWER SUPPLY SUPPLYING THE ADC FROM THE REFERENCE The AD7682/AD7689 use two power supply pins: an analog For simplified applications, the AD7682/AD7689, with their and digital core supply (VDD) and a digital input/output inter- low operating current, can be supplied directly using an face supply (VIO). VIO allows direct interface with any logic external reference circuit like the one shown in Figure 36. The between 1.8 V and VDD. To reduce the supplies needed, the reference line can be driven by: VIO and VDD pins can be tied together. The AD7682/AD7689 • The system power supply directly are independent of power supply sequencing between VIO and • A reference voltage with enough current output capability, VDD. Additionally, it is very insensitive to power supply varia- such as the ADR43x/ADR44x tions over a wide frequency range, as shown in Figure 34. • A reference buffer, such as the AD8605, which can also 75 filter the system power supply, as shown in Figure 36 70 65 5V 5V 60 10Ω 5V 10kΩ 55 1µF 0.1µF 10µF 0.1µF AD8605 1µF 50 1 45 REF VDD VIO 40 AD7689 35 30 1 OPTIONAL REFERENCE BUFFER AND FILTER. 1 10 100 1k 10k FREQUENCY (kHz) Figure 36. Example of an Application Circuit Figure 34. PSRR vs. Frequency The AD7682/AD7689 power down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications. 10,000 1000 VDD = 5V, INTERNAL REF 100 VDD = 5V, EXTERNAL REF 10 VDD = 2.5V, EXTERNAL REF 1 VIO 0.1 0.010 0.001 10 100 1k 10k 100k 1M SAMPLING RATE (SPS) Figure 35. Operating Currents vs. Sampling Rate Rev. D | Page 23 of 32 OPERATING CURRENT (µA) PSSR (dB) 07353-034 07353-040 07353-035 AD7682/AD7689 Data Sheet DIGITAL INTERFACE The AD7682/AD7689 use a simple 4-wire interface and are The SCK frequency required is calculated by compatible with SPI, MICROWIRE™, QSPI™, digital hosts, Number _ SCK _ Edges f ≥ and DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, SCK t DATA ADSP-219x, and ADSP-218x. The time between tDATA and tCONV is a safe time when digital The interface uses the CNV, DIN, SCK, and SDO signals and activity should not occur, or sensitive bit decisions may be corrupt. allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or READING/WRITING AFTER CONVERSION, ANY simultaneous sampling applications. SPEED HOSTS A 14-bit register, CFG[13:0], is used to configure the ADC for When reading/writing after conversion, or during acquisition the channel to be converted, the reference selection, and other (n), conversion results are for the previous (n − 1) conversion, components, which are detailed in the Configuration Register, and writing is for the (n + 1) acquisition. CFG, section. For the maximum throughput, the only time restriction is that When CNV is low, reading/writing can occur during conversion, the reading/writing take place during the tACQ (minimum) time. acquisition, and spanning conversion (acquisition plus conver- For slow throughputs, the time restriction is dictated by the sion), as detailed in the following sections. The CFG word is throughput required by the user, and the host is free to run at updated on the first 14 SCK rising edges, and conversion results any speed. Thus for slow hosts, data access must take place are output on the first 15 (or 16 if busy mode is selected) SCK during the acquisition phase. falling edges. If the CFG readback is enabled, an additional READING/WRITING SPANNING CONVERSION, ANY 14 SCK falling edges are required to output the CFG word SPEED HOST associated with the conversion results with the CFG MSB When reading/writing spanning conversion, the data access starts following the LSB of the conversion result. at the current acquisition (n) and spans into the conversion (n). A discontinuous SCK is recommended because the part is selected Conversion results are for the previous (n − 1) conversion, and with CNV low, and SCK activity begins to write a new writing the CFG register is for the next (n + 1) acquisition and configuration word and clock out data. conversion. Note that in the following sections, the timing diagrams indicate Similar to reading/writing during conversion, reading/writing digital activity (SCK, CNV, DIN, SDO) during the conversion. should only occur up to t . For the maximum throughput, DATA However, due to the possibility of performance degradation, the only time restriction is that reading/writing take place digital activity should occur only prior to the safe data reading/ during the tACQ + tDATA time. writing time, t , because the AD7682/AD7689 provide error DATA For slow throughputs, the time restriction is dictated by the correction circuitry that can correct for an incorrect bit during user’s required throughput, and the host is free to run at any to t , there is no error correction and this time. From tDATA CONV speed. Similar to reading/writing during acquisition, for slow conversion results may be corrupted. The user should configure hosts, the data access must take place during the acquisition the AD7682/AD7689 and initiate the busy indicator (if desired) phase with additional time into the conversion. prior to tDATA. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it Note that data access spanning conversion requires the CNV to is recommended to keep the digital pins quiet for approximately be driven high to initiate a new conversion, and data access is 20 ns before and 10 ns after the rising edge of CNV, using a not allowed when CNV is high. Thus, the host must perform discontinuous SCK whenever possible to avoid any potential two bursts of data access when using this method. performance degradation. CONFIGURATION REGISTER, CFG READING/WRITING DURING CONVERSION, FAST The AD7682/AD7689 use a 14-bit configuration register HOSTS (CFG[13:0]), as detailed in Table 10, to configure the inputs, When reading/writing during conversion (n), conversion the channel to be converted, the one-pole filter bandwidth, results are for the previous (n − 1) conversion, and writing the the reference, and the channel sequencer. The CFG register is CFG register is for the next (n + 1) acquisition and conversion. latched (MSB first) on DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or After the CNV is brought high to initiate conversion, it must be synchronous hosts. brought low again to allow reading/writing during conversion. Reading/writing should only occur up to tDATA and, because this time is limited, the host must use a fast SCK. Rev. D | Page 24 of 32 Data Sheet AD7682/AD7689 The register can be written to during conversion, during acquisi- • IN[7:0] unipolar referenced to GND, sequenced in order tion, or spanning acquisition/conversion, and is updated at the end • Full bandwidth for a one-pole filter of conversion, t (maximum). There is always a one deep CONV • Internal reference/temperature sensor disabled, buffer delay when writing the CFG register. Note that, at power-up, the enabled CFG register is undefined and two dummy conversions are • Enables the internal sequencer required to update the register. To preload the CFG register with a • No readback of the CFG register factory setting, hold DIN high for two conversions. Thus Table 10 summarizes the configuration register bit details. See CFG[13:0] = 0x3FFF. This sets the AD7682/AD7689 for the the Theory of Operation section for more details. following: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG INCC INCC INCC INx INx INx BW REF REF REF SEQ SEQ RB Table 10. Configuration Register Description Bit(s) Name Description [13] CFG Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register. [12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function 1 0 0 X Bipolar differential pairs; INx− referenced to V /2 ± 0.1 V. REF 0 1 0 Bipolar; INx referenced to COM = V /2 ± 0.1 V. REF 0 1 1 Temperature sensor. 1 1 0 X Unipolar differential pairs; INx− referenced to GND ± 0.1 V. 1 1 0 Unipolar, INx referenced to COM = GND ± 0.1 V. Unipolar, INx referenced to GND. 1 1 1 [9:7] INx Input channel selection in binary fashion. AD7682 AD7689 Bit 9 Bit 8 Bit 7 Channel Bit 9 Bit 8 Bit 7 Channel 1 X 0 0 IN0 0 0 0 IN0 1 X 0 1 IN1 0 0 1 IN1 1 X 1 0 IN2 … … … … 1 X 1 1 IN3 1 1 1 IN7 [6] BW Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼. 1 = full BW. [5:3] REF Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section. Bit 5 Bit 4 Bit 3 Function 0 0 0 Internal reference, REF = 2.5 V output, temperature enabled. 0 0 1 Internal reference, REF = 4.096 V output, temperature enabled. 0 1 0 External reference, temperature enabled. 0 1 1 External reference, internal buffer, temperature enabled. 1 1 0 External reference, temperature disabled. 1 1 1 External reference, internal buffer, temperature disabled. [2:1] SEQ Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section. Bit 2 Bit 1 Function 0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature. 1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]). [0] RB Read back the CFG register. 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. 1 X = don’t care. Rev. D | Page 25 of 32 AD7682/AD7689 Data Sheet When CNV is brought low after EOC, SDO is driven from high GENERAL TIMING WITHOUT A BUSY INDICATOR impedance to the MSB. Falling SCK edges clock out bits starting Figure 37 details the timing for all three modes: read/write with MSB − 1. during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating The SCK can idle high or low depending on the clock polarity item for both CFG and data readback is at the end of conversion (CPOL) and clock phase (CPHA) settings if SPI is used. A simple (EOC). At EOC, if CNV is high, the busy indicator is disabled. solution is to use CPOL = CPHA = 0 as shown in Figure 37 with SCK idling low. As detailed previously in the Digital Interface section, the data From power-up, in any read/write mode, the first three conver- access should occur up to safe data reading/writing time, tDATA. sion results are undefined because a valid CFG does not take If the full CFG word was not written to prior to EOC, it is dis- nd place until the 2 EOC; thus two dummy conversions are carded and the current configuration remains. If the conversion required. Also, if the state machine writes the CFG during the result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For power-up state (RDC shown), the CFG register needs to be detailed timing, refer to Figure 40 and Figure 41, which depict rewritten again at the next phase. Note that the first valid data reading/writing spanning conversion with all timing details, occurs in Phase (n + 1) when the CFG register is written during including setup, hold, and SCK. Phase (n − 1). SOC t CYC EOC EOC EOC EOC POWER t t CONV DATA UP CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n – 1) UNDEFINED (n) (n) (n + 1) (n + 1) (n + 2) NOTE 1 CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) RDC MSB MSB MSB DATA (n – 3) DATA (n – 2) MSB DATA (n – 1) DATA (n) SDO (n) (n + 1) XXX XXX XXX XXX XXX 116 1 16 1 16 1 16 SCK NOTE 2 NOTE 1 CNV CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) DIN RAC DATA (n – 2) DATA (n – 1) SDO DATA (n) DATA (n + 1) XXX XXX 1 16 1 16 116 1 SCK NOTE 2 NOTE 1 CNV CFG (n + 3) CFG (n) CFG (n) CFG (n + 1) CFG (n + 1) CFG (n + 2) CFG (n + 2) DIN RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) DATA (n + 1) SDO XXX XXX XXX XXX 1 1 11nn n + 16 n + 116 n n + 116 n 1 SCK NOTE 2 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator Rev. D | Page 26 of 32 07353-043 Data Sheet AD7682/AD7689 bit high-to-low transition. A good example of this occurs when GENERAL TIMING WITH A BUSY INDICATOR an SPI host sends 16 SCKs because these are usually limited to Figure 38 details the timing for all three modes: read/write 8-bit or 16-bit bursts; thus the LSB remains. Because the transi- during conversion (RDC), read/write after conversion (RAC), tion noise of the AD7682/AD7689 is 4 LSBs peak to peak (or and read/write spanning conversion (RSC). Note that the gating greater), the LSB is low 50% of the time. For this interface, the SPI item for both CFG and data readback is at the end of conversion host needs to burst 24 SCKs, or a QSPI interface can be used and (EOC). As detailed previously, the data access should occur up programmed for 17 SCKs. to safe data reading/writing time, t . If the full CFG word is DATA The SCK can idle high or low depending on the CPOL and not written to prior to EOC, it is discarded and the current CPHA settings if SPI is used. A simple solution is to use CPOL = configuration remains. CPHA = 1 (not shown) with SCK idling high. At the EOC, if CNV is low, the busy indicator is enabled. In From power-up, in any read/write mode, the first three conver- addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high sion results are undefined because a valid CFG does not take nd impedance because the last bit on SDO remains active. Unlike the place until the 2 EOC; thus, two dummy conversions are case detailed in the Read/Write Spanning Conversion Without a required. Also, if the state machine writes the CFG during the Busy Indicator section, if the conversion result is not read out power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data fully prior to EOC, the last bit clocked out remains. If this bit is occurs in Phase (n + 1) when the CFG register is written during low, the busy signal indicator cannot be generated because the Phase (n − 1). busy generation requires either a high impedance or a remaining START OF CONVERSION (SOC) t CYC EOC EOC EOC POWER EOC t t UP CONV DATA CONVERSION CONVERSION CONVERSION CONVERSION ACQUISITION ACQUISITION ACQUISITION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n – 1) UNDEFINED (n) (n) (n + 1) (n + 1) (n + 2) NOTE 1 CNV DIN XXX CFG (n) CFG (n + 1) CFG (n + 2) RDC DATA (n – 3) DATA (n – 2) DATA (n – 1) SDO DATA (n) XXX XXX XXX SCK 1 17 1 17 1 17 1 17 NOTE 2 NOTE 1 CNV DIN CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3) RAC DATA (n – 2) DATA (n – 1) SDO DATA (n) DATA (n + 1) XXX XXX 1 1 17 1 17 17 1 SCK NOTE 2 NOTE 1 CNV CFG (n + 2) DIN CFG (n) CFG (n + 1) CFG (n + 3) RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA (n) DATA (n) DATA (n + 1) SDO XXX XXX XXX XXX 1 1n n + 1 17 1 n n + 1 17 1 n n + 1 17 SCK NOTE 2 NOTES 1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR. 2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 38. General Interface Timing for the AD7682/AD7689 With a Busy Indicator Rev. D | Page 27 of 32 07353-044 AD7682/AD7689 Data Sheet Conversion Without a Busy Indicator section for more details. CHANNEL SEQUENCER The sequencer can also be used with the busy indicator and The AD7682/AD7689 include a channel sequencer useful for details for these timings can be found in the General Timing scanning channels in a repeated fashion. Channels are scanned with a Busy Indicator section and the Read/Write Spanning as singles or pairs, with or without the temperature sensor, after Conversion with a Busy Indicator section. the last channel is sequenced. For sequencer operation, the CFG register should be set during The sequencer starts with IN0 and finishes with IN[7:0] set in the (n − 1) phase after power-up. On phase (n), the sequencer CFG[9:7]. For paired channels, the channels are paired depend- setting takes place and acquires IN0. The first valid conversion ing on the last channel set in CFG[9:7]. Note that in sequencer result is available at phase (n + 1). After the last channel set in mode, the channels are always paired with the positive input on CFG[9:7] is converted, the internal temperature sensor data is the even channels (IN0, IN2, IN4, IN6), and with the negative output (if enabled), followed by acquisition of IN0. input on the odd channels (IN1, IN3, IN5, IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive Examples inputs dedicated to IN0, IN2, IN4, and IN6. With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in CFG[2:1] are used to enable the sequencer. After the CFG the following order: register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again. IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, … Note that while operating in a sequence, some bits of the CFG For paired channels with the internal temperature sensor register can be changed. However, if changing CFG[11] (paired enabled, the sequencer scans in the following order: or single channel) or CFG[9:7] (last channel in sequence), the IN0, IN2, IN4, IN6, TEMP, IN0, … sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after Note that IN1, IN3, IN5, and IN7 are referenced to a GND the CFG register is updated. sense or VREF/2, as detailed in the Input Configurations section. Figure 39 details the timing for all three modes without a busy indicator. Refer to the Read/Write Spanning Conversion Without a Busy Indicator section and the Read/Write Spanning SOC t CYC EOC EOC EOC EOC POWER t t CONV DATA UP CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION PHASE (n – 2) UNDEFINED (n – 1) UNDEFINED (n – 1) UNDEFINED (n), IN0 (n), IN0 (n + 1), IN1 (n + 1), IN1 (n + 2), IN2 NOTE 1 CNV DIN XXX CFG (n) RDC MSB DATA (n – 3) DATA (n – 2) MSB DATA (n – 1) MSB MSB SDO DATA IN0 IN0 IN1 XXX XXX XXX XXX XXX 1 16 1 16 1 16 1 16 SCK 2 NOTE 2 CNV DIN CFG (n) RAC DATA (n – 2) DATA (n – 1) SDO DATA IN0 DATA IN1 XXX XXX 1 1 16 1 16 116 SCK NOTE 2 CNV CFG (n) CFG (n) DIN RSC DATA (n – 2) DATA (n – 2) DATA (n – 1) DATA (n – 1) DATA IN0 DATA IN0 DATA IN1 SDO XXX XXX XXX XXX 1 1 11nn n + 16 1 n + 116 n n + 116 n SCK NOTE 2 NOTES 1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR. 2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 39. General Channel Sequencer Timing Without a Busy Indicator Rev. D | Page 28 of 32 07353-046 Data Sheet AD7682/AD7689 CNV low after t (maximum), the MSB is enabled on SDO. READ/WRITE SPANNING CONVERSION WITHOUT CONV The host also must enable the MSB of the CFG register at this A BUSY INDICATOR time (if necessary) to begin the CFG update. While CNV is low, This mode is used when the AD7682/AD7689 are connected both a CFG update and a data readback take place. The first 14 to any host using an SPI, serial port, or FPGA. The connection SCK rising edges are used to update the CFG, and the first 15 diagram is shown in Figure 40, and the corresponding timing SCK falling edges clock out the conversion results starting with is given in Figure 41. For the SPI, the host should use CPHA = MSB − 1. The restriction for both configuring and reading is CPOL = 0. Reading/writing spanning conversion is shown, that they both must occur before the t time of the next conver- DATA which covers all three modes detailed in the Digital Interface sion elapses. All 14 bits of CFG[13:0] must be written, or they section. For this mode, the host must generate the data transfer are ignored. In addition, if the 16-bit conversion result is not based on the conversion time. For an interrupt driven transfer read back before t elapses, it is lost. DATA that uses a busy indicator, refer to the Read/Write Spanning The SDO data is valid on both SCK edges. Although the rising Conversion with a Busy Indicator section. edge can be used to capture the data, a digital host using the A rising edge on CNV initiates a conversion, forces SDO to SCK falling edge allows a faster reading rate, provided it has an high impedance, and ignores data present on DIN. After a th th acceptable hold time. After the 16 (or 30 ) SCK falling edge, or conversion is initiated, it continues until completion irrespec- when CNV goes high (whichever occurs first), SDO returns to tive of the state of CNV. CNV must be returned high before the high impedance. safe data transfer time, t , and then held high beyond the DATA If CFG readback is enabled, the CFG register associated with the conversion time, t , to avoid generation of the busy signal CONV indicator. conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to After the conversion is complete, the AD7682/AD7689 enter return SDO to high impedance if this is enabled. the acquisition phase and power-down. When the host brings DIGITAL HOST AD7682/ AD7689 CNV SS MISO SDO MOSI DIN SCK SCK FOR SPI USE CPHA = 0, CPOL = 0. Figure 40. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator t CYC > t CONV t t CONV CONV t t DATA DATA t CNVH EOC EOC RETURN CNV HIGH RETURN CNV HIGH CNV FOR NO BUSY FOR NO BUSY t ACQ ACQUISITION (QUIET (QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n + 1) (n - 1) TIME) TIME) t SCK UPDATE (n) UPDATE (n + 1) t SCKH SEE NOTE CFG/SDO CFG/SDO 16/ 16/ SCK 14 15 1 2 14 15 30 30 t t CLSCK SCKL t t SDIN HDIN CFG CFG CFG CFG DIN X X MSB – 1 X X LSB LSB MSB t t t HSDO t END CFG (n + 1) EN END CFG (n) EN BEGIN CFG (n + 1) EN t DSDO SEE NOTE SDO LSB MSB MSB – 1 LSB + 1 LSB + 1 LSB t END DATA (n – 1) t t END DATA (n – 2) t DIS DIS BEGIN DATA (n – 1) DIS DIS NOTES 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. Figure 41. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator Rev. D | Page 29 of 32 07353-036 07353-037 AD7682/AD7689 Data Sheet the CFG update. While CNV is low, both a CFG update and a READ/WRITE SPANNING CONVERSION WITH A data readback take place. The first 14 SCK rising edges are used to BUSY INDICATOR update the CFG register, and the first 16 SCK falling edges clock This mode is used when the AD7682/AD7689 are connected to out the conversion results starting with the MSB. The restric- any host using an SPI, serial port, or FPGA with an interrupt tion for both configuring and reading is that they both occur input. The connection diagram is shown in Figure 42, and the before the tDATA time elapses for the next conversion. All 14 bits of corresponding timing is given in Figure 43. For the SPI, the CFG[13:0] must be written or they are ignored. Also, if the 16-bit host should use CPHA = CPOL = 1. Reading/writing spanning conversion result is not read back before tDATA elapses, it is lost. conversion is shown, which covers all three modes detailed in The SDO data is valid on both SCK edges. Although the rising the Digital Interface section. edge can be used to capture the data, a digital host using the A rising edge on CNV initiates a conversion, ignores data SCK falling edge allows a faster reading rate, provided it has an present on DIN and forces SDO to high impedance. After the th st acceptable hold time. After the optional 17 (or 31 ) SCK conversion is initiated, it continues until completion irrespec- falling edge, SDO returns to high impedance. Note that if the tive of the state of CNV. CNV must be returned low before the optional SCK falling edge is not used, the busy feature cannot safe data transfer time, tDATA, and then held low beyond the be detected, as described in the General Timing with a Busy conversion time, tCONV, to generate the busy signal indicator. Indicator section. When the conversion is complete, SDO transitions from high If CFG readback is enabled, the CFG register associated with impedance to low (data ready), and with a pull-up to VIO, SDO the conversion result is read back MSB first following the LSB of can be used to interrupt the host to begin data transfer. the conversion result. A total of 31 SCK falling edges is required After the conversion is complete, the AD7682/AD7689 enter to return SDO to high impedance if this is enabled. the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin VIO AD7682/ DIGITAL HOST AD7689 SDO MISO IRQ SS CNV DIN MOSI SCK SCK FOR SPI USE CPHA = 1, CPOL = 1. Figure 42. Connection Diagram for the AD7682/AD7689 with a Busy Indicator t t CYC CONV t t t DATA ACQ DATA t CNVH CNV CONVERSION (QUIET (QUIET ACQUISITION CONVERSION (n – 1) ACQUISITION (n) CONVERSION (n) (n – 1) TIME) TIME) (n + 1) t SCK UPDATE (n) UPDATE (n + 1) t SCKH SEE NOTE CFG/SDO CFG/SDO 17/ 16 17/ SCK 15 1 2 15 16 31 31 t t HDIN SCKL t SDIN CFG CFG DIN XX X X X X MSB MSB –1 t END CFG (n) t BEIGN CFG (n + 1) HSDO t t DIS EN END CFG (n + 1) DIS t DSDO LSB MSB LSB SDO LSB MSB LSB + 1 – 1 + 1 SEE NOTE END DATA (n – 2) BEGIN DATA (n – 1) END DATA (n – 1) t t t EN DIS EN NOTES: 1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF 16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. Figure 43. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator Rev. D | Page 30 of 32 07353-038 07353-039 Data Sheet AD7682/AD7689 APPLICATION HINTS reference decoupling ceramic capacitor close to, ideally right up LAYOUT against, the REF and GND pins and connecting them with wide, The printed circuit board (PCB) that houses the AD7682/AD7689 low impedance traces. should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of Finally, the power supplies VDD and VIO of the AD7682/ AD7689 should be decoupled with ceramic capacitors, typically the AD7682/AD7689, with all its analog signals on the left side 100 nF, placed close to the AD7682/AD7689, and connected and all its digital signals on the right side, eases this task. using short, wide traces to provide low impedance paths and to Avoid running digital lines under the device because these reduce the effect of glitches on the power supply lines. couple noise onto the die unless a ground plane under the AD7682/AD7689 is used as a shield. Fast switching signals, EVALUATING AD7682/AD7689 PERFORMANCE such as CNV or clocks, should not run near analog signal Other recommended layouts for the AD7682/AD7689 are paths. Avoid crossover of digital and analog signals. outlined in the documentation of the evaluation board for the At least one ground plane should be used. It can be common or AD7682/AD7689 (EVAL-AD7682EDZ/EVAL-AD7689EDZ). split between the digital and analog sections. In the latter case, The evaluation board package includes a fully assembled and the planes should be joined underneath the AD7682/AD7689. tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation The AD7682/AD7689voltage reference input REF has a development data capture board, EVAL-CED1Z. dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the Rev. D | Page 31 of 32 AD7682/AD7689 Data Sheet OUTLINE DIMENSIONS 4.10 0.60 MAX 4.00 SQ 3.90 0.60 MAX 16 20 15 1 PIN 1 0.50 2.65 3.75 EXPOSED INDICATOR BSC BSC SQ PAD 2.50 SQ (BOTTOM VIEW) 2.35 5 11 10 6 0.50 0.25 MIN TOP VIEW 0.40 0.30 0.80 MAX 12° MAX 1.00 FOR PROPER CONNECTION OF 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.23 0.20 REF 0.18 COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-1 Figure 44. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Integral No Missing Temperature Package Ordering 1, 2 Model Nonlinearity Code Range Package Description Option Quantity AD7682BCPZ ±2 LSB max 16 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Tray, 490 AD7682BCPZRL7 ±2 LSB max 16 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Reel, 1,500 AD7689ACPZ ±6 LSB max 15 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Tray, 490 AD7689ACPZRL7 ±6 LSB max 15 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Reel, 1,500 AD7689BCPZ ±2 LSB max 16 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Tray, 490 AD7689BCPZRL7 ±2 LSB max 16 bits −40°C to +85°C 20-Lead QFN (LFCSP_VQ) CP-20-4 Reel, 1,500 EVAL-AD7682EDZ Evaluation Board EVAL-AD7689EDZ Evaluation Board EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED. ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07353-0-4/12(D) Rev. D | Page 32 of 32 PIN 1 INDICATOR 03-08-2012-B