ANALOG DEVICES AD768

16-Bit, 30 MSPS a D/A Converter AD768 FUNCTIONAL BLOCK DIAGRAM FEATURES 30 MSPS Update Rate V DCOM DD 16-Bit Resolution (MSB) Linearity: 1/2 LSB DNL @ 14 Bits AD768 DB15 1 LSB INL @ 14 Bits MSBs: SEGMENTED CURRENT SOURCES Fast Settling: 25 ns Full-Scale Settling to 0.025% AND SWITCHES SFDR @ 1 MHz Output: 86 dBc MSB THD @ 1 MHz Output: 71 dBc DECODER LSBs: IOUTA AND CURRENT SOURCES, Low Glitch Impulse: 35 pV-s EDGE- SWITCHES, AND IOUTB TRIGGERED Power Dissipation: 465 mW 1kΩ R-2R 1k 1k BIT LADDERS On-Chip 2.5 V Reference LATCHES LADCOM Edge-Triggered Latches 2.5V Multiplying Reference Capability BANDGAP CONTROL V EE REFERENCE AMP DB0 APPLICATIONS (LSB) Arbitrary Waveform Generation NR CLOCK NC REFCOM REFOUT IREFIN Communications Waveform Reconstruction Vector Stroke Display PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD768 is a 16-bit, high speed digital-to-analog converter 1. The low glitch and fast settling time provide outstanding (DAC) that offers exceptional ac and dc performance. The dynamic performance for waveform reconstruction or digital AD768 is manufactured on ADI’s Advanced Bipolar CMOS synthesis requirements, including communications. (ABCMOS) process, combining the speed of bipolar transistors, 2. The excellent dc accuracy of the AD768 makes it suitable for the accuracy of laser-trimmable thin film resistors, and the effi- high speed A/D conversion applications. ciency of CMOS logic. A segmented current source architecture is combined with a proprietary switching technique to reduce 3. On-chip, edge-triggered input CMOS latches interface glitch energy and maximize dynamic accuracy. Edge triggered readily to CMOS logic families. The AD768 can support up- input latches and a temperature compensated bandgap reference date rates up to 40 MSPS. have been integrated to provide a complete monolithic DAC 4. A temperature compensated, 2.5 V bandgap reference is solution. included on-chip allowing for generation of the reference The AD768 is a current-output DAC with a nominal full-scale input current with the use of a single external resistor. An ex- output current of 20 mA and a 1 kΩ output impedance. Differ- ternal reference may also be used. ential current outputs are provided to support single-ended 5. The current output(s) of the AD768 may be used singly or or differential applications. The current outputs may be tied differentially, either into a load resistor, external op amp directly to an output resistor to provide a voltage output, or fed summing junction or transformer. to the summing junction of a high speed amplifier to provide a 6. Proper selection of an external resistor and compensation buffered voltage output. Also, the differential outputs may be capacitor allow the performance-conscious user to optimize interfaced to a transformer or differential amplifier. the AD768 reference level and bandwidth for the target The on-chip reference and control amplifier are configured for application. maximum accuracy and flexibility. The AD768 can be driven by the on-chip reference or by a variety of external reference volt- ages based on the selection of an external resistor. An external capacitor allows the user to optimally trade off reference band- width and noise performance. The AD768 operates on ±5 V supplies, typically consuming 465 mW of power. The AD768 is available in a 28-pin SOIC package and is specified for operation over the industrial tem- perature range. REV. B Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1996 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (T to T , V = +5.0 V, V = –5.0 V, LADCOM, REFCOM, DCOM = 0 V, IREFIN = 5 mA, MIN MAX DD EE CLOCK = 10 MHz, unless otherwise noted) AD768–SPECIFICATIONS Parameter Min Typ Max Units RESOLUTION 16 Bits 1 DC ACCURACY Linearity Error T = +25°C–8±4 +8 LSB A to T –8 +8 LSB T MIN MAX Differential Nonlinearity = +25°C–6±2 +6 LSB T A T to T –8 +8 LSB MIN MAX Monotonicity (13-Bit) GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE ANALOG OUTPUT Offset Error –0.2 +0.2 % of FSR Gain Error –1.0 +1.0 % of FSR 2 Full-Scale Output Current 20 mA Output Compliance Range –1.2 +5.0 V Output Resistance 0.8 1.0 1.2 kΩ Output Capacitance 3 pF REFERENCE OUTPUT Reference Voltage 2.475 2.5 2.525 V 3 Reference Output Current +5.0 +15 mA REFERENCE INPUT Reference Input Current 1 5 7 mA 4 Reference Bandwidth Small Signal, IREF = 5 mA ± 0.1 mA 28 MHz Large Signal, IREF = 4 mA ± 2 mA 9 MHz TEMPERATURE COEFFICIENTS o Unipolar Offset Drift –5 +5 ppm of FSR/ C 5 o Gain Drift –20 +20 ppm of FSR/ C 6 o Gain Drift –40 +40 ppm of FSR/ C o Reference Voltage Drift –30 +30 ppm/ C 7 DYNAMIC PERFORMANCE Maximum Output Update Rate 30 40 MSPS Output Settling Time (t ) (to 0.025%) 25 35 ns ST Output Propagation Delay (t)10 ns PD Glitch Impulse 35 pV-s Output Rise Time (10% to 90%) 5 ns Output Fall Time (10% to 90%) 5 ns Output Noise (DB0–DB15 High, into 50 Ω) 3 nV/√Hz Differential Gain Error 0.01 % Differential Phase Error 0.01 Degree DIGITAL INPUTS Logic “1” Voltage 3.5 V Logic “0” Voltage 1.5 V Logic “1” Current –10 +10 μA Logic “0” Current –10 +10 μA Input Capacitance 10 pF Input Setup Time (t)10 ns S Input Hold Time (t)5 ns H Latch Pulse Width (t)10 ns LPW 7 AC LINEARITY Spurious-Free Dynamic Range (SFDR Within a Window) F = 1.002 MHz; CLOCK = 10 MHz; 2 MHz Span 86 79 dB OUT F = 1.002 MHz; CLOCK = 20 MHz; 2 MHz Span 85 dB OUT F = 5.002 MHz; CLOCK = 30 MHz; 10 MHz Span 78 dB OUT Spurious-Free Dynamic Range (SFDR to Nyquist) F = 1.002 MHz; CLOCK = 10 MHz 74 70 dB OUT F = 1.002 MHz; CLOCK = 20 MHz 73 dB OUT F = 5.002 MHz; CLOCK = 30 MHz 67 dB OUT Total Harmonic Distortion (THD) F = 1.002 MHz; CLOCK = 10 MHz –71 –68 dB OUT F = 1.002 MHz; CLOCK = 20 MHz –66 dB OUT F = 5.002 MHz; CLOCK = 30 MHz –61 dB OUT –2– REV. B AD768 Parameter Min Typ Max Units POWER SUPPLY Positive Voltage Range 4.75 5 5.25 V Negative Voltage Range –5.25 –5 –4.75 V Positive Supply Current 30 40 mA Negative Supply Current 63 73 mA Nominal Power Dissipation 465 600 mW Power Supply Rejection Ratio (PSRR) –0.2 +0.2 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal FS output current is 4× the current at IREFIN. Therefore, nominal FS current is 20 mA when IREFIN = 5 mA. 3 Output current is defined as total current available for IREFIN and any external load. 4 Reference bandwidth is a function of external cap at NR pin. Refer to compensation section of data sheet for details. 5 Excludes internal reference drift. 6 Includes internal reference drift. 7 Measured as unbuffered voltage output (1 V range) with FS current into 50 Ω load at IOUTB. Specifications subject to change without notice. * ABSOLUTE MAXIMUM RATINGS Parameter with Respect to Min Max Units Positive Supply Voltage (V ) DCOM, REFCOM, LADCOM –0.5 +6.0 V DD Negative Supply Voltage (V ) DCOM, REFCOM, LADCOM –6.0 +0.5 V EE Analog-to-Other Grounds (REFCOM) DCOM, LADCOM –0.5 +0.5 V Digital-to-Other Grounds (DCOM) LADCOM, REFCOM –0.5 +0.5 V Reference Output (REFOUT) REFCOM V + 0.5 V DD Reference Input Current (IREFIN) +7.5 mA Digital Inputs (DB0–DB15, CLOCK) DCOM –0.5 V + 0.5 V DD Analog Outputs (IOUTA, IOUTB) LADCOM –2.0 +5.0 V Maximum Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature +300 °C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device reliability. DB0–DB15 ORDERING GUIDE t t S H Package Model Package Description Option CLOCK t LPW t PD AD768AR 28-Pin 300 mil SOIC R-28 t ST 0.025% AD768ACHIPS Die IOUTA AD768-EB AD768 Evaluation Board OR IOUTB 0.025% Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD768 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– AD768 1 (T = +258C, V = +5.0 V, V = –5.0 V, I = 5 mA, unless otherwise noted) WAFER TEST LIMITS A DD EE REFIN Parameter AD768ACHIPS Limit Units 2 Integral Nonlinearity ±8 LSB max 2 Differential Nonlinearity ±6 LSB max Offset Error ±0.2 % FSR max Gain Error ±1.0 % FSR max Reference Voltage ±1.0 % of nom. 2.5 V max Positive Supply Current 40 mA max Negative Supply Current 73 mA max Power Dissipation 600 mW max NOTES 1 Electrical test are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. 2 Limits extrapolated from testing of individual bit errors. 3 Die offers latch control pad. Edge triggered latches become level triggered when latch control and clock pads are high. 4 Die substrate is connected to V EE. PIN DESCRIPTIONS Pin No. Symbol Type Name and Function 1 IOUTA AO DAC Current Output. Full-scale current when all data bits are 1s. 2 NR AI Noise Reduction Node. Add capacitor for noise reduction. 3 REFOUT AO Reference Output Voltage. Nominal value is 2.5 V. 4 NC NC No Connect. Reserved for internal use. 5 REFCOM P Reference Ground. 6 IREFIN AI Reference Input Current. Nominal is 5 mA. DAC full-scale is 4× this current. 7 DB0 DI Data Bit 0 (LSB). 8–14 DB1–DB7 DI Data Bits 1–7. 15 DCOM P Digital Ground. 16 CLOCK DI Clock Input. Data latched on positive edge of clock. 17–23 DB8–DB14 DI Data Bits 8–14. 24 DB15 DI Data Bit 15 (MSB). 25 V P Positive Supply Voltage. Nominal is +5 V. DD 26 V P Negative Supply Voltage. Nominal is –5 V. EE 27 IOUTB AO Complementary DAC Current Output. Full-scale current when all data bits are 0s. 28 LADCOM P DAC Ladder Common. Type: AI = Analog Input; DI = Digital Input; AO = Analog Output; P = Power. 3, 4 DICE CHARACTERISTICS PIN CONFIGURATION V V DB15 DB14 DB13 DB12 DB11 DB10 DD DD IOUTA 1 LADCOM 28 NR 2 IOUTB 27 DB9 V EE REFOUT 3 26 V (–5V) EE V EE DB8 NC 4 V (+5V) 25 DD REFCOM 5 DB15 (MSB) 24 IOUTB CLOCK IREFIN 6 23 DB14 AD768 (LSB) DB0 7 TOP VIEW LATCH CONTROL 22 DB13 LADCOM (Not to Scale) 8 DB1 21 DB12 DCOM IOUTA DB2 9 20 DB11 DB7 NR DB3 10 19 DB10 DB6 11 18 DB4 DB9 REFOUT DB5 12 17 DB8 DB5 NC DB6 13 16 CLOCK REFCOM IREFIN DB0 DB1 DB2 DB3 DB4 DB7 14 15 DCOM NC = NO CONNECT Die Size: 0.1106 × 0.1417 inch, 15,672 sq. mils (2.81 × 3.60 mm, 10.116 sq. mm) REV. B –4– AD768 DEFINITIONS OF SPECIFICATIONS Temperature Drift Linearity Error (Also Called Integral Nonlinearity or INL) Temperature drift is specified as the maximum change from the Linearity error is defined as the maximum deviation of the ac- ambient (+25°C) value to the value at either T or T . For MIN MAX tual analog output from the ideal output, determined by a offset and gain drift, the drift is reported in ppm of full-scale straight line drawn from zero to full scale. range (FSR) per degree C. For reference drift, the drift is re- ported in ppm per degree C. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized Power Supply Rejection to full scale, associated with a 1 LSB change in digital input code. The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified Monotonicity voltages. A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Settling Time The time required for the output to reach and remain within a Offset Error specified error band about its final value, measured from the The deviation of the output current from the ideal of zero is start of the output transition. called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected Spurious-Free Dynamic Range when all inputs are set to 1s. The difference, in dB, between the rms amplitude of the input signal and the peak spurious signal over the specified Gain Error bandwidth. The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set Total Harmonic Distortion to 1s minus the output when all inputs are set to 0s. The ideal THD is the ratio of the rms sum of the first six harmonic com- output current span is 4× the current applied to the IREFIN pin. ponents to the rms value of the measured input signal. It is ex- pressed as a percentage or in decibels (dB). Output Compliance Range The range of allowable voltage at the output of a current-output Glitch Impulse DAC. Operation beyond the maximum compliance limits may Asymmetrical switching times in a DAC give rise to undesired cause either output stage saturation or breakdown, resulting in output transients which are quantified by a glitch impulse. It is nonlinear performance. specified as the net area of the glitch in pV-sec. C REFCOMP R REF 1µF 500Ω 4 3 6 NC REFOUT REFIN IOUTA V 1 DD IOUTA +5V 25 +2.5V REF 5mA IOUTB 27 IOUTB 1µF REFCOM R R 5 LAD LAD R LOAD 50Ω 1µF 1kΩ 1kΩ 50Ω NR 2 1µF LADCOM 28 C V NR EE 26 –5V SEGMENTED 15 DCOM AD768 CURRENT CURRENT SOURCES SOURCES AND R-2R LADDER CLOCK MSB DECODE CLOCK 16 LATCHES – LOWER 12 BITS & LATCHES 24 23 22 21 20 19 18 17 14 13 12 11 10 9 8 7 Figure 1. Functional Block Diagram and Basic Hookup FUNCTIONAL DESCRIPTION The digital interface offers CMOS compatible edge-triggered The AD768 is a current-output DAC with a nominal full-scale input latches that interface readily to CMOS logic and supports current of 20 mA and a 1 kΩ output impedance. Differential clock rates up to 40 MSPS. A temperature compensated 2.5 V outputs are provided to support single-ended or differential bandgap reference is integrated on-chip to drive the AD768 ref- applications. The DAC architecture combines segmented cur- erence input current with the use of a single external resistor. rent sources for the top four bits (MSBs) and a 1 kΩ R-2R lad- The functional block diagram in Figure 1 is a simple representa- der for the lower 12 bits (LSBs). The DAC current sources are tion of the internal circuitry to aid the understanding of the implemented with laser-trimmable thin film resistors for excel- AD768’s operation. The DAC transfer function is described, lent dc linearity. A proprietary switching technique is utilized to and followed by a detailed description of each key portion of the reduce glitch energy and maximize dynamic accuracy. circuit. Typical circuit configurations are shown in the section APPLYING THE AD768. REV. B –5– DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AD768 DAC TRANSFER FUNCTION 550 The AD768 may be used in either current-output mode with the output connected to a virtual ground, or voltage-output mode 500 with the output connected to a resistive load. In current output mode, 450 I = (DAC CODE/65536) × (I × 4) OUT REFIN In voltage output mode, 400 V = I × R iR OUT OUT LOAD LAD where: 350 DAC CODE is the decimal representation of the DAC inputs; an integer between 0 and 65535. I is the current applied at the IREFIN pin, determined by 300 REFIN 1.0 2.0 3.0 4.0 5.0 6.0 7.0 V /R . REF REF I – mA REFIN Substituting for I and I , OUT REFIN Figure 3. Power Dissipation vs. I Current REFIN V = –V × (DAC CODE/65536) × 4 × [(R iR )/R ] OUT REF LOAD LAD REF Note the AD768 is optimized for operation at an input current These equations clarify an important aspect of the AD768 of 5 mA. Both linearity and dynamic performance at other input transfer function; the full-scale current output of the DAC is currents may be somewhat degraded. Figure 4 shows typical dc proportional to a current input. The voltage output is then a linearity over a range of input currents. Figure 5 shows typical function of the ratio of (R iR )/R , allowing for cancel- LOAD LAD REF SFDR (to Nyquist) performance over a range of input currents lation of resistor drift by selection of resistors with matched and CLOCK input rates for a 1 MHz output frequency. characteristics. 10 REFERENCE INPUT 9 The IREFIN pin is a current input node with low impedance to REFCOM. This input current sets the magnitude of the DAC 8 current sources such that the full-scale output current is exactly 7 four times the current applied at IREFIN. For the nominal in- 6 put current of 5 mA, the nominal full-scale output current is 20 mA. 5 INL The 5 mA reference input current can be generated from the 4 on-chip 2.5 V reference with an external resistor of 500 Ω from 3 REFOUT to IREFIN. If desired, a variety of external reference 2 voltages may be used based on the selection of an appropriate DNL resistor. However, to maintain stability of the reference ampli- 1 fier, the external impedance at IREFIN must be kept below 0 1kΩ. 1.0 2.0 3.0 4.0 5.0 6.0 7.0 I – mA REFIN REFCOM 5 Figure 4. INL/DNL vs. I Current REFIN IREFIN 6 –85 IFB 5mA CLOCK = 10 MSPS –80 V V EE EE –75 CLOCK = 20 MSPS Figure 2. Equivalent Reference Input Circuit The I current can be varied from 1 mA to 7 mA which –70 REFIN CLOCK = 30 MSPS subsequently will result in a proportional change in the DAC full-scale. Since the operating currents within the DAC vary –65 with I , so does the power dissipation. Figure 3 illustrates CLOCK = 40 MSPS REFIN that relationship. –60 –55 1.0 2.0 3.0 4.0 5.0 6.0 7.0 I – mA REFIN Figure 5. SFDR (to Nyquist) vs. I @ F = 1 MHz REFIN OUT REV. B –6– POWER – mW SFDR – dB ERROR – LSB AD768 REFERENCE OUTPUT 100M The internal 2.5 V bandgap reference is provided for generation of the I current, and must be compensated externally with REFIN 10M a capacitor of 0.1 μF or greater from REFOUT to REFCOM. If an external reference is used, REFOUT should be tied directly to the positive supply voltage, V . This effectively turns off the DD 1M internal reference, eliminating the need for the external capaci- tor at REFOUT. The reference is specified to drive a nominal 100k load of 5 mA with a maximum of 15 mA. Operation with a heavier load will result in degradation of supply rejection and reference voltage accuracy. Therefore, the reference output 10k should be buffered with an amplifier when additional load cur- rent is required. A properly sized pull-up resistor can also be used to source additional current to the load. The resistors value 1k 10p 100p 1n 10n 100n 1µ should be selected such that REFOUT will always source a NOISE REDUCTION CAPACITOR – F minimum of 5 mA to IREFIN and the additional load. Figure 7. External Noise Reduction Capacitor vs. –3 dB AD768 Bandwidth 500Ω 6 IREFIN The sensitivity of the NR node requires that care be taken in 3 REFOUT capacitor placement. The capacitor should be located as physi- CREFCOMP cally close to the package pins as possible and lead lengths 1µF 5 REFCOM should be minimized. For this purpose, the use of a chip capacitor is recommended. For applications that do not require high frequency modulation at IREFIN, it is recommended that a capacitor on the order of 1 μF be connected from NR to V . EE Figure 6. Typical Reference Hookup If the reference input is purely dc, noise may be minimized with multiple capacitors, such as 1 μF and 0.1 μF, to more effectively TEMPERATURE CONSIDERATIONS filter both high and low frequency disturbances. Note that the reference plays a key role in the overall tempera- ture performance of the AD768. Any drift of I shows up REFIN ANALOG OUTPUTS directly in I When the output is taken as a current, the drift OUT. The AD768 offers two analog outputs; IOUTA is trimmed for of I (which depends on both V and R ) must be mini- REFIN REF REF optimal INL and DNL performance and has a full-scale output mized. This can be done by using the internal temperature com- when all bits are high. For applications that require the specified pensated reference for V and a low temperature coefficient REF dc accuracy, IOUTA should be used. IOUTB is the comple- resistor for R If the output is taken as a voltage, it is a func- REF. mentary output with full-scale output when all bits are low. tion of a resistor ratio, not an absolute resistor value. By select- Both IOUTA and IOUTB provide similar dynamic perfor- ing resistors with matched temperature coefficients for R REF mance. Refer to Figures 8 and 9 for typical INL and DNL per- and R the drift in the resistor values will cancel, providing LOAD, formance curves. The outputs can also be used differentially. optimal drift performance. Refer to the section “Applying the AD768” for examples of vari- ous output configurations. REFERENCE NOISE REDUCTION AND MULTIPLYING BANDWIDTH 8 For application flexibility and multiplying capabilities, the refer- 6 ence amplifier is designed to offer adjustable bandwidth that can be reduced by connecting an external capacitor from the NR 4 node to the negative supply pin, V . This capacitor limits the EE 2 bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. 0 The noise reduction capacitor, C , is not required for stability NR –2 and does not affect the settling time of the DAC output. With- out this capacitor, the I bandwidth is 15 MHz allowing REFIN –4 high frequency modulation of the DAC full-scale range through –6 the reference input node. Figure 7 shows the relationship be- tween the external noise reduction capacitor and the –3 dB –8 06 5 10152 2053 305 40455 505 605 bandwidth of the reference amplifier. DIGITAL INPUT CODE – k Figure 8. Typical INL Performance REV. B –7– BANDWIDTH – Hz INL ERROR – LSB AD768 8 LADCOM IOUTB IOUTA 1 28 27 6 1kΩ 1kΩ 4 3pF 3pF 2 I I OUT OUT IREFIN x2.75 0 –2 26 V EE –4 –6 Figure 10. Equivalent Analog Output Circuit –8 DIGITAL INPUTS 06 5 10152 2053 305 40455 505 605 DIGITAL INPUT CODE – k The AD768 digital inputs consist of 16 data input pins and a clock pin. The 16-bit parallel data inputs follow standard posi- tive binary coding, where DB15 is the most significant bit Figure 9. Typical DNL Performance (MSB) and DB0 is the least significant bit (LSB). IOUTA pro- The outputs have a compliance range of –1.2 V to +5.0 V with duces full-scale output current when all data bits are at logic 1. respect to LADCOM. The current steering output stages will IOUTB is the complementary output, with full-scale when all remain functional over this range. Operation beyond the maxi- data bits are at logic 0. The full-scale current is split between mum compliance limits may cause either output stage saturation the two outputs as a function of the input code. or breakdown, resulting in nonlinear performance. The rated dc The digital interface is implemented using an edge-triggered and ac performance specifications are for an output voltage of master slave latch. The DAC output is updated following the 0 V to –1 V. rising edge of the clock, and is designed to support a clock rate The current in LADCOM is proportional to I and has been REFIN as high as 40 MSPS. The clock can be operated at any duty carefully configured to be independent of digital code when the cycle that meets the specified minimum latch pulse width. The output is connected to a virtual ground. This minimizes any det- setup and hold times can also be varied within the clock cycle as rimental effects of ladder ground resistance on linearity. For long as the specified minimums are met, although the location optimal dc linearity, IOUTA should be connected directly to a of these transition edges may affect digital feedthrough. The virtual ground, and IOUTB should be grounded. An example of digital inputs are CMOS compatible with logic thresholds set to this configuration is provided in the section “Buffered Voltage approximately half the positive supply voltage. The small input Output.” If IOUTA is driving a resistive load directly, then current requirements allow for easy interfacing to unbuffered IOUTB should be terminated with an equal impedance. This CMOS logic. Figure 11 shows the equivalent digital input will ensure the current in LADCOM remains constant with digi- circuit. tal code, and is recommended for improved dc linearity in the V unbuffered voltage output configuration. CC V CC As shown in Figure 10, there is an equivalent output impedance of 1 kΩ in parallel with 3 pF at each output terminal. If the out- DIGITAL put voltage deviates from the ladder common voltage, an error INPUT current flows through this 1 kΩ impedance. This is a linear effect which does not change with input code, so it appears as a gain V DCOM EE error. With 50 Ω output termination, the resulting gain error is approximately –5%. An example of this configuration is pro- vided in the section Unbuffered Voltage Output. Figure 11. Equivalent Digital Input Circuit Digital input signals to the DAC should be isolated from the analog output as much as possible. Interconnect distances to the DAC inputs should be kept as short as possible. Termination resistors may improve performance if the digital lines become too long. To minimize digital feedthrough, the inputs should be free from glitches and ringing, and may be further improved with a reduction of edge speed. REV. B –8– DNL ERROR – LSB Typical Performance Curves––AD768 AD768 –0.470 –0.9405 1.00 0.2 R = 50Ω R = 50Ω L L 0.90 –0.9415 V = 0 TO –1V OUT –0.472 V = 0 TO –1V OUT R = 50Ω L –0.9424 0.80 0.0 V = 0 TO –1V OUT 0.70 –0.9433 –0.474 –0.2 –0.9443 0.60 –0.4 –0.476 0.50 –0.9453 –0.9462 0.40 –0.6 –0.478 0.30 –0.9472 –0.8 –0.9481 0.20 –0.480 –1.0 0.10 –0.9498 0.05 0.025 –0.9500 –0.482 TIME – 5ns/Div 12 14 16 18 20 22 24 26 28 30 32 34 36 TIME – 2ns/Div TIME – ns Figure 14. Rise and Fall Figure 13. Glitch Impulse at Major Figure 12. Settling Time Characteristics Carry 0 0 –80 R = 50Ω CLOCK = 10MHz L F = 1.002MHz CLOCK = 10MHz V = 0 TO –1V OUT OUT –75 –20 –20 F = 1.002MHz OUT AMPLITUDE = 0dBm AMPLITUDE = 0dBm OUTPUT IOUTB R = 50Ω L –70 –40 –40 –65 –60 –60 –60 –80 –80 –55 –100 –50 –100 10k 1.0M 2.0M 42 56 7 89100 3040 0.1124 3 5 FREQUENCY – Hz FREQUENCY – MHz FREQUENCY – MHz Figure 15. THD vs. Clock Frequency Figure 16. Typical Spectral Figure 17. Typical SFDR at F = 1 MHz Performance (With a Window) OUT –86 –80 0 CLOCK = 10 MHz CLOCK = 30MHz CLOCK = 1MHz F = 240 kHz OUT1 –82 F = 260 kHz –75 OUT2 CLOCK = 10MHz –20 AMPLITUDE = –6.0 dB FS –78 PER TONE OUTPUT IOUTB –70 R = 50Ω –74 L CLOCK = 10MHz –40 CLOCK = 20MHz –70 –65 CLOCK = 30MHz –66 –60 –60 –62 CLOCK = 40MHz –80 –58 –55 –54 CLOCK = 20MHz –50 –100 –50 0.01 0.1 1 10 150 190 230 270 310 350 1 10 FREQUENCY – MHz FREQUENCY – Hz FREQUENCY – MHz Figure 18. SFDR (Within a Window) Figure 19. THD vs. F Figure 20. Intermodulation OUT vs. F Distortion OUT REV. B –9– OUTPUT – dB SFDR THD – dB ERROR BAND – % OUTPUT – V OUTPUT – dB THD – dB OUTPUT – dB VOLTS OUTPUT – dB AD768 APPLYING THE AD768 DAC output is the parallel combination of the AD768’s output OUTPUT CONFIGURATIONS impedance, R , and bias resistor R . The nominal output swing L B The following sections illustrate some typical output configura- with the values given in Figure 22 is ±0.5 V assuming R >> R . B L tions for the AD768. While most figures take the output at The gain of the circuit will be a function of the tolerances of the IOUTA, IOUTB can be interchanged in all cases. Unless other- impedances R , R , and R . LAD B L wise noted, it is assumed that I and full-scale currents are REFIN Choosing the value of R and C will depend primarily on the B set to nominal values. desired –3 dB high pass cutoff frequency and the bias current, For application that require the specified dc accuracies, proper I , of the subsequent stage connected to R . The –3 dB fre- B B resistor selection is required. In addition to absolute resistor tol- quency can be approximated by the equation, erances, resistor self-heating can result in unexpected errors. For f = 1/[2 × π × (R + R iR ) × C]. –3 dB B L LAD optimal INL, the buffered voltage output is recommended as The dc offset of the output is a function of the bias current of shown in Figure 23. In this configuration, self-heating of R FB the subsequent stage and the value of R . For example, if B may cause a change in gain, producing a bow in the INL curve. C = 390 pF, R = 20 kΩ, and I = 1.0 μA, the –3 dB frequency B B This effect can be minimized by selection of a low temperature is approximately 20.4 kHz and the dc offset would be 20 mV. coefficient resistor. UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS AD768 I B C Figure 21 shows the AD768 configured to provide a unipolar IOUTA 1 output range of approximately 0 V to –1 V. The nominal full- R L IOUTB 27 R scale current of 20 mA flows through the parallel combination B 49.9Ω R L of the 50 Ω R resistor and the 1 kΩ DAC output resistance L 49.9Ω LADCOM 28 (from the R-2R ladder), for a combined 47.6 Ω. This produces an ideal full-scale voltage of –0.952 V with respect to LADCOM. In addition, the 1 kΩ DAC output resistance has a tolerance of Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output ±20% which may vary the full-scale gain by ±1%. This linear variation results in a gain error which can be easily compensated BUFFERED VOLTAGE OUTPUT CONFIGURATIONS for by adjusting I . REFIN Unipolar Configuration For positive output voltages, or voltage ranges greater than AD768 allowed by output compliance limits, some type of external IOUTA buffer is needed. A wide variety of amplifiers may be selected 1 R L based on considerations such as speed, accuracy and cost. The VA 49.9Ω AD9631 is an excellent choice when dynamic performance is LADCOM 28 R L important, offering low distortion up to 10 MHz. Figure 23 VB 49.9Ω shows the implementation of 0 V to +2 V full-scale unipolar IOUTB 27 buffered voltage output. The amplifier establishes a summing node at ground for the DAC output. The buffered output volt- age results from the DAC output current flowing through the Figure 21. 0 V to –1 V Unbuffered Voltage Output amplifier’s feedback resistor, R . In this case, the 20 mA full- FB In this configuration, it is important to note the restrictions from scale current across R (100 Ω) produces an output voltage FB the output compliance limits. The maximum negative voltage range of 0 V through +2 V. The same configuration using a pre- compliance is –1.2 V, prohibiting use of a 100 Ω load to produce cision amplifier such as the AD845 is recommended for optimal a 0 V to –2 V output swing. One additional consideration for dc linearity. operation in this mode is integral nonlinearity. As the voltage at R FB the output node changes, the finite output impedance of the 100Ω DAC current steering switches gives rise to small changes in the AD768 output current that vary with output voltage, producing a bow IOUTA 1 (up to 8 LSBs) in the INL. For optimal INL performance, the A1 buffered voltage output mode is recommended. IOUTB 27 The INL is also slightly dependent on the termination of the LADCOM 28 unused output (IOUTB) as described in the ANALOG OUT- PUT section. To eliminate this effect, IOUTB should be termi- Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output nated with the same impedance as IOUTA, so both outputs see the same resistive divider to ground. This will keep the current Buffered Output Using a Current Divider in LADCOM constant, minimizing any code-dependent IR The configuration shown in Figure 23 may not be possible in drops within the DAC ladder that may give rise to additional cases where the amplifier cannot supply the requisite 20 mA nonlinearities. feedback current. As an alternative, Figure 24 shows amplifier A1 in conjunction with a resistive current divider. The values of AC-Coupled Output R and R are chosen to limit the current, I , which must be FF L 3 Configuring the output as shown in Figure 22 provides a bipolar supplied by A1. Current, I , is shunted to ground through resis- 2 output signal from the AD768 without requiring the use of a tor, R . The parallel combination of R and R should not ex- L FF L summing amplifier. The ac load impedance presented to the ceed 60 Ω to avoid exceeding the specified compliance voltage. REV. B –10– AD768 primary side is multiplied by a factor of 4 (i.e., in this case For the values given in Figure 24, I equals 4 mA, which results 3 200 Ω). To avoid dc current from flowing into the R-2R ladder in a nominal unipolar output swing of 0 V to 2 V. Note, since of the DAC, the center tap of the transformer should be con- A1 has an inverting gain of approximately –4 and a noise gain of nected to LADCOM. +5, A1’s distortion and noise performance should be considered. R FB In order to comply with the minimum voltage compliance of 500Ω –1.2 V, the maximum differential resistance seen between R FF AD768 I I 1 3 100Ω IOUTA and IOUTB should not exceed 240 Ω. Note that the IOUTA 1 differential resistance consists of the load R , referred to the L A1 I 2 R L primary side of the transformer in parallel with any added differ- IOUTB 27 24.9Ω R P ential resistance, R , across the two outputs. R is typically DIFF DIFF 20Ω added to the primary side of the transformer to match the effec- LADCOM 28 tive primary source impedance to the load (i.e., in this case 200 Ω). Figure 24. 0 V to 2 V Buffered Unipolar Output Using a Current Divider AD768 IOUTA 1 Bipolar Configuration Bipolar mode is accomplished by providing an offset current, R DIFF R T1 L 200Ω 50Ω I , to the I/V amplifier’s (A1) summing junction. By set- BIPOLAR ting I to exactly half the full-scale current flowing BIPOLAR IOUTB 27 4:1 IMPEDANCE through R , the resulting output voltage will be symmetrical FB RATIO LADCOM 28 about the summing junction voltage, typically ground. Figure 25 T1 = MINI-CIRCUITS T4-6T shows the implementation for a bipolar ±2.5 V buffered voltage output. The resistor divider sets the full-scale current for I to DAC Figure 26. Differential Output Using a Transformer 5 mA. The internal 2.5 V reference generates a 2.5 mA I BIPOLAR current across R . An output voltage of 0 V is produced when BIP DC COUPLING VIA AN AMPLIFIER the DAC is set to half scale (100. . .0) such that the 2.5 mA cur- A dc differential to single-ended conversion can be easily ac- rent, I , is exactly offset by I . As the DAC is varied DAC BIPOLAR complished using the circuit shown in Figure 27. This circuit from zero to full-scale, the output voltage swings from –2.5 V to will attenuate both ac and dc common-mode error sources due +2.5 V. Note, in configurations that require more than 15 mA to the differential nature of the circuit. Thus, common-mode of total current from REFOUT, an external buffer is required. noise (i.e., clock feedthrough) as well as dc unipolar offset errors will be significantly reduced. Also, excellent temperature stabil- Op amps such as the AD811, AD8001, and AD9631 are good ity can be obtained by using temperature tracking, thin film selections for superior dynamic performance. In dc applications, resistors for R and R . The design equations for the circuit are REF op amps such as the AD845 or AD797 may be more appropriate. provided such that the voltage output swing and IREF can be R BIP AD768 optimized for a given application. 1kΩ REFOUT 3 R R* FB C 1kΩ I BIPOLAR AD768 I IOUTA 75Ω DAC 1 V = ±4 I R OUT REF IOUTA 1 A1 V OUT 2.5V WHERE I = A1 IOUTB 27 REF R REF 24.9Ω IOUTB 27 R* R P V ± 2V OUT 20Ω LADCOM 28 R = 200Ω LADCOM 28 R = 5 x 200Ω REF REFIN 6 R * I REF REF *OHMTEK TDP-1403 Figure 25. Bipolar ±2.5 V Buffered Voltage Output REFOUT 3 DIFFERENTIAL OUTPUT CONFIGURATIONS Figure 27. DC Differential to Single-Ended Conversion AC Coupling via a Transformer Applications that do not require baseband operation typically POWER AND GROUNDING CONSIDERATIONS use transformer coupling. Transformer coupling the comple- In systems seeking to simultaneously achieve high speed and mentary outputs of the AD768 to a load has the inherent benefit high accuracy, the implementation and construction of the of providing electrical isolation while consuming no additional printed circuit board design is often as important as the circuit power. Also, a properly applied transformer should not degrade design. Proper RF techniques must be used in device selection, the AD768’s output signal with respect to noise and distortion, placement and routing, and supply bypassing and grounding. since the transformer is a passive device. Figure 26 shows a center-tapped output transformer that provides the necessary dc Maintaining low noise on power supplies and ground is critical load conditions at the outputs IOUTA and IOUTB to drive a to obtaining optimum results from the AD768. Figure 28 pro- ±0.5 V signal into a 50 Ω load. In this particular circuit, the cen- vides an illustration of the recommended printed circuit board ter-tapped transformer has an impedance ratio of 4 that corre- ground plane layout which is implemented on the AD768 evalu- sponds to a turns ratio of 2. Hence, any load, R , referred to the L ation board. REV. B –11– AD768 Figure 28. Printed Circuit Board Ground Plane Layout Figure 29. Printed Circuit Board Power Plane Layout REV. B –12– AD768 If properly implemented, ground planes can perform a host of A clean digital supply may be generated using the circuit shown functions on high speed circuit boards: bypassing, shielding, in Figure 30. The circuit consists of a differential LC filter with current transport, etc. In mixed signal design, the analog and separate power supply and return lines. Lower noise can be at- digital portions of the board should be distinct from each other, tained using low ESR (Equivalent Series Resistance) type elec- with the analog ground plane confined to the areas covering trolytic and tantalum capacitors. analog signal traces and the digital ground plane confined to areas covering the digital interconnects. TTL/CMOS FERRITE LOGIC BEADS All analog ground pins of the DAC, reference, and other analog CIRCUITS V DD 100µF 10–20µF 0.1µF output components, should be tied directly to the analog ground ELECT. TANT. CER. plane. The two ground planes should be connected by a path DCOM 1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC +5V DGND as shown in Figure 28. Care should be taken to ensure that the +5V ground plane is uninterrupted over crucial signal paths. On the POWER SUPPLY digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this in- cludes the DAC output signal, reference signal, and the supply Figure 30. Differential LC Filter for Single +5 V feeders. Applications The use of wide runs or planes in the routing of power lines is APPLICATIONS also recommended. This serves the dual role of providing a low USING THE AD768 AS A MULTIPLYING DAC series impedance power supply to the part, as well as, providing The AD768 can be easily configured as a multiplying DAC some “free” capacitive decoupling to the appropriate ground since I can be modulated from 1 mA to 7 mA. The refer- REFIN plane. Figure 29 illustrates the power plane layout used in the ence amplifier sets the maximum multiplying bandwidth to 15 AD768 evaluation board. The AD768 evaluation board uses a MHz, while any external capacitor to the NR node serves to four layer P.C. board which illustrates good layout practices as limit the bandwidth according to Figure 7. I can be easily REFIN discussed above. modulated by properly scaling and summing into the IREFIN It is essential that care be taken in the layout of signal and node the modulating signal. Figure 31 demonstrates how the power ground interconnects to avoid inducing extraneous volt- modulating signal VMOD can be properly scaled and converted age drops in the signal ground paths. It is recommended that all to a current via R such that its peak current does not ex- REFMOD connections be short, direct and as physically close to the pack- ceed 3.0 mA. Figure 32 shows the AD768’s typical distortion age as possible, in order to minimize the sharing of conduction versus the reference channel frequency. paths between different currents. When runs exceed an inch in length, some type of termination resistor should be considered. AD768 The necessity and value of this resistor will be dependent upon R REFMOD VMOD 6 IREFIN the logic family used. R REF For maximum ac performance, the DAC should be mounted 625Ω 3 REFOUT directly to the circuit board; sockets should be avoided since 1µF they introduce unwanted capacitive coupling between adjacent VMOD pins of the device. ≤ ±3.0mA R REFMOD POWER SUPPLY AND DECOUPLING One of the most important external components associated with Figure 31. Typical Multiplying DAC Application high speed designs are the capacitors used to bypass the power supplies. Both selection and placement of these capacitors can –75 be critical and, to a large extent, dependent upon the specifics of the system configuration. The dominant consideration in the –70 I = 5.0+/–1 mA REF selection of bypass capacitors for the AD768 is the minimization of the series resistance and inductance. Many capacitors will –65 begin to look inductive at 20 MHz and above. Ceramic and film I = 4.0+/–2 mA REF type capacitors generally feature lower series inductance than –60 tantalum or electrolytic types. –55 It is recommended that each power supply to the AD768 be de- I = 4.0+/–3 mA REF coupled by a 0.1 μF capacitor located as close to the device pins –50 as possible. Surface-mount chip capacitors, by virtue of their low parasitic inductance, are preferable to through-hole types. –45 Some series inductance between the DAC supply pins and the power supply plane may help to provide additional filtering of –40 250 500 750 1000 1250 1500 1750 2000 2250 2500 high frequency power supply noise. This inductance can be gen- FREQUENCY – kHz erated by using small ferrite beads. Figure 32. Reference Channel Distortion vs. Frequency REV. B –13– THD – dB AD768 1.5 AD768 IN MULTITONE TRANSMITTERS (FOR ADSL) Communications applications frequently require aspects of 1.0 component performance that differ significantly from the simple, single tone signals used in typical SNR and THD tests. This is particularly true for spread-spectrum and frequency divi- 0.5 sion multiplexed (FDM) type signals, where information con- tent is held in a number of small signal components spread 0 across the frequency band. In these applications, a combination of wide dynamic range, good fine-scale linearity, and low inter- –0.5 modulation distortion is required. Unfortunately, a part’s full scale SNR and THD performance may not be a reliable indica- –1.0 tor of how it will perform in these multitone applications. One example of an FDM communications system is the DMT –1.5 TIME – 25µs/DIV (discrete multitone) ADSL (Asymmetrical Digital Subscriber Line) standard currently being considered by ANSI. Figure 33 shows a block diagram of a transmitter function. Figure 34b. Time Domain Output Signal of ADSL Test The digital bits are used to QAM modulate each of approxi- Vector mately 200 discrete tones. An inverse FFT turns this modu- Table I and II show the available SNR and THD at the output lated frequency domain information into 512 time points at a of the filter vs. frequency bin for the ADSL application. The 2.2 MSPS sample rate. These time points are then put through AD768’s combination of 16-bit dynamic range and 14-bit lin- an FIR interpolation filter to upsample (in this case to 4.4 MSPS). earity provides excellent performance for the DMT signal. Its The bit stream is run through the AD768, which is followed by fast input rate would support even faster rates of oversampling, a 4th order analog smoothing filter, then run to the line-driving if one were interested in trading off digital filter complexity in circuitry the interpolator for a simplified analog filter. 1024 TIME BIT 256 512 TIME POINTS STREAM MODULATED POINTS 2X @ 4.4MSPS QAM INVERSE INTERPOLATOR FFT ENCODER FREQUENCY @ 2.2MSPS FIR Table I. SNR vs. Frequency BINS Frequency SNR 4TH ORDER AD768 TO SMOOTHING +BUFFER TRANSMITTER FILTER 151 kHz 70.1 dB 349 kHz 69.7 dB 500 kHz 69.4 dB Figure 33. Typical DMT ADSL Transmit Chain 1 MHz 69.8 dB Figure 34a shows a frequency domain representation of a test vector run through this system, while 34b shows the time do- Table II. THD vs. Frequency main representation. (Clearly the frequency domain picture is more informative.) We wish to optimize the SINAD of each Frequency THD 4 kHz frequency band: this is a function of both noise 160 kHz –68.9 dBc (wideband and quantization) and distortion (simple harmonic 418 kHz –64.0 dBc and intermod). 640 kHz –64.3 dBc 0 893 kHz –63.8 dBc –20 –40 –60 –80 0 1.1M FREQUENCY – Hz Figure 34a. Output Spectrum of ADSL Test Vector REV. B –14– OUTPUT – dB OUTPUT – Volts AD768 AD768 EVALUATION BOARD JP1. Buffered op amp output “A”. Jumper JP1 should be GENERAL DESCRIPTION installed if the buffered op amp output is desired. When JP1 The AD768-EB is an evaluation board for the AD768 16-bit is installed, JP2 and JP3 must be removed for proper 30 Msps D/A converter. Careful attention to layout and circuit operation. The output, available on the “A” connector, has a design combined with analog and digital prototyping areas al- nominal voltage swing of 0 V to 2 V and is in-phase with the lows the user to easily and effectively evaluate the AD768 in any digital input. This is the factory default setting. application where high resolution, high speed conversion is JP2. Bipolar 50 Ω transformer output. If jumper JP2 is in- required. stalled, a transformer coupled output is available on the “A” The digital inputs to the AD768-EB may be driven directly us- connector. When JP2 is installed, JP1 and JP3 must be re- ing the standard 40-pin IDC connector. An external clock is moved for proper operation. The transformer acts both as a also required. These signals may be applied from a user’s differential-to-single-ended converter and as an impedance bench, or they can be generated from a circuit built on the transformer. For proper operation, the transformer must be prototyping area. The analog outputs from the AD768-EB are terminated with a 50 Ω resistor. R2 must be replaced with available on BNC connectors. These outputs may be configured the 100 Ω resistor, R7. An additional 100 Ω resistor and the to use either resistors, op amps, or a transformer. transformer are included with the AD768-EB. The additional 100 Ω resistor must be soldered into the appropriate position la- OPERATING PROCEDURE AND FUNCTIONAL beled “R3” and the transformer must be inserted into the DESCRIPTION socket labeled “T1.” The nominal output voltage into a 50 Ω Power load is 1 V p-p centered on a common-mode voltage of 0 V. Power may be supplied to the AD768-EB by applying either JP3. Resistor output “A.” JP3 is used to connect the resistor wires or banana plugs to the metal binding posts included on the R2 to the “A” output. U2 should be removed from its socket. printed circuit board. Using a 24.9 Ω resistor for R2, the output is an unbuffered 0 V DGND. Digital Ground. The digital ground and the analog to –0.5 V output that is out of phase with the digital input. Re- ground are connected together underneath the AD768. Optimal sistor R2 may be replaced with other values, but careful atten- performance can be obtained with separate analog and digital tion to the recommended output compliance range should be supplies. For evaluation purposes, a single-supply which makes observed. When JP3 is installed, JP1 and JP2 must be re- a second analog and digital ground connection at the supply is moved for proper operation. acceptable. JP4. Resistor output “B.” JP4 is used to connect the resistor +5D. The +5 V (±5%) digital supply should be capable of sup- R3 to the “A” output. U3 should be removed from its socket. plying 50 mA. The AD768-EB is shipped from the factory with resistor R3 shorted to ground. A different value selected by the user can be –5A. The –5 V (±5%) analog supply should be capable of sup- installed for R3 to generate an unbuffered output that is in- plying –75 mA. phase with the digital input. Careful attention to the recom- AGND. Analog ground. The analog ground and the digital mended output compliance range should be observed when ground are connected together underneath the AD768. Optimal selecting the value of R3. When JP4 is installed, JP5 must performance can be obtained with separate analog and digital be removed for proper operation. supplies. For evaluation purposes, a single-supply which makes JP5. Buffered op amp output “B.” Jumper JP5 should be in- a second analog and digital ground connection at the supply is stalled if the buffered op amp output is desired. When JP5 is acceptable. installed, JP4 must be removed for proper operation. –V . Negative analog supply; typically –5 V to –15 V. This EE The output is available on the “B” connector and has a nominal supply is used as the negative supply rail for the external op voltage swing determined by the combination of resistors R3, amps. For the AD811 supplied with the AD768-EB, a supply R9, and R10. This op amp is not provided with the AD768-EB. capable of supplying –20 mA (excluding external load require- Reference ments) is required. Either the internal reference of the AD768 or an external refer- +V . Positive analog supply; typically +5 V to +15 V. This CC ence may be selected on the AD768-EB. R12 is used to adjust supply is used as the positive supply rail for the external op the full-scale output current of the AD768. amps. For the AD811 supplied with the AD768-EB, a supply SW2. Internal/External reference select switch. When SW2 is capable of supplying +20 mA (excluding external load require- in position 1, the internal reference of the AD768 is selected. ments) is required. When SW2 is in position 2, an external reference must be pro- Analog Outputs vided by the user. The analog output(s) from the AD768-EB are available on BNC Level-Shifting the Analog Output jacks “A” and “B.” The complementary current outputs from Resistor sockets R8 and R6 can be populated with an appropri- the AD768 can be configured using either resistors, op amps, or ately valued resistor to add dc offset current to an output which a transformer. Only the “A” portion of the AD768-EB is popu- uses the op amp configuration. As an example, to generate a lated and shipped from the factory. The “B” side, or comple- bipolar output signal, a 1.25 kΩ resistor installed into the “R8” mentary output, may be populated by the user if so desired. socket level-shifts the normally unipolar output by –1 V. The factory defaults for R8 and R6 are open circuits. REV. B –15– AD768 Clock Input Table III. Summary of Jumper Functionality An external sample clock must be provided to either the BNC Installed Jumper Function connector labeled “CLOCK” or on Pin 33 of the IDC connec- tor. This clock must comply with the logic levels outlined in the Jumper AD768 data sheet. The “CLOCK” input is terminated with a JP1 Buffered Output A removable 51 Ω resistor. The IDC connector clock connection JP2 50 Ω Transformer Output is unterminated. JP3 (STBY) Unbuffered Output A SW1. Clock source select switch. When SW1 is in position 1, Pin JP4 Unbuffered Output B 33 of the IDC connected is applied to the CLOCK input of the JP5 Buffered Output B AD768. When SW2 is in position 2, the “CLOCK” BNC connec- tor is applied to the CLOCK input of the AD768. Table IV. AD768-EB Parts List Digital Inputs The digital inputs of the AD768, DB0–DB15, are available via Reference Value / Part Type Package Qty/Bd J1, a 40-pin IDC connector. These inputs should comply with U1 AD768 28-Pin SOIC 1 the specifications given in the AD768 data sheet. Layout Considerations U2 AD811 8-Pin DIP 1 Figures 28 and 29 show the AD768-EB ground and power T1 Mini-Circuits Not Installed 1 plane layouts. Figures 35–38 show the schematic diagram, trace T4–6T routing, silk screening, and component layout for the AD768 4 layer evaluation board. A, B, CLOCK BNC JACKs, Small, Vertical 3 Separate ground and power planes have several advantages for Small high speed layouts. (For further information outlining these JP1–5 Header 2-Pin 5 advantages, see the application note “Design and Layout of a Video Graphics System for Reduced EMI” [E1309] available SW1, 2 SPDT, Secme 0.1" × 0.3" 2 from Analog Devices [(617) 461-3392].) A solid ground plane J1 40-Pin IDC R.A., Male, 1 can be used if the digital return current can be routed such that Connector w/ Latches it does not modulate the analog ground plane. If this is not pos- sible, it may be necessary to split the ground plane in order to R1 500 Ω 1/4 W, 0.01%, 1 force currents to flow in a controlled direction. This type of Vishay grounding scheme is shown in the Figure 28. The ground plane is separated into analog and digital planes that are joined R2 25 Ω 1/4 W, 0.01%, 1 together under the AD768. In any case, the AD768 should be Vishay treated as an analog component and a common ground connec- R3, R13–21, & tion should be made underneath the AD768 despite some pins R23–29 Wire Jumpers 17 being labeled “digital” ground and some as “analog” ground. A complete parts list for the AD768 evaluation board is given in R5 500 Ω 1/4 W, 0.01%, 1 Table IV. Vishay R7 100 Ω 1/4 W, 0.01%, 1 Vishay R11 51 Ω 1/8 W, 5%, Carbon 1 R12 10 kΩ Pot. 3266 W 1 C1–4 1 μF Ceram. Cap. Leaded 4 C5–8, C10, 12, 0.1 μF Chip Cap, 14, & C16–19 1206 11 C9, 11, 13, 15 22 μF Tant. Cap., Teardrop, 4 25 V 0.1" Spacing REV. B –16– AD768 R5 AB 499 50 JP5 1 1 R10 +V CC C5 22 499 0.1µF U2 2 7 +V CC 50 C7 JP1 A 6 0.1µF AD811 U3 3 C6 JP2 4 0.1µF 2 7 A 6 AD811 A T1 3 3 A 1 A C8 –V 4 EE 0.1µF 4:1 A 45 6 JP3 –V A EE JP4 R7 R2 R3 –V EE 100 24.9 24.9 C9 C10 47µF, 25V 0.1µF R9 R8 R6 100 ∞ A ∞ +V CC C11 C12 A 47µF, 25V 0.1µF –5A C13 C14 U1 A C17 C2 C3 C18 47µF, 25V 0.1µF R12 0.1µF 1µF 1µF 0.1µF 10k AD768 1 28 LADCOM IOUTA A A 2 27 +5D IOUTB NR A 3 26 C4 C19 C15 C16 (–5V) V REFOUT EE 1µF 0.1µF C1 4 25 47µF, 25V 0.1µF 1 1µF NC (+5V) V DD 5 24 R1 R21 0 SW2 J1 REFCOM 1 (MSB) DB15 499 2 6 23 R23 0 J1 TP1 IREFIN 3 DB14 R13 0 7 22 R24 0 J1 31 DB0 (LSB) 5 J1 DB13 R14 0 8 21 R25 0 J1 29 DB1 7 J1 DB12 R15 0 9 20 R26 0 J1 27 9 J1 DB2 DB11 R16 0 10 19 R27 0 J1 25 11 J1 DB3 DB10 R17 0 11 18 R28 0 J1 23 13 J1 DB4 DB9 12 17 R18 0 R29 0 J1 21 15 J1 DB5 DB8 13 16 R19 0 J1 19 DB6 CLOCK R20 0 14 15 J1 17 DB7 DCOM J1 33 1 SW1 CLOCK 1 2 R11 2 J1 J1 16 J1 30 2 50 DGND J1 4 J1 18 J1 32 J1 6 J1 20 J1 34 AGND CONNECTED TO DGND J1 8 J1 22 J1 36 ON GND PLANE UNDER U1 IN BETWEEN PINS 5 AND 25 J1 10 J1 24 J1 38 J1 12 J1 26 J1 40 AGND J1 14 J1 28 A Figure 35. AD768 Evaluation Board Schematic REV. B –17– AD768 Figure 36. Silkscreen Layer (Not to Scale) REV. B –18– AD768 Figure 37. Component Side PCB Layout (Not to Scale) Figure 38. Solder Side PCB Layout (Not to Scale) REV. B –19– AD768 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). R-28 300 Mil 28-Pin SOIC 0.7125 (18.10) 0.6969 (17.70) 28 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 14 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0500 0.0118 (0.30) 0.0192 (0.49) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) REV. B –20– PRINTED IN U.S.A. C1941a–5–6/96