ANALOG DEVICES AD7679

18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC AD7679 FEATURES FUNCTIONAL BLOCK DIAGRAM PDBUF REF REFGND DVDD DGND 18-bit resolution with no missing codes AGND No pipeline delay (SAR architecture) OVDD AVDD AD7679 Differential input range: ±V (V up to 5 V) REF REF SERIAL OGND REFBUFIN PORT Throughput: 570 kSPS 18 INL: ±2.5 LSB max (±9.5 ppm of full scale) IN+ SWITCHED D[17:0] CAP DAC IN– Dynamic range : 103 dB typ (V = 5 V) REF BUSY S/(N+D): 100 dB typ @ 2 kHz (V = 5 V) PARALLEL REF RD INTERFACE Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface CLOCK CS SPI®/QSPI™/MICROWIRE™/DSP compatible PD CONTROL LOGIC AND MODE0 On-board reference buffer CALIBRATION CIRCUITRY MODE1 RESET Single 5 V supply operation Power dissipation: 76 mW @ 500 kSPS CNVST 150 μW @ 1 kSPS 03085–0–001 48-lead LQFP or 48-lead LFCSP package Figure 1. Functional Block Diagram Pin-to-pin compatible upgrade of AD7674/AD7676/AD7678 Table 1. PulSAR Selection APPLICATIONS 800– CT scanners Type/kSPS 100–250 500–570 1000 High dynamic data acquisition Pseudo- AD7651 AD7650/AD7652 AD7653 Geophone and hydrophone sensors Differential AD7660/AD7661 AD7664/AD7666 AD7667 Σ-Δ replacement (low power, multichannel) True Bipolar AD7663 AD7665 AD7671 Instrumentation True AD7675 AD7676 AD7677 Spectrum analysis Differential Medical instruments 18-Bit AD7678 AD7679 AD7674 Multichannel/ AD7654 Simultaneous AD7655 PRODUCT HGHLIGHTS GENERAL DESCRIPTION 1. High Resolution, Fast Throughput. The AD7679 is an 18-bit, 570 kSPS, charge redistribution SAR, The AD7679 is a 570 kSPS, charge redistribution, 18-bit fully differential analog-to-digital converter that operates on a SAR ADC (no latency). single 5 V power supply. The part contains a high speed 18-bit 2. Excellent Accuracy. sampling ADC, an internal conversion clock, an internal The AD7679 has a maximum integral nonlinearity of reference buffer, error correction circuits, and both serial and 2.5 LSB with no missing 18-bit codes. parallel system interface ports. 3. Serial or Parallel Interface. The part is available in a 48-lead LQFP or 48-lead LFCSP with Versatile parallel (18-, 16-, or 8-bit bus) or 3-wire serial operation specified from –40°C to +85°C. interface arrangement compatible with both 3 V and 5 V logic. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD7679 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 17 Applications ....................................................................................... 1 Power Dissipation versus Throughput .................................... 19 Functional Block Diagram .............................................................. 1 Conversion Control ................................................................... 19 General Description ......................................................................... 1 Digital Interface .......................................................................... 20 Product Hghlights ............................................................................ 1 Parallel Interface ......................................................................... 20 Revision History ............................................................................... 2 Serial Interface ............................................................................ 20 Specif ica t ions ..................................................................................... 3 Master Serial Interface ............................................................... 21 Timing Specifications ....................................................................... 5 Slave Serial Interface .................................................................. 22 Absolute Maximum Ratings ............................................................ 7 Microprocessor Interfacing ....................................................... 24 ESD Caution .................................................................................. 7 Application Hints ........................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Layout .......................................................................................... 25 Definition of Specifications ........................................................... 11 Evaluating the AD7679’s Performance .................................... 25 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 26 Circuit Information ........................................................................ 15 Ordering Guide .......................................................................... 26 Converter Operation .................................................................. 15 REVISION HISTORY 6/09—Rev. 0 to Rev. A Changes to Zero Error, T to T Parameter ........................... 3 MIN MAX Changes to Endnote 3 ...................................................................... 4 Changes to Pin Configuration Section .......................................... 8 Changes to Evaluating the AD7679’s Performance Section ...... 25 Changes to Ordering Guide .......................................................... 26 7/03—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7679 SPECIFICATIONS –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range V – V –V +V V IN+ IN– REF REF Operating Input Voltage V , V to AGND –0.1 AVDD+0.1 V IN+ IN– Analog Input CMRR f = 100 kHz 68 dB IN Input Current 570 kSPS Throughput 25 μA 1 Input Impedance THROUGHPUT SPEED Complete Cycle 1.75 μs Throughput Rate 0 570 kSPS DC ACCURACY 2 Integral Linearity Error –2.5 +2.5 LSB Differential Linearity Error –1 +1.75 LSB No Missing Codes 18 Bits Transition Noise V = 5 V 0.7 LSB REF Zero Error, T to T –40 +40 LSB MIN MAX Zero Error Temperature Drift ±0.5 ppm/°C 3 Gain Error, TMIN to TMAX –0.048 See Note 3 +0.048 % of FSR Gain Error Temperature Drift ±1.6 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB AC ACCURACY 4 Signal-to-Noise fIN = 2 kHz, VREF = 5 V 101 dB VREF = 4.096 V 97.5 99 dB f = 10 kHz, V = 4.096 V 98 dB IN REF f = 100 kHz, V = 4.096 V 97 dB IN REF Dynamic Range V = V = V /2 = 2.5 V 103 dB IN+ IN– REF Spurious-Free Dynamic Range f = 2 kHz 120 dB IN f = 10 kHz 118 dB IN fIN = 100 kHz 105 dB Total Harmonic Distortion fIN = 2 kHz –115 dB fIN = 10 kHz –113 dB f = 100 kHz –98 dB IN Signal-to-(Noise + Distortion) f = 2 kHz, V = 4.096 V 98 dB IN REF f = 2 kHz, –60 dB Input 40 dB IN –3 dB Input Bandwidth 26 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 250 ns Overvoltage Recovery 250 ns REFERENCE External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V REFBUFIN Input Current –1 +1 μA REF Current Drain 570 kSPS Throughput 235 μA Rev. A | Page 3 of 28 AD7679 Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V V 2.0 DVDD + 0.3 V IH I –1 +1 μA IL I –1 +1 μA IH DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = –500 μA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 DVDD + 0.3 V Operating Current 500 kSPS Throughput AVDD PDBUF High 10.8 mA 8 DVDD 4.5 mA 8 OVDD 50 μA 8 POWER DISSIPATION PDBUF High @ 500 kSPS 76 90 mW PDBUF High @ 1 kSPS 150 μW PDBUF Low @ 500 kSPS 89 103 mW 9 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Inputs section. 2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV. 3 See Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 Parallel or Serial 18-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 Tested in Parallel Reading mode. 9 Contact factory for extended temperature range. Rev. A | Page 4 of 28 AD7679 TIMING SPECIFICATIONS –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit Refer to Figure 32 and Figure 33 Convert Pulsewidth t 10 ns 1 Time between Conversions t2 1.75 μs CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.5 μs Aperture Delay t 2 ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t7 1.5 μs Acquisition Time t8 250 ns RESET Pulsewidth t9 10 ns Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes) CNVST LOW to Data Valid Delay t10 1.5 μs Data Valid to BUSY LOW Delay t11 20 ns Bus Access Request to Data Valid t 45 ns 12 Bus Relinquish Time t 5 15 ns 13 1 Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 CS LOW to Internal SCLK Valid Delay t 10 ns 15 t 10 ns CS LOW to SDOUT Delay 16 CNVST LOW to SYNC Delay t17 525 ns 2 SYNC Asserted to SCLK First Edge Delay t18 3 ns 2 Internal SCLK Period t 25 40 ns 19 2 Internal SCLK HIGH t 12 ns 20 2 Internal SCLK LOW t 7 ns 21 2 SDOUT Valid Setup Time t22 4 ns 2 SDOUT Valid Hold Time t23 2 ns 2 SCLK Last Edge to SYNC Delay t24 3 ns CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 t 10 ns CS HIGH to SDOUT HI-Z 27 2 BUSY HIGH in Master Serial Read after Convert t28 See Table 4 CNVST LOW to SYNC Asserted Delay t29 1.5 μs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t 5 ns 33 SDIN Hold Time t 5 ns 34 External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2 In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode. Rev. A | Page 5 of 28 AD7679 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t 3 17 17 17 ns 18 Internal SCLK Period Minimum t 25 60 120 240 ns 19 Internal SCLK Period Maximum t 40 80 160 320 ns 19 Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t 2 4 30 89 ns 23 SCLK Last Edge to SYNC Delay Minimum t 3 60 140 300 ns 24 Busy High Width Maximum t 2.25 3 4.5 7.5 μs 28 Rev. A | Page 6 of 28 AD7679 ABSOLUTE MAXIMUM RATINGS 1 Table 5.AD7679 Absolute Maximum Ratings Parameter Rating 1.6mA I OL Analog Inputs 2 2 IN+ , IN– , REF, REFBUFIN, REFGND to AVDD + 0.3 V to AGND TO OUTPUT 1.4V AGND – 0.3 V PIN C L 1 Ground Voltage Differences 60pF AGND, DGND, OGND ±0.3 V I 500μA OH Supply Voltages AVDD, DVDD, OVDD –0.3 V to +7 V 1 IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD AVDD to DVDD, AVDD to OVDD ±7 V C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. L DVDD to OVDD –0.3 V to +7 V 03085–0–002 Figure 2. Load Circuit for Digital Interface Timing Digital Inputs –0.3 V to DVDD + 0.3 V SDOUT, SYNC, SCLK Outputs, CL = 10 pF 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W 2V Junction Temperature 150°C 0.8V t DELAY t Storage Temperature Range –65°C to +150°C DELAY 2V 2V Lead Temperature Range 0.8V 0.8V (Soldering 10 sec) 300°C 03085–0–003 Figure 3. Voltage Reference Levels for Timing 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. ESD CAUTION Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Inputs section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θ = 30°C/W. JC 3 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. Rev. A | Page 7 of 28 AD7679 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 2 AV DD IDENTIFIER 35 CNVST 3 MODE0 34 PD MODE1 4 33 RESET 5 D0/OB/2C 32 CS AD7679 NC 6 31 RD TOP VIEW 7 NC 30 DGND (Not to Scale) D1/A0 8 29 BUSY 9 D2/A1 28 D17 10 D3 27 D16 11 D4/DIVSCLK[0] 26 D15 D5/DIVSCLK[1] 12 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM. Figure 4. Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 44 AGND P Analog Power Ground Pin. 2, 47 AVDD P Input Analog Power Pins. Nominally 5 V. 3 MODE0 DI Data Output Interface Mode Selection. 4 MODE1 DI Data Output Interface Mode Selection: Interface MODE MODE1 MODE0 Description 0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface 5 D0/OB/2C DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6, 7, 40–NC No Connect. 42, 45 8 D1/A0 DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 9 D2/A1 DI/O When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 10 D3 DO In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5]or DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. A | Page 8 of 28 PDBUF D6/EXT/INT AVDD D7/INVSYNC REFBUFIN D8/INVSCLK NC D9/RDC/SDIN AGND OGND IN+ OVDD NC DVDD DGND NC D10/SDOUT NC D11/SCLK IN– REFGND D12/SYNC REF D13/RDERROR 03085-004 AD7679 1 Pin No. Mnemonic Type Description 13 D6 DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. or EXT/INT When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D7 DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D8 DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. 16 D9 DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus. or RDC/SDIN When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3 V. 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D10 DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus. or SDOUT When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7679 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on the next rising edge. 22 D11 DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus. or SCLK When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D12 DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus. or SYNC When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D13 DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus. or RDERROR In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. 25–28 D[14:17] DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the interface mode. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7679. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Rev. A | Page 9 of 28 AD7679 1 Pin No. Mnemonic Type Description 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold state and a conversion is started immediately. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. 38 REFGND AI Reference Input Analog Ground. 39 IN– AI Differential Negative Analog Input. 43 IN+ AI Differential Positive Analog Input. 46 REFBUFIN AI Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically when 2.5 V is applied on this pin. 48 PDBUF DI Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off. 49 Exposed Pad The exposed pad is internally connected to AGND. This connection is not required to meet the (EPAD) (EPAD) electrical performances however, for increased reliability of the solder joints, it is recommended that the pad be soldered to the analog ground of the system. 1 AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Table 7. Data Bus Interface Definitions MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel 1 0 1 OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word 1 0 1 OB/2C A0:1 R[0] R[1] All Zeros 16-Bit Low Word 2 1 0 OB/2C A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte 2 1 0 OB/2C A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte 2 1 0 OB/2C A0:1 A1:0 All Hi-Z R[0:1] All Zeros 8-Bit LOW Byte 2 1 0 OB/2C A0:1 A1:1 All Hi-Z All Zeros R[0:1] 8-Bit LOW Byte 3 1 1 OB/2C All Hi-Z Serial Interface Serial Interface R[0:17] is the 18-bit ADC value stored in its output register. Rev. A | Page 10 of 28 AD7679 DEFINITION OF SPECIFICATIONS Total Harmonic Distortion (THD) Integral Nonlinearity Error (INL) THD is the ratio of the rms sum of the first five harmonic Linearity error refers to the deviation of each individual code components to the rms value of a full-scale input signal, and is from a line drawn from negative full scale through positive full expressed in decibels. scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level Dynamic Range 1½ LSB beyond the last code transition. The deviation is Dynamic range is the ratio of the rms value of the full scale to measured from the middle of each code to the true straight line. the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-Noise Ratio (SNR) nonlinearity is the maximum deviation from this ideal value. It SNR is the ratio of the rms value of the actual input signal to the is often specified in terms of resolution for which no missing rms sum of all other spectral components below the Nyquist codes are guaranteed. frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Gain Error The first transition (from 000…00 to 000…01) should occur for Signal-to-(Noise + Distortion) Ratio (S/[N+D]) an analog voltage ½ LSB above the nominal –full scale S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the (–4.095991 V for the ±4.096 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage Nyquist frequency, including harmonics but excluding dc. The 1½ LSB below the nominal full scale (4.095977 V for the value for S/(N+D) is expressed in decibels. ±4.096 V range). The gain error is the deviation of the Aperture Delay difference between the actual level of the last transition and the Aperture delay is a measure of the acquisition performance and actual level of the first transition from the difference between is measured from the falling edge of the CNVST input to when the ideal levels. the input signal is held for a conversion. Zero Error Transient Response The zero error is the difference between the ideal midscale Transient response is the time required for the AD7679 to input voltage (0 V) from the actual voltage producing the achieve its rated accuracy after a full-scale step function is midscale output code. applied to its input. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input, and is expressed in bits. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02 Rev. A | Page 11 of 28 AD7679 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0 0.5 –0.5 0 –1.0 –1.5 –0.5 –2.0 –2.5 –1.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE 03085-0-005 03085-0-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 70000 90000 V = 5V V = 5V REF REF 59001 80000 58510 60000 70000 50000 60000 40000 50000 30000 40000 30000 20000 23080 22496 20000 7584 10000 4616 10000 3838 0 2 799 59 0 0 0 73 264 0 0 0 0 1FEBD1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 1FEBE1FEBF 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX CODE IN HEX 03085-0-006 03085-0-009 Figure 6. Histogram of 131,072 Conversions of a Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Transition DC Input at the Code Center 100 120 100 80 80 60 60 40 40 20 20 0 0 0 0.5 1.0 1.5 2.0 2.5 –2.5 –2.0 –1.5 –1.0 –0.5 0 POSITIVE INL (LSB) NEGATIVE INL (LSB) 03085-0-007 03085-0-010 Figure 7. Typical Positive INL Distribution (424 Units) Figure 10. Typical Negative INL Distribution (424 Units) Rev. A | Page 12 of 28 INL-LSB (18-Bit) COUNTS NUMBER OF UNITS DNL-LSB (18-Bit) COUNTS NUMBER OF UNITS AD7679 17.0 120 105 100 16.5 100 SNR 80 16.0 95 90 60 15.5 S/(N+D) 15.0 40 85 ENOB 14.5 20 80 14.0 0 75 0 0.5 1.0 1.5 2.0 1 10 100 1000 POSITIVE DNL (LSB) FREQUENCY (kHz) 03085-0-011 03085-0-015 Figure 11. Typical Positive DNL Distribution (424 Units) Figure 14. SNR, S/(N+D), and ENOB vs. Frequency 140 180 –60 160 –70 120 SFDR 140 100 –80 120 80 –90 100 THIRD HARMONIC 80 60 –100 THD 60 40 –110 SECOND 40 HARMONIC 20 –120 20 0 0 –130 –1.00 –0.75 –0.50 –0.25 0 1 10 100 1000 NEGATIVE DNL (LSB) FREQUENCY (kHz) 03085-0-014 03085-0-016 Figure 12. Typical Negative DNL Distribution (424 Units) Figure 15. THD, SFDR, and Harmonics vs. Frequency 0 102 f = 570kSPS S V = 4.096V REF –20 f = 10kHz IN V = 4.096V REF SNR = 98.5dB –40 THD = 115.8dB SFDR = 117.4dB –60 100 S/(N+D) = 98.4dB SNR S/(N+D) –80 –100 –120 98 –140 –160 –180 96 0 30 60 90 120 150 180 210 240 270 –60 –50 –40 –30 –20 –10 0 FREQUENCY (kHz) INPUT LEVEL (dB) 03085-0-012 03085-0-017 Figure 13. FFT (10 kHz Tone) Figure 16. SNR and S/(N+D) vs. Input Level Rev. A | Page 13 of 28 AMPLITUDE (dB of Full Scale) NUMBER OF UNITS NUMBER OF UNITS THD, HARMONICS (dB) SNR AND S/[N+D] (dB) SNR REFERRED TO FULL SCALE (dB) ENOB (Bits) SFDR (dB) AD7679 100 16.5 1000 900 SNR 800 16.0 99 700 S/(N+D) 500 ENOB DVDD 15.5 500 98 400 AVDD 300 97 15.0 200 OVDD 100 14.5 96 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –155 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) 03085-0-021 03085-0-018 Figure 17. SNR, S/(N+D), and ENOB vs. Temperature Figure 20. Power-Down Operating Currents vs. Temperature –100 25 20 THD 15 NEGATIVE –110 FULL SCALE THIRD 10 HARMONIC 5 –120 0 ZERO ERROR –5 SECOND POSITIVE HARMONIC –10 FULL SCALE –130 –15 –20 –140 –25 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) 03085-0-019 03085-0-022 Figure 18. THD and Harmonics vs. Temperature Figure 21. Zero Error Positive and Negative Full Scale vs. Temperature 100000 50 10000 OVDD = 2.7V @ 85°C 40 1000 100 30 AVDD 10 DVDD 20 1 OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C PDBUF HIGH 0.1 OVDD = 5V @ 25°C 10 OVDD 0.01 0.001 0 1 10 100 1k 10k 100k 1M 0 50 100 150 200 SAMPLING RATE (SPS) C (pF) L 03085-0-020 03085-0-024 Figure 19. Operating Current vs. Sampling Rate Figure 22. Typical Delay vs. Load Capacitance C L Rev. A | Page 14 of 28 SNR, S/[N+D] (dB) OPERATING CURRENTS (μA) THD, HARMONICS (dB) ZERO ERROR,POSITIVE AND POWER-DOWN OPERATING CURRENTS (nA) t DELAY (ns) 12 NEGATIVE FULL SCALE (LSB) AD7679 CIRCUIT INFORMATION IN+ SWITCHES CONTROL SW+ MSB LSB 262,144C 131,072C 4C 2C C C BUSY REF CONTROL COMP LOGIC OUTPUT REFGND CODE 4C 2C C C 262,144C 131,072C LSB MSB SW– CNVST IN– 03085–0–025 Figure 23. ADC Simplified Schematic The AD7679 is a very fast, low power, single-supply, precise During the acquisition phase, terminals of the array tied to the 18-bit analog-to-digital converter (ADC) using successive comparator’s input are connected to AGND via SW+ and SW–. approximation architecture. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and The AD7679’s linearity and dynamic range are similar or better acquire the analog signal on IN+ and IN– inputs. When the than many Σ-Δ ADCs. With the advantages of its successive acquisition phase is complete and the CNVST input goes low, a architecture, which ease multiplexing and reduce power with conversion phase is initiated. When the conversion phase throughput, it can be advantageous in applications that begins, SW+ and SW– are opened first. The two capacitor normally use Σ-Δ ADCs. arrays are then disconnected from the inputs and connected to The AD7679 provides the user with an on-chip track/hold, the REFGND input. Therefore, the differential voltage between successive approximation ADC that does not exhibit any the IN+ and IN– inputs captured at the end of the acquisition pipeline or latency, making it ideal for multiple multiplexed phase is applied to the comparator inputs, causing the channel applications. comparator to become unbalanced. By switching each element The AD7679 can be operated from a single 5 V supply and can of the capacitor array between REFGND and REF, the be interfaced to either 5 V or 3 V digital logic. It is housed in a comparator input varies by binary weighted voltage steps 48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings (VREF/2, VREF/4...VREF/262144). The control logic toggles these and allows for flexible configurations as either a serial or switches, starting with the MSB first, to bring the comparator parallel interface. The AD7679 is pin-to-pin compatible with back into a balanced condition. After completing this process, the AD7674, AD7676, and AD7678. the control logic generates the ADC output code and brings the BUSY output low. CONVERTER OPERATION The AD7679 is a successive approximation ADC based on a charge redistribution DAC. Figure 23 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary weighted capacitors that are connected to the two comparator inputs. Rev. A | Page 15 of 28 AD7679 Transfer Functions Table 8. Output Codes and Ideal Input Voltages Straight Twos Except in 18-bit interface mode, the AD7679 offers straight Analog Input Binary Complement binary and twos complement output coding when using OB/2C. Description VREF = 4.096 V (Hex) (Hex) See Figure 24 and Table 8 for the ideal transfer characteristic. 1 1 FSR –1 LSB 4.095962 V 3FFFF 1FFFF FSR – 2 LSB 4.095924 V 3FFFE 1FFFE Midscale + 31.25 μV 20001 00001 111...111 1 LSB 111...110 111...101 Midscale 0 V 20000 00000 Midscale – –31.25 μV 1FFFF 3FFFF 1 LSB –FSR + 1 LSB -4.095962 V 00001 20001 2 2 –FSR -4.096 V 00000 20000 000...010 000...001 1 000...000 This is also the code for overrange analog input (VIN+ – VIN– –FS –FS + 1 LSB +FS – 1 LSB above V – V ). REF REFGND 2 –FS + 0.5 LSB This is also the code for underrange analog input (VIN+ – VIN– +FS – 1.5 LSB below –V + V ). REF REFGND ANALOG INPUT 03085-0-026 Figure 24. ADC Ideal Transfer Function DVDD ANALOG 20Ω DIGITAL SUPPLY SUPPLY NOTE 5 (3.3V OR 5V) (5V) + + + 100nF 10μF 10μ F 100nF 100nF 10μ F ADR421 AVDD AGND DGND DVDD OVDD OGND REFBUFIN SERIAL PORT 2.5V REF SCLK 1MΩ 50kΩ 100nF NOTE 1 100nF SDOUT NOTE 2 REF C REF BUSY 47μF NOTE 1 μC/μP/DSP REFGND 50Ω CNVST D NOTE 6 – 30Ω NOTE 3 MODE1 U1 IN+ AD7679 + ANALOG INPUT+ MODE0 OB/2C DVDD C 2.7nF C AD8021 NOTE 4 CLOCK PDBUF CS RD – 30Ω NOTE 3 IN– U2 RESET ANALOG INPUT– + PD C 2.7nF C AD8021 NOTE 4 NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. SEE ANALOG INPUTS SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 03085-0-027 Figure 25. Typical Connection Diagram (Internal Reference Buffer, Serial Interface) Rev. A | Page 16 of 28 ADC CODE (Straight Binary) AD7679 undesirable aliasing effect and limits the noise coming from the TYPICAL CONNECTION DIAGRAM inputs. Figure 25 shows a typical connection diagram for the AD7679. Because the input impedance of the AD7679 is very high, the Different circuitry shown on this diagram is optional and is discussed later in this data sheet. part can be driven directly by a low impedance source without gain error. This allows the user to put an external 1-pole RC Analog Inputs filter between the amplifier output and the ADC analog inputs, Figure 26 shows a simplified analog input section of the as shown in Figure 25, to even further improve the noise AD7679. The diodes shown in Figure 26 provide ESD filtering done by the AD7679 analog input circuit. However, the protection for the inputs. Care must be taken to ensure that the source impedance has to be kept low because it affects the ac analog input signal never exceeds the absolute ratings on these performance, especially the total harmonic distortion (THD). inputs. This will cause these diodes to become forward biased The maximum source impedance depends on the amount of and start conducting current. These diodes can handle a THD that can be tolerated. The THD degrades as a function of forward-biased current of 120 mA max. This condition could source impedance and the maximum input frequency, as shown eventually occur when the input buffer’s U1 or U2 supplies are in Figure 28. different from AVDD. In such a case, an input buffer with a –95 short-circuit current limitation can be used to protect the part. AVDD 20kHz –100 –105 R+ = 102Ω IN+ 10kHz C S C –110 S IN– R– = 102Ω 2kHz –115 AGND 03085-0-028 –120 Figure 26. Simplified Analog Input 15 45 75 105 INPUT RESISTANCE (Ω) 03085-0-030 This analog input structure is a true differential structure. By Figure 28. THD vs. Analog Input Frequency and Source Resistance using these differential inputs, signals common to both inputs are rejected as shown in Figure 27, which represents typical Driver Amplifier Choice CMRR over frequency. Although the AD7679 is easy to drive, the driver amplifier 80 needs to meet the following requirements: • The driver amplifier and the AD7679 analog input circuit 75 have to be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). In the amplifier’s data 70 sheet, settling at 0.1% or 0.01% is more commonly specified. This could differ significantly from the settling 65 time at an 18-bit level and, therefore, should be verified prior to driver selection. The tiny op amp AD8021, which 60 combines ultralow noise and high gain-bandwidth, meets this settling time requirement. 55 • The noise generated by the driver amplifier needs to be 50 kept as low as possible in order to preserve the SNR and 110 100 1000 10000 FREQUECY (kHz) transition noise performance of the AD7679. The noise 03085-0-029 Figure 27. Analog Input CMRR vs. Frequency coming from the driver is filtered by the AD7679 analog input circuit 1-pole low-pass filter made by R+, R–, and C . S During the acquisition phase for ac signals, the AD7679 behaves like a 1-pole RC filter consisting of the equivalent resistance, R+, R–, and CS. Resistors R+ and R– are typically 102 Ω and are lumped components made up of a serial resistor and the on resistance of the switches. CS is typically 60 pF and mainly consists of the ADC sampling capacitor. This 1-pole filter with a –3 dB cutoff frequency of 26 MHz typ reduces any Rev. A | Page 17 of 28 CMRR (dB) THD (dB) AD7679 The SNR degradation due to the amplifier is If the application can tolerate more noise, the AD8138, differential driver can be used. ⎛ ⎞ ⎜ ⎟ 25 ⎜ ⎟ SNRLOSS= 20 log ⎜ ⎟ 2 ⎜ ⎟ f ⎜ 625+π (NeN) ⎟ –3dB U1 ⎝ ⎠ ANALOG INPUT AD8021 (UNIPOLAR where: 10pF 0V TO 4.096V) f is the –3 dB input bandwidth in MHz of the AD7679 –3dB 590Ω 30Ω (26 MHz) or the cutoff frequency of the input filter, if used. IN+ 590Ω N is the noise factor of the amplifiers (1 if in buffer 2.7nF AD7679 configuration). 30Ω IN– U2 1.82kΩ REFBUFIN eN is the equivalent input noise voltage of each op amp in REF 2.7nF AD8021 10μF nV/√Hz. 10pF 100nF 8.25kΩ For instance, for a driver with an equivalent input noise of 2.5V 2 nV/√Hz (e.g., AD8021) configured as a buffer, thus with 03085-0-031 a noise gain of +1, the SNR degrades by only 0.34 dB with Figure 29. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) the filter in Figure 25, and by 1.8 dB without it. Voltage Reference • The driver needs to have a THD performance suitable to The AD7679 allows the use of an external voltage reference that of the AD7679. either with or without the internal reference buffer. The AD8021 meets these requirements and is usually Using the internal reference buffer is recommended when appropriate for almost all applications. The AD8021 needs a sharing a common reference voltage between multiple ADCs is 10 pF external compensation capacitor, which should have good desired. linearity as an NPO ceramic or mica type. However, the advantages of using the external reference voltage The AD8022 could be used if a dual version is needed and gain directly are of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not • The SNR and dynamic range improvement (about 1.7 dB) required. In gain of 1 applications, it requires an 82 pF resulting from the use of a reference voltage very close to compensation capacitor. The AD8610 is another option when the supply (5 V) instead of a typical 4.096 V reference low bias current is needed in low frequency applications. when the internal buffer is used. • The power saving when the internal reference buffer is Single-to-Differential Driver powered down (PDBUF high). For applications using unipolar analog signals, a single-ended- to-differential driver will allow for a differential input into the To use the internal reference buffer, PDBUF should be LOW. A 2.5 V reference voltage applied on the REFBUFIN input will part. The schematic is shown in Figure 29. When provided an result in a 4.096 V reference on the REF pin. input signal of 0 to VREF, this configuration will produce a differential ±VREF with midscale at VREF/2. In both cases, the voltage reference input REF has a dynamic input impedance and therefore requires an efficient decoupling between REF and REFGND inputs. The decoupling consists of a low ESR 47 μF tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. Care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. For instance, a ±4 ppm/°C temperature coefficient of the reference changes the full scale by ±1 LSB/°C. Rev. A | Page 18 of 28 AD7679 1000000 Power Supply The AD7679 uses three sets of power supply pins: an analog 5 V 100000 supply (AVDD), a digital 5 V core supply (DVDD), and a digital 10000 output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic 1000 working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be 100 supplied through a simple RC filter from the analog supply, as shown in Figure 25. The AD7679 is independent of power 10 supply sequencing once OVDD does not exceed DVDD by 1 more than 0.3 V, and is therefore free from supply voltage PDBUF HIGH induced latch-up. Additionally, it is very insensitive to power 0.1 1 100 1k 10k 100k 1M 10 supply variations over a wide frequency range (see Figure 30). SAMPLING RATE (SPS) 03085-0-033 65 Figure 31. Power Dissipation vs. Sample Rate CONVERSION CONTROL 60 Figure 32 shows the detailed timing diagrams of the conversion process. The AD7679 is controlled by the CNVST signal, which 55 initiates conversion. Once initiated, it cannot be restarted or aborted, even by PD, until the conversion is complete. The 50 CNVST signal operates independently of CS and RD. t 2 45 t 1 CNVST 40 110 100 1000 10000 BUSY FREQUECY (kHz) 03085-0-032 t 4 t Figure 30. PSRR vs. Frequency 3 t 6 t 5 POWER DISSIPATION VERSUS THROUGHPUT MODE ACQUIRE CONVERT ACQUIRE CONVERT The AD7679 automatically reduces its power consumption at t t 7 8 the end of each conversion phase. During the acquisition phase, 03085-0-034 the operating currents are very low, which allows for a Figure 32. Basic Conversion Timing significant power savings when the conversion rate is reduced, Although CNVST is a digital signal, it should be designed with as shown in Figure 31. This feature makes the AD7679 ideal for special care with fast, clean edges and levels with minimum very low power battery applications. overshoot and undershoot or ringing. It should be noted that the digital interface remains active even For applications where SNR is critical, the signal should CNVST during the acquisition phase. To reduce the operating digital have very low jitter. This may be achieved by using a dedicated supply currents even further, the digital inputs need to be oscillator for generation, or to clock it with a high CNVST driven close to the power rails (DVDD and DGND), and frequency low jitter clock, as shown in Figure 25. OVDD should not exceed DVDD by more than 0.3 V. For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7679 controls the acquisition phase and automatically initiates a new conversion. By keeping low, the AD7679 keeps the CNVST conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, should be brought low once to initiate the CNVST conversion process. In this mode, the AD7679 could sometimes run slightly faster than the guaranteed limits of 570 kSPS. Rev. A | Page 19 of 28 PSRR (dB) POWER DISSAPATION (μW) AD7679 conversion circuitry. Refer to Table 7 for a detailed description DIGITAL INTERFACE of the different options available. The AD7679 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The CS AD7679 digital interface also accommodates both 3 V and 5 V logic by simply connecting the AD7679’s OVDD supply pin to RD the host system interface digital supply. Finally, by using the input pin in any mode but 18-bit interface mode, both OB/2C BUSY twos complement and straight binary coding can be used. DATA CURRENT BUS CONVERSION The two signals, and , control the interface. When at least CS RD t t one of these signals is high, the interface outputs are in high 12 13 03085-0-037 impedance. Usually, CS allows the selection of each AD7679 in Figure 35. Slave Parallel Data Timing for Reading (Read after Convert) multicircuit applications, and is held low in a single AD7679 CS = 0 design. is generally used to enable the conversion result on RD t 1 CNVST, the data bus. RD t 9 RESET BUSY t 4 t 3 DATA PREVIOUS BUSY CONVERSION BUS t t 12 13 03085-0-038 Figure 36. Slave Parallel Data Timing for Reading (Read during Convert) DATA BUS t 8 CS CNVST RD 03085-0-035 Figure 33. RESET Timing A0, A1 CS = RD = 0 t 1 HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE CNVST t t t 12 12 13 t HI-Z HI-Z 10 PINS D[7:0] LOW BYTE HIGH BYTE t BUSY 4 03085-0-039 t 3 Figure 37. 8-Bit and 16-Bit Parallel Interface t 11 SERIAL INTERFACE DATA PREVIOUS CONVERSION DATA NEW DATA BUS The AD7679 is configured to use the serial interface when 03085-0-036 MODE0 and MODE1 are held high. The AD7679 outputs 18 Figure 34. Master Parallel Data Timing for Reading (Continuous Read) bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK PARALLEL INTERFACE pin. The output data is valid on both the rising and falling edge The AD7679 is configured to use the parallel interface with an of the data clock. 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 35 and Figure 36, respectively. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog Rev. A | Page 20 of 28 AD7679 In Read during Conversion mode, the serial clock and data MASTER SERIAL INTERFACE toggle at appropriate instants, minimizing potential Internal Clock feedthrough between digital activity and critical conversion The AD7679 is configured to generate and provide the serial decisions. data clock SCLK when the EXT/ pin is held low. The INT In Read after Conversion mode, it should be noted that unlike AD7679 also generates a SYNC signal to indicate to the host in other modes, the BUSY signal returns low after the 18 data when the serial data is valid. The serial clock SCLK and the bits are pulsed out and not at the end of the conversion phase, SYNC signal can be inverted if desired. Depending on the which results in a longer BUSY width. RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 38 and Figure 39 show To accommodate slow digital hosts, the serial clock can be the detailed timing diagrams of these two modes. slowed down by using DIVSCLK. Usually, because the AD7679 is used with a fast throughput, the mode master read during conversion is the most recommended serial mode. RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SCLK t 15 t 27 SDOUT X D17 D16 D2 D1 D0 t t 16 23 t 22 03085-0-040 Figure 38. Master Serial Data Timing for Reading (Read after Convert) Rev. A | Page 21 of 28 AD7679 EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 16 17 18 t 18 t 27 X D17 D16 D2 D1 D0 SDOUT t t 23 16 t 22 03085-0-041 Figure 39. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) External Discontinuous Clock Data Read after SLAVE SERIAL INTERFACE Conversion External Clock This mode is the most recommended of the serial slave modes. The AD7679 is configured to accept an externally supplied Figure 40 shows the detailed timing diagrams of this method. serial data clock on the SCLK pin when the EXT/INT pin is After a conversion is complete, indicated by BUSY returning held high. In this mode, several methods can be used to read low, the result of this conversion can be read while both CS and the data. The external serial clock is gated by CS. When CS and are low. Data is shifted out MSB first with 18 clock pulses, RD RD are both low, the data can be read after each conversion or and is valid on the rising and falling edge of the clock. during the following conversion. The external clock can be Among the advantages of this method, the conversion either a continuous or a discontinuous clock. A discontinuous performance is not degraded because there are no voltage clock can be either normally high or normally low when transients on the digital interface during the conversion process. inactive. Figure 40 and Figure 41 show the detailed timing Also, data can be read at speeds up to 40 MHz, accommodating diagrams of these methods. both slow digital host interface and the fastest serial reading. While the AD7679 is performing a bit decision, it is important Finally, in this mode only, the AD7679 provides a daisy-chain that voltage transients not occur on digital input/output pins or feature using the RDC/SDIN input pin to cascade multiple degradation of the conversion result could occur. This is converters together. This feature is useful for reducing particularly important during the second half of the conversion component count and wiring connections when desired (for phase because the AD7679 provides error correction circuitry instance, in isolated multiconverter applications). that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is An example of the concatenation of two devices is shown in recommended that when an external clock is being provided, it Figure 42. Simultaneous sampling is possible by using a is a discontinuous clock that toggles only when BUSY is low or, common CNVST signal. It should be noted that the RDC/SDIN more importantly, that it does not transition during the latter input is latched on the edge of SCLK opposite the one used to half of BUSY high. shift out data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. Rev. A | Page 22 of 28 AD7679 INVSCLK = 0 EXT/INT = 1 RD = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 17 18 19 20 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 X17 X16 t 16 t 34 SDIN X17 X16 X15 X1 X0 Y17 Y16 t 33 03085-0-042 Figure 40. Slave Serial Data Timing for Reading (Read after Convert) INVSCLK = 0 EXT/INT = 1 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 17 18 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 t 16 03085-0-043 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. A | Page 23 of 28 AD7679 MICROPROCESSOR INTERFACING BUSY OUT The AD7679 is ideally suited for traditional dc measurement BUSY BUSY applications supporting a microprocessor, and for ac signal AD7679 AD7679 processing applications interfacing to a digital signal processor. #2 (UPSTREAM) #1 (DOWNSTREAM) The AD7679 is designed to interface either with a parallel 8-bit DATA or 16-bit wide interface, or with a general-purpose serial port or RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST I/O ports on a microcontroller. A variety of external buffers can CS CS be used with the AD7679 to prevent digital noise from coupling SCLK SCLK into the ADC. The following section illustrates the use of the SCLK IN AD7679 with an SPI equipped DSP, the ADSP-219x. CS IN CNVST IN SPI Interface (ADSP-219x) 03085-0-044 Figure 42. Two AD7679s in a Daisy-Chain Configuration Figure 43 shows an interface diagram between the AD7679 and the SPI equipped ADSP-219x. To accommodate the slower External Clock Data Read during Conversion speed of the DSP, the AD7679 acts as a slave device, and data must be read after conversion. This mode also allows the daisy- Figure 41 shows the detailed timing diagrams of this method. chain feature. The convert command could be initiated in During a conversion, while both CS and RD are low, the result response to an internal timer interrupt. The 18-bit output data of the previous conversion can be read. The data is shifted out are read with 3-byte SPI access. The reading process could be MSB first with 18 clock pulses, and is valid on both the rising initiated in response to the end-of-conversion signal (BUSY and falling edge of the clock. The 18 bits have to be read before going low) using an interrupt line of the DSP. The serial the current conversion is complete. If that is not done, interface (SPI) on the ADSP-219x is configured for master RDERROR is pulsed high and can be used to interrupt the host mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase interface to prevent incomplete data reading. There is no daisy- Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by chain feature in this mode, and the RDC/SDIN input should writing to the SPI Control register (SPICLTx). It should be always be tied either high or low. noted that to meet all timing requirements, the SPI clock should To reduce performance degradation due to digital activity, a fast be limited to 17 Mbits/s, which allow it to read an ADC result in discontinuous clock is recommended to ensure that all bits are about 1.1 μs. When a higher sampling rate is desired, use of one read during the first half of the conversion phase. It is also of the parallel interface modes is recommended. possible to begin to read the data after conversion and continue DVDD to read the last bits even after a new conversion has been ADSP-219x* AD7679* initiated. SER/PAR EXT/INT BUSY PFx CS SPIxSEL (PFx) RD SDOUT MISOx INVSCLK SCLK SCKx CNVST PFx or TFSx *ADDITIONAL PINS OMITTED FOR CLARITY 03085-0-045 Figure 43. Interfacing the AD7679 to an SPI Interface Rev. A | Page 24 of 28 AD7679 APPLICATION HINTS The DVDD supply of the AD7679 can be a separate supply or LAYOUT can come from the analog supply, AVDD, or the digital The AD7679 has very good immunity to noise on the power interface supply, OVDD. When the system digital supply is supplies. However, care should still be taken with regard to noisy or when fast switching digital signals are present, and if grounding layout. no separate supply is available, the user should connect the The printed circuit board that houses the AD7679 should be DVDD digital supply to the analog supply AVDD through an designed so that the analog and digital sections are separated RC filter, (see Figure 25), and connect the system supply to the and confined to certain areas of the board. This facilitates the interface digital supply OVDD and the remaining digital use of ground planes that can be easily separated. Digital and circuitry. When DVDD is powered from the system supply, it is analog ground planes should be joined in only one place, useful to insert a bead to further reduce high frequency spikes. preferably underneath the AD7679, or at least as close to the The AD7679 has four different ground pins: REFGND, AGND, AD7679 as possible. If the AD7679 is in a system where DGND, and OGND. REFGND senses the reference voltage and multiple devices require analog-to-digital ground connections, should be a low impedance return to the reference because it the connection should still be made at one point only, a star carries pulsed currents. AGND is the ground to which most ground point that should be established as close to the AD7679 internal ADC analog signals are referenced. This ground must as possible. be connected with the least resistance to the analog ground The user should avoid running digital lines under the device, as plane. DGND must be tied to the analog or digital ground plane these will couple noise onto the die. The analog ground plane depending on the configuration. OGND is connected to the should be allowed to run under the AD7679 to avoid noise digital system ground. coupling. Fast switching signals like or clocks should be CNVST The layout of the decoupling of the reference voltage is shielded with digital ground to avoid radiating noise to other important. The decoupling capacitor should be close to the sections of the board, and should never run near analog signal ADC and should be connected with short and large traces to paths. Crossover of digital and analog signals should be minimize parasitic inductances. avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of EVALUATING THE AD7679’S PERFORMANCE feedthrough through the board. The power supply lines to the An evaluation board for the AD7679 allows a quick means AD7679 should use as large a trace as possible to provide low to measure both dc (histograms and time domain) and ac (time impedance paths and reduce the effect of glitches on the power and frequency domain) performances of the converter. The supply lines. Good decoupling is also important to lower the EVAL-AD7679CBZ is an evaluation board package that supply’s impedance presented to the AD7679 and to reduce the includes a fully assembled and tested evaluation board, magnitude of the supply spikes. Decoupling ceramic capacitors, documentation, and software. The accompanying software typically 100 nF, should be placed close to and ideally right up requires the use of a capture board, which must be ordered against each power supply pin (AVDD, DVDD, and OVDD) separately from the evaluation board (see the Ordering Guide and their corresponding ground pins. Additionally, low ESR for information). The evaluation board can also be used in a 10 μF capacitors should be located near the ADC to further standalone configuration and does not use the software when reduce low frequency ripple. in this mode. Refer to the EVAL-AD76XXEDZ and EVAL- AD76XXCBZ data sheets available from www.analog.com for evaluation board details. Two types of data capture boards can be used with the EVAL- AD7679CBZ: • USB based (EVAL-CED1Z recommended) • Parallel port based (EVAL-CONTROL BRD3Z not recommended because many newer PCs do not include parallel ports any longer) The recommended board layout for the AD7679 is outlined in the evaluation board data sheet. Rev. A | Page 25 of 28 AD7679 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 44. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY 0.50 BSC SECTION OF THIS DATA SHEET. 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7679ASTZ –40°C to +85°C 48-Lead LQFP ST-48 1 AD7679ASTZRL –40°C to +85°C 48-Lead LQFP ST-48 1 AD7679ACPZ –40°C to +85°C 48-Lead LFCSP_VQ CP-48-1 1 AD7679ACPZRL –40°C to +85°C 48-Lead LFCSP_VQ CP-48-1 1, 2 EVAL-AD7679CBZ Evaluation Board 1, 3 EVAL-CONTROL BRD2Z Parallel Port Capture Board, 32k RAM 1, 3 EVAL-CONTROL BRD3Z Parallel Port Capture Board, 128k RAM 1 EVAL-CED1Z USB Data Capture Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 3 These capture boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL BRDxZ ( x = 2, 3). Rev. A | Page 26 of 28 051706-A 080108-A AD7679 NOTES Rev. A | Page 27 of 28 AD7679 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03085-0-6/09(A) Rev. A | Page 28 of 28