ANALOG DEVICES AD7678

18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC AD7678 FUNCTIONAL BLOCK DIAGRAM FEATURES PDBUF REF REFGND DVDD DGND 18-bit resolution with no missing codes No pipeline delay (SAR architecture) AGND OVDD AVDD AD7678 Differential input range: ±V (V up to 5 V) REF REF SERIAL OGND REFBUFIN Throughput: 100 kSPS PORT INL: ±2.5 LSB max (±9.5 ppm of full scale) 18 IN+ SWITCHED D[17:0] CAP DAC Dynamic range: 103 dB typ (V = 5 V) IN– REF BUSY S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V) PARALLEL RD INTERFACE Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface CLOCK CS SPI®/QSPI™/MICROWIRE™/DSP compatible PD CONTROL LOGIC AND MODE0 CALIBRATION CIRCUITRY On-board reference buffer RESET MODE1 Single 5 V supply operation Power dissipation: 18 mW @ 100 kSPS CNVST 03084–0–001 180 μW @ 1 kSPS 48-lead LQFP or 48-lead LFCSP package Figure 1. Functional Block Diagram Pin-to-pin compatible upgrade of AD7674/AD7676/AD7679 Table 1. PulSAR Selection APPLICATIONS 800– CT scanners Type/kSPS 100–250 500–570 1000 High dynamic data acquisition Pseudo- AD7651 AD7650/AD7652 AD7653 Geophone and hydrophone sensors Differential AD7660/AD7661 AD7664/AD7666 AD7667 - replacement (low power, multichannel) True Bipolar AD7663 AD7665 AD7671 Instrumentation True AD7675 AD7676 AD7677 Spectrum analysis Differential Medical instruments 18-Bit AD7678 AD7679 AD7674 Multichannel/ AD7654 Simultaneous AD7655 GENERAL DESCRIPTION The AD7678 is an 18-bit, 100 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates on a PRODUCT HIGHLIGHTS single 5 V power supply. The part contains a high speed 18-bit 1. High Resolution, Fast Throughput. sampling ADC, an internal conversion clock, an internal The AD7678 is a 100 kSPS, charge redistribution, 18-bit reference buffer, error correction circuits, and both serial and SAR ADC (no latency). parallel system interface ports. 2. Excellent Accuracy. The part is available in 48-lead LQFP or 48-lead LFCSP The AD7678 has a maximum integral nonlinearity of packages with operation specified from –40°C to +85°C. 2.5 LSB with no missing 18-bit codes. 3. Serial or Parallel Interface. Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial interface arrangement compatible with both 3 V and 5 V logic. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD7678 TABLE OF CONTENTS Specif ica t ions ..................................................................................... 3  Digital Interface .......................................................................... 20  Timing Specifications ....................................................................... 5  Parallel Interface ......................................................................... 20  Absolute Maximum Ratings ............................................................ 7  Serial Interface ............................................................................ 20  ESD Caution .................................................................................. 7  Master Serial Interface ............................................................... 21  Pin Configuration and Function Descriptions ............................. 8  Slave Serial Interface .................................................................. 22  Definition of Specifications ........................................................... 11  Microprocessor Interfacing ....................................................... 24  Typical Performance Characteristics ........................................... 12  Application Hints ........................................................................... 25  Circuit Information ........................................................................ 15  Layout .......................................................................................... 25  Converter Operation .................................................................. 15  Evaluating the AD7678’s Performance .................................... 25  Typical Connection Diagram ................................................... 17  Outline Dimensions ....................................................................... 26  Power Dissipation versus Throughput .................................... 19  Ordering Guide .......................................................................... 26  Conversion Control .................................................................... 19  REVISION HISTORY 6/09—Rev. 0 to Rev. A Removed Endnote 3 from DC Accuracy; Zero Error, TMIN to T Parameter; Table 2 ................................................................... 3 MAX Changes to Endnote 3, Table 2 ........................................................ 4 Moved ESD Caution ......................................................................... 7 Changes to Figure 4 and Table 6 ..................................................... 8 Changes to Evaluating the AD7678’s Performance Section ...... 25 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 8/03—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7678 SPECIFICATIONS Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range VIN+ – VIN– –VREF +VREF V Operating Input Voltage V , V to AGND –0.1 AVDD + 0.1 V IN+ IN– Analog Input CMRR f = 100 kHz 65 dB IN Input Current 100 kSPS Throughput 4 μA 1 Input Impedance THROUGHPUT SPEED Complete Cycle 10 μs Throughput Rate 0 100 kSPS DC ACCURACY 2 Integral Linearity Error –2.5 +2.5 LSB Differential Linearity Error –1 +1.75 LSB No Missing Codes 18 Bits Transition Noise V = 5 V 0.7 LSB REF Zero Error, T to T –40 ±40 LSB MIN MAX Zero Error Temperature Drift ±0.5 ppm/°C 3 Gain Error, TMIN to TMAX –0.048 See Note 3 +0.048 % of FSR Gain Error Temperature Drift ±1.6 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB AC ACCURACY 4 Signal-to-Noise fIN = 2 kHz, VREF = 5 V 101 dB VREF = 4.096 V 98 100 dB f = 10 kHz, V = 4.096 V 99.5 dB IN REF fIN = 45 kHz, VREF = 4.096 V 98 dB Dynamic Range V = V = V /2 = 2.5 V 103 dB IN+ IN– REF Spurious-Free Dynamic Range f = 2 kHz 120 dB IN fIN = 10 kHz 117 dB fIN = 45 kHz 110 dB Total Harmonic Distortion fIN = 2 kHz –118 dB f = 10 kHz –115 dB IN f = 45 kHz –110 dB IN Signal-to-(Noise + Distortion) f = 2 kHz 100 dB IN fIN = 2 kHz, –60 dB Input 41 dB –3 dB Input Bandwidth 900 kHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 8.5 μs Overvoltage Recovery 8.5 μs REFERENCE External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V REFBUFIN Input Current –1 +1 μA REF Current Drain 100 kSPS Throughput 42 μA Rev. A | Page 3 of 28 AD7678 Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V V 2.0 DVDD + 0.3 V IH I –1 +1 μA IL I –1 +1 μA IH DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = –500 μA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 DVDD + 0.3 V Operating Current 100 kSPS Throughput AVDD PDBUF High 2.6 mA 8 DVDD 1 mA 8 OVDD 40 μA PDBUF High @ 100 kSPS 18 26 mW PDBUF High @ 1 kSPS 180 μW PDBUF Low @ 100 kSPS 31 mW 9 TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX 1 See the Analog Inputs section. 2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV. 3 See the Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 5 Data format parallel or serial 18-bit. 6 Conversion results are available immediately after completed conversion. 7 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 8 Tested in Parallel Reading mode. 9 Contact factory for extended temperature range. Rev. A | Page 4 of 28 AD7678 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Symbol Min Typ Max Unit Refer to Figure 27 and Figure 28 Convert Pulse Width t 10 ns 1 Time between Conversions t 10 μs 2 CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.5 μs Aperture Delay t 2 ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 1.5 μs 7 Acquisition Time t8 8.5 μs RESET Pulsewidth t9 10 ns Refer to Figure 29, Figure 30, and Figure 31 (Parallel Interface Modes) CNVST LOW to Data Valid Delay t10 1.5 μs Data Valid to BUSY LOW Delay t11 20 ns Bus Access Request to Data Valid t12 45 ns Bus Relinquish Time t 5 15 ns 13 1 Refer to Figure 33 and Figure 34 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t 10 ns 16 CNVST LOW to SYNC Delay t17 525 ns 2 SYNC Asserted to SCLK First Edge Delay t18 3 ns 2 Internal SCLK Period t19 25 40 ns 2 Internal SCLK HIGH t 12 ns 20 2 Internal SCLK LOW t 7 ns 21 2 SDOUT Valid Setup Time t 4 ns 22 2 SDOUT Valid Hold Time t23 2 ns 2 SCLK Last Edge to SYNC Delay t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t 10 ns 27 2 BUSY HIGH in Master Serial Read after Convert t See Table 4 28 CNVST LOW to SYNC Asserted Delay t29 1.5 μs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 35 and Figure 36 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t 5 ns 33 SDIN Hold Time t 5 ns 34 External SCLK Period t 25 ns 35 External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2 In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode. Rev. A | Page 5 of 28 AD7678 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t 25 60 120 240 ns 19 Internal SCLK Period Maximum t 40 80 160 320 ns 19 Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t 2 4 30 89 ns 23 SCLK Last Edge to SYNC Delay Minimum t 3 60 140 300 ns 24 Busy High Width Maximum t 2.25 3 4.5 7.5 μs 28 Rev. A | Page 6 of 28 AD7678 ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7678 Absolute Maximum Ratings Parameter Rating 1.6mA I OL Analog Inputs 2 2 IN+ , IN– , REF, REFBUFIN, REFGND AVDD + 0.3 V to to AGND AGND – 0.3 V TO OUTPUT 1.4V PIN C L Ground Voltage Differences 1 60pF AGND, DGND, OGND ±0.3 V I Supply Voltages 500A OH AVDD, DVDD, OVDD –0.3 V to +7 V 1 IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND AVDD to DVDD, AVDD to OVDD ±7 V SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. L DVDD to OVDD –0.3 V to +7 V 03084–0–002 Digital Inputs –0.3 V to DVDD + 0.3 V Figure 2. Load Circuit for Digital Interface Timing, 3 Internal Power Dissipation 700 mW SDOUT, SYNC, SCLK Outputs, CL = 10 pF 4 Internal Power Dissipation 2.5 W Junction Temperature 150°C Storage Temperature Range –65°C to +150°C 2V 0.8V Lead Temperature Range t DELAY t DELAY (Soldering 10 sec) 300°C 2V 2V 0.8V 0.8V 03084–0–003 1 Stresses above those listed under Absolute Maximum Ratings may cause Figure 3. Voltage Reference Levels for Timing permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. ESD CAUTION Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Inputs section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θ = 30°C/W. JC 4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. Rev. A | Page 7 of 28 AD7678 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 2 AV DD IDENTIFIER 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET 5 D0/OB/2C 32 CS AD7678 NC 6 31 RD TOP VIEW 7 NC 30 DGND (Not to Scale) D1/A0 8 29 BUSY 9 D2/A1 28 D17 10 D3 27 D16 11 D4/DIVSCLK[0] 26 D15 D5/DIVSCLK[1] 12 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES; HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM. Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 44 AGND P Analog Power Ground Pin. 2, 47 AVDD P Input Analog Power Pins. Nominally 5 V. 3 MODE0 DI Data Output Interface Mode Selection. 4 MODE1 DI Data Output Interface Mode Selection: Interface MODE # MODE1 MODE0 Description 0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface 5 D0/OB/2C DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6, 7, NC No Connect. 40–42, 45 8 D1/A0 DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 9 D2/A1 DI/O When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 10 D3 DO In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5]or DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. A | Page 8 of 28 PDBUF D6/EXT/INT AVDD D7/INVSYNC REFBUFIN D8/INVSCLK NC D9/RDC/SDIN AGND OGND OVDD IN+ DVDD NC DGND NC D10/SDOUT NC D11/SCLK IN– REFGND D12/SYNC REF D13/RDERROR 03084-004 AD7678 1 Pin No. Mnemonic Type Description 13 D6 DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. or EXT/INT When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D7 DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D8 DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. 16 D9 DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus. or RDC/SDIN When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3 V. 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D10 DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus. or SDOUT When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7678 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on the next rising edge. 22 D11 DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus. or SCLK When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D12 DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus. or SYNC When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D13 DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus. or RDERROR In MODE = 3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. 25–28 D[14:17] DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the interface mode. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7678. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Rev. A | Page 9 of 28 AD7678 1 Pin No. Mnemonic Type Description 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold state and a conversion is started immediately. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. 38 REFGND AI Reference Input Analog Ground. 39 IN– AI Differential Negative Analog Input. 43 IN+ AI Differential Positive Analog Input. 46 REFBUFIN AI Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically when 2.5 V is applied on this pin. 48 PDBUF DI Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off. 49 Exposed Pad The exposed pad is internally connected to AGND. This connection is not required to meet the (EPAD) (EPAD) electrical performances; however, for increased reliability of the solder joints, it is recommended that the pad be soldered to the analog ground of the system. 1 AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Table 7. Data Bus Interface Definitions MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel 1 0 1 OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word 1 0 1 OB/2C A0:1 R[0] R[1] All Zeros 16-Bit Low Word 2 1 0 OB/2C A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte 2 1 0 OB/2C A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte 2 1 0 OB/2C A0:1 A1:0 All Hi-Z R[0:1] All Zeros 8-Bit LOW Byte 2 1 0 OB/2C A0:1 A1:1 All Hi-Z All Zeros R[0:1] 8-Bit LOW Byte 3 1 1 OB/2C All Hi-Z Serial Interface Serial Interface R[0:17] is the 18-bit ADC value stored in its output register. Rev. A | Page 10 of 28 AD7678 DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal, and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Dynamic Range 1½ LSB beyond the last code transition. The deviation is Dynamic range is the ratio of the rms value of the full scale to measured from the middle of each code to the true straight line. the rms noise measured with the inputs shorted together. The Differential Nonlinearity Error (DNL) value for dynamic range is expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-Noise Ratio (SNR) nonlinearity is the maximum deviation from this ideal value. It SNR is the ratio of the rms value of the actual input signal to the is often specified in terms of resolution for which no missing rms sum of all other spectral components below the Nyquist codes are guaranteed. frequency, excluding harmonics and dc. The value for SNR is Gain Error expressed in decibels. The first transition (from 000…00 to 000…01) should occur for Signal-to-(Noise + Distortion) Ratio (S/[N+D]) an analog voltage ½ LSB above the nominal –full scale S/(N+D) is the ratio of the rms value of the actual input signal (–4.095991 V for the ±4.096 V range). The last transition (from to the rms sum of all other spectral components below the 111…10 to 111…11) should occur for an analog voltage Nyquist frequency, including harmonics but excluding dc. The 1½ LSB below the nominal full scale (4.095977 V for the value for S/(N+D) is expressed in decibels. ±4.096 V range). The gain error is the deviation of the differ- ence between the actual level of the last transition and the Aperture Delay actual level of the first transition from the difference between Aperture delay is a measure of the acquisition performance and the ideal levels. is measured from the falling edge of the input to when CNVST Zero Error the input signal is held for a conversion. The zero error is the difference between the ideal midscale Transient Response input voltage (0 V) from the actual voltage producing the Transient response is the time required for the AD7678 to midscale output code. achieve its rated accuracy after a full-scale step function is Spurious-Free Dynamic Range (SFDR) applied to its input. SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input, and is expressed in bits. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02 Rev. A | Page 11 of 28 AD7678 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0 0.5 –0.5 0 –1.0 –1.5 –0.5 –2.0 –2.5 –1.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE 03084-0-005 03084-0-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 70000 90000 83610 V = 5V V = 5V REF REF 60158 59966 80000 60000 70000 50000 60000 40000 50000 40000 30000 30000 23000 20000 21862 20000 10000 5919 10000 3931 1053 1 0300 2 420 000 522 0 0 20015 20016 20017 20018 20019 2001A2001B2001C2001D2001E 2001B 2001C 2001D 2001E 2001F 20020 20021 20022 20023 CODE IN HEX CODE IN HEX 03084-0-006 03084-0-009 Figure 6. Histogram of 131,072 Conversions of a Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Transition DC Input at the Code Center 0 102 16.6 f = 100kSPS S –20 f = 11kHz IN V = 4.096V REF SNR = 99.6dB –40 100 16.4 THD = –116dB SFDR = 116.2dB –60 S/(N+D) = 99.5dB –80 SNR 98 16.2 S/(N+D) –100 –120 16.0 96 –140 ENOB –160 15.8 –180 94 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) FREQUENCY (kHz) 03084-0-012 03084-0-015 Figure 7. FFT (11 kHz Tone) Figure 10. SNR, S/(N+D), and ENOB vs. Frequency Rev. A | Page 12 of 28 INL-LSB (18-Bit) AMPLITUDE (dB of Full Scale) COUNTS SNR AND S/[N+D] (dB) DNL-LSB (18-Bit) COUNTS ENOB (Bits) AD7678 –80 –100 –90 –110 –100 THD –110 THIRD THD –120 HARMONIC –120 THIRD SECOND HARMONIC SECOND HARMONIC HARMONIC –130 –130 –140 –150 –140 0 10 20 30 40 50 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (C) 03084-0-016 03084-0-019 Figure 11. THD and Harmonics vs. Frequency Figure 14. THD and Harmonics vs. Temperature 104 10000 V = 4.096V REF 1000 103 100 102 10 SNR 101 S/(N+D) 1 AVDD DVDD 100 0.1 OVDD 99 0.01 98 0.001 –60 –50 –40 –30 –20 –10 0 1 10 100 1k 10k 100k INPUT LEVEL (dB) SAMPLING RATE (SPS) 03084-0-017 03084-0-020 Figure 12. SNR and S/(N+D) vs. Input Level Figure 15. Operating Current vs. Sampling Rate 16.5 101 1000 SNR 800 16.0 100 S/(N+D) DVDD 600 ENOB 99 15.5 400 AVDD 98 15.0 200 OVDD 14.5 97 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –155 25456585 105 125 TEMPERATURE (C) TEMPERATURE (C) 03084-0-021 03084-0-018 Figure 13. SNR, S/(N+D), and ENOB vs. Temperature Figure 16. Power-Down Operating Currents vs. Temperature Rev. A | Page 13 of 28 SNR, S/[N+D] (dB) THD, HARMONICS (dB) SNR REFERRED TO FULL SCALE (dB) OPERATING CURRENT (A) POWER-DOWN OPERATING CURRENTS (nA) THD, HARMONICS (dB) AD7678 50 50 40 OVDD = 2.7V @ 85°C 30 40 GAIN ERROR 20 10 30 0 ZERO ERROR –10 20 OVDD = 2.7V @ 25°C –20 OVDD = 5V @ 85°C OVDD = 5V @ 25°C –30 10 –40 –50 0 –55 –35 –15 5 25 45 65 85 105 125 0 50 100 150 200 TEMPERATURE (C) C (pF) L 03083-0-022 03084-0-024 Figure 17. Zero Error and Gain Error vs. Temperature Figure 18. Typical Delay vs. Load Capacitance C L Rev. A | Page 14 of 28 ZERO ERROR, GAIN ERROR (LSB) t DELAY (ns) 12 AD7678 CIRCUIT INFORMATION IN+ SWITCHES CONTROL SW+ MSB LSB 262,144C 131,072C 4C 2C C C BUSY REF CONTROL COMP LOGIC OUTPUT REFGND CODE 4C 2C C C 262,144C 131,072C LSB MSB SW– CNVST IN– 03084–0–025 Figure 19. ADC Simplified Schematic The AD7678 is a very fast, low power, single-supply, precise CONVERTER OPERATION 18-bit analog-to-digital converter (ADC) using successive The AD7678 is a successive approximation ADC based on a approximation architecture. charge redistribution DAC. Figure 19 shows the simplified schematic of the ADC. The capacitive DAC consists of two The AD7678’s linearity and dynamic range are similar or better identical arrays of 18 binary weighted capacitors, which are than many - ADCs. With the advantages of its successive connected to the two comparator inputs. architecture, which ease multiplexing and reduce power with throughput, it can be advantageous in applications that During the acquisition phase, terminals of the array tied to the normally use - ADCs. comparator’s input are connected to AGND via SW+ and SW–. All independent switches are connected to the analog inputs. The AD7678 provides the user with an on-chip track/hold, Thus, the capacitor arrays are used as sampling capacitors and successive approximation ADC that does not exhibit any acquire the analog signal on IN+ and IN– inputs. When the pipeline or latency, making it ideal for multiple multiplexed CNVST acquisition phase is complete and the input goes low, a channel applications. conversion phase is initiated. When the conversion phase The AD7678 can be operated from a single 5 V supply and can begins, SW+ and SW– are opened first. The two capacitor be interfaced to either 5 V or 3 V digital logic. It is housed in a arrays are then disconnected from the inputs and connected to 48-lead LQFP, or a tiny 48-lead LFCSP package that offers space the REFGND input. Therefore, the differential voltage between savings and allows for flexible configurations as either a serial the IN+ and IN– inputs captured at the end of the acquisition or parallel interface. The AD7678 is pin-to-pin compatible with phase is applied to the comparator inputs, causing the the AD7674, AD7676, and AD7679. comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (V /2, V /4...V /262144). The control logic toggles these REF REF REF switches, starting with the MSB first, to bring the comparator back into a balanced condition. After completing this process, the control logic generates the ADC output code and brings the BUSY output low. Rev. A | Page 15 of 28 AD7678 Transfer Functions Table 8. Output Codes and Ideal Input Voltages Except in 18-bit interface mode, the AD7678 offers straight Straight Twos binary and twos complement output coding when using OB/2C. Analog Input Binary Complement See Figure 20 and Table 8 for the ideal transfer characteristic. Description V = 4.096 V (Hex) (Hex) REF 1 1 FSR –1 LSB 4.095962 V 3FFFF 1FFFF FSR – 2 LSB 4.095924 V 3FFFE 1FFFE 111...111 Midscale + 31.25 μV 20001 00001 111...110 1 LSB 111...101 Midscale 0 V 20000 00000 Midscale – –31.25 μV 1FFFF 3FFFF 1 LSB –FSR + 1 LSB -4.095962 V 00001 20001 2 2 –FSR -4.096 V 00000 20000 000...010 000...001 000...000 1 This is also the code for overrange analog input (VIN+ – VIN– –FS –FS + 1 LSB +FS – 1 LSB above V – V ). REF REFGND –FS + 0.5 LSB 2 +FS – 1.5 LSB This is also the code for underrange analog input (VIN+ – VIN– ANALOG INPUT below –V + V ). REF REFGND 03084-0-026 Figure 20. ADC Ideal Transfer Function DVDD ANALOG 20 DIGITAL SUPPLY SUPPLY (3.3V OR 5V) NOTE 5 (5V) + + + 100nF 10F 10 F 100nF 100nF 10 F ADR421 AVDD AGND DGND DVDD OVDD OGND REFBUFIN SERIAL PORT 2.5V REF SCLK 1M 50k 100nF NOTE 1 100nF SDOUT NOTE 3 REF C REF BUSY 10F NOTE 2 C/P/DSP REFGND CNVST 50 – NOTE 4 IN+ MODE1 U1 AD7678 + ANALOG INPUT+ MODE0 OB/2C DVDD C C AD8021 PDBUF CLOCK 50 CS RD – NOTE 4 U2 IN– RESET ANALOG INPUT– + PD C C AD8021 NOTES 1. SEE VOLTAGE REFERENCE SECTION. 2. C is 10F CERAMIC CAPACITOR OR LOW ESR TANTALUM. CERAMIC SIZE REF 1206 PANASONIC ECJ-3xB0J106 IS RECOMMENDED. SEE VOLTAGE REFERENCE SECTION. 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 03084-0-027 Figure 21. Typical Connection Diagram (Internal Reference Buffer, Serial Interface) Rev. A | Page 16 of 28 ADC CODE (Straight Binary) AD7678 TYPICAL CONNECTION DIAGRAM During the acquisition phase for ac signals, the AD7678 behaves like a 1-pole RC filter consisting of the equivalent resistance, Figure 21 shows a typical connection diagram for the AD7678. Different circuitry shown on this diagram is optional and is R+, R–, and C . Resistors R+ and R– are typically 3 k and are S discussed later in this data sheet. lumped components made up of a serial resistor and the on resistance of the switches. C is typically 60 pF and mainly S Analog Inputs consists of the ADC sampling capacitor. This 1-pole filter with a Figure 22 shows a simplified analog input section of the –3 dB cutoff frequency of 900 kHz typ reduces any undesirable AD7678. The diodes shown in Figure 22 provide ESD protec- aliasing effect and limits the noise coming from the inputs. tion for the inputs. Care must be taken to ensure that the analog Because the input impedance of the AD7678 is very high, the input signal never exceeds the absolute ratings on these inputs. part can be driven directly by a low impedance source without This will cause these diodes to become forward-biased and start gain error. conducting current. These diodes can handle a forward-biased current of 120 mA max. This condition could eventually occur Driver Amplifier Choice when the input buffer’s U1 or U2 supplies are different from Although the AD7678 is easy to drive, the driver amplifier AVDD. In such a case, an input buffer with a short-circuit needs to meet the following requirements: current limitation can be used to protect the part. AVDD  The driver amplifier and the AD7678 analog input circuit have to be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). In the amplifier’s data sheet, settling at 0.1% or 0.01% is more commonly R+ = 3k IN+ specified. This could differ significantly from the settling C S time at an 18-bit level and, therefore, should be verified C S IN– prior to driver selection. The tiny op amp AD8021, which R– = 3k combines ultralow noise and high gain-bandwidth, meets this settling time requirement. AGND 03084-0-028  The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and Figure 22. Simplified Analog Input transition noise performance of the AD7678. The noise This analog input structure is a true differential structure. By coming from the driver is filtered by the AD7678 analog using these differential inputs, signals common to both inputs input circuit 1-pole low-pass filter made by R+, R–, and C . S are rejected as shown in Figure 23, which represents typical CMRR over frequency. The SNR degradation due to the amplifier is     25   80 SNRLOSS 20 log    2  625 f (Ne )   –3dB N   75 where: 70 f–3dB is the –3 dB input bandwidth in MHz of the AD7678 (0.9 MHz). 65 N is the noise factor of the amplifiers (1 if in buffer configuration). 60 e is the equivalent input noise voltage of each op amp in N nV/Hz. 55 For instance, for a driver with an equivalent input noise of 50 6 nV/Hz (e.g., AD8610) configured as a buffer, thus with 110 100 1000 10000 a noise gain of +1, the SNR degrades by only 0.65 dB. FREQUECY (kHz) 03084-0-029 Figure 23. Analog Input CMRR vs. Frequency  The driver needs to have a THD performance suitable to that of the AD7678. Rev. A | Page 17 of 28 CMRR (dB) AD7678 The AD8021 meets these requirements and is usually appropri- To use the internal reference buffer, PDBUF should be LOW. A ate for almost all applications. The AD8021 needs a 10 pF 2.5 V reference voltage applied on the REFBUFIN input will external compensation capacitor, which should have good result in a 4.096 V reference on the REF pin. linearity as an NPO ceramic or mica type. In both cases, the voltage reference input REF has a dynamic The AD8022 could be used if a dual version is needed and gain input impedance and therefore requires an efficient decoupling of 1 is present. The AD829 is an alternative in applications between REF and REFGND inputs. The decoupling consists of where high frequency (above 100 kHz) performance is not a low ESR 47 μF tantalum capacitor connected to the REF and required. In gain of 1 applications, it requires an 82 pF REFGND inputs with minimum parasitic inductance. compensation capacitor. The AD8610 is another option when Care should also be taken with the reference temperature low bias current is needed in low frequency applications. coefficient of the voltage reference, which directly affects the Single-to-Differential Driver full-scale accuracy if this parameter matters. For instance, a ±4 ppm/°C temperature coefficient of the reference changes the For applications using unipolar analog signals, a single-ended- full scale by ±1 LSB/°C. to-differential driver will allow for a differential input into the part. The schematic is shown in Figure 24. When provided an Power Supply input signal of 0 to V , this configuration will produce a REF The AD7678 uses three sets of power supply pins: an analog 5 V differential ±V with midscale at V /2. REF REF supply (AVDD), a digital 5 V core supply (DVDD), and a digital If the application can tolerate more noise, the AD8138 output interface supply (OVDD). The OVDD supply defines differential driver can be used. the output logic level and allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as U1 shown in Figure 21. The AD7678 is independent of power ANALOG INPUT AD8021 (UNIPOLAR supply sequencing once OVDD does not exceed DVDD by 10pF 0V TO 4.096V) more than 0.3 V, and is therefore free from supply voltage 590 induced latch-up. Additionally, it is very insensitive to power IN+ 590 supply variations over a wide frequency range, as shown in AD7678 Figure 25. IN– U2 1.82k REF REFBUFIN AD8021 10F 100nF 10pF 8.25k 65 2.5V 03084-0-030 60 Figure 24. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) 55 Voltage Reference The AD7678 allows the use of an external voltage reference with 50 or without the internal reference buffer. 45 Using the internal reference buffer is recommended when sharing a common reference voltage between multiple ADCs is desired. 40 110 100 1000 10000 FREQUECY (kHz) However, the advantages of using the external reference voltage 03084-0-031 directly are Figure 25. PSRR vs. Frequency  The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage very close to the supply (5 V) instead of a typical 4.096 V reference when the internal buffer is used.  The power saving when the internal reference buffer is powered down (PDBUF HIGH). Rev. A | Page 18 of 28 PSRR (dB) AD7678 POWER DISSIPATION VERSUS THROUGHPUT t 2 t 1 The AD7678 automatically reduces its power consumption at CNVST the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows for a signifi- BUSY cant power savings when the conversion rate is reduced, as t 4 shown in Figure 26. This feature makes the AD7678 ideal for t 3 t 6 very low power battery applications. t 5 MODE ACQUIRE CONVERT ACQUIRE CONVERT It should be noted that the digital interface remains active even t t 7 8 during the acquisition phase. To reduce the operating digital 03084-0-033 supply currents even further, the digital inputs need to be Figure 27. Basic Conversion Timing driven close to the power rails (DVDD and DGND), and OVDD should not exceed DVDD by more than 0.3 V. Although CNVST is a digital signal, it should be designed with 100000 special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. 10000 For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7678 1000 controls the acquisition phase and then automatically initiates a new conversion. By keeping low, the AD7678 keeps the 100 CNVST conversion process running by itself. It should be noted that the 10 analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the 1 conversion process. In this mode, the AD7678 could sometimes PDBUF HIGH run slightly faster than the guaranteed limits of 100 kSPS. 0.1 1 100 1k 10k 100k 10 SAMPLING RATE (SPS) 03084-0-032 t 9 Figure 26. Power Dissipation vs. Sample Rate RESET CONVERSION CONTROL Figure 27 shows the detailed timing diagrams of the conversion BUSY process. The AD7678 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the DATA BUS conversion is complete. The CNVST signal operates independently of the and signals. CS RD t 8 CNVST 03084-0-034 Figure 28. RESET Timing Rev. A | Page 19 of 28 POWER DISSIPATION (mW) AD7678 DIGITAL INTERFACE CS The AD7678 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. RD The serial interface is multiplexed on the parallel data bus. The AD7678 digital interface also accommodates both 3 V and 5 V BUSY logic by simply connecting the AD7678’s OVDD supply pin to DATA CURRENT the host system interface digital supply. Finally, by using the BUS CONVERSION input pin in any mode except 18-bit interface mode, OB/2C t t 12 13 both twos complement and straight binary coding can be used. 03084-0-036 Figure 30. Slave Parallel Data Timing for Reading (Read after Convert) The two signals, and , control the interface. When at least CS RD one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7678 in CS = 0 t multicircuit applications, and is held low in a single AD7678 1 CNVST, design. is generally used to enable the conversion result on RD RD the data bus. BUSY t 4 CS = RD = 0 t t 1 3 CNVST DATA PREVIOUS CONVERSION BUS t 10 t t 12 13 t BUSY 4 03084-0-037 t 3 Figure 31. Slave Parallel Data Timing for Reading (Read during Convert) t 11 DATA PREVIOUS CONVERSION DATA NEW DATA BUS 03084-0-035 CS Figure 29. Master Parallel Data Timing for Reading (Continuous Read) RD PARALLEL INTERFACE A0, A1 The AD7678 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The HI-Z HI-Z HIGH BYTE LOW BYTE data can be read either after each conversion, which is during PINS D[15:8] the next acquisition phase, or during the following conversion, t t t 12 12 13 HI-Z HI-Z as shown in Figure 30 and Figure 31, respectively. When the PINS D[7:0] LOW BYTE HIGH BYTE data is read during the conversion, however, it is recommended 03084-0-038 that it is read only during the first half of the conversion phase. Figure 32. 8-Bit and 16-Bit Parallel Interface This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog SERIAL INTERFACE conversion circuitry. Refer to Table 7 for a detailed description The AD7678 is configured to use the serial interface when of the different options available. MODE0 and MODE1 are held high. The AD7678 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. Rev. A | Page 20 of 28 AD7678 MASTER SERIAL INTERFACE In Read during Conversion mode, the serial clock and data Internal Clock toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion The AD7678 is configured to generate and provide the serial decisions. data clock SCLK when the EXT/ pin is held low. The INT AD7678 also generates a SYNC signal to indicate to the host In Read after Conversion mode, it should be noted that unlike when the serial data is valid. The serial clock SCLK and the in other modes, the BUSY signal returns low after the 18 data SYNC signal can be inverted if desired. Depending on the bits are pulsed out and not at the end of the conversion phase, RDC/SDIN input, the data can be read after each conversion or which results in a longer BUSY width. during the following conversion. Figure 33 and Figure 34 show the detailed timing diagrams of these two modes. To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. Usually, because the AD7678 is used with a fast throughput, the mode master read during conversion is the most recommended serial mode. RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SCLK t 15 t 27 SDOUT X D17 D16 D2 D1 D0 t t 16 23 t 22 03084-0-039 Figure 33. Master Serial Data Timing for Reading (Read after Convert) Rev. A | Page 21 of 28 AD7678 EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 16 17 18 t 18 t 27 X D17 D16 D2 D1 D0 SDOUT t t 23 16 t 22 03084-0-040 Figure 34. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion The AD7678 is configured to accept an externally supplied This mode is the most recommended of the serial slave modes. serial data clock on the SCLK pin when the EXT/INT pin is Figure 35 shows the detailed timing diagrams of this method. held high. In this mode, several methods can be used to read After a conversion is complete, indicated by BUSY returning the data. The external serial clock is gated by CS. When CS and low, the result of this conversion can be read while both CS and RD are both low, the data can be read after each conversion or are low. Data is shifted out MSB first with 18 clock pulses, RD during the following conversion. The external clock can be and is valid on both the rising and falling edge of the clock. either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when Among the advantages of this method, the conversion perfor- inactive. Figure 35 and Figure 36 show the detailed timing mance is not degraded because there are no voltage transients diagrams of these methods. on the digital interface during the conversion process. Also, data can be read at speeds up to 40 MHz, accommodating both While the AD7678 is performing a bit decision, it is important slow digital host interface and the fastest serial reading. that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is Finally, in this mode only, the AD7678 provides a daisy-chain particularly important during the second half of the conversion feature using the RDC/SDIN input pin to cascade multiple phase because the AD7678 provides error correction circuitry converters together. This feature is useful for reducing that can correct for an improper bit decision made during the component count and wiring connections when desired (for first half of the conversion phase. For this reason, it is recom- instance, in isolated multiconverter applications). mended that when an external clock is being provided, it is a discontinuous clock that only toggles when BUSY is low or, An example of the concatenation of two devices is shown in more importantly, that it does not transition during the latter Figure 37. Simultaneous sampling is possible by using a half of BUSY high. common signal. It should be noted that the RDC/SDIN CNVST input is latched on the edge of SCLK opposite the one used to shift out data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. Rev. A | Page 22 of 28 AD7678 INVSCLK = 0 EXT/INT = 1 RD = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 16 17 18 19 20 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 X17 X16 t 16 t 34 SDIN X17 X16 X15 X1 X0 Y17 Y16 t 33 03084-0-041 Figure 35. Slave Serial Data Timing for Reading (Read after Convert) INVSCLK = 0 EXT/INT = 1 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 16 17 18 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 t 16 03084-0-042 Figure 36. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. A | Page 23 of 28 AD7678 BUSY OUT MICROPROCESSOR INTERFACING BUSY BUSY The AD7678 is ideally suited for traditional dc measurement AD7678 AD7678 applications supporting a microprocessor, and for ac signal #2 (UPSTREAM) #1 (DOWNSTREAM) processing applications interfacing to a digital signal processor. The AD7678 is designed to interface either with a parallel 8-bit DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT or 16-bit wide interface, or with a general-purpose serial port or CNVST CNVST CS CS I/O ports on a microcontroller. A variety of external buffers can SCLK SCLK be used with the AD7678 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the SCLK IN CS IN AD7678 with an SPI equipped DSP, the ADSP-219x. CNVST IN 03084-0-043 SPI Interface (ADSP-219x) Figure 37. Two AD7678s in a Daisy-Chain Configuration Figure 38 shows an interface diagram between the AD7678 and the SPI equipped ADSP-219x. To accommodate the slower External Clock Data Read during Conversion speed of the DSP, the AD7678 acts as a slave device, and data must be read after conversion. This mode also allows the daisy- Figure 36 shows the detailed timing diagrams of this method. chain feature. The convert command could be initiated in During a conversion, while both CS and RD are low, the result response to an internal timer interrupt. The 18-bit output data of the previous conversion can be read. The data is shifted out are read with 3-byte SPI access. The reading process could be MSB first with 18 clock pulses, and is valid on both the rising initiated in response to the end-of-conversion signal (BUSY and falling edge of the clock. The 18 bits have to be read before going low) using an interrupt line of the DSP. The serial the current conversion is complete. If that is not done, interface (SPI) on the ADSP-219x is configured for master RDERROR is pulsed high and can be used to interrupt the host mode (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase interface to prevent incomplete data reading. There is no daisy- bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by chain feature in this mode, and the RDC/SDIN input should writing to the SPI control register (SPICLTx). It should be noted always be tied either high or low. that to meet all timing requirements, the SPI clock should be To reduce performance degradation due to digital activity, a fast limited to 17 Mbits/s, which allow it to read an ADC result in discontinuous clock is recommended to ensure that all bits are about 1.1 μs. read during the first half of the conversion phase. It is also DVDD possible to begin to read the data after conversion and continue ADSP-219x* AD7678* to read the last bits even after a new conversion has been SER/PAR initiated. EXT/INT BUSY PFx CS SPIxSEL (PFx) RD SDOUT MISOx INVSCLK SCLK SCKx CNVST PFx or TFSx *ADDITIONAL PINS OMITTED FOR CLARITY 03084-0-044 Figure 38. Interfacing the AD7678 to an SPI Interface Rev. A | Page 24 of 28 AD7678 APPLICATION HINTS interface digital supply OVDD and the remaining digital LAYOUT circuitry. When DVDD is powered from the system supply, it is The AD7678 has very good immunity to noise on the power useful to insert a bead to further reduce high frequency spikes. supplies. However, care should still be taken with regard to The AD7678 has four different ground pins: REFGND, AGND, grounding layout. DGND, and OGND. REFGND senses the reference voltage and The printed circuit board that houses the AD7678 should be should be a low impedance return to the reference because it designed so that the analog and digital sections are separated carries pulsed currents. AGND is the ground to which most and confined to certain areas of the board. This facilitates the internal ADC analog signals are referenced. This ground must use of ground planes that can be easily separated. Digital and be connected with the least resistance to the analog ground analog ground planes should be joined in only one place, plane. DGND must be tied to the analog or digital ground plane preferably underneath the AD7678, or at least as close to the depending on the configuration. OGND is connected to the AD7678 as possible. If the AD7678 is in a system where digital system ground. multiple devices require analog-to-digital ground connections, The layout of the decoupling of the reference voltage is the connection should still be made at one point only, a star important. The decoupling capacitor should be close to the ground point that should be established as close to the AD7678 ADC and should be connected with short and large traces to as possible. minimize parasitic inductances. The user should avoid running digital lines under the device, because these will couple noise onto the die. The analog ground EVALUATING THE AD7678’S PERFORMANCE plane should be allowed to run under the AD7678 to avoid The evaluation board for the AD7678 allows a quick means to noise coupling. Fast switching signals like or clocks CNVST measure both dc (histograms and time domain) and ac (time should be shielded with digital ground to avoid radiating noise and frequency domain) performances of the converter. The to other sections of the board, and should never run near EVAL-AD7678CBZ is an evaluation board package that includes analog signal paths. Crossover of digital and analog signals a fully assembled and tested evaluation board, documentation, should be avoided. Traces on different but close layers of the and software. The accompanying software requires the use of a board should run at right angles to each other. This will reduce capture board that must be ordered seperately from the evalua- the effect of feedthrough through the board. The power supply tion board (see the Ordering Guide for information). The lines to the AD7678 should use as large a trace as possible to evaluation board can also be used in a standalone configuration provide low impedance paths and reduce the effect of glitches and does not use the software when in this mode. Refer to the on the power supply lines. Good decoupling is also important EVAL-AD76XXEDZ and EVAL-AD76XXCBZ data sheets to lower the supply’s impedance presented to the AD7678 and available from www.analog.com for evaluation board details. to reduce the magnitude of the supply spikes. Decoupling Two types of data capture boards can be used with the EVAL- ceramic capacitors, typically 100 nF, should be placed close to AD7678CBZ: and ideally right up against each power supply pin (AVDD, DVDD, and OVDD) and their corresponding ground pins.  USB based (EVAL-CED1Z recommended) Additionally, low ESR 10 μF capacitors should be located near  Parallel port based (EVAL-CONTROL BRD3Z not the ADC to further reduce low frequency ripple. recommended because many newer PCs do not include The DVDD supply of the AD7678 can be a separate supply or parallel ports any longer) can come from the analog supply, AVDD, or the digital The recommended board layout for the AD7678 is outlined in interface supply, OVDD. When the system digital supply is the evaluation board data sheet. noisy or when fast switching digital signals are present, and if no separate supply is available, the user should connect the DVDD digital supply to the analog supply AVDD through an RC filter (see Figure 21), and connect the system supply to the Rev. A | Page 25 of 28 AD7678 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED 5.25 TOP 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY 0.50 BSC SECTION OF THIS DATA SHEET. 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7678ASTZ –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7678ASTZRL –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7678ACPZ –40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7678ACPZRL –40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 2 EVAL-AD7678CBZ Evaluation Board 1, 3 EVAL-CONTROL BRD2Z Parallel Port Capture Board, 32k RAM 1, 3 EVAL-CONTROL BRD3Z Parallel Port Capture Board, 128k RAM 1, 3 EVAL-CED1Z USB Data Capture Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the a capture board for evaluation/demonstration purposes. 3 These capture board allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL BRDxZ (x = 2, 3). Rev. A | Page 26 of 28 051706-A 080108-A AD7678 NOTES Rev. A | Page 27 of 28 AD7678 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. D03084-0-6/09(A) Rev. A | Page 28 of 28