ANALOG DEVICES AD7676

16-Bit, �1 LSB INL, a 500 kSPS, Differential ADC AD7676 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: 500 kSPS AVDD AGND REF REFGND DVDD DGND INL: �1 LSB Max (�0.0015% of Full Scale) 16-Bit Resolution with No Missing Codes OVDD S/(N+D): 94 dB Typ @ 45 kHz AD7676 OGND THD: –110 dB Typ @ 45 kHz SERIAL PORT Differential Input Range: �2.5 V IN+ SWITCHED SER/PAR Both AC and DC Specifications CAP DAC IN– BUSY No Pipeline Delay 16 Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface D[15:0] PARALLEL CLOCK SPI™/QSPI™/MICROWIRE™/DSP Compatible CS INTERFACE PD Single 5 V Supply Operation CONTROL LOGIC AND RD CALIBRATION CIRCUITRY RESET 67 mW Typical Power Dissipation, 15 �W @ 100 SPS OB/2C Power-Down Mode: 7 �W Max BYTESWAP Packages: 48-Lead Quad Flatpack (LQFP) CNVST 48-Lead Frame Chip Scale (LFCSP) Pin-to-Pin Compatible with the AD7675 Table I. PulSAR Selection APPLICATIONS CT Scanners Type/kSPS 100–250 500–570 800–1000 Data Acquisition Pseudo Differential AD7660 AD7650 Instrumentation AD7664 Spectrum Analysis Medical Instruments True Bipolar AD7663 AD7665 AD7671 Battery-Powered Systems True Differential AD7675 AD7676 AD7677 Process Control 18-Bit AD7678 AD7679 AD7674 Simultaneous/ AD7654 Multichannel GENERAL DESCRIPTION The AD7676 is a 16-bit, 500 kSPS, charge redistribution SAR, fully differential analog-to-digital converter (ADC) that oper- ates from a single 5 V power supply. The part contains a high PRODUCT HIGHLIGHTS speed 16-bit sampling ADC, an internal conversion clock, 1. Excellent INL error correction circuits, and both serial and parallel system The AD7676 has a maximum integral nonlinearity of 1.0 LSB interface ports. with no missing 16-bit code. The AD7676 is hardware factory-calibrated and is comprehen- 2. Superior AC Performances sively tested to ensure such ac parameters as signal-to-noise ratio The AD7676 has a minimum dynamic of 92 dB, 94 dB typical. (SNR) and total harmonic distortion (THD), in addition to the 3. Fast Throughput more traditional dc parameters of gain, offset, and linearity. The AD7676 is a 500 kSPS, charge redistribution, 16-bit It is fabricated using Analog Devices’ high performance, 0.6 micron SAR ADC with internal error correction circuitry. CMOS process and is available in a 48-lead LQFP or a tiny 4. Single-Supply Operation 48-lead LFCSP with operation specified from –40°C to +85°C. The AD7676 operates from a single 5 V supply and typically dissipates only 67 mW. It consumes 7 µW maximum when in power-down. 5. Serial or Parallel Interface Versatile parallel (8 bits or 16 bits) or 2-wire serial interface SPI and QSPI are trademarks of Motorola, Inc. MIRCOWIRE is a trademark of National Semiconductor Corporation. arrangement compatible with either 3 V or 5 V logic. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD7676–SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V –V +V V IN+ IN– REF REF Operating Input Voltage V V to AGND –0.1 +3 V IN+, IN– Analog Input CMRR f = 10 kHz 79 dB IN Input Current 500 kSPS Throughput 5 µA Input Impedance See Analog Inputs Section THROUGHPUT SPEED Complete Cycle 2 µs Throughput Rate 0 500 kSPS DC ACCURACY 1 Integral Linearity Error –1 +1 LSB No Missing Codes 16 Bits Transition Noise 0.35 LSB 2 +Full-Scale Error –22 +22 LSB 2 –Full-Scale Error –22 +22 LSB 2 Zero Error –8 +8 LSB Power Supply Sensitivity AVDD = 5 V ± 5% ±0.7 LSB AC ACCURACY 3 Signal-to-Noise f = 20 kHz 92 94 dB IN 3 f = 45 kHz 94 dB IN 3 Spurious-Free Dynamic Range f = 20 kHz 104.5 110 dB IN 3 f = 45 kHz 110 dB IN 3 Total Harmonic Distortion f = 20 kHz –110 –103.5 dB IN 3 f = 45 kHz –110 dB IN 3 Signal-to-(Noise + Distortion) f = 20 kHz 92 94 dB IN 3 f = 45 kHz 94 dB IN 3 f = 45 kHz, –60 dB Input 34 dB IN –3 dB Input Bandwidth 3.9 MHz SAMPLING DYNAMICS Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 750 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 500 kSPS Throughput 170 µA DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V +2.0 OVDD + 0.3 V IH –1 +1 µA I IL I –1 +1 µA IH DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bit Conversion Results Available Pipeline Delay Immediately after Completed Conversion I = 1.6 mA 0.4 V V OL SINK V I = –100 µA OVDD – 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 4 OVDD 2.7 5.25 V Operating Current 500 kSPS Throughput AVDD 9.5 mA 5 DVDD 3.9 mA 5 OVDD 37 µA 5 Power Dissipation 500 kSPS Throughput 67 74 mW 100 SPS Throughput 15 µW 6 In Power-Down Mode 7 µW 7 TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX NOTES 1 LSB means Least Significant Bit. Within the ±2.5 V input range, one LSB is 76.3 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 5 Tested in Parallel Reading Mode. 6 With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively. 7 Contact factory for extended temperature range. Specifications subject to change without notice. –2– REV. B AD7676 TIMING SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit Refer to Figures 11 and 12 Convert Pulsewidth t5ns 1 Time between Conversions t 2 µs 2 CNVST LOW to BUSY HIGH Delay t 30 ns 3 BUSY HIGH All Modes except in Master Serial Read t 1.25 µs 4 Convert Mode Aperture Delay t 2ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 1.25 µs 7 Acquisition Time t 750 ns 8 RESET Pulsewidth t 10 ns 9 Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t 1.25 ns 10 DATA Valid to BUSY LOW Delay t 45 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 515ns 13 1 Refer to Figures 16 and 17 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t 10 ns 16 CNVST LOW to SYNC Delay t 525 ns 17 2 SYNC Asserted to SCLK First Edge Delay t3ns 18 2 Internal SCLK Period t 25 40 ns 19 2 Internal SCLK HIGH t 12 ns 20 2 Internal SCLK LOW t7ns 21 2 SDOUT Valid Setup Time t4ns 22 2 SDOUT Valid Hold Time t2ns 23 2 SCLK Last Edge to SYNC Delay t3ns 24 CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t 10 ns 27 2 BUSY HIGH in Master Serial Read after Convert t See Table I 28 CNVST LOW to SYNC Asserted Delay t 1.25 µs 29 SYNC Deasserted to BUSY LOW Delay t 25 ns 30 Refer to Figures 18 and 19 (Slave Serial Interface Modes) External SCLK Setup Time t5ns 31 External SCLK Active Edge to SDOUT Delay t 318ns 32 SDIN Setup Time t5ns 33 SDIN Hold Time t5ns 34 External SCLK Period t 25 ns 35 External SCLK HIGH t 10 ns 36 External SCLK LOW t 10 ns 37 NOTES 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 2 In Serial Master Read during Convert Mode, see Table II. Specifications subject to change without notice. REV. B –3– AD7676 Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0011 DIVSCLK[0] 0101 Unit SYNC to SCLK First Edge Delay Minimum t 317 1717ns 18 Internal SCLK Period Minimum t 25 50 100 200 ns 19 Internal SCLK Period Maximum t 40 70 140 280 ns 19 Internal SCLK HIGH Minimum t 12 22 50 100 ns 20 Internal SCLK LOW Minimum t 721 4999ns 21 SDOUT Valid Setup Time Minimum t 418 1818ns 22 SDOUT Valid Hold Time Minimum t 2430 89ns 23 SCLK Last Edge to SYNC Delay Minimum t 360 140 300 ns 24 Busy High Width Maximum t 2 2.5 3.5 5.75 µs 28 1 ABSOLUTE MAXIMUM RATINGS I 1.6mA OL Analog Inputs 2 2 IN+ , IN– , REF, REFGND . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V TO OUTPUT 1.4V PIN C L Ground Voltage Differences * 60pF AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V Supply Voltages I 500�A OH AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V * AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Digital Inputs . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V 3 Figure 1. Load Circuit for Digital Interface Timing Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 700 mW 4 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 2V Lead Temperature Range 0.8V (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C t t DELAY DELAY NOTES 1 2V 2V Stresses above those listed under Absolute Maximum Ratings may cause perma- 0.8V 0.8V nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating Figure 2. Voltage Reference Levels for Timings conditions for extended periods may affect device reliability. 2 See Analog Inputs section. 3 Specification is for device in free air: 48-Lead LQFP: � = 91°C/W, � = 30°C/W. JA JC 4 Specification is for device in free air: 48-Lead LFCSP: � = 26°C/W. JA ORDERING GUIDE Package Model Temperature Range Package Description Option AD7676AST –40°C to +85°CQuad Flatpack (LQFP) ST-48 AD7676ASTRL –40°C to +85°CQuad Flatpack (LQFP) ST-48 AD7676ACP –40°C to +85°CChip Scale (LFCSP) CP-48 AD7676ACPRL –40°C to +85°CChip Scale (LFCSP) CP-48 1 EVAL-AD7676CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7676 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. –4– REV. B AD7676 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 6, 7, NC No Connect 40–42, 44–48 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary. When LOW, the MSB is inverted resulting in a twos complement output from its internal shift register. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected. When HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these pins are high impedance outputs. 13 D[4] DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Modes. 16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input or a Read Mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface, Digital Power Ground 18 OVDD P Input/Output Interface, Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground REV. B –5– AD7676 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type Description 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When or SDOUT SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7676 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or output, depending on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal. 30 DGND P Must Be Tied to Digital Ground 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, resets the AD7676. Current conversion if any is aborted. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t ) is complete, the next falling 8 edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t ) is complete, the internal sample-and-hold is put into the hold state and a 8 conversion is started immediately. 36 AGND P Must Be Tied to Analog Ground 37 REF AI Reference Input Voltage 38 REFGND AI Reference Input Analog Ground 39 IN– AI Differential Negative Analog Input 43 IN+ AI Differential Positive Analog Input NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power –6– REV. B AD7676 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET 5 OB/2C 32 CS AD7676 6 NC 31 RD TOP VIEW 7 NC 30 DGND (Not to Scale) 8 29 SER/PAR BUSY D0 9 28 D15 D1 10 27 D14 11 D2/DIVSCLK[0] 26 D13 12 D3/DIVSCLK[1] 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT DEFINITION OF SPECIFICATIONS Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) ENOB is a measurement of the resolution with a sine wave Integral nonlinearity is the maximum deviation of a straight line input. It is related to S/(N+D) by the following formula: drawn through the transfer function of the actual ADC. The ENOB=+ S/– N D 17. 6/6.02 deviation is measured from the middle of each code. () [] dB Differential Nonlinearity Error (DNL) and is expressed in bits. In an ideal ADC, code transitions are 1 LSB apart. Differential Total Harmonic Distortion (THD) nonlinearity is the maximum deviation from this ideal value. It is THD is the ratio of the rms sum of the first five harmonic often specified in terms of resolution for which no missing codes components to the rms value of a full-scale input signal and is are guaranteed. expressed in decibels. +Full-Scale Error Signal-to-Noise Ratio (SNR) The last transition (from 011... 10 to 011 . . . 11 in twos comple- SNR is the ratio of the rms value of the actual input signal to the ment coding) should occur for an analog voltage 1 1/2 LSB below rms sum of all other spectral components below the Nyquist the nominal +full scale (+2.499886 V for the ±2.5 V range). The frequency, excluding harmonics and dc. The value for SNR is +full-scale error is the deviation of the actual level of the last expressed in decibels (dB). transition from the ideal level. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) –Full-Scale Error S/(N+D) is the ratio of the rms value of the actual input signal The first transition (from 100... 00 to 100 . . . 01 in twos comple- to the rms sum of all other spectral components below the ment coding) should occur for an analog voltage 1/2 LSB above Nyquist frequency, including harmonics but excluding dc. The the nominal –full scale (–2.499962 V for the ±2.5 V range). The value for S/(N+D) is expressed in decibels (dB). –full-scale error is the deviation of the actual level of the last Aperture Delay transition from the ideal level. Aperture delay is a measure of the acquisition performance and Bipolar Zero Error is measured from the falling edge of the CNVST input to when The bipolar zero error is the difference between the ideal midscale the input signal is held for a conversion. input voltage (0 V) and the actual voltage producing the midscale Transient Response output code. The time required for the AD7676 to achieve its rated accuracy Spurious-Free Dynamic Range (SFDR) after a full-scale step function is applied to its input. The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. REV. B –7– NC D4/EXT/INT NC D5/INVSYNC NC D6/INVSCLK NC D7/RDC/SDIN NC OGND OVDD IN+ DVDD NC DGND NC D8/SDOUT NC D9/SCLK IN– REFGND D10/SYNC REF D11/RDERROR AD7676–Typical Performance Characteristics 1.00 16000 14640 0.75 14000 0.50 12000 0.25 10000 0 8000 –0.25 6000 –0.50 4000 –0.75 2000 880 863 0 0 0 0 0 0 0 0 –1.00 0000 0 16384 32768 49152 65536 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE CODE IN HEXA TPC 1. Integral Nonlinearity vs. Code TPC 4. Histogram of 16,384 Conversions of a DC Input at the Code Center 9000 20 8271 8094 8000 16 7000 6000 12 5000 4000 8 3000 2000 4 1000 0 0 0 8 11 0 0 0 0000 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0.0 CODE IN HEXA NEGATIVE INL – LSB TPC 2. Histogram of 16,384 Conversions of a DC Input at TPC 5. Typical Negative INL Distribution (199 Units) the Code Transition 0 20 f = 500kSPS S –20 f = 45.01kHz IN SNR = 94dB 16 THD = –110dB –40 SFDR = 110dB SINAD = 93.9dB –60 12 –80 –100 8 –120 –140 4 –160 –180 0 050 100 150 200 250 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY – kHz POSITIVE INL – LSB TPC 3. Typical Positive INL Distribution (199 Units) TPC 6. FFT Plot –8– REV. B INL – LSB COUNTS NUMBER OF UNITS AMPLITUDE – dB of Full Scale COUNTS NUMBER OF UNITS AD7676 100 16.0 50 OVDD = 2.7V @ 85�C 95 15.5 40 OVDD = 2.7V @ 25�C SNR 90 15.0 30 S/(N�D) 85 14.5 OVDD = 5.0V @ 85�C 20 ENOB OVDD = 5.0V @ 25�C 80 14.0 10 75 13.5 70 13.0 0 1 10 100 1000 0 50 100 150 200 FREQUENCY – kHz C – pF L TPC 7. SNR, S/(N+D), and ENOB vs. Frequency TPC 10. Typical Delay vs. Load Capacitance C L 96 100k SNR 10k S/(N�D) 93 1k 100 AVDD DVDD 90 10 1 OVDD 87 0.1 0.01 83 0.001 –60 –50 –40 –30 –20 –10 0 10 100 1k 10k 100k 1M INPUT LEVEL – dB SAMPLING RATE – SPS TPC 8. SNR and S/(N+D) vs. Input Level TPC 11. Operating Currents vs. Sample Rate 96 –104 250 DVDD SNR 200 93 –106 150 90 –108 100 87 –110 THD 50 AVDD OVDD 84 –112 0 –55 –35 –15 0 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE – �C TEMPERATURE – �C TPC 9. SNR, THD vs. Temperature TPC 12. Power-Down Operating Currents vs. Temperature REV. B –9– SNR – dB SNR AND S/(N�D) – dB SNR (REFERENCED TO FULL SCALE) – dB THD – dB ENOB – Bits OPERATING CURRENTS – �A POWER-DOWN OPERATING CURRENTS – nA t DELAY – ns 12 AD7676 5 During the acquisition phase, terminals of the array tied to the 4 comparator’s input are connected to AGND via SW and SW . + – All independent switches are connected to the analog inputs. 3 Thus, the capacitor arrays are used as sampling capacitors and 2 acquire both analog signals. –FS 1 When the acquisition phase is complete and the CNVST input 0 goes or is low, a conversion phase is initiated. When the conversion phase begins, SW and SW are opened first. The two capacitor + – –1 OFFSET arrays are then disconnected from the inputs and connected to –2 the REFGND input. Therefore, the differential voltage between +FS –3 the output of IN+ and IN– captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator –4 to become unbalanced. –5 –55 –35 –15 –5 15 35 55 75 95 115 135 By switching each element of the capacitor array between TEMPERATURE – �C REFGND or REF, the comparator input varies by binary TPC 13. Drift vs. Temperature weighted voltage steps (V /2, V /4...V /65536). The REF REF REF control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output LOW. CIRCUIT INFORMATION Transfer Functions The AD7676 is a fast, low power, single-supply, precise 16-bit Using the OB/2C digital input, the AD7676 offers two output analog-to-digital converter (ADC). The AD7676 is capable of codings: straight binary and twos complement. The ideal transfer converting 500,000 samples per second (500 kSPS) and allows characteristic for the AD7676 is shown in Figure 4. power saving between conversions. When operating at 100 SPS, for example, it typically consumes only 15 µW. This feature makes the AD7676 ideal for battery-powered applications. The AD7676 provides the user with an on-chip track-and-hold, 111...111 111...110 successive-approximation ADC that does not exhibit any pipeline 111...101 or latency, making it ideal for multiple multiplexed channel applications. The AD7676 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP package or a 48-lead LFCSP package that combines space savings and allows flexible configurations as either serial 000...010 or parallel interface. The AD7676 is pin-to-pin compatible with 000...001 the AD7675. 000...000 –FS –FS + 1 LSB +FS – 1 LSB –FS + 0.5 LSB CONVERTER OPERATION +FS – 1.5 LSB The AD7676 is a successive-approximation analog-to-digital ANALOG INPUT converter based on a charge redistribution DAC. Figure 3 shows Figure 4. ADC Ideal Transfer Function the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors. IN+ SWITCHES CONTROL MSB LSB SW + 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC OUTPUT REFGND CODE 4C 2C C C 32,768C 16,384C SW LSB – MSB CNVST IN– Figure 3. ADC Simplified Schematic –10– REV. B LSB ADC CODE – Straight Binary AD7676 DVDD ANALOG 100� DIGITAL SUPPLY SUPPLY (3.3V OR 5V) NOTE 6 (5V) + + + 10�F 100nF 10�F 100nF 100nF 10�F ADR421 AVDD AGND DGND DVDD OVDD OGND REF SERIAL PORT 2.5V REF SCLK 1M� C + REF 50k� 1�F NOTE 1 100nF SDOUT NOTE 2 REFGND NOTE 3 50� BUSY �C/�P/DSP 50� – 15� CNVST D NOTE 4 IN+ U1 + ANALOG INPUT+ NOTE 7 C 2.7nF C AD8021 AD7676 NOTE 5 OB/2C SER/PAR DVDD 50� – CS CLOCK 15� NOTE 4 U2 IN– RD ANALOG INPUT– + BYTESWAP C 2.7nF C AD8021 RESET NOTE 5 PD NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C IS 47�F. SEE VOLTAGE REFERENCE INPUT SECTION. REF 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. SEE ANALOG INPUTS SECTION. 6. OPTION, SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 5. Typical Connection Diagram (±2.5 V Range Shown) TYPICAL CONNECTION DIAGRAM current. These diodes can handle a forward-biased current of Figure 5 shows a typical connection diagram for the AD7676. 120 mA maximum. This condition could eventually occur when Different circuitry shown on this diagram is optional and is the input buffer’s (U1) or (U2) supplies are different from discussed below. AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. Analog Inputs The AD7676 is specified to operate with a differential ±2.5 V This analog input structure is a true differential structure. By range. The typical input impedance for each analog input range using these differential inputs, signals common to both inputs is also shown. Figure 6 shows a simplified analog input section are rejected as shown in Figure 7, which represents the typical of the AD7676. CMRR over frequency. AVDD 85 80 75 R+ = 684� IN+ 70 C S 65 C S IN– R– = 684� 60 55 AGND 50 Figure 6. Simplified Analog Input 45 The diodes shown in Figure 6 provide ESD protection for the 40 1k 10k 100k 1M 10M inputs. Care must be taken to ensure that the analog input signal FREQUENCY – Hz never exceeds the absolute ratings on these inputs. This will cause these diodes to become forward-biased and start conducting Figure 7. Analog Input CMRR vs. Frequency REV. B –11– CMRR – dB AD7676 During the acquisition phase for ac signals, the AD7676 behaves performance of the AD7676. The noise coming from the driver is like a one-pole RC filter consisting of the equivalent resistance filtered by the AD7676 analog input circuit one-pole, low-pass R+, R–, and C . The resistors R+ and R– are typically 684 Ω and filter made by R+, R–, and C . The SNR degradation due to S S are lumped components made up of some serial resistors and the the amplifier is: on resistance of the switches. The capacitor C is typically 60 pF S   28 and is mainly the ADC sampling capacitor. This one-pole filter   SNR = 20LOG LOSS with a typical –3 dB cutoff frequency of 3.88 MHz reduces unde- 2   784 + πfN()e −3 dB  N  sirable aliasing effects and limits the noise coming from the inputs. where: Because the input impedance of the AD7676 is very high, the AD7676 can be driven directly by a low impedance source without f is the –3 dB input bandwidth of the AD7676 (3.9 MHz) –3 dB gain error. That allows users to put, as shown in Figure 5, an or the cutoff frequency of the input filter if any is used. external one-pole RC filter between the output of the amplifier N is the noise factor of the amplifier (1 if in buffer output and the ADC analog inputs to even further improve the configuration). noise filtering done by the AD7676 analog input circuit. However, e is the equivalent input noise voltage of the op amp in nV/√Hz. N the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion (THD). For instance, a driver with an equivalent input noise of The maximum source impedance depends on the amount of 2 nV/√Hz like the AD8021 and configured as a buffer, thus THD that can be tolerated. The THD degrades proportionally with a noise gain of +1, will degrade the SNR by only 0.26 dB. to the source impedance. The AD8021 meets these requirements and is usually appropriate Single-to-Differential Driver for almost all applications. The AD8021 needs an external For applications using unipolar analog signals, a single-ended-to- compensation capacitor of 10 pF. This capacitor should have differential driver will allow for a differential input into the part. good linearity as an NPO ceramic or mica type. The schematic is shown in Figure 8. The AD8022 could also be used where a dual version is needed and a gain of 1 is used. The AD8132 or the AD8138 could also be used to generate U1 ANALOG INPUT AD8021 a differential signal from a single-ended signal. (UNIPOLAR) C C The AD829 is another alternative where high frequency (above 500 kHz) performance is not required. In a gain of 1, it requires 590� IN+ an 82 pF compensation capacitor. 590� AD7676 The AD8610 is also another option where low bias current is needed in low frequency applications. IN– U2 590� REF 2.5V REF AD8021 Voltage Reference Input 590� C C 2.5V REF The AD7676 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7676 has a dynamic Figure 8. Single-Ended-to-Differential Driver Circuit input impedance. Therefore, it should be driven by a low imped- ance source with an efficient decoupling between the REF and This configuration, when provided an input signal of 0 to V , REF REFGND inputs. This decoupling depends on the choice of the will produce a differential ±2.5 V with a common mode at 1.25 V. voltage reference but usually consists of a low ESR tantalum If the application can tolerate more noise, the AD8138 can be used. capacitor connected to the REF and REFGND inputs with Driver Amplifier Choice minimum parasitic inductance. 47 µF is an appropriate value for Although the AD7676 is easy to drive, the driver amplifier needs the tantalum capacitor when used with one of the recommended to meet the following requirements: reference voltages: • The driver amplifier and the AD7676 analog input circuit have • The low noise, low temperature drift ADR421 and AD780 to be able, together, to settle for a full-scale step of the capaci- voltage references tor array at a 16-bit level (0.0015%). In the amplifier’s data • The low power ADR291 voltage reference sheet, the settling at 0.1% or 0.01% is more commonly specified. It could significantly differ from the settling time • The low cost AD1582 voltage reference at the 16-bit level and, therefore, it should be verified prior to For applications using multiple AD7676s, it is more effective to the driver selection. The tiny op amp AD8021, which com- buffer the reference voltage with a low noise, very stable op amp bines ultralow noise and a high gain bandwidth, meets this like the AD8031. settling time requirement even when used with a high gain up to 13. Care should also be taken with the reference temperature coeffi- cient of the voltage reference, which directly affects the full-scale • The driver needs to have a THD performance suitable to accuracy if this parameter matters. For instance, a ±15 ppm/°C that of the AD7676. tempco of the reference changes the full scale by ±1 LSB/°C. • The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise –12– REV. B AD7676 1M V , as mentioned in the specification table, could be increased REF to AVDD – 1.85 V. The benefit here is the increased SNR obtained 100k as a result of this increase. Since the input range is defined in terms of V , this would essentially increase the range to make REF 10k it a ±3 V input range with an AVDD above 4.85 V. The theo- retical improvement as a result of this increase in reference is 1k 1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise, however, the observed improvement is approximately 1 dB. The 100 AD780 can be selected with a 3 V reference voltage. 10 Power Supply The AD7676 uses three sets of power supply pins: an analog 5 V 1 supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows 0.1 direct interface with any logic working between 2.7 V and 10 100 1k 10k 100k 1M SAMPLING RATE – SPS DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter Figure 10. Power Dissipation vs. Sample Rate from the analog supply as shown in Figure 5. The AD7676 is independent of power supply sequencing once OVDD does not CONVERSION CONTROL exceed DVDD by more than 0.3 V and thus free from supply Figure 11 shows the detailed timing diagrams of the conversion voltage-induced latch-up. Additionally, it is very insensitive to process. The AD7676 is controlled by the signal CNVST, which power supply variations over a wide frequency range, as shown in initiates conversion. Once initiated, it cannot be restarted or Figure 9. aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS 75 and RD signals. 70 t 2 65 t 1 CNVST 60 55 BUSY t 4 50 t 3 t 6 t 5 45 ACQUIRE CONVERT MODE ACQUIRE CONVERT 40 t t 7 8 35 1k 10k 100k 1M 10M Figure 11. Basic Conversion Timing FREQUENCY – Hz For true sampling applications, the recommended operation of Figure 9. PSRR vs. Frequency the CNVST signal is the following: CNVST must be held HIGH from the previous falling edge of POWER DISSIPATION BUSY, and during a minimum delay corresponding to the acqui- The AD7676 automatically reduces its power consumption at sition time t ; then, when CNVST is brought LOW, a conversion 8 the end of each conversion phase. During the acquisition phase, is initiated and the BUSY signal goes HIGH until the comple- the operating currents are very low, which allows a significant tion of the conversion. Although CNVST is a digital signal, it power savings when the conversion rate is reduced, as shown in should be designed with this special care with fast, clean edges, Figure 10. This feature makes the AD7676 ideal for very low and levels, with minimum overshoot and undershoot or ringing. power battery-operated applications. For applications where the SNR is critical, the CNVST signal It should be noted that the digital interface remains active even should have a very low jitter. To achieve this, some use a dedicated during the acquisition phase. To reduce the operating digital oscillator for CNVST generation or, at least, to clock it with a supply currents even further, the digital inputs need to be driven high frequency low jitter clock as shown in Figure 5. close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V. REV. B –13– PSRR – dB POWER DISSIPATION – �W AD7676 t PARALLEL INTERFACE 9 The AD7676 is configured to use the parallel interface (Figure 13) RESET when the SER/PAR is held LOW. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in BUSY Figures 14 and 15. When the data is read during the conversion, however, it is recommended that it be read-only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most DATABUS critical analog conversion circuitry. t 8 CS CNVST RD Figure 12. RESET Timing For other applications, conversions can be automatically initiated. BUSY If CNVST is held LOW when BUSY is LOW, the AD7676 CURRENT controls the acquisition phase and then automatically initiates a DATABUS CONVERSION new conversion. By keeping CNVST LOW, the AD7676 keeps the conversion process running by itself. It should be noted that t t 12 13 the analog input has to be settled when BUSY goes LOW. Also, Figure 14. Slave Parallel Data Timing for Reading at power-up, CNVST should be brought LOW once to initiate the (Read after Conversion) conversion process. In this mode, the AD7676 could sometimes run slightly faster than the guaranteed limit of 500 kSPS. CS = 0 t 1 DIGITAL INTERFACE CNVST, RD The AD7676 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. BUSY t 4 The serial interface is multiplexed on the parallel databus. The AD7676 digital interface also accommodates both 3 V or 5 V t 3 logic by simply connecting the OVDD supply pin of the AD7676 PREVIOUS to the host system interface digital supply. Finally, by using the DATABUS CONVERSION OB/2C input pin, either twos complement or straight binary t t 12 13 coding can be used. The two signals CS and RD control the interface. When at least Figure 15. Slave Parallel Data Timing for Reading (Read one of these signals is HIGH, the interface outputs are in high during Conversion) impedance. Usually, CS allows the selection of each AD7676 in The BYTESWAP pin allows a glueless interface to an 8-bit bus. multicircuit applications and is held LOW in a single AD7676 As shown in Figure 16, the LSB byte is output on D[7:0] and the design. RD is generally used to enable the conversion result on MSB is output on D[15:8] when BYTESWAP is LOW. When the databus. BYTESWAP is HIGH, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. CS = RD = 0 By connecting BYTESWAP to an address line, the 16-bit data t 1 can be read in two bytes on either D[15:8] or D[7:0]. CNVST t 10 CS t BUSY 4 t 3 t 11 RD PREVIOUS CONVERSION DATA NEW DATA DATABUS BYTE Figure 13. Master Parallel Data Timing for Reading HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE (Continuous Read) t t t 12 12 13 HI-Z HI-Z LOW BYTE HIGH BYTE PINS D[7:0] Figure 16. 8-Bit Parallel Interface –14– REV. B AD7676 SERIAL INTERFACE data is valid. The serial clock SCLK and the SYNC signal can be The AD7676 is configured to use the serial interface when the inverted if desired. The output data is valid on both the rising SER/PAR is held HIGH. The AD7676 outputs 16 bits of data and falling edges of the data clock. Depending on RDC/SDIN MSB first, on the SDOUT pin. This data is synchronized with input, the data can be read after each conversion or during the the 16 clock pulses provided on the SCLK pin. following conversion. Figures 17 and 18 show the detailed timing diagrams of these two modes. MASTER SERIAL INTERFACE Usually, because the AD7676 has a longer acquisition phase Internal Clock than the conversion phase, the data is read immediately after The AD7676 is configured to generate and provide the serial data conversion. That makes the mode master, read after conversion, clock SCLK when the EXT/INT pin is held LOW. The AD7676 also the most recommended serial mode when it can be used. generates a SYNC signal to indicate to the host when the serial RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 17. Master Serial Data Timing for Reading (Read after Conversion) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 X D15 D14 D2 D1 D0 SDOUT t t 23 16 t 22 Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Conversion) REV. B –15– AD7676 In Read-after-Conversion Mode, unlike in other modes, it should an external clock is being provided, it is a discontinuous clock be noted that the signal BUSY returns LOW after the 16 data that is toggling only when BUSY is LOW or, more importantly, bits are pulsed out and not at the end of the conversion phase, that it does not transition during the latter half of BUSY HIGH. which results in a longer BUSY width. External Discontinuous Clock Data Read after Conversion In Read-during-Conversion Mode, the serial clock and data This mode is the most recommended of the serial slave modes. toggle at appropriate instances, which minimizes potential feed- Figure 19 shows the detailed timing diagrams of this method. through between digital activity and the critical conversion decisions. After a conversion is complete, indicated by BUSY returning LOW, the result of this conversion can be read while both CS and SLAVE SERIAL INTERFACE RD are LOW. The data is shifted out, MSB first, with 16 clock External Clock pulses and is valid on both the rising and falling edges of the clock. The AD7676 is configured to accept an externally supplied serial Among the advantages of this method, the conversion perfor- data clock on the SCLK pin when the EXT/INT pin is held HIGH. mance is not degraded because there are no voltage transients In this mode, several methods can be used to read the data. The on the digital interface during the conversion process. external serial clock is gated by CS and the data are output when Another advantage is to be able to read the data at any speed up to both CS and RD are LOW. Thus, depending on CS, the data can 40 MHz, which accommodates both slow digital host interface be read after each conversion or during the following conversion. and the fastest serial reading. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally HIGH or Finally, in this mode only, the AD7676 provides a “daisy chain” normally LOW when inactive. Figures 19 and 20 show the detailed feature using the RDC/SDIN input pin for cascading multiple timing diagrams of these methods. Usually, because the AD7676 converters together. This feature is useful for reducing component has a longer acquisition phase than the conversion phase, the count and wiring connections when it is desired as it is, for data are read immediately after conversion. instance, in isolated multiconverter applications. While the AD7676 is performing a bit decision, it is important An example of the concatenation of two devices is shown in that voltage transients not occur on digital input/output pins or Figure 21. Simultaneous sampling is possible by using a common degradation of the conversion result could occur. This is particu- CNVST signal. It should be noted that the RDC/SDIN input is larly important during the second half of the conversion phase latched on the opposite edge of SCLK of the one used to shift because the AD7676 provides error correction circuitry that can out the data on SDOUT. Thus, the MSB of the “upstream” correct for an improper bit decision made during the first half of converter just follows the LSB of the “downstream” converter the conversion phase. For this reason, it is recommended that when on the next SCLK cycle. INVSCLK = 0 EXT/INT = 1 RD = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 14 15 16 17 18 t 31 t 32 SDOUT X D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 19. Slave Serial Data Timing for Reading (Read after Conversion) –16– REV. B AD7676 External Clock Data Read During Conversion interface or with a general-purpose Serial Port or I/O Ports on a Figure 20 shows the detailed timing diagrams of this method. microcontroller. A variety of external buffers can be used with During a conversion, while both CS and RD are LOW, the result the AD7676 to prevent digital noise from coupling into the ADC. of the previous conversion can be read. The data is shifted out, The following sections illustrate the use of the AD7676 with MSB first, with 16 clock pulses, and is valid on both rising and an SPI-equipped microcontroller, and the ADSP-21065L and falling edges of the clock. The 16 bits have to be read before the ADSP-218x signal processors. current conversion is complete. If that is not done, RDERROR is SPI Interface (MC68HC11) pulsed HIGH and can be used to interrupt the host interface to Figure 22 shows an interface diagram between the AD7676 and an prevent incomplete data reading. There is no daisy chain feature SPI-equipped microcontroller, such as the MC68HC11. To accom- in this mode, and RDC/SDIN input should always be tied either modate the slower speed of the microcontroller, the AD7676 acts HIGH or LOW. as a slave device and data must be read after conversion. This mode To reduce performance degradation due to digital activity, a fast also allows the daisy chain feature. The convert command could discontinuous clock of at least 18 MHz is recommended to ensure be initiated in response to an internal timer interrupt. The reading that all the bits are read during the first half of the conversion of output data, one byte at a time if necessary, could be initiated phase. For this reason, this mode is more difficult to use. in response to the end-of-conversion signal (BUSY going LOW) using an interrupt line of the microcontroller. The serial periph- MICROPROCESSOR INTERFACING eral interface (SPI) on the MC68HC11 is configured for Master The AD7676 is ideally suited for traditional dc measurement Mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase applications supporting a microprocessor and ac signal processing Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing applications interfacing to a digital signal processor. The AD7676 to the SPI Control Register (SPCR). The IRQ is configured for is designed to interface either with a parallel 8-bit or 16-bit wide edge-sensitive-only operation (IRQE = 1 in OPTION register). EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t t 3 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 SDOUT X D15 D14 D13 D1 D0 t 16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Conversion) BUSY OUT BUSY BUSY AD7676 NO. 2 AD7676 NO. 1 (UPSTREAM) (DOWNSTREAM) DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN Figure 21. Two AD7676s in a Daisy Chain Configuration REV. B –17– AD7676 DVDD ground planes that can be easily separated. Digital and analog MC68HC11* ground planes should be joined in only one place, preferably AD7676* underneath the AD7676, or, at least, as close as possible to the SER/PAR AD7676. If the AD7676 is in a system where multiple devices EXT/INT require analog to digital ground connections, the connection CS BUSY IRQ should still be made at one point only, a star ground point RD SDOUT MISO/SDI that should be established as close as possible to the AD7676. SCLK SCK INVSCLK CNVST I/O PORT It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7676 to avoid noise *ADDITIONAL PINS OMITTED FOR CLARITY coupling. Fast switching signals like CNVST or clocks should be Figure 22. Interfacing the AD7676 to SPI Interface shielded with digital ground to avoid radiating noise to other sec- tions of the board and should never run near analog signal paths. ADSP-21065L in Master Serial Interface Crossover of digital and analog signals should be avoided. Traces As shown in Figure 23, the AD7676 can be interfaced to the on different but close layers of the board should run at right ADSP-21065L using the serial interface in Master Mode without angles to each other. This will reduce the effect of feedthrough any glue logic required. This mode combines the advantages of through the board. reducing the wire connections and the ability to read the data during or after conversion maximum speed transfer (DIVSCLK[0:1] The power supply lines to the AD7676 should use as large a both LOW). trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is The AD7676 is configured for the Internal Clock Mode (EXT/INT also important to lower the supply’s impedance presented to LOW) and acts, therefore, as the master device. The convert the AD7676 and reduce the magnitude of the supply spikes. command can be generated by either an external low jitter oscil- Decoupling ceramic capacitors, typically 100 nF, should be lator or, as shown, by a FLAG output of the ADSP-21065L or by placed on each power supply’s pins, AVDD, DVDD, and OVDD, a frame output TFS of one serial port of the ADSP-21065L that close to and ideally right up against these pins and their corre- can be used like a timer. The Serial Port on the ADSP-21065L sponding ground pins. Additionally, low ESR 10 µF capacitors is configured for external clock (IRFS = 0), rising edge active should be located in the vicinity of the ADC to further reduce (CKRE = 1), external late framed sync signals (IRFS = 0, low frequency ripple. LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial Port of the ADSP-21065L is configured by writing to its receive The DVDD supply of the AD7676 can be either a separate control register (SRCTL)—see the ADSP-2106x SHARC User’s supply or come from the analog supply, AVDD, or from the Manual. Because the Serial Port within the ADSP-21065L will digital interface supply, OVDD. When the system digital supply be seeing a discontinuous clock, an initial word reading has to is noisy, or fast switching digital signals are present, it is recom- be done after the ADSP-21065L has been reset to ensure that mended if no separate supply is available, to connect the DVDD the Serial Port is properly synchronized to this clock during each digital supply to the analog supply AVDD through an RC filter as following data read operation. shown in Figure 5 and to connect the system supply to the inter- face digital supply OVDD and the remaining digital circuitry. DVDD When DVDD is powered from the system supply, it is useful to ADSP-21065L* AD7676* insert a bead to further reduce high frequency spikes. SHARC SER/PAR The AD7676 has four different ground pins: REFGND, AGND, RDC/SDIN DGND, and OGND. REFGND senses the reference voltage and RD SYNC RFS should be a low impedance return to the reference because it EXT/INT SDOUT DR carries pulsed currents. AGND is the ground to which most inter- CS SCLK RCLK nal ADC analog signals are referenced. This ground must be INVSYNC CNVST FLAG OR TFS connected with the least resistance to the analog ground plane. INVSCLK DGND must be tied to the analog or digital ground plane, *ADDITIONAL PINS OMITTED FOR CLARITY depending on the configuration. OGND is connected to the digital system ground. Figure 23. Interfacing to the ADSP-21065L Using The layout of the decoupling of the reference voltage is important. the Serial Master Mode The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic APPLICATION HINTS inductances. Layout Evaluating the AD7676 Performance The AD7676 has very good immunity to noise on the power A recommended layout for the AD7676 is outlined in the supplies as can be seen in Figure 21. However, care should still evaluation board for the AD7676. The evaluation board package be taken with regard to grounding layout. includes a fully assembled and tested evaluation board, The printed circuit board that houses the AD7676 should be documentation, and software for controlling the board from a designed so the analog and digital sections are separated and PC via the Eval-Control BRD2. confined to certain areas of the board. This facilitates the use of –18– REV. B AD7676 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 9.00 BSC 0.60 0.45 48 37 36 1 SEATING PLANE 1.45 0.20 TOP VIEW 7.00 1.40 (PINS DOWN) BSC 0.09 1.35 VIEW A 7� 3.5� 0.15 0� 12 25 SEATING 0.05 0.08 MAX 24 13 PLANE COPLANARITY 0.27 0.50 VIEW A BSC 0.22 ROTATED 90� CCW 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ PIN 1 0.18 0.60 MAX INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 TOP BOTTOM BSC SQ 4.70 VIEW VIEW 2.25 0.50 12 0.40 25 13 24 0.30 5.50 0.70 MAX REF 1.00 12� MAX 0.65 NOM 0.90 0.05 MAX 0.80 0.02 NOM 0.25 0.50 BSC COPLANARITY REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 REV. B –19– Revision History Location Page 10/02—Data Sheet changed from REV. A to REV. B. Added 48-Lead LFCSP to FEATURES and GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Edit to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Edit to Transfer Functions section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Changes to Power Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Added 48-Lead Frame Chip Scale Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 –20– REV. B PRINTED IN U.S.A. C02690–0–10/02(B)