ANALOG DEVICES AD7674

18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC AD7674 FEATURES FUNCTIONAL BLOCK DIAGRAM PDBUF REF REFGND DVDD DGND 18-bit resolution with no missing codes AGND No pipeline delay (SAR architecture) OVDD AVDD AD7674 Differential input range: ±V (V up to 5 V) REF REF SERIAL OGND REFBUFIN PORT Throughput: 800 kSPS (Warp mode) 18 666 kSPS (Normal mode) IN+ SWITCHED D[17:0] CAP DAC IN– 570 kSPS (Impulse mode) BUSY INL: ±2.5 LSB max (±9.5 ppm of full scale) PARALLEL RD INTERFACE Dynamic range : 103 dB typ (V = 5 V) REF CLOCK CS S/(N+D): 100 dB typ @ 2 kHz (V = 5 V) REF PD CONTROL LOGIC AND MODE0 Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface CALIBRATION CIRCUITRY RESET MODE1 SPI®/QSPI™/MICROWIRE™/DSP compatible On-board reference buffer CNVST WARP IMPULSE Single 5 V supply operation 03083–0–001 Power dissipation: 98 mW typ @ 800 kSPS Figure 1. Functional Block Diagram 78 mW typ@ 500 kSPS (Impulse mode) TM Table 1. PulSAR Selection 160 μW @ 1 kSPS (Impulse mode) 800– 48-lead LQFP or 48-lead LFCSP package Type/kSPS 100–250 500–570 1000 Pin-to-pin compatible upgrade of AD7676/AD7678/AD7679 Pseudo- AD7651 AD7650/AD7652 AD7653 APPLICATIONS Differential AD7660/AD7661 AD7664/AD7666 AD7667 True Bipolar AD7663 AD7665 AD7671 CT scanners True AD7675 AD7676 AD7677 High dynamic data acquisition Differential Geophone and hydrophone sensors 18-Bit AD7678 AD7679 AD7674 Σ-Δ replacement (low power, multichannel) Multichannel/ AD7654 Instrumentation Simultaneous AD7655 Spectrum analysis Medical instruments GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7674 is an 18-bit, 800 kSPS, charge redistribution SAR, 1. High Resolution, Fast Throughput. fully differential analog-to-digital converter that operates on a The AD7674 is an 800 kSPS, charge redistribution, 18-bit single 5 V power supply. The part contains a high speed 18-bit SAR ADC (no latency). sampling ADC, an internal conversion clock, an internal 2. Excellent Accuracy. reference buffer, error correction circuits, and both serial and The AD7674 has a maximum integral nonlinearity of parallel system interface ports. 2.5 LSB with no missing 18-bit codes. The part is available in 48-lead LQFP or 48-lead LFCSP 3. Serial or Parallel Interface. packages with operation specified from –40°C to +85°C. Versatile parallel (18-, 16- or 8-bit bus) or 3-wire serial interface arrangement compatible with both 3 V and 5 V logic. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD7674 TABLE OF CONTENTS Features .............................................................................................. 1 Converter Operation .................................................................. 16 Applications ....................................................................................... 1 Typical Connection Diagram ................................................... 18 General Description ......................................................................... 1 Power Dissipation versus Throughput .................................... 20 Functional Block Diagram .............................................................. 1 Conversion Control ................................................................... 20 Product Highlights ........................................................................... 1 Digital Interface .......................................................................... 20 Table of Contents .............................................................................. 2 Parallel Interface ......................................................................... 21 Revision History ............................................................................... 2 Serial Interface ............................................................................ 21 Specif ica t ions ..................................................................................... 3 Master Serial Interface ............................................................... 21 Timing Specifications ....................................................................... 5 Slave Serial Interface .................................................................. 22 Absolute Maximum Ratings ............................................................ 7 Microprocessor Interfacing ....................................................... 24 ESD Caution .................................................................................. 7 Application Hints ........................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Layout .......................................................................................... 25 Definitions of Specifications ......................................................... 11 Evaluating the AD7674’s Performance .................................... 25 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 26 Circuit Information ........................................................................ 16 Ordering Guide .......................................................................... 26 REVISION HISTORY 6/09—Rev. 0 to Rev. A Changes to Zero Error, T to T Parameter ........................... 3 MIN MAX Changes to Gain Error, T to T Parameter ........................... 3 MIN MAX Changes to Endnote 3 ...................................................................... 4 Changes to Pin Configuration Section .......................................... 8 Changes to Evaluating the AD7679’s Performance Section ...... 25 Changes to Ordering Guide .......................................................... 26 7/03—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7674 SPECIFICATIONS Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range VIN+ – VIN– –VREF +VREF V Operating Input Voltage V , V to AGND –0.1 AVDD V IN+ IN– Analog Input CMRR f = 100 kHz 65 dB IN Input Current 800 kSPS throughput 100 μA 1 Input Impedance THROUGHPUT SPEED Complete Cycle In warp mode 1.25 μs Throughput Rate In warp mode 1 800 kSPS Time between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.5 μs Throughput Rate In normal mode 0 666 kSPS Complete Cycle In impulse mode 1.75 μs Throughput Rate In impulse mode 0 570 kSPS DC ACCURACY 2 Integral Linearity Error –2.5 +2.5 LSB Differential Linearity Error –1 +1.75 LSB No Missing Codes 18 Bits Transition Noise VREF = 5 V 0.7 LSB Zero Error, T to T In warp mode –25 +25 LSB MIN MAX Zero Error, T to T In normal or impulse mode –85 +85 LSB MIN MAX Zero Error Temperature Drift All modes ±0.5 ppm/°C 3 Gain Error, TMIN to TMAX In warp mode –0.034 +0.034 % of FSR 3 Gain Error, TMIN to TMAX In normal or impulse mode –0.048 +0.048 % of FSR Gain Error Temperature Drift All modes ±1.6 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB AC ACCURACY 4 Signal-to-Noise f = 2 kHz, V = 5 V 101 dB IN REF VREF = 4.096 V 97.5 99 dB f = 10 kHz, V = 4.096 V 98 dB IN REF f = 100 kHz, V = 4.096 V 97 dB IN REF Dynamic Range V = V = V /2 = 2.5 V 103 dB IN+ IN– REF Spurious-Free Dynamic Range fIN = 2 kHz 120 dB f = 10 kHz 118 dB IN fIN = 100 kHz 105 dB Total Harmonic Distortion f = 2 kHz –115 dB IN fIN = 10 kHz –113 dB f = 100 kHz –98 dB IN Signal-to-(Noise + Distortion) fIN = 2 kHz, VREF = 4.096 V 98 dB f = 2 kHz, –60 dB input 40 dB IN –3 dB Input Bandwidth 26 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns Overvoltage Recovery 250 ns Rev. A | Page 3 of 28 AD7674 Parameter Conditions Min Typ Max Unit REFERENCE External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V REFBUFIN Input Current –1 +1 μA REF Current Drain 800 kSPS throughput 330 μA DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V VIH +2.0 DVDD + 0.3 V IIL –1 +1 μA I –1 +1 μA IH DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK V I = –500 μA OVDD – 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 DVDD + 0.3 V 8 Operating Current 800 kSPS throughput AVDD 16 mA 9 DVDD 6.5 mA 9 OVDD 50 μA 9 10 POWER DISSIPATION PDBUF high @ 500 kSPS 78 90 mW 10 PDBUF high @ 1 kSPS 160 μW 8 PDBUF high @ 800 kSPS 114 126 mW 8 PDBUF low @ 800 kSPS 126 138 mW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Inputs section. 2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV. 3 See Definitions of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 Data Format Parallel or Serial 18-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 In Warp mode. 9 Tested in Parallel Reading mode. 10 In Impulse mode. 11 Contact factory for extended temperature range. Rev. A | Page 4 of 28 AD7674 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Symbol Min Typ Max Unit Refer to Figure 34 and Figure 35 Convert Pulsewidth t 10 ns 1 1 Time between Conversions (Warp Mode/Normal Mode/Impulse Mode) t 1.25/1.5/1.75 μs 2 CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) t4 1/1.25/1.5 μs Aperture Delay t 2 ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 1/1.25/1.5 μs Acquisition Time t8 250 ns RESET Pulsewidth t9 10 ns Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes) CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t10 1/1.25/1.5 μs Data Valid to BUSY LOW Delay t11 20 ns Bus Access Request to Data Valid t 45 ns 12 Bus Relinquish Time t 5 15 ns 13 2 Refer to Figure 40 and Figure 41 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 25/275/525 ns 3 SYNC Asserted to SCLK First Edge Delay t18 3 ns 3 Internal SCLK Period t 25 40 ns 19 3 Internal SCLK HIGH t 12 ns 20 3 Internal SCLK LOW t 7 ns 21 3 SDOUT Valid Setup Time t22 4 ns 3 SDOUT Valid Hold Time t23 2 ns 3 SCLK Last Edge to SYNC Delay t24 3 CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 t 10 ns CS HIGH to SDOUT HI-Z 27 3 BUSY HIGH in Master Serial Read after Convert t28 Table 4 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) t 1/1.25/1.5 μs 29 SYNC Deasserted to BUSY LOW Delay t 25 ns 30 Refer to Figure 42 and Figure 43 (Slave Serial Interface Modes) External SCLK Setup Time t 5 ns 31 External SCLK Active Edge to SDOUT Delay t 3 18 ns 32 SDIN Setup Time t 5 ns 33 SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t 10 ns 37 1 In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode. Rev. A | Page 5 of 28 AD7674 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t 25 60 120 240 ns 19 Internal SCLK Period Maximum t 40 80 160 320 ns 19 Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t 2 4 30 89 ns 23 SCLK Last Edge to SYNC Delay Minimum t 3 60 140 300 ns 24 Busy High Width Maximum (Warp) t 1.75 2.5 4 7 μs 28 Busy High Width Maximum (Normal) t28 2 2.75 4.25 7.25 μs Busy High Width Maximum (Impulse) t28 2.25 3 4.5 7.5 μs Rev. A | Page 6 of 28 AD7674 ABSOLUTE MAXIMUM RATINGS 1 1.6mA I OL Table 5. AD7674 Absolute Maximum Ratings Parameter Rating Analog Inputs TO OUTPUT 1.4V PIN 2 2 C L IN+ , IN– , REF, REFBUFIN, AGND – 0.3 V to 1 60pF REFGND to AGND AVDD + 0.3 V Ground Voltage Differences I 500μA OH AGND, DGND, OGND ±0.3 V NOTE 1 IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND Supply Voltages SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. L AVDD, DVDD, OVDD –0.3 V to +7 V 03083–0–002 AVDD to DVDD, AVDD to OVDD ±7 V Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK DVDD to OVDD –0.3 V to +7 V Outputs, CL = 10 pF Digital Inputs –0.3 V to DVDD + 0.3 V 3 Internal Power Dissipation 700 mW 2V 4 Internal Power Dissipation 2.5 W 0.8V t Junction Temperature 150°C t DELAY DELAY Storage Temperature Range –65°C to +150°C 2V 2V 0.8V 0.8V Lead Temperature Range 03083–0–003 (Soldering 10 sec) 300°C Figure 3. Voltage Reference Levels for Timing 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional ESD CAUTION operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θ = 30°C/W. JC 4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. Rev. A | Page 7 of 28 AD7674 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 1 36 AGND PIN 1 AVDD 2 35 CNVST INDICATOR MODE0 3 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS AD7674 WARP 6 31 RD TOP VIEW IMPULSE 7 30 DGND (Not to Scale) D1/A0 8 29 BUSY D17 D2/A1 9 28 D3 10 27 D16 D4/DIVSCLK[0] 11 26 D15 D5/DIVSCLK[1] 12 25 D14 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM. Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 44 AGND P Analog Power Ground Pin. 2, 47 AVDD P Input Analog Power Pins. Nominally 5 V. 3 MODE0 DI Data Output Interface Mode Selection. 4 MODE1 DI Data Output Interface Mode Selection: Interface MODE MODE1 MODE0 Description # 0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface 5 D0/OB/2C DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When this input is HIGH and the IMPULSE pin is LOW, WARP selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Conversion Mode Selection. When this input is HIGH and the WARP pin is LOW, IMPULSE selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. When WARP and IMPULSE pins are LOW, the NORMAL mode is selected. 8 D1/A0 DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. Rev. A | Page 8 of 28 D6/EXT/INT 13 48 PDBUF D7/INVSYNC 14 47 AVDD 46 REFBUFIN D8/INVSCLK 15 D9/RDC/SDIN 16 45 NC OGND 17 44 AGND OVDD 18 43 IN+ DVDD 19 42 NC DGND 20 41 NC D10/SDOUT 21 40 NC D11/SCLK 22 39 IN– 38 REFGND D12/SYNC 23 D13/RDERROR 24 37 REF 03083-004 AD7674 1 Pin No. Mnemonic Type Description 9 D2/A1 DI/O When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 10 D3 DO In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5]or DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE = 3 (serial mode), when EXT/INT is LOW and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. 13 D6 or DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. EXT/INT When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D7 or DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus. INVSYNC When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D8 or DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus. INVSCLK When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. 16 D9 or DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus. RDC/SDIN When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3 V. 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D10 or DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus. SDOUT When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on the next rising edge. 22 D11 or DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus. SCLK When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D12 or DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus. SYNC When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D13 or DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus. RDERROR In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. 25–28 D[14:17] DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the interface mode. Rev. A | Page 9 of 28 AD7674 1 Pin No. Mnemonic Type Description 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into hold and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. 38 REFGND AI Reference Input Analog Ground. 39 IN– AI Differential Negative Analog Input. 40–42, NC No Connect. 45 43 IN+ AI Differential Positive Analog Input. 46 REFBUFIN AI Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically when 2.5 V is applied on this pin. 48 PDBUF DI Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off. 49 Exposed Pad The exposed pad is internally connected to AGND. This connection is not required to meet the electrical (EPAD) performances however, for increased reliability of the solder joints, it is recommended that the pad be soldered to the analog ground of the system. 1 AI = Analog Input; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Table 7. Data Bus Interface Definitions MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel 1 0 1 OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word 1 0 1 OB/2C A0:1 R[0] R[1] All Zeros 16-Bit Low Word 2 1 0 OB/2C A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte 2 1 0 OB/2C A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte 2 1 0 OB/2C A0:1 A1:0 All Hi-Z R[0:1] All Zeros 8-Bit LOW Byte 2 1 0 OB/2C A0:1 A1:1 All Hi-Z All Zeros R[0:1] 8-Bit LOW Byte 3 1 1 OB/2C All Hi-Z Serial Interface Serial Interface R[0:17] is the 18-bit ADC value stored in its output register. Rev. A | Page 10 of 28 AD7674 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal, and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Dynamic Range 1½ LSB beyond the last code transition. The deviation is Dynamic range is the ratio of the rms value of the full scale to measured from the middle of each code to the true straight line. the rms noise measured with the inputs shorted together. The Differential Nonlinearity Error (DNL) value for dynamic range is expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-Noise Ratio (SNR) nonlinearity is the maximum deviation from this ideal value. It SNR is the ratio of the rms value of the actual input signal to the is often specified in terms of resolution for which no missing rms sum of all other spectral components below the Nyquist codes are guaranteed. frequency, excluding harmonics and dc. The value for SNR is Gain Error expressed in decibels. The first transition (from 000…00 to 000…01) should occur for Signal-to-(Noise + Distortion) Ratio (S/[N+D]) an analog voltage ½ LSB above the nominal negative full scale S/(N+D) is the ratio of the rms value of the actual input signal (–4.095991 V for the ±4.096 V range). The last transition (from to the rms sum of all other spectral components below the 111…10 to 111…11) should occur for an analog voltage Nyquist frequency, including harmonics but excluding dc. The 1½ LSB below the nominal full scale (4.095977 V for the value for S/(N+D) is expressed in decibels. ±4.096 V range). The gain error is the deviation of the Aperture Delay difference between the actual level of the last transition and the actual level of the first transition from the difference between Aperture delay is a measure of the acquisition performance and the ideal levels. is measured from the falling edge of the input to when CNVST Zero Error the input signal is held for a conversion. The zero error is the difference between the ideal midscale Transient Response input voltage (0 V) from the actual voltage producing the Transient response is the time required for the AD7674 to midscale output code. achieve its rated accuracy after a full-scale step function is Spurious-Free Dynamic Range (SFDR) applied to its input. SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input, and is expressed in bits. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02 Rev. A | Page 11 of 28 AD7674 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.5 –1.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE 03083-0-005 03083-0-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 70000 90000 V = 5V V = 5V REF REF 80000 59121 28939 60000 58556 70000 50000 60000 40000 50000 40000 30000 30000 26939 25964 20000 20000 7165 10000 10000 5073 87 793 0 0 47 0 0 0 1 627 8 0 0 0 2004C2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 2004D 2004E 2004F 20050 20051 20052 20053 20054 20055 CODE IN HEX CODE IN HEX 03083-0-009 03083-0-006 Figure 6. Histogram of 131,072 Conversions of a Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Transition DC Input at the Code Center 100 120 90 100 80 70 80 60 60 50 40 40 30 20 20 10 0 0 0 0.5 1.0 1.5 2.0 –2.5 –2.0 –1.5 1.0 –0.5 0 2.5 NEGATIVE INL (LSB) POSITIVE INL (LSB) 03083-0-010 03083-0-007 Figure 10. Typical Negative INL Distribution (424 Units) Figure 7. Typical Positive INL Distribution (424 Units) Rev. A | Page 12 of 28 INL-LSB (18-Bit) COUNTS NUMBER OF UNITS DNL-LSB (18-Bit) COUNTS NUMBER OF UNITS AD7674 120 250 100 200 80 150 60 100 40 50 20 0 0 0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.5 0 POSITIVE DNL (LSB) NEGATIVE DNL (LSB) 03083-0-011 03083-0-014 Figure 11. Typical Positive DNL Distribution (424 Units) Figure 14. TypicalNegative DNL Distribution (424 Units) 16.5 0 102 f = 800kSPS S f = 10kHz –20 99 IN V = 4.096V 16.0 REF SNR = 98.4dB –40 96 THD = 119.1dB SNR SFDR = 120.4dB –60 15.5 93 SINAD = 98.4dB –80 90 15.0 S/(N+D) –100 87 14.5 –120 84 ENOB –140 81 14.0 –160 78 13.5 –180 75 0 50 100 150 200 250 300 350 400 10 100 1000 1 FREQUENCY (kHz) FREQUENCY (kHz) 03083-0-012 03083-0-015 Figure 12. FFT (10 kHz Tone) Figure 15. SNR, S/(N+D), and ENOB vs. Frequency 140 0 –60 f = 800kSPS S f = 100kHz –20 IN –70 120 V = 4.096V REF SFDR SNR = 98.8dB –40 THD = 104.3dB 100 –80 SFDR = 104.9dB –60 SINAD = 97.8dB 80 –90 –80 THIRD HARMONIC –100 60 –100 THD –120 40 –110 SECOND –140 HARMONIC 20 –120 –160 0 –180 –130 0 50 100 150 200 250 300 350 400 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) 03083-0-013 03083-0-016 Figure 13. FFT (100 kHz Tone) Figure 16. THD, SFDR, and Harmonics vs. Frequency Rev. A | Page 13 of 28 AMPLITUDE (dB of Full Scale) AMPLITUDE (dB of Full Scale) NUMBER OF UNITS THD, HARMONICS (dB) SNR AND S/[N+D] (dB) NUMBER OF UNITS ENOB (Bits) SFDR (dB) AD7674 105 100000 AVDD, WARP/NORMAL V = 4.096V 104 REF 10000 103 DVDD, WARP/NORMAL 1000 102 100 101 AVDD, IMPULSE 100 10 SNR DVDD, IMPULSE S/(N+D) 99 1 98 PDBUF HIGH 0.1 97 OVDD, ALL MODES 0.01 96 95 0.001 –60 –50 –40 –30 –20 –10 0 1 10 100 1k 10k 100k 1M INPUT LEVEL (dB) SAMPLING RATE (SPS) 03083-0-017 03083-0-020 Figure 17. SNR and S/(N+D) vs. Input Level Figure 20. Operating Current vs. Sampling Rate 16.5 100 800 V = 4.096V REF 700 SNR 16.0 99 600 S/(N+D) DVDD ENOB 500 98 15.5 400 AVDD 300 97 15.0 OVDD 100 14.5 96 0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25456585 105 125 TEMPERATURE (°C) TEMPERATURE (°C) 03083-0-021 03083-0-018 Figure 18. SNR, S/(N+D), and ENOB vs. Temperature Figure 21. Power-Down Operating Currents vs. Temperature –100 25 20 15 –110 THD NEGATIVE 10 FULL SCALE 5 –120 THIRD 0 ZERO ERROR HARMONIC –5 SECOND POSITIVE –10 HARMONIC FULL SCALE –130 –15 –20 –140 –25 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) 03083-0-019 03083-0-022 Figure 19. THD and Harmonics vs. Temperature Figure 22. Zero Error, Positive and Negative Full Scale vs. Temperature Rev. A | Page 14 of 28 SNR, S/[N+D] (dB) THD, HARMONICS (dB) SNR REFERRED TO FULL SCALE (dB) OPERATING CURRENTS (μA) ZERO ERROR,POSITIVE AND POWER-DOWN OPERATING CURRENTS (nA) NEGATIVE FULL SCALE (LSB) AD7674 30 50 OVDD = 2.7V @ 85°C 20 40 POSITIVE 10 FULL SCALE 30 0 ZERO ERROR 20 OVDD = 2.7V @ 25°C 10 OVDD = 5V @ 85°C OVDD = 5V @ 25°C 10 20 NEGATIVE FULL SCALE –30 0 4.50 4.75 5.00 5.25 5.50 0 50 100 150 200 AVDD (V) C (pF) L 03083-0-023 03083-0-024 Figure 23. Zero Error, Positive and Negative Full Scale vs. Supply Figure 24. Typical Delay vs. Load Capacitance C L Rev. A | Page 15 of 28 ZERO ERROR,POSITIVE AND NEGATIVE FULL SCALE (LSB) t DELAY (ns) 12 AD7674 CIRCUIT INFORMATION IN+ SWITCHES CONTROL SW+ MSB LSB 262,144C 131,072C 4C 2C C C BUSY REF CONTROL COMP LOGIC OUTPUT REFGND CODE 4C 2C C C 262,144C 131,072C LSB MSB SW– CNVST 03083–0–025 IN– Figure 25. ADC Simplified Schematic The AD7674 is a very fast, low power, single-supply, precise arrays are then disconnected from the inputs and connected to 18-bit analog-to-digital converter (ADC) using successive the REFGND input. Therefore, the differential voltage between approximation architecture. the IN+ and IN– inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the The AD7674’s linearity and dynamic range are similar to or comparator to become unbalanced. By switching each element better than many Σ-Δ ADCs. With the advantages of its of the capacitor array between REFGND and REF, the successive architecture, which ease multiplexing and reduce comparator input varies by binary weighted voltage steps power with throughput, it can be advantageous in applications (V /2, V /4, ... V /262144). The control logic toggles these REF REF REF that normally use Σ-Δ ADCs. switches, starting with the MSB first, to bring the comparator The AD7674 features different modes to optimize performance back into a balanced condition. After completing this process, according to the applications. In Warp mode, the AD7674 is the control logic generates the ADC output code and brings the capable of converting 800,000 samples per second (800 kSPS). BUSY output low. The AD7674 provides the user with an on-chip track/hold, Modes of Operation successive approximation ADC that does not exhibit any The AD7674 features three modes of operation: Warp, Normal, pipeline or latency, making it ideal for multiple multiplexed and Impulse. Each mode is more suited for specific applications. channel applications. Warp mode allows conversion rates up to 800 kSPS. However, The AD7674 can be operated from a single 5 V supply and can in this mode and this mode only, the full specified accuracy is be interfaced to either 5 V or 3 V digital logic. It is housed in a guaranteed only when the time between conversions does not 48-lead LQFP, or a tiny 48-lead LFCSP package that offers space exceed 1 ms. If the time between two consecutive conversions is savings and allows for flexible configurations as either a serial longer than 1 ms (e.g., after power-up), the first conversion or parallel interface. The AD7674 is a pin-to-pin compatible result should be ignored. This mode makes the AD7674 ideal upgrade of the AD7676, AD7678, and AD7679. for applications where a fast sample rate is required. CONVERTER OPERATION Normal mode is the fastest mode (666 kSPS) without any The AD7674 is a successive approximation ADC based on a limitation on the time between conversions. This mode makes charge redistribution DAC. Figure 25 shows the simplified the AD7674 ideal for asynchronous applications such as data schematic of the ADC. The capacitive DAC consists of two acquisition systems, where both high accuracy and fast sample identical arrays of 18 binary weighted capacitors that are rate are required. connected to the two comparator inputs. Impulse mode, the lowest power dissipation mode, allows During the acquisition phase, terminals of the array tied to the power saving between conversions. The maximum throughput comparator’s input are connected to AGND via SW+ and SW–. in this mode is 570 kSPS. When operating at 1 kSPS, for All independent switches are connected to the analog inputs. example, it typically consumes only 136 μW. This feature makes Thus, the capacitor arrays are used as sampling capacitors and the AD7674 ideal for battery-powered applications. acquire the analog signal on the IN+ and IN– inputs. When the acquisition phase is complete and the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW– are opened first. The two capacitor Rev. A | Page 16 of 28 AD7674 Transfer Functions Table 8. Output Codes and Ideal Input Voltages Straight Twos Except in 18-bit interface mode, the AD7674 offers straight Analog Input Binary Complement binary and twos complement output coding when using OB/2C. Description VREF = 4.096 V (Hex) (Hex) See Figure 26 and Table 8 for the ideal transfer characteristic. 1 1 FSR – 1 LSB 4.095962 V 3FFFF 1FFFF FSR – 2 LSB 4.095924 V 3FFFE 1FFFE Midscale + 1 LSB 31.25 μV 20001 00001 111...111 111...110 Midscale 0 V 20000 00000 111...101 Midscale – 1 LSB –31.25 μV 1FFFF 3FFFF –FSR + 1 LSB –4.095962 V 00001 20001 2 2 –FSR –4.096 V 00000 20000 1 This is also the code for overrange analog input (V – V IN+ IN– 000...010 above VREF – VREFGND). 2 This is also the code for underrange analog input (V – V 000...001 IN+ IN– below –VREF + VREFGND). 000...000 –FS –FS + 1 LSB +FS – 1 LSB –FS + 0.5 LSB +FS – 1.5 LSB ANALOG INPUT 03083-0-026 Figure 26. ADC Ideal Transfer Function DVDD ANALOG 20Ω DIGITAL SUPPLY SUPPLY NOTE 5 (3.3V OR 5V) (5V) + + + 100nF 10μF 10μ F 100nF 100nF 10μ F ADR421 AVDD AGND DGND DVDD OVDD OGND REFBUFIN SERIAL PORT 2.5V REF SCLK 1MΩ 50kΩ 100nF NOTE 1 100nF SDOUT NOTE 2 REF C REF BUSY 47μF NOTE 1 μC/μP/DSP REFGND 50Ω CNVST D 50Ω NOTE 6 – 15Ω NOTE 3 MODE1 U1 IN+ AD7674 ANALOG INPUT+ + MODE0 OB/2C DVDD C 2.7nF C AD8021 NOTE 4 PDBUF CLOCK 50Ω CS RD – 15Ω NOTE 3 U2 IN– RESET ANALOG INPUT– + PD C 2.7nF C AD8021 NOTE 4 NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. SEE ANALOG INPUTS SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 03083-0-027 Figure 27. Typical Connection Diagram (Internal Reference Buffer, Serial Interface) Rev. A | Page 17 of 28 ADC CODE (Straight Binary) AD7674 and the on resistance of the switches. C is typically 60 pF and TYPICAL CONNECTION DIAGRAM S mainly consists of the ADC sampling capacitor. This 1-pole Figure 27 shows a typical connection diagram for the AD7674. filter with a –3 dB cutoff frequency of 26 MHz typ reduces any Different circuitry shown on this diagram is optional and is undesirable aliasing effect and limits the noise coming from the discussed later in this data sheet. inputs. Analog Inputs Because the input impedance of the AD7674 is very high, the Figure 28 shows a simplified analog input section of the part can be driven directly by a low impedance source without AD7674. The diodes shown in Figure 28 provide ESD gain error. This allows the user to put an external 1-pole RC protection for the inputs. Care must be taken to ensure that the filter between the amplifier output and the ADC analog inputs, analog input signal never exceeds the absolute ratings on these as shown in Figure 27, to improve the noise filtering done by inputs. This will cause these diodes to become forward biased the AD7674 analog input circuit. However, the source and start conducting current. These diodes can handle a impedance has to be kept low because it affects the ac forward-biased current of 120 mA max. This condition could performance, especially the total harmonic distortion (THD). eventually occur when the input buffer’s U1 or U2 supplies are The maximum source impedance depends on the amount of different from AVDD. In such a case, an input buffer with a THD that can be tolerated. The THD degrades as a function of short-circuit current limitation can be used to protect the part. source impedance and the maximum input frequency, as shown AVDD in Figure 30. –95 R+ = 102Ω 20kHz IN+ –100 C S C S IN– –105 R– = 102Ω 10kHz –110 AGND 03083-0-028 2kHz Figure 28. Simplified Analog Input –115 This analog input structure is a true differential structure. By using these differential inputs, signals common to both inputs –120 15 45 75 105 are rejected as shown in Figure 29, which represents typical INPUT RESISTANCE (Ω) 03083-0-030 CMRR over frequency. Figure 30. THD vs. Analog Input Frequency and Source Resistance 66 Driver Amplifier Choice 64 Although the AD7674 is easy to drive, the driver amplifier needs to meet the following requirements: 62 • The driver amplifier and the AD7674 analog input circuit 60 have to be able to settle for a full-scale step of the capacitor 58 array at an 18-bit level (0.0004%). In the amplifier’s data sheet, settling at 0.1% or 0.01% is more commonly 56 specified. This could differ significantly from the settling 54 time at an 18-bit level and, therefore, should be verified prior to driver selection. The tiny op amp AD8021, which 52 combines ultralow noise and high gain-bandwidth, meets 50 this settling time requirement. 110 100 1000 10000 FREQUECY (kHz) 03083-0-029 • The noise generated by the driver amplifier needs to be Figure 29. Analog Input CMRR vs. Frequency kept as low as possible in order to preserve the SNR and transition noise performance of the AD7674. The noise During the acquisition phase for ac signals, the AD7674 coming from the driver is filtered by the AD7674 analog behaves like a 1-pole RC filter consisting of the equivalent input circuit 1-pole low-pass filter made by R+, R–, and CS. resistance R+, R–, and CS. The resistors R+ and R– are typically The SNR degradation due to the amplifier is 102 Ω and are lumped components made up of a serial resistor Rev. A | Page 18 of 28 CMRR (dB) THD (dB) AD7674 ⎛ ⎞ Voltage Reference ⎜ ⎟ 25 ⎜ ⎟ SNRLOSS= 20 log The AD7674 allows the use of an external voltage reference ⎜ ⎟ 2 ⎜ ⎟ f ⎜ 625+π (Ne ) ⎟ either with or without the internal reference buffer. N –3dB ⎝ ⎠ Using the internal reference buffer is recommended when where: sharing a common reference voltage between multiple ADCs is f is the –3 dB input bandwidth in MHz of the AD7674 –3dB desired. (26 MHz) or the cutoff frequency of the input filter, if used. However, the advantages of using the external reference voltage N is the noise factor of the amplifiers (1 if in buffer directly are: configuration). • The SNR and dynamic range improvement (about 1.7 dB) eN is the equivalent input noise voltage of each op amp in resulting from the use of a reference voltage very close to nV/√Hz. the supply (5 V) instead of a typical 4.096 V reference For instance, for a driver with an equivalent input noise of when the internal buffer is used 2 nV/√Hz (e.g., AD8021) configured as a buffer, thus with • The power saving when the internal reference buffer is a noise gain of +1, the SNR degrades by only 0.34 dB with powered down (PDBUF High) the filter in Figure 27, and by 1.8 dB without it. To use the internal reference buffer, PDBUF should be LOW. A • The driver needs to have a THD performance suitable to 2.5 V reference voltage applied on the REFBUFIN input will that of the AD7674. result in a 4.096 V reference on the REF pin. The AD8021 meets these requirements and is usually In both cases, the voltage reference input REF has a dynamic appropriate for almost all applications. The AD8021 needs a input impedance and therefore requires an efficient decoupling 10 pF external compensation capacitor, which should have good between REF and REFGND inputs, The decoupling consists of linearity as an NPO ceramic or mica type. a low ESR 47 μF tantalum capacitor connected to the REF and The AD8022 could be used if a dual version is needed and gain REFGND inputs with minimum parasitic inductance. of 1 is present. The AD829 is an alternative in applications Care should also be taken with the reference temperature where high frequency (above 100 kHz) performance is not coefficient of the voltage reference, which directly affects the required. In gain of 1 applications, it requires an 82 pF full-scale accuracy if this parameter matters. For instance, a compensation capacitor. The AD8610 is another option when ±4 ppm/°C temperature coefficient of the reference changes the low bias current is needed in low frequency applications. full scale by ±1 LSB/°C. Single-to-Differential Driver Power Supply For applications using unipolar analog signals, a single-ended- The AD7674 uses three sets of power supply pins: an analog 5 V to-differential driver will allow for a differential input into the supply (AVDD), a digital 5 V core supply (DVDD), and a digital part. The schematic is shown in Figure 31. When provided an output interface supply (OVDD). The OVDD supply defines input signal of 0 to VREF, this configuration will produce a the output logic level and allows direct interface with any logic differential ±VREF with midscale at VREF/2. working between 2.7 V and DVDD + 0.3 V. To reduce the If the application can tolerate more noise, the AD8138 number of supplies needed, the digital core (DVDD) can be differential driver can be used. supplied through a simple RC filter from the analog supply, as shown in Figure 27. The AD7674 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is therefore free from supply voltage U1 ANALOG INPUT induced latch-up. Additionally, it is very insensitive to power AD8021 (UNIPOLAR 0V TO 4.096V) 10pF supply variations over a wide frequency range, as shown in Figure 32. 590Ω 15Ω IN+ 590Ω 2.7nF AD7674 15Ω IN– U2 1.82kΩ REF REFBUFIN 2.7nF AD8021 10μF 100nF 10pF 8.25kΩ 2.5V 03083-0-031 Figure 31. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) Rev. A | Page 19 of 28 AD7674 70 t 2 t 1 CNVST 65 60 BUSY t 4 t 3 t 55 6 t 5 MODE ACQUIRE CONVERT ACQUIRE CONVERT 50 t t 7 8 03083-0-034 45 Figure 34. Basic Conversion Timing 40 Although CNVST is a digital signal, it should be designed with 110 100 1000 10000 FREQUECY (kHz) special care with fast, clean edges and levels with minimum 03083-0-032 overshoot and undershoot or ringing. Figure 32. PSRR vs. Frequency For applications where SNR is critical, the signal should CNVST have very low jitter. This may be achieved by using a dedicated POWER DISSIPATION VERSUS THROUGHPUT oscillator for generation, or to clock it with a high CNVST In Impulse mode, the AD7674 automatically reduces its power frequency low jitter clock, as shown in Figure 27. consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which In Impulse mode, conversions can be initiated automatically. If allows for a significant power savings when the conversion rate CNVST is held low when BUSY goes low, the AD7674 controls is reduced, as shown in Figure 33. This feature makes the the acquisition phase and automatically initiates a new AD7674 ideal for very low power battery applications. It should conversion. By keeping low, the AD7674 keeps the CNVST be noted that the digital interface remains active even during conversion process running by itself. Note that the analog input the acquisition phase. To reduce the operating digital supply has to be settled when BUSY goes low. Also, at power-up, currents even further, the digital inputs need to be driven close should be brought low once to initiate the conversion CNVST to the power rails (DVDD and DGND), and OVDD should not process. In this mode, the AD7674 could sometimes run exceed DVDD by more than 0.3 V. slightly faster than the guaranteed limits of 570 kSPS in Impulse 1000000 mode. This feature does not exist in Warp or Normal modes. WARP/NORMAL 100000 DIGITAL INTERFACE The AD7674 has a versatile digital interface; it can be interfaced 10000 with the host system by using either a serial or parallel interface. 1000 The serial interface is multiplexed on the parallel data bus. The AD7674 digital interface also accommodates both 3 V and 5 V 100 logic by simply connecting the AD7674’s OVDD supply pin to IMPULSE the host system interface digital supply. Finally, by using the 10 PDBUF HIGH input pin in any mode but 18-bit interface mode, both OB/2C 1 twos complement and straight binary coding can be used. The two signals, and , control the interface. When at least CS RD 0.1 1 100 1k 10k 100k 1M 10 one of these signals is high, the interface outputs are in high SAMPLING RATE (SPS) 03083-0-033 impedance. Usually, CS allows the selection of each AD7674 in Figure 33. Power Dissipation vs. Sample Rate multicircuit applications, and is held low in a single AD7674 design. is generally used to enable the conversion result on RD CONVERSION CONTROL the data bus. Figure 34 shows the detailed timing diagrams of the conversion process. The AD7674 is controlled by the signal, which CNVST initiates conversion. Once initiated, it cannot be restarted or aborted, even by PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. Rev. A | Page 20 of 28 POWER DISSAPATION (μW) PSRR (dB) AD7674 CS = 0 t 9 t 1 RESET CNVST, RD BUSY t 4 BUSY t 3 PREVIOUS DATA BUS CONVERSION DATA t t BUS 12 13 03083-0-038 t 8 Figure 38. Slave Parallel Data Timing for Reading (Read during Convert) CNVST 03083-0-035 CS Figure 35. RESET Timing RD CS = RD = 0 t 1 CNVST A0, A1 t 10 HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE t BUSY 4 t t t 12 12 13 t 3 HI-Z HI-Z t 11 LOW BYTE HIGH BYTE PINS D[7:0] DATA 03083-0-039 PREVIOUS CONVERSION DATA NEW DATA BUS Figure 39. 8-Bit and 16-Bit Parallel Interface 03083-0-036 SERIAL INTERFACE Figure 36. Master Parallel Data Timing for Reading (Continuous Read) The AD7674 is configured to use the serial interface when MODE0 and MODE1 are held high. The AD7674 outputs 18 PARALLEL INTERFACE bits of data, MSB first, on the SDOUT pin. This data is The AD7674 is configured to use the parallel interface with an synchronized with the 18 clock pulses provided on the SCLK 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The pin. The output data is valid on both the rising and falling edge data can be read either after each conversion, which is during of the data clock. the next acquisition phase, or during the following conversion, as shown in Figure 37 and Figure 38, respectively. When the MASTER SERIAL INTERFACE data is read during the conversion, however, it is recommended Internal Clock that it is read only during the first half of the conversion phase. The AD7674 is configured to generate and provide the serial This avoids any potential feedthrough between voltage data clock SCLK when the EXT/INT pin is held low. The transients on the digital interface and the most critical analog AD7674 also generates a SYNC signal to indicate to the host conversion circuitry. Refer to Table 7 for a detailed description when the serial data is valid. The serial clock SCLK and the of the different options available. SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or CS during the following conversion. Figure 40 and Figure 41 show the detailed timing diagrams of these two modes. RD Usually, because the AD7674 is used with a fast throughput, the BUSY Master Read during Conversion mode is the most recommended serial mode. DATA CURRENT BUS CONVERSION In Read during Conversion mode, the serial clock and data t t 12 13 toggle at appropriate instants, minimizing potential 03083-0-037 feedthrough between digital activity and critical conversion Figure 37. Slave Parallel Data Timing for Reading (Read after Convert) decisions. Rev. A | Page 21 of 28 AD7674 In Read after Conversion mode, it should be noted that unlike To accommodate slow digital hosts, the serial clock can be in other modes, the BUSY signal returns low after the 18 data slowed down by using DIVSCLK. bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SCLK t 15 t 27 X D17 D16 D2 D1 D0 SDOUT t t 16 23 t 22 03083-0-040 Figure 40. Master Serial Data Timing for Reading (Read after Convert) RDC/SDIN = 1 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 16 17 18 t 18 t 27 X D17 D16 D2 D1 D0 SDOUT t t 23 16 t 22 03083-0-046 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) during the following conversion. The external clock can be SLAVE SERIAL INTERFACE either a continuous or a discontinuous clock. A discontinuous External Clock clock can be either normally high or normally low when The AD7674 is configured to accept an externally supplied inactive. Figure 42 and Figure 43 show the detailed timing serial data clock on the SCLK pin when the EXT/INT pin is diagrams of these methods. held high. In this mode, several methods can be used to read While the AD7674 is performing a bit decision, it is important the data. The external serial clock is gated by . When and CS CS that voltage transients not occur on digital input/output pins or RD are both low, the data can be read after each conversion or Rev. A | Page 22 of 28 AD7674 degradation of the conversion result could occur. This is Among the advantages of this method, the conversion particularly important during the second half of the conversion performance is not degraded because there are no voltage phase because the AD7674 provides error correction circuitry transients on the digital interface during the conversion process. that can correct for an improper bit decision made during the Also, data can be read at speeds up to 40 MHz, accommodating first half of the conversion phase. For this reason, it is both slow digital host interface and the fastest serial reading. recommended that when an external clock is being provided, it Finally, in this mode only, the AD7674 provides a daisy-chain is a discontinuous clock that only toggles when BUSY is low or, feature using the RDC/SDIN input pin to cascade multiple more importantly, that it does not transition during the latter converters together. This feature is useful for reducing half of BUSY high. component count and wiring connections when desired (for External Discontinuous Clock Data Read after instance, in isolated multiconverter applications). Conversion An example of the concatenation of two devices is shown in Though maximum throughput cannot be achieved using this Figure 44. Simultaneous sampling is possible by using a mode, it is the most recommended of the serial slave modes. common CNVST signal. It should be noted that the RDC/SDIN Figure 42 shows the detailed timing diagrams of this method. input is latched on the edge of SCLK opposite the one used to After a conversion is complete, indicated by BUSY returning shift out data on SDOUT. Thus, the MSB of the upstream low, the result of this conversion can be read while both CS and converter follows the LSB of the downstream converter on the RD are low. Data is shifted out MSB first with 18 clock pulses, next SCLK cycle. and is valid on the rising and falling edge of the clock. EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 16 17 18 19 20 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 X17 X16 t 16 t 34 SDIN X17 X16 X15 X1 X0 Y17 Y16 t 33 03083-0-042 Figure 42. Slave Serial Data Timing for Reading (Read after Convert) Rev. A | Page 23 of 28 AD7674 INVSCLK = 0 EXT/INT = 1 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 16 17 18 t 31 t 32 SDOUT X D17 D16 D15 D1 D0 t 16 03083-0-043 Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) BUSY The AD7674 is designed to interface either with a parallel 8-bit OUT or 16-bit wide interface, or with a general-purpose serial port or BUSY BUSY I/O ports on a microcontroller. A variety of external buffers can AD7674 AD7674 be used with the AD7674 to prevent digital noise from coupling #2 (UPSTREAM) #1 (DOWNSTREAM) into the ADC. The following section illustrates the use of the DATA AD7674 with an SPI equipped DSP, the ADSP-219x. RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST SPI Interface (ADSP-219x) CS CS SCLK SCLK Figure 45 shows an interface diagram between the AD7674 and the SPI equipped ADSP-219x. To accommodate the slower SCLK IN CS IN speed of the DSP, the AD7674 acts as a slave device, and data CNVST IN 03083-0-044 must be read after conversion. This mode also allows the daisy- chain feature. The convert command could be initiated in Figure 44. Two AD7674s in a Daisy-Chain Configuration response to an internal timer interrupt. The 18-bit output data are read with 3-byte SPI access. The reading process could be External Clock Data Read during Conversion initiated in response to the end-of-conversion signal (BUSY Figure 43 shows the detailed timing diagrams of this method. going low) using an interrupt line of the DSP. The serial During a conversion, while both CS and RD are low, the result interface (SPI) on the ADSP-219x is configured for master of the previous conversion can be read. The data is shifted out mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase MSB first with 18 clock pulses, and is valid on both the rising Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by and falling edge of the clock. The 18 bits have to be read before writing to the SPI Control register (SPICLTx). It should be the current conversion is complete. If that is not done, noted that to meet all timing requirements, the SPI clock should RDERROR is pulsed high and can be used to interrupt the host be limited to 17 Mbps, which allows it to read an ADC result in interface to prevent incomplete data reading. There is no daisy- about 1.1 μs. When a higher sampling rate is desired, use of one chain feature in this mode, and the RDC/SDIN input should of the parallel interface modes is recommended. always be tied either high or low. DVDD To reduce performance degradation due to digital activity, a fast 1 1 AD7674 ADSP-219x discontinuous clock is recommended to ensure that all bits are MODE0/MODE1 read during the first half of the conversion phase. It is also EXT/INT possible to begin to read the data after conversion and continue BUSY PFx to read the last bits even after a new conversion has been SPIxSEL (PFx) CS RD initiated. SDOUT MISOx SCLK SCKx INVSCLK MICROPROCESSOR INTERFACING CNVST PFx OR TFSx The AD7674 is ideally suited for traditional dc measurement 1 ADDITIONAL PINS OMITTED FOR CLARITY. applications supporting a microprocessor, and for ac signal Figure 45. Interfacing the AD7674 to an SPI Interface processing applications interfacing to a digital signal processor. Rev. A | Page 24 of 28 03083-045 AD7674 APPLICATION HINTS interface digital supply OVDD and the remaining digital LAYOUT circuitry. When DVDD is powered from the system supply, it is The AD7674 has very good immunity to noise on the power useful to insert a bead to further reduce high frequency spikes. supplies. However, care should still be taken with regard to The AD7674 has four different ground pins: REFGND, AGND, grounding layout. DGND, and OGND. REFGND senses the reference voltage and The printed circuit board that houses the AD7674 should be should be a low impedance return to the reference because it designed so that the analog and digital sections are separated carries pulsed currents. AGND is the ground to which most and confined to certain areas of the board. This calls for the use internal ADC analog signals are referenced. This ground must of ground planes, which can be easily separated. Digital and be connected with the least resistance to the analog ground analog ground planes should be joined in only one place, plane. DGND must be tied to the analog or digital ground plane preferably underneath the AD7674, or at least as close to the depending on the configuration. OGND is connected to the AD7674 as possible. If the AD7674 is in a system where digital system ground. multiple devices require analog-to-digital ground connections, The layout of the decoupling of the reference voltage is the connection should still be made at one point only, a star important. The decoupling capacitor should be close to the ground point that should be established as close to the AD7674 ADC and should be connected with short and large traces to as possible. minimize parasitic inductances. The user should avoid running digital lines under the device, as EVALUATING THE AD7674’S PERFORMANCE these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7674 to avoid noise An evaluation board for the AD7674 allows a quick means to coupling. Fast switching signals like or clocks should be CNVST measure both DC (histograms and time domain) and AC (time shielded with digital ground to avoid radiating noise to other and frequency domain) performances of the converter. The sections of the board, and should never run near analog signal EVAL-AD7674CBZ is an evaluation board package that paths. Crossover of digital and analog signals should be includes a fully assembled and tested evaluation board, avoided. Traces on different but close layers of the board should documentation, and software. The accompanying software run at right angles to each other. This will reduce the effect of requires the use of a capture board which must be ordered seperately from the evaluation board (see the Ordering Guide feedthrough through the board. The power supply lines to the for information). The evaluation board can also be used in a AD7674 should use as large a trace as possible to provide low stand alone configuration and does not use the software when impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the in this mode. Refer to the EVAL-AD76XXEDZ and EVAL- supply’s impedance presented to the AD7674 and to reduce the AD76XXCBZ documents available from www.analog.com for magnitude of the supply spikes. Decoupling ceramic capacitors, evaluation board details. typically 100 nF, should be placed close to and ideally right up Two types of data capture boards can be used with the EVAL- against each power supply pin (AVDD, DVDD, and OVDD) AD7674CBZ: and their corresponding ground pins. Additionally, low ESR • USB based (EVAL-CED1Z recommended) 10 μF capacitors should be located near the ADC to further reduce low frequency ripple. • Parallel port based (EVAL-CONTROL BRD3Z not recommended as many newer PC’s do not include parallel The DVDD supply of the AD7674 can be a separate supply or ports any longer) can come from the analog supply, AVDD, or the digital interface supply, OVDD. When the system digital supply is The recommended board layout for the AD7674 is outlined in noisy or when fast switching digital signals are present, and if the evaluation board data sheet. no separate supply is available, the user should connect the DVDD digital supply to the analog supply AVDD through an RC filter, (see Figure 27), and connect the system supply to the Rev. A | Page 25 of 28 AD7674 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 37 48 1 36 PIN 1 SEATING 10° PLANE TOP VIEW 7.00 1.45 6° 0.20 (PINS DOWN ) BSC SQ 2° 1.40 0.09 1.35 VIEW A 7° 3.5° 12 25 0.15 0° 24 13 SEATING 0.05 0.10 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 46. 48-Lead Low Profile Quad Flat Package (LQFP) (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED 5.25 TOP 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 0.40 12 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS 0.50 BSC SECTION OF THIS DATA SHEET. 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 47. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7674ASTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD7674ASTZL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD7674ACPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48 AD7674ACPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48 2 EVAL-AD7674CBZ Evaluation Board 3 EVAL-CED1Z USB Data Capture Board 3 EVAL-CONTROL BRD2Z Parallel Port Capture Board, 32k RAM 3 EVAL-CONTROL BRD3Z Parallel Port Capture Board, 128k RAM 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with a capture board for evaluation/demonstration purposes. 3 These capture boards allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL BRDxZ (x = 2, 3) Rev. A | Page 26 of 28 080108-A AD7674 NOTES Rev. A | Page 27 of 28 AD7674 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03083-0-6/09(A) Rev. A | Page 28 of 28