ANALOG DEVICES AD7666

® 16-Bit 500 kSPS PulSAR Unipolar ADC with Reference AD7666 FUNCTIONAL BLOCK DIAGRAM FEATURES REFBUFIN REF REFGND DVDD DGND 2.5 V internal reference: typical drift 3 ppm/°C Guaranteed max drift 15 ppm/°C OVDD AGND AD7666 Throughput: 500 kSPS AVDD OGND SERIAL REF INL: ±2.0 LSB max (±0.0038% of full scale) PORT 16 16-bit resolution with no missing codes IN SWITCHED DATA[15:0] CAP DAC S/(N+D): 88 dB min @ 20 kHz INGND BUSY PARALLEL THD: –96 dB max @ 20 kHz PDREF INTERFACE RD PDBUF Analog input voltage range: 0 V to 2.5 V CLOCK CS PD Both AC and DC specifications CONTROL LOGIC AND SER/PAR RESET CALIBRATION CIRCUITRY No pipeline delay OB/2C Parallel and serial 5 V/3 V interface BYTESWAP TM TM SPI®/QSPI /MICROWIRE /DSP compatible CNVST Single 5 V supply operation Figure 1. Functional Block Diagram Power dissipation 66 mW typ, 132 µW @ 1 kSPS without REF Table 1. PulSAR Selection 81 mW typ with REF 800– 48-lead LQFP and 48-lead LFCSP packages Type/kSPS 100–250 500–570 1000 Pin-to-pin compatible with PulSAR ADCs Pseudo- AD7651 AD7650/AD7652 AD7653 Differential AD7660/AD7661 AD7664/AD7666 AD7667 APPLICATIONS True Bipolar AD7663 AD7665 AD7671 Data acquisition True AD7675 AD7676 AD7677 Medical instruments Differential Digital signal processing 18-Bit AD7678 AD7679 AD7674 Spectrum analysis Multichannel/ AD7654 Simultaneous Instrumentation AD7655 Battery-powered systems Process control PRODUCT HIGHLIGHTS 1. Fast Throughput. The AD7666 is a 500 kSPS, charge redistribution, 16-bit GENERAL DESCRIPTION SAR ADC with internal error correction circuitry. The AD7666 is a 16-bit, 500 kSPS, charge redistribution SAR 2. Superior INL. analog-to-digital converter that operates from a single 5 V The AD7666 has a maximum integral nonlinearity of power supply. The part contains a high speed, 16-bit sampling 2.0 LSB with no missing 16-bit codes. ADC, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system inter- 3. Internal Reference. face ports. The AD7666 is hardware factory-calibrated and The AD7666 has an internal reference with a typical comprehensively tested to ensure ac parameters such as signal- temperature drift of 3 ppm/°C. to-noise ratio (SNR) and total harmonic distortion (THD), in 4. Single-Supply Operation. addition to the more traditional dc parameters of gain, offset, The AD7666 operates from a single 5 V supply. Its power and linearity. dissipation decreases with throughput. The AD7666 is available in a 48-lead LQFP and a tiny 48-lead 5. Serial or Parallel Interface. LFCSP, with operation specified from –40°C to +85°C. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03034-0-001 AD7666 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Interface.......................................................................... 22 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 22 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 22 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 23 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 24 Definitions of Specifications ......................................................... 11 Microprocessor Interfacing....................................................... 26 Typical Performance Characteristics ........................................... 12 Application Hints ........................................................................... 27 Circuit Information........................................................................ 16 Bipolar and Wider Input Ranges.............................................. 27 Converter Operation.................................................................. 16 Layout .......................................................................................... 27 Typical Connection Diagram ................................................... 18 Evaluating the AD7666’s Performance .................................... 27 Power Dissipation versus Throughput .................................... 20 Outline Dimensions ....................................................................... 28 Conversion Control.................................................................... 21 Ordering Guide .......................................................................... 28 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7666 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V 0 V V IN INGND REF Operating Input Voltage VIN –0.1 +3 V VINGND –0.1 +0.5 V Analog Input CMRR fIN = 10 kHz 65 dB Input Current 500 kSPS Throughput 7.7 µA 1 Input Impedance THROUGHPUT SPEED Complete Cycle 2 µs Throughput Rate 0 500 kSPS DC ACCURACY 2 Integral Linearity Error –2.0 +2.0 LSB No Missing Codes 16 Bits Differential Linearity Error –1.0 +1.5 LSB Transition Noise 0.7 LSB 3 Unipolar Zero Error, TMIN to TMAX ±5 LSB Unipolar Zero Error Temperature Drift ±0.5 ppm/°C 3 Full-Scale Error, T to T REF = 2.5 V ±0.08 % of FSR MIN MAX Full-Scale Error Temperature Drift ±1.4 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB AC ACCURACY 4 Signal-to-Noise f = 20 kHz 88 89.2 dB IN Spurious Free Dynamic Range fIN = 20 kHz 96 107 dB Total Harmonic Distortion fIN = 20 kHz –106 –96 dB Signal-to-(Noise + Distortion) fIN = 20 kHz 88 89.1 dB –60 dB Input, f = 20 kHz 30 dB IN –3 dB Input Bandwidth 12 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 750 ns REFERENCE Internal Reference Voltage VREF @ 25°C 2.493 2.5 2.507 V Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C Output Voltage Hysteresis –40°C to +85°C 50 ppm Long Term Drift 100 ppm/1000 Hours Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Turn-On Settling Time C = 10 µF 5 ms REF Temperature Pin Voltage Output @ 25°C 300 mV Temperature Sensitivity 1 mV/°C Output Resistance 4 kΩ External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 500 kSPS Throughput 120 µA Rev. 0 | Page 3 of 28 AD7666 Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL VIH 2.0 DVDD + 0.3 V IIL –1 +1 µA IIH –1 +1 µA DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK V I = –500 µA OVDD – 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 5.25 V Operating Current 500 kSPS Throughput 8 AVDD With Reference and Buffer 12.2 mA 9 AVDD Reference and Buffer Alone 3 mA 10 DVDD 4.1 mA 10 OVDD 102 µA 8, 10 Power Dissipation without REF 500 kSPS Throughput 66 75 mW 1 kSPS Throughput 132 µW 8, 10 Power Dissipation with REF 500 kSPS Throughput 81 90 mW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Input section. 2 LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. 3 See the Definitions of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or Serial 16-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 9 With PDREF, PDBUF LOW and PD HIGH. 10 Tested in parallel reading mode. 11 Consult factory for extended temperature range. Rev. 0 | Page 4 of 28 AD7666 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit Refer to Figure 33 and Figure 34 Convert Pulse Width t 10 ns 1 Time between Conversions t 2 µs 2 CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.25 µs Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 1.25 µs 7 Acquisition Time t8 750 ns RESET Pulse Width t9 10 ns Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 12 ns Bus Access Request to DATA Valid t 45 ns 12 Bus Relinquish Time t 5 15 ns 13 1 Refer to Figure 39 and Figure 40 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay 10 ns t14 1 CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t 525 ns 17 SYNC Asserted to SCLK First Edge Delay t 3 ns 18 2 Internal SCLK Period t 25 40 ns 19 2 Internal SCLK HIGH t20 12 ns 2 Internal SCLK LOW t21 7 ns 2 SDOUT Valid Setup Time t22 4 ns 2 SDOUT Valid Hold Time t 2 ns 23 2 SCLK Last Edge to SYNC Delay t 3 ns 24 CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns 2 BUSY HIGH in Master Serial Read after Convert t28 See Table 4 CNVST LOW to SYNC Asserted Delay t 1.25 µs 29 SYNC Deasserted to BUSY LOW Delay t 25 ns 30 1 Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes) External SCLK Setup Time t 5 ns 31 External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t 25 ns 35 External SCLK HIGH t 10 ns 36 External SCLK LOW t 10 ns 37 1 In serial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Rev. 0 | Page 5 of 28 AD7666 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns Internal SCLK Period Minimum t 25 50 100 200 ns 19 Internal SCLK Period Maximum t 40 70 140 280 ns 19 Internal SCLK HIGH Minimum t 12 22 50 100 ns 20 Internal SCLK LOW Minimum t21 7 21 49 99 ns SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns SDOUT Valid Hold Time Minimum t 2 4 30 80 ns 23 SCLK Last Edge to SYNC Delay Minimum t 3 55 130 290 ns 24 BUSY HIGH Width Maximum t 2 2.5 3.5 5.75 µs 24 Rev. 0 | Page 6 of 28 AD7666 ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7666 Stress Ratings 1.6mA I OL Parameter Rating 2 2 IN , TEMP , REF, REFBUFIN, INGND, AVDD + 0.3 V to TO OUTPUT REFGND to AGND AGND – 0.3 V 1.4V PIN C L Ground Voltage Differences 60pF* AGND, DGND, OGND ±0.3 V I 500µA OH Supply Voltages *IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND AVDD, DVDD, OVDD –0.3 V to +7 V SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD AVDD to DVDD, AVDD to OVDD ±7 V C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. L DVDD to OVDD –0.3 V to +7 V Figure 2. Load Circuit for Digital Interface Timing, Digital Inputs –0.3 V to DVDD + 0.3 V SDOUT, SYNC, SCLK Outputs C = 10 pF L 3 PDREF, PDBUF ±20 mA 4 Internal Power Dissipation 700 mW 5 Internal Power Dissipation 2.5 W 2V Junction Temperature 150°C 0.8V t t Storage Temperature Range –65°C to +150°C DELAY DELAY 2V 2V Lead Temperature Range 300°C 0.8V 0.8V (Soldering 10 sec) Figure 3. Voltage Reference Levels for Timing 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 See the Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, θ = 30°C/W JA JC 5 Specification is for the device in free air: 48-Lead LFCSP; θ = 26°C/W. JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 03033-0-002 03033-0-003 AD7666 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 2 IDENTIFIER AVDD 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7666 NC 6 31 RD TOP VIEW NC 7 30 DGND (Not to Scale) SER/PAR 8 29 BUSY D0 9 28 D15 10 D1 27 D14 11 D2/DIVSCLK0 26 D13 12 D3/DIVSCLK1 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 6, NC No Connect. 7, 40 4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. 13 D4 or DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. Rev. 0 | Page 8 of 28 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN DVDD AGND DGND AGND D8/SDOUT NC D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF 03034-0-004 AD7666 1 Pin No. Mnemonic Type Description 16 D7 or DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D8 or DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7666 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D9 or DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 or DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. 24 D11 or DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When RDERROR SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7666 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t ) is complete, the next falling edge 8 on CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 37 REF AI/O Reference Input Voltage. On-chip reference output voltage. 38 REFGND AI Reference Input Analog Ground. 39 INGND AI Analog Input Ground. Rev. 0 | Page 9 of 28 AD7666 1 Pin No. Mnemonic Type Description 43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V. 45 TEMP AO Temperature Sensor Voltage Output. 46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input. 47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used. 48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer. When LOW, the buffer is selected. When HIGH, the buffer is switched off. 1 AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Rev. 0 | Page 10 of 28 AD7666 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Aperture Delay Linearity error refers to the deviation of each individual code Aperture delay is a measure of the acquisition performance and from a line drawn from negative full scale through positive full is measured from the falling edge of the input to when CNVST scale. The point used as negative full scale occurs ½ LSB before the input signal is held for a conversion. the first code transition. Positive full scale is defined as a level Transient Response 1½ LSB beyond the last code transition. The deviation is Transient response is the time required for the AD7666 to measured from the middle of each code to the true straight line. achieve its rated accuracy after a full-scale step function is Differential Nonlinearity Error (DNL) applied to its input. In an ideal ADC, code transitions are 1 LSB apart. Differential Reference Voltage Temperature Coefficient nonlinearity is the maximum deviation from this ideal value. It Reference voltage temperature coefficient is derived from the is often specified in terms of resolution for which no missing maximum and minimum reference output voltage (V ) REF codes are guaranteed. measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C Full-Scale Error using the following equation: The last transition (from 011…10 to 011…11 in twos V (Max) –V (Min) 6 REF REF complement coding) should occur for an analog voltage 1½ LSB TCV (ppm/°C)= ×10 REF V (25°C)× (T –T ) REF MAX MIN below the nominal full scale (2.49994278 V for the 0 V to 2.5 V range). The full-scale error is the deviation of the actual level of where: the last transition from the ideal level. V (Max) = Maximum V at T , T(25°C), or T REF REF MIN MAX Unipolar Zero Error (Min) = Minimum V at T , T(25°C), or T VREF REF MIN MAX The first transition should occur at a level ½ LSB above analog VREF(25°C) = VREF at +25°C ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero TMAX = +85°C error is the deviation of the actual transition from that point. TMIN = –40°C Spurious-Free Dynamic Range (SFDR) Thermal Hysteresis SFDR is the difference, in decibels (dB), between the rms Thermal hysteresis is defined as the absolute maximum change amplitude of the input signal and the peak spurious signal. of reference output voltage after the device is cycled through temperature from either Effective Number Of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave T_HYS+ = +25°C to TMAX to +25°C input. It is related to S/(N+D) and is expressed in bits by the T_HYS– = +25°C to T to +25°C MIN following formula: It is expressed in ppm using the following equation: ENOB = (S/[N+D]dB – 1.76)/6.02 V (25°C)− V (T _ HYS) REF REF 6 Total Harmonic Distortion (THD) V (ppm)= × 10 HYS V (25°C) REF THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is where: expressed in decibels. V (25°C) = V at 25°C REF REF Signal-to-Noise Ratio (SNR) V (T_HYS) = Maximum change of V at T_HYS+ or REF REF T_HYS–. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Rev. 0 | Page 11 of 28 AD7666 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –1.0 –0.5 –1.5 –2.0 –1.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 8. Differential Nonlinearity vs. Code Figure 5. Integral Nonlinearity vs. Code 20 20 15 15 10 10 5 5 0 0 –2.0 –1.5 –1.0 –0.5 0 0 0.5 1.0 1.5 2.0 NEGATIVE INL (LSB) POSITIVE INL (LSB) Figure 9. Typical Negative INL Distribution (99 Units) Figure 6. Typical Positive INL Distribution (99 Units) 40 30 30 20 20 10 10 0 0 –1.00 –0.75 –0.50 –0.25 0 0 0.25 0.50 0.75 1.00 1.25 1.50 NEGATIVE DNL (LSB) POSITIVE DNL (LSB) Figure 10. Typical Negative DNL Distribution (99 Units) Figure 7. Typical Positive DNL Distribution (99 Units) Rev. 0 | Page 12 of 28 NUMBER OF UNITS NUMBER OF UNITS INL (LSB) 03034-0-006 03034-0-007 03034-0-005 NUMBER OF UNITS NUMBER OF UNITS DNL (LSB) 03034-0-008 03034-0-010 03034-0-009 AD7666 120000 180000 111791 112335 160000 148481 100000 140000 80000 120000 100000 60000 80000 52691 53814 40000 60000 40000 15968 20187 20000 20000 2789 3300 623 0 1 211 4 0 34 0 11 0 0 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 CODE IN HEX CODE IN HEX Figure 11. Histogram of 261,120 Conversions of a Figure 14. Histogram of 261,120 Conversions of a DC Input at the Code Transition DC Input at the Code Center –70 120 0 –75 110 –20 f = 500kSPS S SFDR f = 101.361kHz IN –80 100 –40 SNR = 88.6dB THD = –98.1dB –85 90 –60 SFDR = 99.2dB S/[N+D] = 88.1dB –90 80 –80 –95 70 –100 –100 60 SECOND THD –120 HARMONIC –105 50 –140 –110 40 THIRD HARMONIC –160 –115 30 –180 –120 20 1 10 100 1000 0 50 100 150 200 250 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. FFT Plot Figure 15. THD, Harmonics, and SFDR vs. Frequency 91 15.5 91 90 89 15.0 88 90 SNR 87 14.5 SNR 86 S/[N+D] S/[N+D] 85 14.0 89 84 ENOB 83 13.5 82 81 13.0 88 1 10 100 1000 –50 –40 –30 –20 –10 0 –60 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 16. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) Figure 13. SNR, S/(N+D), and ENOB vs. Frequency Rev. 0 | Page 13 of 28 COUNTS SNR, S/[N+D] (dB) AMPLITUDE (dB of Full Scale) 03034-0-013 03034-0-012 ENOB (Bits) 03034-0-011 COUNTS SNR, S/[N+D] REFERRED TO FULL-SCALE (dB) THD, HARMONICS (dB) SFDR (dB) 03034-0-016 03034-0-015 03034-0-014 7.5 AD7666 92 6 15.5 5 4 91 15.0 FULL-SCALE 3 ERROR 2 ENOB 90 14.5 1 0 –1 89 14.0 ZERO ERROR SNR –2 –3 S/[N+D] 88 13.5 –4 –5 –6 87 13.0 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. Zero Error, Full-Scale Error without Reference vs. Temperature Figure 17. SNR, S/(N+D), and ENOB vs. Temperature 2.5016 –100 2.5014 2.5012 2.5010 –105 2.5008 THD 2.5006 2.5004 2.5002 –110 2.5000 2.4998 SECOND THIRD HARMONIC 2.4996 HARMONIC 2.4994 –115 –40 –20 0 20 40 60 80 100 120 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 21.Typical Reference Voltage Output vs. Temperature (2 Units) Figure 18. THD and Harmonics vs. Temperature 25 100000 10000 20 1000 100 15 AVDD 10 DVDD 10 OVDD 1 0.1 5 0.01 PDREF = PDBUF = HIGH 0 0.001 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 8.0 10 100 1k 10k 100k 1M REFERENCE DRIFT (ppm/°C) SAMPLING RATE (SPS) Figure 22. Reference Voltage Temperature Coefficient Distribution (93 Units) Figure 19. Operating Current vs. Sample Rate Rev. 0 | Page 14 of 28 TEMPERATURE (°C) OPERATING CURRENTS (µA) THD, HARMONICS (dB) SNR, S/[N+D] (dB) ENOB (Bits) 03034-0-019 03034-0-018 03034-0-017 VREF (V) ZERO ERROR, FULL-SCALE ERROR (LSB) NUMBER OF UNITS 03034-0-039 03034-0-020 03034-0-021 AD7666 50 OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25°C 40 35 30 25 OVDD = 5V @ 85°C 20 OVDD = 5V @ 25°C 15 10 5 0 0 50 100 150 200 C (pF) L Figure 23. Typical Delay vs. Load Capacitance, CL Rev. 0 | Page 15 of 28 t DELAY (ns) 12 03035-0-023 AD7666 CIRCUIT INFORMATION IN REF REFGND SWITCHES CONTROL MSB LSB SW A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC INGND OUTPUT 65,536C CODE SW B CNVST Figure 24. ADC Simplified Schematic The AD7666 is a very fast, low power, single supply, precise During the acquisition phase, the common terminal of the array 16-bit analog-to-digital converter (ADC). The AD7666 is tied to the comparator's positive input is connected to AGND capable of converting 100,000 samples per second (500 kSPS) via SW . All independent switches are connected to the analog A and allows power savings between conversions. input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN. Similarly, the The AD7666 provides the user with an on-chip track/hold, dummy capacitor acquires the analog signal on INGND. successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed When CNVST goes LOW, a conversion phase is initiated. When channel applications. the conversion phase begins, SW and SW are opened. The A B capacitor array and dummy capacitor are then disconnected The AD7666 can be operated from a single 5 V supply and can from the inputs and connected to REFGND. Therefore, the be interfaced to either 5 V or 3 V digital logic. It is housed in differential voltage between IN and INGND captured at the end either a 48-lead LQFP or a 48-lead LFCSP that saves space and of the acquisition phase is applied to the comparator inputs, allows flexible configurations as either a serial or parallel inter- causing the comparator to become unbalanced. By switching face. The AD7666 is pin-to-pin compatible with PulSAR ADCs each element of the capacitor array between REFGND and REF, and is an upgrade of the AD7661 and AD7664. the comparator input varies by binary weighted voltage steps (V /2, V /4, …V /65536). The control logic toggles these REF REF REF CONVERTER OPERATION switches, starting with the MSB, to bring the comparator back The AD7666 is a successive-approximation ADC based on a into a balanced condition. charge redistribution DAC. Figure 24 shows a simplified sche- matic of the ADC. The capacitive DAC consists of an array of After this process is completed, the control logic generates the 16 binary weighted capacitors and an additional LSB capacitor. ADC output code and brings the BUSY output LOW. The comparator’s negative input is connected to a dummy capacitor of the same value as the capacitive DAC array. Rev. 0 | Page 16 of 28 03033-0-020 AD7666 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Digital Output Code (Hex) 2C Using the OB/ digital input, the AD7666 offers two output Analog Straight Twos codings: straight binary and twos complement. The LSB size is Description Input Binary Complement V /65536, which is about 38.15 µV. The AD7666’s ideal REF 1 1 FSR –1 LSB 2.499962 V FFFF 7FFF transfer characteristic is shown in Figure 25 and Table 7. FSR – 2 LSB 2.499923 V FFFE 7FFE Midscale + 1 LSB 1.250038 V 8001 0001 1 LSB = V /65536 REF Midscale 1.25 V 8000 0000 111...111 Midscale – 1 LSB 1.249962 V 7FFF FFFF 111...110 –FSR + 1 LSB 38 µV 0001 8001 111...101 2 2 –FSR 0 V 0000 8000 1 This is also the code for overrange analog input (V – V above IN INGND VREF – VREFGND). 2 This is also the code for underrange analog input (V below V ). IN INGND 000...010 000...001 000...000 0V 1LSB V – 1 LSB REF 0.5 LSB V – 1.5 LSB REF ANALOG INPUT Figure 25. ADC Ideal Transfer Function ANALOG 20Ω DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) + + + 100nF 100nF 100nF 10µF 10µF 10µF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT SCLK REF SDOUT 4 1 C REFBUFIN R 100nF µC/µP/DSP REFGND BUSY AD7666 3 CNVST D 15Ω 2 U1 IN OB/2C ANALOG INPUT (0VTO 2.5V) DVDD SER/PAR C 2.7nF C INGND PDREF PD PDBUF RESET CS RD BYTESWAP CLOCK NOTES 1 THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER. 2 THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3 OPTIONAL LOW JITTER. 4 A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. Figure 26. Typical Connection Diagram Rev. 0 | Page 17 of 28 ADC CODE (Straight Binary) 03033-0-021 03034-0-022 AD7666 TYPICAL CONNECTION DIAGRAM Figure 26 shows a typical connection diagram for the AD7666. During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor Analog Input C1 and the network formed by the series connection of R1 and Figure 27 shows an equivalent circuit of the input structure of C2. C1 is primarily the pin capacitance. R1 is typically 168 Ω the AD7666. and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 60 pF and The two diodes, D1 and D2, provide ESD protection for the is mainly the ADC sampling capacitor. During the conversion analog inputs IN and INGND. Care must be taken to ensure phase, where the switches are opened, the input impedance is that the analog input signal never exceeds the supply rails by limited to C1. R1 and C2 make a 1-pole low-pass filter that more than 0.3 V. This will cause these diodes to become reduces undesirable aliasing effect and limits the noise. forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For When the source impedance of the driving circuit is low, the instance, these conditions could eventually occur when the AD7666 can be driven directly. Large source impedances will input buffer’s (U1) supplies are different from AVDD. In such a significantly affect the ac performance, especially total case, an input buffer with a short-circuit current limitation can harmonic distortion (THD). The maximum source impedance be used to protect the part. depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the AVDD maximum input frequency, as shown in Figure 29. D1 C2 R1 IN OR INGND C1 –50 D2 R = 500Ω S AGND –60 R = 100Ω S Figure 27. Equivalent Analog Input Circuit –70 R = 50Ω S R = 20Ω S This analog input structure allows the sampling of the differen- –80 tial signal between IN and INGND. Unlike other converters, INGND is sampled at the same time as IN. By using this –90 differential input, small signals common to both inputs are rejected, as shown in Figure 28, which represents the typical –100 CMRR over frequency with on-chip and external references. For instance, by using INGND to sense a remote signal ground, –110 1 10 100 1000 ground potential differences between the sensor and the local INPUT FREQUENCY (kHz) ADC ground are eliminated. Figure 29. THD vs. Analog Input Frequency and Source Resistance 90 Driver Amplifier Choice EXT REF 80 Although the AD7666 is easy to drive, the driver amplifier REF needs to meet the following requirements: 70 • The driver amplifier and the AD7666 analog input circuit 60 must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data 50 sheet, settling at 0.1% to 0.01% is more commonly speci- fied. This could differ significantly from the settling time at 40 a 16-bit level and should be verified prior to driver selection. The tiny op amp AD8021, which combines ultra 30 low noise and high gain-bandwidth, meets this settling 1 10 100 1000 10000 time requirement even when used with gains up to 13. FREQUENCY (kHz) Figure 28. Analog Input CMRR vs. Frequency Rev. 0 | Page 18 of 28 CMRR (dB) 03033-0-023 03034-0-028 THD (dB) 03034-0-029 AD7666 • The noise generated by the driver amplifier needs to be Voltage Reference Input kept as low as possible in order to preserve the SNR and The AD7666 allows the choice of either a very low temperature transition noise performance of the AD7666. The noise drift internal voltage reference or an external 2.5 V reference. coming from the driver is filtered by the AD7666 analog Unlike many ADCs with internal references, the internal input circuit, 1-pole, low-pass filter made by R1 and C2 or reference of the AD7666 provides excellent performance and by the external filter, if one is used. The SNR degradation can be used in almost all applications. due to the amplifier is To use the internal reference along with the internal buffer, ⎛ ⎞ ⎜ ⎟ PDREF and PDBUF should both be LOW. This will produce 28 ⎜ ⎟ SNR = 20 log 1.2 V on REFBUFIN which, amplified by the buffer, will result LOSS ⎜ ⎟ π 2 ⎜ 784+ f (Ne ) ⎟ in a 2.5 V reference on the REF pin. −3dB N 2 ⎝ ⎠ The output impedance of REFBUFIN is 11 kΩ (minimum) when where: the internal reference is enabled. It is necessary to decouple f is the input bandwidth of the AD7666 (13 MHz) or –3dB REFBUFIN with a ceramic capacitor greater than 10 nF. Thus the cutoff frequency of the input filter (3.9 MHz), if the capacitor provides an RC filter for noise reduction. one is used. To use an external reference along with the internal buffer, N is the noise factor of the amplifier (+1 in buffer PDREF should be HIGH and PDBUF should be LOW. This configuration). powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN. e is the equivalent input noise voltage of the op amp, in N nV/√Hz. To use an external reference directly on REF pin, PDREF and PDBUF should both be HIGH. For instance, a driver with an equivalent input noise of 2 nV/√Hz, like the AD8021 with a noise gain of +1 when PDREF and PDBUF power down the internal reference and the configured as a buffer, degrades the SNR by only 0.13 dB internal reference buffer, respectively. Note that the PDREF and when using the filter shown in Figure 26, and by 0.43 dB PDBUF input current should never exceed 20 mA. This could without the filter shown in Figure 26. eventually occur when input voltage is above AVDD (for instance at power up). In this case, a 100 Ω series resistor is • The driver needs to have a THD performance suitable to recommended. that of the AD7666. Figure 15 gives the THD versus frequency that the driver should exceed. The internal reference is temperature compensated to 2.5 V ± 7 mV. The reference is trimmed to provide a typical drift of The AD8021 meets these requirements and is appropriate for 3 ppm/°C . This typical drift characteristic is shown in almost all applications. The AD8021 needs a 10 pF external Figure 22. For improved drift performance, an external compensation capacitor that should have good linearity as an reference, such as the AD780, can be used. NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the The AD7666 voltage reference input REF has a dynamic input best signal-to-noise ratio. impedance; it should therefore be driven by a low impedance source with efficient decoupling between the REF and The AD8022 could also be used if a dual version is needed and REFGND inputs. This decoupling depends on the choice of the gain of 1 is present. The AD829 is an alternative in applications voltage reference, but usually consists of a low ESR tantalum where high frequency (above 100 kHz) performance is not capacitor connected to REF and REFGND, with minimum required. In gain of 1 applications, it requires an 82 pF parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip compensation capacitor. The AD8610 is an option when low capacitor (or 47 µF tantalum capacitor) is appropriate when bias current is needed in low frequency applications. using either the internal reference or one of these recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 • The low power ADR291 • The low cost AD1582 Rev. 0 | Page 19 of 28 AD7666 90 For applications that use multiple AD7666s, it is more effective to use the internal buffer to buffer the reference voltage. 80 EXT REF Care should be taken with the voltage reference’s temperature coefficient, which directly affects the full-scale accuracy if this 70 parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. 60 INT REF Note that V can be increased to AVDD – 1.85 V. Since the REF 50 input range is defined in terms of V , this would essentially REF increase the range to 0 V to 3 V with an AVDD above 4.85 V. 40 The AD780 can be selected with a 3 V reference voltage. 30 The TEMP pin, which measures the temperature of the 1 10 100 1000 10000 AD7666, can be used as shown in Figure 30. The output of FREQUENCY (kHz) TEMP pin is applied to one of the inputs of the analog switch Figure 31. PSRR vs. Frequency (e.g., ADG779), and the ADC itself is used to measure its own temperature. This configuration is very useful for improving the POWER DISSIPATION VERSUS THROUGHPUT calibration accuracy over the temperature range. Operating currents are very low during the acquisition phase, allowing significant power savings when the conversion rate is TEMP ADG779 reduced (see Figure 32). The AD7666 automatically reduces its TEMPERATURE power consumption at the end of each conversion phase. This SENSOR IN ANALOG INPUT (UNIPOLAR) makes the part ideal for very low power battery applications. AD7666 C AD8021 C The digital interface and the reference remain active even during the acquisition phase. To reduce operating digital supply Figure 30. Temperature Sensor Connection Diagram currents even further, digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND), and OVDD Power Supply should not exceed DVDD by more than 0.3 V. The AD7666 uses three power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/ 1M output interface supply OVDD. OVDD allows direct interface with any logic between 2.7 V and DVDD + 0.3 V. To reduce the 100k supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 26. The AD7666 is independent of power supply 10k sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is thus free of supply voltage induced latch-up. 1k Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 31, which 100 represents PSRR over frequency with on-chip and external references. PDREF = PDBUF = HIGH 10 10 100 1k 10k 100k 1M SAMPLING RATE (SPS) Figure 32. Power Dissipation vs. Sampling Rate Rev. 0 | Page 20 of 28 03034-0-024 POWER DISSIPATION (µW) PSRR (dB) 03034-0-031 03034-0-032 AD7666 t 2 CONVERSION CONTROL t 1 Figure 33 shows the detailed timing diagrams of the conversion CNVST process. The AD7666 is controlled by the signal, which CNVST initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion BUSY is complete. CNVST operates independently of CS and RD. t 4 t 3 t 6 t Conversions can be automatically initiated with the AD7666. If 5 CNVST is held LOW when BUSY is LOW, the AD7666 controls MODE ACQUIRE CONVERT ACQUIRE CONVERT the acquisition phase and automatically initiates a new t t 7 8 conversion. By keeping LOW, the AD7666 keeps the CNVST Figure 33. Basic Conversion Timing conversion process running by itself. It should be noted that the analog input must be settled when BUSY goes LOW. Also, at t power-up, CNVST should be brought LOW once to initiate the 9 RESET conversion process. In this mode, the AD7666 can run slightly faster than the guaranteed 500 kSPS. BUSY Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum DATA overshoot and undershoot or ringing. t 8 trace should be shielded with ground and a low The CNVST CNVST value serial resistor (i.e., 50 Ω) termination should be added close to the output of the component that drives this line. Figure 34. RESET Timing For applications where SNR is critical, the signal should CNVST CS = RD = 0 have very low jitter. This may be achieved by using a dedicated t 1 oscillator for CNVST generation, or to clock CNVST with a CNVST high frequency, low jitter clock, as shown in Figure 26. t 10 BUSY t 4 t 3 t 11 DATA PREVIOUS CONVERSION DATA NEW DATA BUS Figure 35. Master Parallel Data Timing for Reading (Continuous Read) Rev. 0 | Page 21 of 28 03033-0-028 03033-0-027 03033-0-026 AD7666 DIGITAL INTERFACE CS The AD7666 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel RD interface. The serial interface is multiplexed on the parallel data bus. The AD7666 digital interface also accommodates both 3 V and 5 V logic by simply connecting the OVDD supply pin of the AD7666 to the host system interface digital supply. Finally, by BUSY using the OB/2C input pin, both twos complement or straight binary coding can be used. DATA CURRENT BUS CONVERSION The two signals, CS and RD, control the interface. CS and RD t t have a similar effect because they are OR’d together internally. 12 13 When at least one of these signals is HIGH, the interface Figure 36. Slave Parallel Data Timing for Reading (Read after Convert) outputs are in high impedance. Usually allows the selection CS of each AD7666 in multicircuit applications and is held low in a CS = 0 single AD7666 design. RD is generally used to enable the CNVST, t 1 conversion result on the data bus. RD PARALLEL INTERFACE The AD7666 is configured to use the parallel interface when BUSY t SER/ is held LOW. The data can be read either after each 4 PAR conversion, which is during the next acquisition phase, or t 3 during the following conversion, as shown in Figure 36 and Figure 37, respectively. When the data is read during the DATA PREVIOUS CONVERSION BUS conversion, however, it is recommended that it is read only t t 12 13 during the first half of the conversion phase. This avoids any Figure 37. Slave Parallel Data Timing for Reading (Read during Convert) potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. The BYTESWAP pin allows a glueless interface to an 8-bit bus. CS As shown in Figure 38, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is LOW. When RD BYTESWAP is HIGH, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data BYTESWAP can be read in two bytes on either D[15:8] or D[7:0]. HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE SERIAL INTERFACE t t t 12 12 13 The AD7666 is configured to use the serial interface when HI-Z HI-Z LOW BYTE HIGH BYTE PINS D[7:0] SER/ is held HIGH. The AD7666 outputs 16 bits of data, PAR Figure 38. 8-Bit Parallel Interface MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock. Rev. 0 | Page 22 of 28 03033-0-031 03033-0-030 03033-0-029 AD7666 MASTER SERIAL INTERFACE Usually, because the AD7666 is used with a fast throughput, the Internal Clock Master Read During Conversion mode is the most recommen- ded serial mode. In this mode, the serial clock and data toggle at The AD7666 is configured to generate and provide the serial appropriate instants, minimizing potential feedthrough between data clock SCLK when the EXT/INT pin is held LOW. The digital activity and critical conversion decisions. AD7666 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the In Read After Conversion mode, it should be noted that unlike SYNC signal can be inverted if desired. Depending on the in other modes, the BUSY signal returns LOW after the 16 data RDC/SDIN input, the data can be read after each conversion or bits are pulsed out and not at the end of the conversion phase, during the following conversion. Figure 39 and Figure 40 show which results in a longer BUSY width. detailed timing diagrams of these two modes. RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 39. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 23 of 28 03033-0-032 03033-0-033 AD7666 SLAVE SERIAL INTERFACE External Clock While the AD7666 is performing a bit decision, it is important The AD7666 is configured to accept an externally supplied that voltage transients be avoided on digital input/output pins serial data clock on the SCLK pin when the EXT/INT pin is or degradation of the conversion result could occur. This is held HIGH. In this mode, several methods can be used to read particularly important during the second half of the conversion the data. The external serial clock is gated by . When and CS CS phase because the AD7666 provides error correction circuitry RD are both LOW, the data can be read after each conversion or that can correct for an improper bit decision made during the during the following conversion. The external clock can be first half of the conversion phase. For this reason, it is either a continuous or a discontinuous clock. A discontinuous recommended that when an external clock is being provided, it clock can be either normally HIGH or normally LOW when is a discontinuous clock that is toggling only when BUSY is inactive. Figure 41 and Figure 42 show the detailed timing LOW, or, more importantly, that it does not transition during diagrams of these methods. Usually, because the AD7666 has a the latter half of BUSY HIGH. longer acquisition phase than conversion phase, the data are read immediately after conversion. EXT/INT = 1 INVSCLK = 0 RD = 0 RD BUSY t 35 t t 36 37 SCLK 1 2 3 14 151617 18 t 31 t 32 X D15 D14 D13 D1 X15 X14 SDOUT D0 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 41. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 X D1 SDOUT D15 D14 D13 D0 t 16 Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 24 of 28 03033-0-034 03033-0-035 AD7666 External Discontinuous Clock Data Read After External Clock Data Read During Conversion Conversion Figure 42 shows the detailed timing diagrams of this method. Though the maximum throughput cannot be achieved using During a conversion, while both CS and RD are LOW, the result this mode, it is the most recommended of the serial slave of the previous conversion can be read. The data is shifted out modes. Figure 41 shows the detailed timing diagrams of this MSB first with 16 clock pulses, and is valid on both the rising method. After a conversion is complete, indicated by BUSY and falling edges of the clock. The 16 bits must be read before returning LOW, the conversion’s result can be read while both the current conversion is complete; otherwise, RDERROR is CS and RD are LOW. Data is shifted out MSB first with 16 clock pulsed HIGH and can be used to interrupt the host interface to pulses and is valid on the rising and falling edges of the clock. prevent incomplete data reading. There is no daisy-chain feature in this mode and the RDC/SDIN input should always be tied Among the advantages of this method is the fact that either HIGH or LOW. conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion To reduce performance degradation due to digital activity, a fast process. Another advantage is the ability to read the data at any discontinuous clock of at least 18 MHz is recommended to speed up to 40 MHz, which accommodates both the slow digital ensure that all the bits are read during the first half of the host interface and the fastest serial reading. conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new Finally, in this mode only, the AD7666 provides a daisy-chain conversion has been initiated. This allows the use of a slower feature using the RDC/SDIN pin for cascading multiple con- clock speed like 14 MHz. verters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 43. Simultaneous sampling is possible by using a common signal. It should be noted that the RDC/SDIN CNVST input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7666 AD7666 #2 #1 (UPSTREAM) (DOWNSTREAM) DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN Figure 43. Two AD7666s in a Daisy-Chain Configuration Rev. 0 | Page 25 of 28 03034-0-036 AD7666 MICROPROCESSOR INTERFACING going LOW) using an interrupt line of the DSP. The serial inter- face (SPI) on the ADSP-219x is configured for master mode— The AD7666 is ideally suited for traditional dc measurement (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit applications supporting a microprocessor, and for ac signal (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by processing applications interfacing to a digital signal processor. writing to the SPI control register (SPICLTx). To meet all timing The AD7666 is designed to interface either with a parallel 8-bit requirements, the SPI clock should be limited to 17 Mbps, or 16-bit wide interface, or with a general-purpose serial port or which allows it to read an ADC result in less than 1 µs. When a I/O ports on a microcontroller. A variety of external buffers can higher sampling rate is desired, use of one of the parallel be used with the AD7666 to prevent digital noise from coupling interface modes is recommended. into the ADC. The following section discusses the use of an AD7666 with an ADSP-219x SPI equipped DSP. DVDD SPI Interface (ADSP-219x) ADSP-219x* AD7666* Figure 44 shows an interface diagram between the AD7666 and SER/PAR the SPI equipped ADSP-219x. To accommodate the slower EXT/INT speed of the DSP, the AD7666 acts as a slave device and data BUSY PFx must be read after conversion. This mode also allows the daisy- CS SPIxSEL (PFx) RD chain feature. The convert command can be initiated in SDOUT MISOx INVSCLK SCLK SCKx response to an internal timer interrupt. The reading process can CNVST PFx or TFSx be initiated in response to the end-of-conversion signal (BUSY *ADDITIONAL PINS OMITTED FOR CLARITY Figure 44. Interfacing the AD7666 to an SPI Interface Rev. 0 | Page 26 of 28 03034-0-037 AD7666 APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES Running digital lines under the device should be avoided since these will couple noise onto the die. The analog ground plane In some applications, it is desirable to use a bipolar or wider should be allowed to run under the AD7666 to avoid noise analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although coupling. Fast switching signals like or clocks should be CNVST the AD7666 has only one unipolar range, simple modifications shielded with digital ground to avoid radiating noise to other of input driver circuitry allow bipolar and wider input ranges to sections of the board, and should never run near analog signal be used without any performance degradation. Figure 45 shows paths. Crossover of digital and analog signals should be avoided. a connection diagram that allows this. Component values Traces on different but close layers of the board should run at required and resulting full-scale ranges are shown in Table 8. right angles to each other. This will reduce the effect of crosstalk When desired, accurate gain and offset can be calibrated by through the board. acquiring a ground and voltage reference using an analog The power supply lines to the AD7666 should use as large a multiplexer (U2), as shown in Figure 45. trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is C F also important to lower the supply’s impedance presented to the R1 AD7666 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be R2 ANALOG placed on each power supply pin—AVDD, DVDD, and 15Ω INPUT U1 IN OVDD—close to, and ideally right up against these pins and 2.7nF their corresponding ground pins. Additionally, low ESR 10 µF AD7666 capacitors should be located near the ADC to further reduce U2 R3 R4 100nF low frequency ripple. INGND REF The DVDD supply of the AD7666 can be a separate supply, or can come from the analog supply AVDD or the digital interface C REF supply OVDD. When the system digital supply is noisy or when REFGND fast switching digital signals are present, if no separate supply is available, the user should connect DVDD to AVDD through an Figure 45. Using the AD7666 in 16-Bit Bipolar and/or Wider Input Ranges RC filter (see Figure 26) and the system supply to OVDD and the remaining digital circuitry. When DVDD is powered from Table 8. Component Values and Input Ranges the system supply, it is useful to insert a bead to further reduce Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ) high frequency spikes. ±10 V 500 4 2.5 2 ±5 V 500 2 2.5 1.67 The AD7666 has five different ground pins: INGND, REFGND, 0 V to –5 V 500 1 None 0 AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and, because LAYOUT it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC The AD7666 has very good immunity to noise on the power analog signals are referenced; it must be connected with the supplies. However, care should still be taken with regard to least resistance to the analog ground plane. DGND must be tied grounding layout. to the analog or digital ground plane depending on the config- The printed circuit board that houses the AD7666 should be uration. OGND is connected to the digital system ground. designed so the analog and digital sections are separated and EVALUATING THE AD7666’S PERFORMANCE confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. Digital and analog A recommended layout for the AD7666 is outlined in the ground planes should be joined in only one place, preferably EVAL-AD7666 evaluation board for the AD7666. The underneath the AD7666, or as close as possible to the AD7666. evaluation board package includes a fully assembled and tested If the AD7666 is in a system where multiple devices require evaluation board, documentation, and software for controlling analog-to-digital ground connections, the connection should the board from a PC via the EVAL-CONTROL BRD2. still be made at one point only, a star ground point that should be established as close as possible to the AD7666. Rev. 0 | Page 27 of 28 03034-0-038 AD7666 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 37 48 1 36 PIN 1 SEATING 10° PLANE TOP VIEW 7.00 1.45 6° 0.20 (PINS DOWN ) BSC SQ 2° 1.40 0.09 1.35 VIEW A 7° 3.5° 12 25 0.15 0° 24 13 SEATING 0.05 0.10 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 46. 48-Lead Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 BOTTOM TOP BSC SQ VIEW 5.10 SQ VIEW 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 PADDLE CONNECTED TO AGND. 12° MAX
0.65 TYP THIS CONNECTION IS NOT 0.85 0.05 MAX REQUIRED TO MEET THE 0.80 ELECTRICAL PERFORMANCES 0.02 NOM 0.50 BSC COPLANARITY 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 47. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48] Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7666AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7666ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7666ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 AD7666ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 1 EVAL-AD7666CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03034–0–1/04(0) Rev. 0 | Page 28 of 28