ANALOG DEVICES AD7664

16-Bit, 570 kSPS ® a PulSAR Unipolar CMOS ADC * AD7664 FUNCTIONAL BLOCK DIAGRAM FEATURES Throughput: AVDD AGND REF REFGND DVDD DGND 570 kSPS (Warp Mode) 500 kSPS (Normal Mode) OVDD AD7664 444 kSPS (Impulse Mode) OGND SERIAL INL: �2.5 LSB Max (�0.0038% of Full Scale) PORT IN SWITCHED 16-Bit Resolution with No Missing Codes 16 CAP DAC INGND D[15:0] S/(N+D): 90 dB Typ @ 45 kHz BUSY THD: –100 dB Typ @ 45 kHz PARALLEL Analog Input Voltage Range: 0 V to 2.5 V INTERFACE RD CLOCK Both AC and DC Specifications CS PD No Pipeline Delay CONTROL LOGIC AND SER/PAR RESET CALIBRATION CIRCUITRY Parallel and Serial 5 V/3 V Interface OB/2C TM TM ® SPI /QSPI /MICROWIRE /DSP Compatible Single 5 V Supply Operation WARP IMPULSE CNVST Power Dissipation 115 mW Maximum, Table I. PulSAR Selection 21 �W @ 100 SPS Power-Down Mode: 7 �W Max Type/kSPS 100–250 500–570 800–1000 Package: 48-Lead Quad Flat Pack (LQFP) Pseudo AD7651 AD7650/AD7652 AD7653 48-Lead Chip Scale Package (LFCSP) Differential AD7660/AD7661 AD7664/AD7666 AD7667 Pin-to-Pin Compatible Upgrade of the AD7660 True Bipolar AD7663 AD7665 AD7671 APPLICATIONS Data Acquisition True AD7675 AD7676 AD7677 Instrumentation Differential Digital Signal Processing 18-Bit AD7678 AD7679 AD7674 Spectrum Analysis Medical Instruments Simultaneous/ AD7654 Battery-Powered Systems Multichannel AD7655 Process Control GENERAL DESCRIPTION It is fabricated using Analog Devices’ high performance, 0.6 micron The AD7664 is a 16-bit, 570 kSPS, charge redistribution SAR, CMOS process, with correspondingly low cost and is available in a analog-to-digital converter that operates from a single 5 V power 48-lead LQFP and a tiny 48-lead LFCSP with operation specified supply. The part contains a high speed 16-bit sampling ADC, from –40°C to +85°C. an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. PRODUCT HIGHLIGHTS The AD7664 is hardware factory-calibrated and is comprehensively 1. Fast Throughput tested to ensure such ac parameters as signal-to-noise ratio (SNR) The AD7664 is a 570 kSPS, charge redistribution, 16-bit and total harmonic distortion (THD), in addition to the more SAR ADC with internal error correction circuitry. traditional dc parameters of gain, offset, and linearity. 2. Superior INL The AD7664 has a maximum integral nonlinearity of 2.5 LSBs It features a very high sampling rate mode (Warp), a fast mode with no missing 16-bit code. (Normal) for asynchronous conversion rate applications, and for 3. Single-Supply Operation low power applications, a reduced power mode (Impulse) where The AD7664 operates from a single 5 V supply and dissipates the power is scaled with the throughput. only a maximum of 115 mW. In Impulse Mode, its power dissipation decreases with the throughput to, for instance, only 21 µW at a 100 SPS throughput. It consumes 7 µW maximum when in power-down. 4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement REV. E compatible with both 3 V or 5 V logic. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD7664–SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V 0V V IN INGND REF Operating Input Voltage V –0.1 +3 V IN V –0.1 +0.5 V INGND Analog Input CMRR f = 10 kHz 62 dB IN Input Current 570 kSPS Throughput 7 µA Input Impedance See Analog Input Section THROUGHPUT SPEED Complete Cycle In Warp Mode 1.75 µs Throughput Rate In Warp Mode 1 570 kSPS Time between Conversions In Warp Mode 1 ms Complete Cycle In Normal Mode 2 µs Throughput Rate In Normal Mode 0 500 kSPS Complete Cycle In Impulse Mode 2.25 µs Throughput Rate In Impulse Mode 0 444 kSPS DC ACCURACY 1 Integral Linearity Error –2.5 +2.5 LSB Differential Linearity Error –1 +1.5 LSB No Missing Codes 16 Bits Transition Noise 0.7 LSB 2 Full-Scale Error REF = 2.5 V ±0.08 % of FSR 2 Unipolar Zero Error ±5 ±15 LSB Power Supply Sensitivity AVDD = 5 V ±5% ±3 LSB AC ACCURACY 3 Signal-to-Noise f = 100 kHz 90 dB IN Spurious-Free Dynamic Range f = 45 kHz 100 dB IN f = 100 kHz 100 dB IN Total Harmonic Distortion f = 45 kHz –100 dB IN f = 100 kHz –100 dB IN Signal-to-(Noise+Distortion) f = 45 kHz 90 dB IN f = 100 kHz 89 dB IN –60 dB Input, f = 100 kHz 30 dB IN –3 dB Input Bandwidth 18 MHz SAMPLING DYNAMICS Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 570 kSPS Throughput 115 µA DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V 2.0 OVDD + 0.3 V IH I –1 +1 µA IL I –1 +1 µA IH DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bits Pipeline Delay Conversion Results Available Immediately after Completed Conversion V I = 1.6 mA 0.4 V OL SINK V I = –500 µA OVDD – 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V 4 Operating Current 500 kSPS Throughput AVDD 15.5 mA 5 DVDD 3.8 mA 5 OVDD 100 µA 5 4 Power Dissipation 500 kSPS Throughput 115 mW 6 100 SPS Throughput 21 µW 7 In Power-Down Mode 7 µW –2– REV. E AD7664 Parameter Conditions Min Typ Max Unit 8 TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX NOTES 1 LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 In Normal Mode. 5 Tested in Parallel Reading Mode. 6 In Impulse Mode. 7 With all digital inputs forced to OVDD or OGND, respectively. 8 Contact factory for extended temperature range. Specifications subject to change without notice. TIMING SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit REFER TO FIGURES 11 AND 12 Convert Pulse Width t5ns 1 Time between Conversions t 1.75/2/2.25 Note 1 µs 2 (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay t 25 ns 3 BUSY HIGH All Modes Except in t 1.5/1.75/2 µs 4 Master Serial Read after Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay t 2ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 1.5/1.75/2 µs 7 (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time t 250 ns 8 RESET Pulsewidth t 10 ns 9 REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t 1.5/1.75/2 µs 10 (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay t 45 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 515 ns 13 2 REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 2 CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t 10 ns 16 CNVST LOW to SYNC Delay t 25/275/525 ns 17 (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay t4ns 18 Internal SCLK Period t 40 75 ns 19 3 Internal SCLK HIGH (INVSCLK Low) t 30 ns 20 3 Internal SCLK LOW (INVSCLK Low) t 9.5 ns 21 SDOUT Valid Setup Time t 4.5 ns 22 SDOUT Valid Hold Time t3ns 23 SCLK Last Edge to SYNC Delay t 3 24 CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t 10 ns 27 BUSY HIGH in Master Serial Read after Convert t 2.75/3/3.25 µs 28 (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay t 1/1.25/1.5 µs 29 (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay t 50 ns 30 2 REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes) External SCLK Setup Time t5ns 31 External SCLK Active Edge to SDOUT Delay t 316 ns 32 SDIN Setup Time t5ns 33 SDIN Hold Time t5ns 34 External SCLK Period t 25 ns 35 External SCLK HIGH t 10 ns 36 External SCLK LOW t 10 ns 37 NOTES 1 In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 3 If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice. REV. E –3– AD7664 1 ABSOLUTE MAXIMUM RATINGS I 2 1.6mA OL IN , REF, INGND, REFGND to AGND . . . . . . . . . . . . . . . . . . . . . . .AVDD + 0.3 V to AGND – 0.3 V Ground Voltage Differences TO OUTPUT 1.4V PIN C AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . . ±0.3 V L 60pF* Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V I 500�A OH AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V * IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD Digital Inputs C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Except the Databus D(7:4) . . . . . –0.3 V to DVDD + 3.0 V Databus D(7:4) . . . . . . . . . . . . . . –0.3 V to OVDD + 3.0 V Figure 1. Load Circuit for Digital Interface Timing, 3 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 700 mW SDOUT, SYNC, SCLK Outputs, C = 10 pF L 4 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 2V Lead Temperature Range 0.8V t DELAY t (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C DELAY NOTES 2V 2V 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- 0.8V 0.8V nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections Figure 2. Voltage Reference Levels for Timing of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, θ = 30°C/W. JA JC 4 Specification is for device in free air: 48-Lead LFCSP; θ = 26°C/W. JA ORDERING GUIDE Temperature Model Range Package Description Package Option AD7664AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7664ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7664ACP –40°C to +85°C Chip Scale (LFCSP) CP-48 AD7664ACPRL –40°C to +85°C Chip Scale (LFCSP) CP-48 1 EVAL-AD7664CB Evaluation Board 2 EVAL-CONTROL-BRD2 Controller Board NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD2 for evaluation/ demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7664 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. –4– REV. E AD7664 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 IDENTIFIER AVDD 2 35 CNVST NC 3 34 PD DGND 4 33 RESET OB/2C 5 32 CS AD7664 WARP 6 31 RD TOP VIEW 7 IMPULSE 30 DGND (Not to Scale) SER/PAR 8 29 BUSY 9 D0 28 D15 10 D1 27 D14 11 D2 26 D13 D3 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 40–42, NC No Connect. 44–48 4 DGND DI Must Be Tied to the Ground Where DVDD Is Referred. 5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port. 9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. 13 D4 DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Mode. REV. E –5– D4/EXT/INT NC D5/INVSYNC NC D6/INVSCLK NC D7/RDC/SDIN NC OGND NC OVDD IN DVDD NC DGND NC D8/SDOUT NC D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF AD7664 Pin No. Mnemonic Type Description 16 D7 DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input or a Read Mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D8 DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D9 DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data or SCLK Output Bus. When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 DO When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. 24 D11 DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard- less of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. –6– REV. E AD7664 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In Impulse Mode (IMPULSE HIGH and WARP LOW), if CNVST is held LOW when the acquisition phase (t ) is complete, the internal sample-and-hold is put 8 into the hold state and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage. 38 REFGND AI Reference Input Analog Ground. 39 INGND AI Analog Input Ground. 43 IN AI Primary Analog Input with a Range of 0 V to V . REF NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power Total Harmonic Distortion (THD) DEFINITION OF SPECIFICATIONS THD is the ratio of the rms sum of the first five harmonic Integral Nonlinearity Error (INL) components to the rms value of a full-scale input signal and is Linearity error refers to the deviation of each individual code expressed in decibels. from a line drawn from negative full scale through positive full Signal-to-Noise Ratio (SNR) scale. The point used as negative full scale occurs 1/2 LSB SNR is the ratio of the rms value of the actual input signal to before the first code transition. Positive full scale is defined as a the rms sum of all other spectral components below the Nyquist level 1 1/2 LSB beyond the last code transition. The deviation is frequency, excluding harmonics and dc. The value for SNR is measured from the middle of each code to the true straight line. expressed in decibels. Differential Nonlinearity Error (DNL) Signal to (Noise + Distortion) Ratio (S/[N+D]) In an ideal ADC, code transitions are 1 LSB apart. Differential S/(N+D) is the ratio of the rms value of the actual input signal to nonlinearity is the maximum deviation from this ideal value. It is the rms sum of all other spectral components below the Nyquist often specified in terms of resolution for which no missing codes frequency, including harmonics but excluding dc. The value for are guaranteed. S/(N+D) is expressed in decibels. Full-Scale Error Aperture Delay The last transition (from 011 . . . 10 to 011 . . . 11 in twos Aperture delay is a measure of the acquisition performance and complement coding) should occur for an analog voltage 1 1/2 LSB is measured from the falling edge of the CNVST input to when below the nominal full scale (2.49994278 V for the 0 V–2.5 V the input signal is held for a conversion. range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. Transient Response The time required for the AD7664 to achieve its rated accuracy Unipolar Zero Error after a full-scale step function is applied to its input. The first transition should occur at a level 1/2 LSB above analog ground (19.073 µV for the 0 V–2.5 V range). Unipolar zero Overvoltage Recovery error is the deviation of the actual transition from that point. The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of Spurious-Free Dynamic Range (SFDR) the full-scale value. The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: ENOB=+ S N D −17.. 6 6 02 () [] dB and is expressed in bits. REV. E –7– AD7664–Typical Performance Characteristics 2.5 1.50 2.0 1.25 1.5 1.00 1.0 0.75 0.5 0.50 0 0.25 –0.5 0 –1.0 –0.25 –1.5 –0.50 –2.0 –0.75 –2.5 –1.00 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE TPC 1. Integral Nonlinearity vs. Code TPC 4. Differential Nonlinearity vs. Code 8000 10000 7288 7148 9008 9000 7000 8000 6000 7000 5000 6000 4000 5000 4000 3643 3000 3340 3000 2000 2000 1173 753 1000 1000 257 0 0 12 10 0 0 0 0 00 136 0 0 7F86 7F87 7F88 7F89 7F8A 7F8B 7F8C 7F8D 7F8E 7F8F 7FB3 7FB4 7FB5 7FB6 7FB7 7FB8 7FB9 7FBA 7FBB CODE – Hexa CODE – Hexa TPC 2. Histogram of 16,384 Conversions of a DC Input TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Transition at the Code Center 140 180 170 130 160 120 150 110 140 130 100 120 90 110 80 100 90 70 80 60 70 50 60 40 50 40 30 30 20 20 10 10 0 0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 00.5 1.0 1.5 2.0 2.5 NEGATIVE INL (LSB) POSITIVE INL (LSB) TPC 3. Typical Positive INL Distribution (600 Units) TPC 6. Typical Negative INL Distribution (600 Units) –8– REV. E NUMBER OF UNITS COUNTS INL – LSB COUNTS DNL – LSB NUMBER OF UNITS AD7664 0 92 8192 POINT FFT –20 f = 570kHz S f = 45.5322kHz, –0.5dB IN –40 SNR = 90.1dB SINAD = 89.4dB SNR THD = –97.1dB –60 90 SFDR = 97.5dB S/(N+D) –80 –100 –120 88 –140 –160 –180 86 –60 –50 –40 –30 –20 –10 0 057 114 171 228 285 FREQUENCY (kHz) INPUT LEVEL – dB TPC 7. FFT Plot TPC 10. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) 16.0 100 96 –96 15.5 95 –98 93 SNR 15.0 90 THD S/(N+D) 14.5 85 90 –100 ENOB SNR 14.0 80 87 –102 13.5 75 13.0 70 –104 84 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY – kHz TEMPERATURE – �C TPC 8. SNR, S/(N+D), and ENOB vs. Frequency TPC 11. SNR, S/(N+D), THD vs. Temperature 110 –60 100k AVDD, WARP/NORMAL 105 –65 10k 100 –70 DVDD, WARP/NORMAL SFDR 1k 95 –75 AVDD, IMPULSE 100 90 –80 DVDD, IMPULSE 85 –85 10 80 –90 1 THD 75 –95 0.1 OVDD, ALL MODES SECOND HARMONIC 70 –100 0.01 65 –105 THIRD HARMONIC 60 0.001 –110 1 10 100 1000 0.1 1 10 100 1k 10k 100k 1M FREQUENCY – kHz SAMPLING RATE – SPS TPC 9. THD, Harmonics, and SFDR vs. Frequency TPC 12. Operating Currents vs. Sample Rate REV. E –9– THD, HARMONIC – dB AMPLITUDE (dB of Full Scale) SNR AND S/[N+D] – dB SFDR – dB ENOB – Bits OPERATING CURRENTS – �A SNR (REFERRED TO FULL SCALE) – dB SNR AND S/(N+D) – dB THD – dB AD7664 100 10 90 8 FULL-SCALE ERROR 80 6 70 4 60 DVDD 2 ZERO ERROR 50 0 40 –2 30 –4 20 –6 10 AVDD 0 –8 OVDD –10 –10 –40 –15 10 35 60 85 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (�C) TEMPERATURE – �C TPC 13. Zero Error, Full-Scale Error vs. Temperature TPC 15. Power-Down Operating Currents vs. Temperature 50 OVDD = 2.7V, 85�C 40 30 OVDD = 2.7V, 25�C 20 OVDD = 5V, 85�C 10 OVDD = 5V, 25�C 0 0 50 100 150 200 C – pF L TPC 14. Typical Delay vs. Load Capacitance C L –10– REV. E ZERO ERROR, FULL-SCALE ERROR (LSB) t DELAY – ns 12 POWER-DOWN OPERATING CURRENTS – nA AD7664 CIRCUIT INFORMATION input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on the IN input. Similarly, the The AD7664 is a very fast, low power, single-supply, precise dummy capacitor acquires the analog signal on the INGND input. 16-bit analog-to-digital converter (ADC). The AD7664 features different modes to optimize performances according to the When the CNVST input goes LOW, a conversion phase is applications. initiated. When the conversion phase begins, SW and SW A B are opened first. The capacitor array and the dummy capacitor In Warp Mode, the AD7664 is capable of converting 570,000 samples per second (570 kSPS). are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between IN The AD7664 provides the user with an on-chip track-and-hold, and INGND captured at the end of the acquisition phase is successive-approximation ADC that does not exhibit any pipeline applied to the comparator inputs, causing the comparator to or latency, making it ideal for multiple multiplexed channel become unbalanced. By switching each element of the capacitor applications. array between REFGND or REF, the comparator input varies by The AD7664 can be operated from a single 5 V supply and binary-weighted voltage steps (V /2, V /4, . . . V /65536). REF REF REF interfaced to either 5 V or 3 V digital logic. It is housed in a The control logic toggles these switches, starting with the MSB 48-lead LQFP package or a 48-lead LFCSP package that first, to bring the comparator back into a balanced condition. After saves space and allows flexible configurations as either a the completion of this process, the control logic generates the serial or parallel interface. The AD7664 is a pin-to-pin com- ADC output code and brings BUSY output LOW. patible upgrade of the AD7660. Modes of Operation The AD7664 features three modes of operation: Warp, Nor- CONVERTER OPERATION mal, and Impulse. Each of these modes is suitable for specific The AD7664 is a successive-approximation analog-to-digital applications. converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive The Warp Mode allows the fastest conversion rate up to 570 kSPS. However, in this mode and this mode only, the full specified accuracy DAC consists of an array of 16 binary weighted capacitors is guaranteed only when the time between conversions does not and an additional LSB capacitor. The comparator’s negative input is connected to a dummy capacitor of the same value as exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion the capacitive DAC array. result should be ignored. This mode makes the AD7664 ideal During the acquisition phase, the common terminal of the array for applications where both high accuracy and fast sample rate tied to the comparator’s positive input is connected to AGND are required. via SW . All independent switches are connected to the analog A IN REF REFGND SWITCHES CONTROL MSB LSB SW A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC INGND OUTPUT 65,536C CODE SW B CNVST Figure 3. ADC Simplified Schematic REV. E –11– AD7664 The Normal Mode is the fastest mode (500 kSPS) without any Table II. Output Codes and Ideal Input Voltages limitation on the time between conversions. This mode makes the Digital Output Code AD7664 ideal for asynchronous applications such as data Hexa acquisition systems, where both high accuracy and fast sample Analog Straight Twos rate are required. Description Input Binary Complement The Impulse Mode, the lowest power dissipation mode, allows 1 1 FSR – 1 LSB 2.499962 V FFFF 7FFF power saving between conversions. When operating at 100 SPS, FSR – 2 LSB 2.499923 V FFFE 7FFE for example, it typically consumes only 21 µW. This feature Midscale + 1 LSB 1.250038 V 8001 0001 makes the AD7664 ideal for battery-powered applications. Midscale 1.25 V 8000 0000 Transfer Functions Midscale – 1 LSB 1.249962 V 7FFF FFFF Using the OB/2C digital input, the AD7664 offers two output –FSR + 1 LSB 38 µV0001 8001 codings: straight binary and twos complement. The LSB size is 2 2 –FSR 0 V 0000 8000 V /65536, which is about 38.15 µV. The ideal transfer charac- REF NOTES teristics for the AD7664 are shown in Figure 4 and Table II. 1 This is also the code for overrange analog input (V – V above IN INGND V – V ). REF REFGND 2 This is also the code for underrange analog input (V below V ). IN INGND 1 LSB = V /65536 REF TYPICAL CONNECTION DIAGRAM 111...111 Figure 5 shows a typical connection diagram for the AD7664. 111...110 111...101 000...010 000...001 000...000 0V 1 LSB V – 1 LSB REF 0.5 LSB V – 1.5 LSB REF ANALOG INPUT Figure 4. ADC Ideal Transfer Function ANALOG 100� DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) 10�F 100nF 10�F 100nF 100nF 10�F AVDD AGND DGND DVDD OVDD OGND SERIAL PORT SCLK 1 2.5V REF REF SDOUT 1 C 1�F REF REFGND BUSY �C/�P/DSP AD7664 CNVST 3 D 15� 2 U1 IN ANALOG INPUT OB/2C (0V TO 2.5V) SER/PAR DVDD C 4.7nF C WARP INGND IMPULSE PD RESET CS RD CLOCK NOTES 1 THE ADR421 IS RECOMMENDED WITH C = 47�F. REF 2 THE AD8021 IS RECOMMENDED WITH A COMPENSATION CAPACITOR C = 10 pF, TYPE CERAMIC NPO. C 3 OPTIONAL LOW JITTER CNVST. Figure 5. Typical Connection Diagram –12– REV. E ADC CODE – Straight Binary AD7664 Analog Input significantly affect the ac performances, especially the total Figure 6 shows an equivalent circuit of the input structure of harmonic distortion (THD). The maximum source impedance the AD7664. depends on the amount of THD that can be tolerated. The THD degrades in function of the source impedance and the AVDD maximum input frequency as shown in Figure 8. –70 D1 C2 R1 IN OR INGND R = 50� C1 –75 D2 AGND –80 Figure 6. Equivalent Analog Input Circuit R = 100� R = 11� –85 The two diodes D1 and D2 provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure –90 that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward- –95 biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, –100 these conditions could eventually occur when the input buffer’s 10 100 1000 (U1) supplies are different from AVDD. In such cases, an input FREQUENCY – kHz buffer with a short circuit current limitation can be used to Figure 8. THD vs. Analog Input Frequency and protect the part. Source Resistance This analog input structure allows the sampling of the differen- Driver Amplifier Choice tial signal between IN and INGND. Unlike other converters, Although the AD7664 is easy to drive, the driver amplifier needs the INGND input is sampled at the same time as the IN input. to meet at least the following requirements: By using this differential input, small signals common to both inputs are rejected, as shown in Figure 7, which represents the • The driver amplifier and the AD7664 analog input circuit typical CMRR over frequency. For instance, by using INGND must be able, together, to settle for a full-scale step of the to sense a remote signal ground, difference of ground potentials capacitor array at a 16-bit level (0.0015%). In the amplifier’s between the sensor and the local ADC ground are eliminated. data sheet, the settling at 0.1% to 0.01% is more commonly specified. It could significantly differ from the settling time at 70 16-bit level and it should, therefore, be verified prior to the driver selection. The tiny op amp AD8021, which combines 60 ultralow noise and a high gain bandwidth, meets this settling time requirement even when used with high gain up to 13. 50 • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition 40 noise performance of the AD7664. The noise coming from the driver is filtered by the AD7664 analog input circuit one- 30 pole low-pass filter made by R1 and C2 or the external filter, if 20 any is used. The SNR degradation due to the amplifier is: 10   0 1k 10k 100k 1M   28 FREQUENCY – Hz   SNR = 20 log LOSS   π 2 Figure 7. Analog Input CMRR vs. Frequency 784 + fNe ()  –3dB N  2   During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. where: Capacitor C1 is primarily the pin capacitance. The resistor R1 is typically 140 Ω and is a lumped component made up of some f is the –3 dB input bandwidth in MHz of the AD7664 –3 dB serial resistors and the on resistance of the switches. The capacitor (18 MHz) or the cutoff frequency of the input filter, if C2 is typically 60 pF and is mainly the ADC sampling capacitor. any used. During the conversion phase, where the switches are opened, the input N is the noise gain of the amplifier (1, if in buffer impedance is limited to C1. The R1, C2 makes a one-pole low-pass configuration). filter that reduces the undesirable aliasing effect and limits the noise. e is the equivalent input noise voltage of the op amp in N When the source impedance of the driving circuit is low, the nV/√Hz. AD7664 can be driven directly. Large source impedances will REV. E –13– CMRR – dB THD – dB AD7664 For instance, in a driver like the AD8021, with an equivalent (DVDD) can be supplied through a simple RC filter from the input noise of 2 nV/√Hz and configured as a buffer, thus with a analog supply as shown in Figure 5. The AD7664 is independent noise gain of 1, the SNR degrades by 0.58 dB. of power supply sequencing and thus free from supply voltage induced latch-up. Additionally, it is very insensitive to power supply • The driver needs to have a THD performance suitable to that variations over a wide frequency range, as shown in Figure 9. of the AD7664. TPC 12 gives the THD versus frequency that the driver should preferably exceed. POWER DISSIPATION VERSUS THROUGHPUT The AD8021 meets these requirements and is usually appropri- Operating currents are very low during the acquisition phase, which ate for almost all applications. The AD8021 needs an external allows significant power savings when the conversion rate is compensation capacitor of 10 pF. This capacitor should have reduced, as shown in Figure 10. This power saving depends on the good linearity as an NPO ceramic or mica type. mode used. In Impulse Mode, the AD7664 automatically reduces its power consumption at the end of each conversion phase. This The AD8022 could also be used where a dual version is needed feature makes the AD7664 ideal for very low power battery- and a gain of 1 is used. operated applications. It should be noted that the digital interface The AD829 is another alternative where high frequency (above remains active even during the acquisition phase. To reduce the 100 kHz) performance is not required. In a gain of 1, it requires operating digital supply currents even further, the digital inputs an 82 pF compensation capacitor. need to be driven close to the power supply rails (i.e., DVDD or The AD8610 is another option where low bias current is needed DGND for all inputs except EXT/INT, INVSYNC, INVSCLK, in low frequency applications. RDC/SDIN, and OVDD or OGND for these last four inputs). Voltage Reference Input –50 The AD7664 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7664 has a dynamic –55 input impedance; it should, therefore, be driven by a low imped- ance source with an efficient decoupling between REF and –60 REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a 1 µF ceramic capacitor and a low ESR tantalum capacitor connected to the REF and –65 REFGND inputs with minimum parasitic inductance. 47 µF is an appropriate value for the tantalum capacitor when used with one –70 of the recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 –75 voltage references –80 • The low power ADR291 voltage reference 1 10 100 1000 INPUT FREQUENCY – kHz • The low cost AD1582 voltage reference Figure 9. PSRR vs. Frequency For applications using multiple AD7664s, it is more effective to buffer the reference voltage with a low noise, very stable op amp 100k like the AD8031. WARP/NORMAL Care should also be taken with the reference temperature coeffi- 10k cient of the voltage reference that directly affects the full-scale accuracy, if this parameter matters. For instance, a ±15 ppm/°C 1k tempco of the reference changes the full scale by ±1 LSB/°C. V , as mentioned in the specification table, could be increased to REF 100 AVDD – 1.85 V. The benefit here is the increased SNR obtained IMPULSE as a result of this increase. Since the input range is defined in 10 terms of V , this would essentially increase the range to make it REF a 0 V to 3 V input range with an AVDD above 4.85 V. The 1 theoretical improvement as a result of this increase in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical quantization noise, however, the observed improvement is approximately 1 dB. The 0.1 0.1 1 10 100 1k 10k 100k 1M AD780 can be selected with a 3 V reference voltage. SAMPLING RATE – SPS Power Supply Figure 10. Power Dissipation vs. Sample Rate The AD7664 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core –14– REV. E POWER DISSIPATION – �W PSRR – dB AD7664 CONVERSION CONTROL DIGITAL INTERFACE Figure 11 shows the detailed timing diagrams of the conversion The AD7664 has a versatile digital interface; it can be interfaced process. The AD7664 is controlled by the signal CNVST, which with the host system by using either a serial or parallel interface. initiates conversion. Once initiated, it cannot be restarted or The serial interface is multiplexed on the parallel databus. The aborted, even by the power-down input PD, until the conver- AD7664 digital interface also accommodates both 3 V or 5 V logic sion is complete. The CNVST signal operates independently of by simply connecting the OVDD supply pin of the AD7664 to CS and RD signals. the host system interface digital supply. Finally, by using the OB/2C input pin, either twos complement or straight binary t 2 coding can be used. t 1 The two signals CS and RD control the interface. CS and RD CNVST have a similar effect, because they are OR’d together internally. When at least one of these signals is HIGH, the interface out- puts are in high impedance. Usually, CS allows the selection of each AD7664 in multicircuit applications and is held LOW in a BUSY t 4 single AD7664 design. RD is generally used to enable the con- t 3 version result on the databus. t 6 t 5 CS = RD = 0 MODE ACQUIRE CONVERT ACQUIRE CONVERT t 1 t t 7 8 CNVST Figure 11. Basic Conversion Timing t 10 In Impulse Mode, conversions can be automatically initiated. If BUSY CNVST is held LOW when BUSY is LOW, the AD7664 controls t 4 t the acquisition phase and then automatically initiates a new 3 t 11 conversion. By keeping CNVST LOW, the AD7664 keeps the conversion process running by itself. It should be noted that the DATA BUS PREVIOUS CONVERSION DATA NEW DATA analog input has to be settled when BUSY goes LOW. Also, at power-up, CNVST should be brought LOW once to initiate the Figure 13. Master Parallel Data Timing for Reading conversion process. In this mode, the AD7664 could sometimes (Continuous Read) run slightly faster then the guaranteed limits in the Impulse Mode of 444 kSPS. This feature does not exist in Warp or PARALLEL INTERFACE Normal Modes. The AD7664 is configured to use the parallel interface when the SER/PAR is held LOW. The data can be read either after t 9 each conversion, which is during the next acquisition phase, RESET or during the following conversion as shown, respectively, in Figures 14 and 15. When the data is read during the conversion, however, it is recommended that it be read-only during the first half of the conversion phase. This avoids any potential feed- BUSY through between voltage transients on the digital interface and the most critical analog conversion circuitry. DATABUS CS t 8 RD CNVST Figure 12. RESET Timing Although CNVST is a digital signal, it should be designed with BUSY special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. It is a good thing to shield the CNVST trace with ground and CURRENT DATABUS CONVERSION also to add a low value serial resistor (i.e., 50 Ω) termination t t 12 close to the output of the component that drives this line. 13 For applications where the SNR is critical, the CNVST signal Figure 14. Slave Parallel Data Timing for Reading should have a very low jitter. This may be achieved by using a (Read after Convert) dedicated oscillator for CNVST generation or, at least, to clock it with a high frequency, low jitter clock as shown in Figure 5. REV. E –15– AD7664 SERIAL INTERFACE CS = 0 t The AD7664 is configured to use the serial interface when the 1 CNVST, SER/PAR is held HIGH. The AD7664 outputs 16 bits of data, RD MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. BUSY t 4 MASTER SERIAL INTERFACE t 3 Internal Clock The AD7664 is configured to generate and provide the serial data PREVIOUS DATABUS clock SCLK when the EXT/INT pin is held LOW. The AD7664 CONVERSION also generates a SYNC signal to indicate to the host when the t t 12 13 serial data is valid. The serial clock SCLK and the SYNC signal can be inverted, if desired. Depending on RDC/SDIN input, Figure 15. Slave Parallel Data Timing for Reading the data can be read after each conversion or during the fol- (Read during Convert) lowing conversion. Figures 16 and 17 show the detailed timing diagrams of these two modes. EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 16. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) –16– REV. E AD7664 CS EXT/INT = 1 INVSCLK = 0 RD = 0 BUSY t 35 t t 36 37 SCLK 12 3 14 15 1617 18 t 31 t 32 X SDOUT D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 18. Slave Serial Data Timing for Reading (Read after Convert) Because the AD7664 is used with a fast throughput, the Mas- while both CS and RD are LOW. The data is shifted out, ter Read During Conversion Mode is the most often recom- MSB first, with 16 clock pulses and is valid on both the rising mended Serial Mode, when it can be used. In this mode, the and falling edge of the clock. serial clock and data toggle at appropriate instants that mini- Among the advantages of this method, the conversion perfor- mize potential feedthrough between digital activity and the mance is not degraded, because there are no voltage tran- critical conversion decisions. sients on the digital interface during the conversion process. In Read-after-Conversion Mode, it should be noted that, unlike Another advantage is the ability to read the data at any speed up to in other modes, the signal BUSY returns LOW after the 16 data 40 MHz, which accommodates both slow digital host interface bits are pulsed out and not at the end of the conversion phase, and the fastest serial reading. which results in a longer BUSY width. Finally, in this mode only, the AD7664 provides a daisy-chain feature using the RDC/SDIN input pin for cascading multiple SLAVE SERIAL INTERFACE converters together. This feature is useful for reducing component External Clock count and wiring connections when desired as, for instance, in The AD7664 is configured to accept an externally supplied isolated multiconverter applications. serial data clock on the SCLK pin when the EXT/INT pin is held HIGH. In this mode, several methods can be used to read An example of the concatenation of two devices is shown in the data. The external serial clock is gated by CS. When CS and Figure 19. Simultaneous sampling is possible by using a com- RD are both LOW, the data can be read after each conversion mon CNVST signal. It should be noted that the RDC/SDIN or during the following conversion. The external clock can be input is latched on the edge of SCLK opposite to the one used either a continuous or discontinuous clock. A discontinuous to shift out the data on SDOUT. Therefore, the MSB of the clock can be either normally HIGH or normally LOW, when upstream converter just follows the LSB of the downstream inactive. Figures 18 and 20 show the detailed timing diagrams of converter on the next SCLK cycle. these methods. BUSY While the AD7664 is performing a bit decision, it is important OUT that voltage transients not occur on digital input/output pins or BUSY BUSY degradation of the conversion result could occur. This is par- ticularly important during the second half of the conversion AD7664 AD7664 phase, because the AD7664 provides error correction circuitry #2 #1 (UPSTREAM) (DOWNSTREAM) that can correct for an improper bit decision made during the DATA RDC/SDIN SDOUT RDC/SDIN SDOUT first half of the conversion phase. For this reason, it is recom- OUT mended that when an external clock is being provided, it is a CNVST CNVST discontinuous clock that is toggling only when BUSY is LOW CS CS or, more importantly, that it does not transition during the latter SCLK SCLK half of BUSY HIGH. External Discontinuous Clock Data Read after Conversion SCLK IN Though the maximum throughput cannot be achieved using this CS IN mode, it is the most often recommended of the serial Slave CNVST IN Modes. Figure 18 shows the detailed timing diagrams of this Figure 19. Two AD7664s in a Daisy-Chain Configuration method. After a conversion is complete, indicated by BUSY returning LOW, the result of this conversion can be read REV. E –17– AD7664 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 SDOUT X D15 D14 D13 D1 D0 t 16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion SPI Interface (ADSP-219x) Figure 20 shows the detailed timing diagram of this method. Figure 21 shows an interface diagram between the AD7664 and During a conversion, while both CS and RD are LOW, the result an SPI-equipped ADSP-219x. To accommodate the slower speed of the previous conversion can be read. The data is shifted out of the DSP, the AD7664 acts as a slave device and data must be MSB first with 16 clock pulses, and is valid on both the rising and read after conversion. This mode also allows the daisy-chain falling edge of the clock. The 16 bits have to be read before the feature. The convert command can be initiated in response to current conversion is complete; otherwise, RDERROR is pulsed an internal timer interrupt. The reading process can be initi- HIGH and can be used to interrupt the host interface to ated in response to the end-of-conversion signal (BUSY going prevent incomplete data reading. There is no daisy-chain LOW) using an interrupt line of the DSP. The serial interface feature in this mode and RDC/SDIN input should always be tied (SPI) on the ADSP-219x is configured for master mode— either HIGH or LOW. (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00— by To reduce performance degradation due to digital activity, a fast writing to the SPI control register (SPICLTx). To meet all discontinuous clock of at least 18 MHz when in Impulse Mode, timing requirements, the SPI clock should be limited to 17 25 MHz when in Normal Mode, or 40 MHz when in Warp Mbps, which allows it to read an ADC result in less than 1 µs. Mode is recommended to ensure that all the bits are read during When a higher sampling rate is desired, use of one of the the first half of the conversion phase. It is also possible to begin parallel interface modes is recommended. to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. That allows the use of a slower clock speed such as 14 MHz in Impulse Mode, 18 MHz DVDD AD7664* ADSP-219x* in Normal Mode, and 25 MHz in Warp Mode. SER/PAR MICROPROCESSOR INTERFACING EXT/INT BUSY PFx The AD7664 is ideally suited for traditional dc measurement SPIxSEL (PFx) CS applications supporting a microprocessor and ac signal processing RD SDOUT MISOx applications interfacing to a digital signal processor. The AD7664 INVSCLK SCLK SCKx is designed to interface either with a parallel 8-bit or 16-bit wide CNVST PFx or TFSx interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used *ADDITIONAL PINS OMITTED FOR CLARITY with the AD7664 to prevent digital noise from coupling into the Figure 21. Interfacing the AD7664 to an SPI Interface ADC. The following section discusses the use of an AD7664 with an ADSP-219x SPI equipped DSP. –18– REV. E AD7664 APPLICATION HINTS It is recommended to avoid running digital lines under the Bipolar and Wider Input Ranges device, because these couple noise onto the die. The analog In some applications, it is desired to use a bipolar or wider ana- ground plane should be allowed to run under the AD7664 to avoid log input range like, for instance, ±10 V, ±5 V, or 0 V to 5 V. noise coupling. Fast switching signals like CNVST or clocks Although the AD7664 has only one unipolar range, by simple should be shielded with digital ground to avoid radiating modifications of the input driver circuitry, bipolar and wider noise to other sections of the board and should never run input ranges can be used without any performance degradation. near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the Figure 22 shows a connection diagram that allows this. board should run at right angles to each other. This reduces the Component values required and resulting full-scale ranges are effect of feedthrough through the board. shown in Table III. The power supplies’ lines to the AD7664 should use as large a For applications where accurate gain and offset are desired, they trace as possible to provide low impedance paths and reduce the can be calibrated by acquiring a ground and a voltage reference effect of glitches on the power supplies’ lines. Good decoupling using an analog multiplexer, U2, as shown for bipolar input is also important to lower the supplies’ impedance presented to ranges in Figure 22. the AD7664 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be R1 placed on each power supply’s pins AVDD, DVDD, and OVDD R2 close to, and ideally right up against, these pins and their corre- ANALOG 5� INPUT U1 IN sponding ground pins. Additionally, low ESR 10 µF capacitors 10nF should be located in the vicinity of the ADC to further reduce low frequency ripple. AD7664 U2 100nF R3 R4 The DVDD supply of the AD7664 can be either a separate supply or come from the analog supply AVDD or the digital interface INGND supply OVDD. When the system digital supply is noisy, or fast 2.5V REF REF switching digital signals are present, it is recommended that, if no C 1�F REF separate supply is available, to connect the DVDD digital supply to the analog supply, AVDD, through an RC filter, as shown REFGND in Figure 5, and to connect the system supply to the interface digital supply, OVDD, and the remaining digital circuitry. When Figure 22. Using the AD7664 in 16-Bit Bipolar and/or DVDD is powered from the system supply, it is useful to insert Wider Input Ranges a bead to further reduce high frequency spikes. The AD7664 has five different ground pins: INGND, REFGND, Table III. Component Values and Input Ranges AGND, DGND, and OGND. INGND is used to sense the Input Range R1 (k�) R2 (k�) R3 (k�) R4 (k�) analog input signal. REFGND senses the reference, voltage and should be a low impedance return to the reference because it ±10 V 1 8 10 8 carries pulsed currents. AGND is the ground to which most ±5 V 1 4 10 6.67 internal ADC analog signals are referenced. This ground must 0 V to –5 V 1 2 None 0 be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground Layout plane, depending on the configuration. OGND is connected to The AD7664 has very good immunity to noise on the power the digital system ground. supplies, as can be seen in Figure 9. However, care should still be taken with regard to grounding layout. Evaluating the AD7664 Performance A recommended layout for the AD7664 is outlined in the The printed circuit board that houses the AD7664 should be EVAL-AD7664 evaluation board for the AD7664. The evaluation designed so that the analog and digital sections are separated board package includes a fully assembled and tested evaluation and confined to certain areas of the board. This facilitates the board, documentation, and software for controlling the board use of ground planes that can be easily separated. Digital and from a PC via the EVAL-CONTROL-BRD2. analog ground planes should be joined in only one place, preferably underneath the AD7664, or, at least, as close as possible to the AD7664. If the AD7664 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7664. REV. E –19– AD7664 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 48 37 36 1 PIN 1 SEATING 10� PLANE TOP VIEW 7.00 1.45 6� 0.20 (PINS DOWN) BSC SQ 2� 1.40 0.09 1.35 VIEW A 7� 3.5� 25 12 0.15 0� 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90� CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 x7 mm Body (CP-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 BOTTOM TOP BSC SQ 5.10 SQ VIEW VIEW 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12� MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 –20– REV. E AD7664 Revision History Location Page 1/04—Data Sheet changed from REV. D to REV. E. Changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10/03—Data Sheet changed from REV. C to REV. D. Changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Added new TPC 2, 3, and 13 and renumbered successive TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to Circuit Information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Replaced MICROPROCESSOR INTERFACING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Deleted Figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Added CP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11/01—Data Sheet changed from REV. B to REV. C. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TPC 12 replaced with new data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edits to Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8/01 Revision History continued on next page REV. E –21– AD7664 Revision History Location Page 8/01—Data Sheet changed from REV. A to REV. B. Edit to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edit to Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edits to TPCs 7, 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edit to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edit to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edit to CONVERSION CONTROL section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edit to Voltage Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edit to External Clock section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Edit to Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Edit to Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Edits to Bipolar and Wider Input Range section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Edits to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Edit to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 –22– REV. E –23– –24– C02046–0–1/04(E)