ANALOG DEVICES AD7663

a 16-Bit, 250 kSPS CMOS ADC AD7663 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: 250 kSPS AVDD AGND REF REFGND DVDD DGND INL: �3 LSB Max (�0.0046% of Full Scale) 16-Bit Resolution with No Missing Codes 4R S/(N+D): 90 dB Typ @ 100 kHz IND(4R) AD7663 OVDD 4R THD: –100 dB Typ @ 100 kHz INC(4R) OGND 2R SERIAL Analog Input Voltage Ranges INB(2R) PORT R Bipolar: �10 V, �5 V, �2.5 V INA(R) SWITCHED SER/PAR Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V CAP DAC INGND BUSY Both AC and DC Specifications PARALLEL 16 D[15:0] No Pipeline Delay INTERFACE CLOCK Parallel (8/16 Bits) and Serial 5 V/3 V Interface PD CS ® SPI /QSPI™/MICROWIRE™/DSP Compatible RESET RD CONTROL LOGIC AND CALIBRATION CIRCUITRY Single 5 V Supply Operation OB/2C Power Dissipation BYTESWAP 35 mW Typical CNVST 15 �W @ 100 SPS Power-Down Mode: 7 �W Max Package: 48-Lead Quad Flatpack (LQFP) PulSAR Selection Package: 48-Lead Chip Scale (LFCSP) Pin-to-Pin Compatible with the AD7660/AD7664/AD7665 Type/kSPS 100–250 500–570 800–1000 APPLICATIONS Pseudo AD7660 AD7650 Data Acquisition Differential AD7664 Motor Control True Bipolar AD7663 AD7665 AD7671 Communication Instrumentation True Differential AD7675 AD7676 AD7677 Spectrum Analysis 18-Bit AD7678 AD7679 AD7674 Medical Instruments Process Control Simultaneous/ AD7654 AD7655 Multichannel GENERAL DESCRIPTION The AD7663 is a 16-bit, 250 kSPS, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power PRODUCT HIGHLIGHTS supply. It contains a high speed 16-bit sampling ADC, a resistor 1. Fast Throughput input scaler that allows various input ranges, an internal conver- The AD7663 is a 250 kSPS charge redistribution, 16-bit sion clock, error correction circuits, and both serial and parallel SAR ADC with various bipolar and unipolar input ranges. system interface ports. 2. Single-Supply Operation The AD7663 operates from a single 5 V supply and dissipates The AD7663 is hardware factory-calibrated and is comprehen- only 35 mW typical. Its power dissipation decreases with sively tested to ensure such ac parameters as signal-to-noise ratio the throughput to, for instance, only 15 µW at a 100 SPS (SNR) and total harmonic distortion (THD), in addition to the throughput. more traditional dc parameters of gain, offset, and linearity. It consumes 7 µW maximum when in power-down. It is fabricated using Analog Devices’ high performance, 0.6 micron 3. Superior INL CMOS process and is available in a 48-lead LQFP and a tiny The AD7663 has a maximum integral nonlinearity of 3 LSB 48-lead LFCSP with operation specified from –40°C to +85°C. with no missing 16-bit code. 4. Serial or Parallel Interface Versatile parallel (8 bits or 16 bits) or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. (–40 (–40� �C to +85 C to +85� �C, AVDD = DVDD = 5 V, OVDD = C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise 2.7 V to 5.25 V, unless otherwise noted noted. .) ) AD7663–SPECIFICATIONS Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V ±4 REF, 0 V to 4 REF, ±2 REF (See Table I) IND INGND Common-Mode Input Voltage V –0.1 +0.5 V INGND Analog Input CMRR f = 45 kHz 62 dB IN Input Impedance See Table I THROUGHPUT SPEED Complete Cycle 4µs Throughput Rate 0 250 kSPS DC ACCURACY 1 Integral Linearity Error –3+3 LSB No Missing Codes 16 Bits Transition Noise 0.7 LSB 2 Bipolar Zero Error , T to T ±5 V Range –25 +25 LSB MIN MAX Other Range –0.06 +0.06 % of FSR 2 Bipolar Full-Scale Error , T to T –0.25 +0.25 % of FSR MIN MAX 2 Unipolar Zero Error , T to T –0.18 +0.18 % of FSR MIN MAX 2 Unipolar Full-Scale Error , T to T –0.38 +0.38 % of FSR MIN MAX Power Supply Sensitivity AVDD = 5 V ±5% ±0.1 LSB AC ACCURACY 3 Signal-to-Noise f = 10 kHz 89 90 dB IN f = 100 kHz 90 dB IN Spurious-Free Dynamic Range f = 100 kHz 100 dB IN Total Harmonic Distortion f = 100 kHz –100 dB IN Signal-to-(Noise+Distortion) f = 10 kHz 88.5 90 dB IN f = 100 kHz, –60 dB Input 30 dB IN –3 dB Input Bandwidth 800 kHz SAMPLING DYNAMICS Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 2.75 µs REFERENCE External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 250 kSPS Throughput 50 µA DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V +2.0 DVDD + 0.3 V IH I –1+1µA IL I –1+1µA IH DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bit Pipeline Delay Conversion Results Available Immediately after Completed Conversion V I = 1.6 mA 0.4 V OL SINK V I = –500 µA OVDD – 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 4 OVDD 2.7 5.25 V Operating Current 250 kSPS Throughput AVDD 5mA 5 DVDD 1.8 mA 5 OVDD 10 µA 6 5 Power Dissipation 250 kSPS Throughput 35 41 mW 5 100 SPS Throughput 15 µW 7 In Power-Down Mode 7µW –2– REV. B AD7663 Parameter Conditions Min Typ Max Unit 8 TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX NOTES 1 LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 5 Tested in Parallel Reading Mode. 6 Tested with the 0 V to 5 V range and V – V = 0 V. See Power Dissipation section. IN INGND 7 With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively. 8 Contact factory for extended temperature range. Specifications subject to change without notice. Table I. Analog Input Configuration Input Voltage Input 1 Range IND(4R) INC(4R) INB(2R) INA(R) Impedance 2 ±4 REF V INGND INGND REF 5.85 kW IN ±2 REF V V INGND REF 3.41 kW IN IN ±REF V V V REF 2.56 kW IN IN IN 0 V to 4 REF V V INGND INGND 3.41 kW IN IN 0 V to 2 REF V V V INGND 2.56 kW IN IN IN 0 V to REF V V V V Note 3 IN IN IN IN NOTES 1 Typical analog input impedance. 2 With REF = 3 V, in this range, the input should be limited to –11 V to +12 V. 3 For this range the input is high impedance. (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit Refer to Figures 11 and 12 Convert Pulsewidth t5ns 1 Time between Conversions t4µs 2 CNVST LOW to BUSY HIGH Delay t 30 ns 3 BUSY HIGH All Modes Except in t 1.25 µs 4 Master Serial Read after Convert Mode Aperture Delay t 2ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 1.25 µs 7 Acquisition Time t 2.75 µs 8 RESET Pulsewidth t 10 ns 9 Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t 1.25 µs 10 DATA Valid to BUSY LOW Delay t 20 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t515ns 13 1 Refer to Figures 17 and 18 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t 10 ns 16 CNVST LOW to SYNC Delay (Read during Convert) t 0.5 µs 17 2 SYNC Asserted to SCLK First Edge Delay t4ns 18 2 Internal SCLK Period t 25 40 ns 19 2 Internal SCLK HIGH t 15 ns 20 2 Internal SCLK LOW t 9.5 ns 21 2 SDOUT Valid Setup Time t 4.5 ns 22 2 SDOUT Valid Hold Time t2ns 23 2 SCLK Last Edge to SYNC Delay t3ns 24 REV. B –3– AD7663 TIMING SPECIFICATIONS (continued) Parameter Symbol Min Typ Max Unit 1 Refer to Figures 17 and 18 (Master Serial Interface Modes) CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t 10 ns 27 BUSY HIGH in Master Serial Read after Convert t See Table II µs 28 CNVST LOW to SYNC Asserted Delay t 1.25 µs 29 (Master Serial Read after Convert) SYNC Deasserted to BUSY LOW Delay t 25 ns 30 Refer to Figures 19 and 21 (Slave Serial Interface Modes) External SCLK Setup Time t5ns 31 External SCLK Active Edge to SDOUT Delay t316ns 32 SDIN Setup Time t5ns 33 SDIN Hold Time t5ns 34 External SCLK Period t 25 ns 35 External SCLK HIGH t 10 ns 36 External SCLK LOW t 10 ns 37 NOTES 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 2 In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode. Specifications subject to change without notice. Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0011 DIVSCLK[0] 0101 Unit SYNC to SCLK First Edge Delay Minimum t 420 2020 ns 18 Internal SCLK Period Minimum t 25 50 100 200 ns 19 Internal SCLK Period Maximum t 40 70 140 280 ns 19 Internal SCLK HIGH Minimum t 15 25 50 100 ns 20 Internal SCLK LOW Minimum t 9.5 24 49 99 ns 21 SDOUT Valid Setup Time Minimum t 4.5 22 22 22 ns 22 SDOUT Valid Hold Time Minimum t 2430 90 ns 23 SCLK Last Edge to SYNC Delay Minimum t 360 140 300 ns 24 BUSY HIGH Width Maximum t 2 2.5 3.5 5.75 µs 28 1.6mA I OL TO OUTPUT 1.4V PIN C L 60pF* I 2V 500�A OH 0.8V t t *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND DELAY DELAY SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD 2V 2V C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L 0.8V 0.8V Figure 1. Load Circuit for Digital Interface Timing Figure 2. Voltage Reference Levels for Timing –4– REV. B AD7663 1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Analog Inputs ST-48 and CP-48 2 2 2 IND , INC , INB . . . . . . . . . . . . . . . . . . . . –11 V to +30 V INA, REF, INGND, REFGND . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to AVDD + 0.3 V Ground Voltage Differences 48 47 46 45 44 43 42 41 40 39 38 37 AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V AGND 1 Supply Voltages 36 AGND PIN 1 IDENTIFIER AVDD 2 35 CNVST AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V NC 3 34 PD AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ±7 V BYTESWAP 4 33 RESET DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V OB/2C 5 32 CS AD7663 Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V NC 6 31 RD 3 TOP VIEW 7 NC 30 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . 700 mW DGND (Not to Scale) 4 SER/PAR 8 29 BUSY Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 2.5 W D0 9 28 D15 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C 10 D1 27 D14 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C D2/DIVSCLK[0] 11 26 D13 Lead Temperature Range D3/DIVSCLK[1] 12 25 D12 (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Inputs section. 3 Specification is for device in free air: 48-Lead LQFP: q = 91°C/W, q = 30°C/W. JA JC 4 Specification is for device in free air: 48-Lead LFCSP: q = 26�C/W. JC ORDERING GUIDE Model Temperature Range Package Description Package Option AD7663AST –40°C to +85°CQuad Flatpack (LQFP) ST-48 AD7663ASTRL –40°C to +85°CQuad Flatpack (LQFP) ST-48 AD7663ACP –40�C to +85�CChip Scale (LFCSP) CP-48 AD7663ACPRL –40�C to +85�CChip Scale (LFCSP) CP-48 1 EVAL-AD7663CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7663 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– D4/EXT/INT NC D5/INVSYNC NC D6/INVSCLK NC D7/RDC/SDIN NC OGND NC OVDD IND(4R) DVDD INC(4R) DGND INB(2R) D8/SDOUT INA(R) D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF AD7663 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 6, 7, NC No Connect. 44–48 4 BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the Data bus are used as a Serial Port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these pins are high impedance outputs. 13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock, called respectively, Master and Slave Modes. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input, and external clock is gated by CS. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both master and slave mode. 16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. –6– REV. B AD7663 PIN FUNCTION DESCRIPTION (continued) Pin No. Mnemonic Type Description 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7663 provides the conversion result, MSB first, from its internal shift register. The Data format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7663. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t ) is complete, the next falling 8 edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t ) is complete, the internal sample-and-hold is put into the hold state and a 8 conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage . 38 REFGND AI Reference Input Analog Ground. 39 INGND AI Analog Input Ground. 40, 41, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration. 42, 43 INC, IND NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power REV. B –7– AD7663 DEFINITION OF SPECIFICATIONS Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL) A measurement of the resolution with a sine wave input. It is Linearity error refers to the deviation of each individual code related to S/(N+D) by the following formula: from a line drawn from “negative full scale” through “positive ENOB=+ S N D -17.. 6 602 ) () [] dB full scale.” The point used as negative full scale occurs 1/2 LSB and is expressed in bits. before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is Total Harmonic Distortion (THD) measured from the middle of each code to the true straight line. The ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-Noise Ratio (SNR) nonlinearity is the maximum deviation from this ideal value. It is The ratio of the rms value of the actual input signal to the rms often specified in terms of resolution for which no missing codes sum of all other spectral components below the Nyquist fre- are guaranteed. quency, excluding harmonics and dc. The value for SNR is expressed in decibels. Full-Scale Error The last transition (from 011 . . . 10 to 011 ... 11 in twos Signal-to-(Noise + Distortion) Ratio (S/[N+D]) complement coding) should occur for an analog voltage 1 1/2 LSB The ratio of the rms value of the actual input signal to the below the nominal full scale (2.499886 V for the ±2.5 V range). rms sum of all other spectral components below the Nyquist The full-scale error is the deviation of the actual level of the last frequency, including harmonics but excluding dc. The value for transition from the ideal level. S/(N+D) is expressed in decibels. Bipolar Zero Error Aperture Delay The difference between the ideal midscale input voltage (0 V) and A measure of the acquisition performance measured from the the actual voltage producing the midscale output code. falling edge of the CNVST input to when the input signal is held for a conversion. Unipolar Zero Error In Unipolar Mode, the first transition should occur at a level Transient Response 1/2 LSB above analog ground. The unipolar zero error is the The time required for the AD7663 to achieve its rated accuracy deviation of the actual transition from that point. after a full-scale step function is applied to its input. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. –8– REV. B Typical Performance Characteristics–AD7663 3.0 8000 2.5 6802 6745 7000 2.0 1.5 6000 1.0 5000 0.5 0 4000 –0.5 3000 –1.0 1800 –1.5 2000 –2.0 1000 1000 –2.5 00 33 40 0 –3.0 0 0 16384 32768 49152 65536 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8004 8005 CODE CODE IN HEXA TPC 1. Integral Nonlinearity vs. Code TPC 4. Histogram of 16,384 Conversions of a DC Input at the Code Transition 50 9000 8032 45 8000 40 7000 35 6000 30 5000 25 3944 3902 4000 20 3000 15 2000 10 1000 5 233 271 00 2 00 0 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.1 2.7 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 POSITIVE INL – LSB CODE IN HEXA TPC 2. Typical Positive INL Distribution (446 Units) TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Center 80 –0 4096 POINT FFT FS = 250kHz –20 70 f = 45kHz, –0.5dB IN SNR = 90.1dB –40 60 SINAD = 89.8dB THD = –100.5dB –60 SFDR = 102.7dB 50 –80 40 –100 30 –120 20 –140 10 –160 0 –180 –3 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3 0 25 50 75 100 125 FREQUENCY – kHz NEGATIVE INL – LSB TPC 3. Typical Negative INL Distribution (446 Units) TPC 6. FFT Plot REV. B –9– INL – LSB NUMBER OF UNITS NUMBER OF UNITS COUNTS AMPLITUDE – dB OF FULL SCALE COUNTS AD7663 100 16.0 –60 110 –65 105 95 15.5 SFDR –70 100 SNR –75 95 90 15.0 –80 SINAD 90 –85 85 14.5 85 –90 80 –95 14.0 80 THD SECOND HARMONIC 75 –100 ENOB 70 –105 13.5 75 65 –110 THIRD HARMONIC 13.0 70 –115 60 1 10 100 1000 1 10 100 1000 FREQUENCY – kHz FREQUENCY – kHz TPC 7. SNR, S/(N+D), and ENOB vs. Frequency TPC 10. THD, Harmonics, and SFDR vs. Frequency 92 –60 –70 –80 –90 90 –100 THD –110 –120 88 –130 THIRD HARMONIC SECOND HARMONIC –140 –150 –160 86 –80 –70 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0 INPUT LEVEL – dB INPUT LEVEL – dB TPC 8. SNR vs. Input Level TPC 11. THD, Harmonics vs. Input Level 96 –98 50 THD 40 93 –100 30 90 SNR 20 –102 87 10 84 –104 0 –55 –35 –15 5 25 45 65 85 105 125 050 100 150 200 C – pF TEMPERATURE – �C L TPC 9. SNR and THD vs. Temperature TPC 12. Typical Delay vs. Load Capacitance, C L –10– REV. B SNR AND S/[N+D] – dB SNR – dB SNR – (REFERRED TO FULL SCALE) – dB ENOB – Bits THD – dB THD, HARMONICS – dB THD, HARMONICS – dB t DELAY – ns 12 SFDR – dB AD7663 100000 CIRCUIT INFORMATION The AD7663 is a fast, low power, single-supply, precise 16-bit 10000 analog-to-digital converter (ADC). The AD7663 is capable of AVDD converting 250,000 samples per second (250 kSPS) and allows 1000 power saving between conversions. When operating at 100 SPS, 100 for example, it consumes typically only 15 µW. This feature DVDD makes the AD7663 ideal for battery-powered applications. 10 The AD7663 provides the user with an on-chip track-and-hold, 1 successive approximation ADC that does not exhibit any pipeline OVDD or latency, making it ideal for multiple multiplexed channel 0.1 applications. 0.01 It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. 0.001 1 10 100 1000 10000 100000 1000000 The AD7663 can be operated from a single 5 V supply and can be SAMPLING RATE – SPS interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead TPC 13. Operating Currents vs. Sample Rate LQFP package or a 48-lead LFCSP package that combines space savings and flexible configurations as either serial or parallel inter- face. The AD7663 is pin-to-pin compatible with the AD7660. 500 CONVERTER OPERATION 450 The AD7663 is a successive approximation analog-to-digital 400 converter based on a charge redistribution DAC. Figure 3 shows 350 the simplified schematic of the ADC. The input analog signal is DVDD first scaled down and level shifted by the internal input resistive 300 scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V, 250 and 0 V to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V). 200 The output voltage range of the resistive scaler is always 0 V to 2.5 V. The capacitive DAC consists of an array of 16 binary 150 weighted capacitors and an additional “LSB” capacitor. The OVDD 100 AVDD comparator’s negative input is connected to a “dummy” capacitor 50 of the same value as the capacitive DAC array. 0 During the acquisition phase, the common terminal of the array –55 –35 –15 5 25 45 65 85 105 tied to the comparator’s positive input is connected to AGND TEMPERATURE – �C via SW . All independent switches are connected to the output A TPC 14. Power-Down Operating Currents vs. Temperature of the resistive scaler. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal. Similarly, the dummy capacitor acquires the analog signal on INGND input. 10 When the acquisition phase is complete and the CNVST input 8 goes or is LOW, a conversion phase is initiated. When the conver- 6 sion phase begins, SW and SW are opened first. The capacitor A B array and the dummy capacitor are then disconnected from the 4 –FS OFFSET inputs and connected to the REFGND input. Therefore, the differ- 2 ential voltage between the output of the resistive scaler and INGND 0 +FS captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. –2 By switching each element of the capacitor array between –4 REFGND or REF, the comparator input varies by binary –6 weighted voltage steps (V /2, V /4 . ..V /65,536). The REF REF REF –8 control logic toggles these switches, starting with the MSB first, –10 in order to bring the comparator back into a balanced condition. –55 –35 –15 5 25 456585105 125 After the completion of this process, the control logic generates TEMPERATURE – �C the ADC output code and brings the BUSY output LOW. TPC 15. +FS, Offset, and –FS vs. Temperature REV. B –11– OPERATING CURRENTS – �A POWER-DOWN OPERATING CURRENTS – nA LSB AD7663 4R IND REF 4R REFGND INC SWITCHES CONTROL 2R MSB SW LSB A INB 32,768C 16,384C 4C 2C CC R BUSY INA CONTROL COMP LOGIC INGND OUTPUT 65,536C CODE SW B CNVST Figure 3. ADC Simplified Schematic Transfer Functions Using the OB/2C digital input, the AD7663 offers two output codings: straight binary and twos complement. The ideal transfer 111...111 characteristic for the AD7663 is shown in Figure 4 and Table III. 111...110 111...101 TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7663. Different circuitry shown on this diagram is optional and is discussed in the figure’s notes. Analog Inputs 000...010 The AD7663 is specified to operate with six full-scale analog 000...001 input ranges. Connections required for each of the four analog 000...000 inputs, IND, INC, INB, and INA, and the resulting full-scale –FS –FS + 1 LSB +FS – 1 LSB ranges are shown in Table I. The typical input impedance for –FS + 0.5 LSB +FS – 1.5 LSB each analog input range is also shown. ANALOG INPUT Figure 4. ADC Ideal Transfer Function Table III. Output Codes and Ideal Input Voltages Digital Output Code (Hexa) Straight Twos Description Analog Input Binary Complement 1 Full-Scale Range ±10 V ±5 V ±2.5 V 0 V to 10 V 0 V to 5 V 0 V to 2.5 V Least Significant Bit 305.2 µV 152.6 µV 76.3 µV 152.6 µV 76.3 µV 38.15 µV 2 2 FSR – 1 LSB 9.999695 V 4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF 7FFF Midscale + 1 LSB 305.2 µV 152.6 µV 76.3 µV 5.000153 V 2.570076 V 1.257038 V 8001 0001 Midscale 0 V 0 V 0 V 5 V 2.5 V 1.25 V 8000 0000 Midscale – 1 LSB –305.2 µV –152.6 µV –76.3 µV 4.999847 V 2.499924 V 1.249962 V 7FFF FFFF –FSR + 1 LSB –9.999695 V –4.999847 V –2.499924 V 152.6 µV 76.3 µV 38.15 µV 0001 8001 3 3 –FSR –10 V –5 V –2.5 V 0 V 0 V 0 V 0000 8000 NOTES 1 Values with REF = 2.5 V, with REF = 3 V, all values will scale linearly. 2 This is also the code for an overrange analog input. 3 This is also the code for an underrange analog input. –12– REV. B ADC CODE – Straight Binary AD7663 DVDD ANALOG 100� DIGITAL SUPPLY SUPPLY (3.3V OR 5V) NOTE 7 + (5V)++ 100nF 10�F 10�F 100nF 10�F 100nF ADR421 AVDD AGND DGND DVDD OVDD OGND SERIAL REF PORT 2.5V REF SCLK 1M� + NOTE 1 C 50k� REF SDOUT NOTE 2 100nF REFGND BUSY NOTE 3 50� �C/�P/DSP D CNVST AD7663 U2 INA + NOTE 8 + 10�F 100nF AD8031 OB/2C NOTE 4 DVDD 50� SER/PAR CLOCK 15� U1 NOTE 5 IND ANALOG + INPUT 2.7nF CS (�10V) AD8021 NOTE RD 6 C C BYTESWAP INGND RESET INB PD INC NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C IS 47�F. SEE VOLTAGE REFERENCE INPUT SECTION. REF 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. FOR BIPOLAR RANGE ONLY. SEE SCALER REFERENCE INPUT SECTION. 5. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 6. WITH 0V TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION. 7. OPTION. SEE POWER SUPPLY SECTION. 8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION. Figure 5. Typical Connection Diagram (±10 V Range Shown) Figure 6 shows a simplified analog input section of the AD7663. The diodes shown in Figure 6 provide ESD protection for the four analog inputs. The inputs INB, INC, and IND have a high voltage AVDD protection (–11 V to +30 V) to allow wide input voltage range. Care must be taken to ensure that the analog input signal never 4R exceeds the absolute ratings on these inputs, including INA IND (0 V to 5 V). This will cause these diodes to become forward- 4R INC biased and start conducting current. These diodes can handle a R1 2R forward-biased current of 120 mA maximum. For instance, when INB R C using the 0 V to 2.5 V input range, these conditions could even- S INA tually occur on the input INA when the input buffer’s (U1) supplies are different from AVDD. In such cases, an input buffer with a R = 1.28k� short-circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential AGND signal between the output of the resistive scaler and INGND. Unlike Figure 6. Simplified Analog Input other converters, the INGND input is sampled at the same time as the inputs. By using this differential input, small signals common The four resistors connected to the four analog inputs form a resis- to both inputs are rejected as shown in Figure 7, which represents tive scaler that scales down and shifts the analog input range to a the typical CMRR over frequency. For instance, by using INGND common input range of 0 V to 2.5 V at the input of the switched to sense a remote signal ground, the difference of ground potentials capacitive ADC. between the sensor and the local ADC ground is eliminated. By connecting the four inputs INA, INB, INC, and IND to the input signal itself, the ground, or a 2.5 V reference, other analog input ranges can be obtained. REV. B –13– AD7663 75 Driver Amplifier Choice Although the AD7663 is easy to drive, the driver amplifier needs 70 to meet at least the following requirements: 65 • The driver amplifier and the AD7663 analog input circuit have to be able, together, to settle for a full-scale step of the 60 capacitor array at a 16-bit level (0.0015%). In the amplifier’s 55 data sheet, the settling at 0.1% to 0.01% is more commonly specified. It could significantly differ from the settling time at 50 16-bit level and, therefore, it should be verified prior to the driver selection. The tiny op amp AD8021, which combines 45 ultralow noise and a high gain bandwidth, meets this settling 40 time requirement even when used with a high gain up to 13. • The noise generated by the driver amplifier needs to be kept 35 0 10 100 1000 as low as possible in order to preserve the SNR and transition FREQUENCY – kHz noise performance of the AD7663. The noise coming from the driver is first scaled down by the resistive scaler according Figure 7. Analog Input CMRR vs. Frequency to the analog input voltage range used, and is then filtered by During the acquisition phase for ac signals, the AD7663 behaves the AD7663 analog input circuit one-pole, low-pass filter like a one-pole RC filter consisting of the equivalent resistance of made by (R/2 + R1) and C . The SNR degradation due to S the resistive scaler R/2 in series with R1 and C . The resistor R1 S the amplifier is is typically 2700 W and is a lumped component made up of some serial resistors and the on-resistance of the switches. The capacitor Ê ˆ C is typically 60 pF and is mainly the ADC sampling capacitor. S Á ˜ This one-pole filter with a typical –3 dB cutoff frequency of Á 28 ˜ 800 kHz reduces undesirable aliasing effects and limits the noise SNR = 20 log LOSS Á ˜ 2 coming from the inputs. Ê25 . Ne ˆ Á p ˜ N 784 + f Á ˜ –3dB Á ˜ Except when using the 0 V to 2.5 V analog input voltage range, 2 Ë FSR ¯ Ë ¯ the AD7663 has to be driven by a very low impedance source to avoid gain errors. That can be done by using a driver amplifier where: whose choice is eased by the primarily resistive analog input f is the –3 dB input bandwidth in MHz of the AD7663 –3 dB circuitry of the AD7663. (0.8 MHz) or the cut-off frequency of the input filter When using the 0 V to 2.5 V analog input voltage range, the input if any used (0 V to 2.5 V range). impedance of the AD7663 is very high so the AD7663 can be N is the noise factor of the amplifier (1 if in buffer driven directly by a low impedance source without gain error. configuration). That allows, as shown in Figure 5, putting an external one-pole e is the equivalent input noise voltage of the op amp RC filter between the output of the amplifier output and the ADC N 1/2 analog inputs to even further improve the noise filtering by the in nV/Hz . AD7663 analog input circuit. However, the source impedance FSR is the full-scale span (i.e., 5 V for ±2.5 V range). has to be kept low because it affects the ac performances, especially For instance, when using the 0 V to 2.5 V range, a driver the total harmonic distortion (THD). The maximum source like the AD8610 with an equivalent input noise of 6 nV/÷Hz impedance depends on the amount of THD that can be tolerated. and configured as a buffer, thus with a noise gain of 1, the The THD degradation is a function of the source impedance SNR degrades by only 0.24 dB. and the maximum input frequency as shown in Figure 8. • The driver needs to have a THD performance suitable to –70 that of the AD7663. TPC 10 gives the THD versus frequency that the driver should preferably exceed. The AD8021 meets these requirements and is usually appropri- –80 ate for almost all applications. The AD8021 needs an external compensation capacitor of 10 pF. This capacitor should have good R = 100� linearity as an NPO ceramic or mica type. –90 R = 50� The AD8022 could also be used where a dual version is needed and gain of 1 is used. R = 11� The AD829 is another alternative where high frequency (above –100 100 kHz) performance is not required. In a gain of 1, it requires an 82 pF compensation capacitor. The AD8610 is also another option where low bias current is –110 10 100 1000 needed in low frequency applications. FREQUENCY – kHz Figure 8. THD vs. Analog Input Frequency and Input Resistance (0 V to 2.5 V Only) –14– REV. B CMRR – dB THD AD7663 Voltage Reference Input Power Supply The AD7663 uses an external 2.5 V voltage reference. The AD7663 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital The voltage reference input REF of the AD7663 has a dynamic input/output interface supply OVDD. The OVDD supply allows input impedance; it should therefore be driven by a low impedance direct interface with any logic working between 2.7 V and DVDD source with an efficient decoupling between REF and REFGND + 0.3 V. To reduce the number of supplies needed, the digital inputs. This decoupling depends on the choice of the voltage core (DVDD) can be supplied through a simple RC filter from the reference but usually consists of a 1 µF ceramic capacitor and a analog supply as shown in Figure 5. The AD7663 is independent low ESR tantalum capacitor connected to the REF and REFGND of power supply sequencing, once OVDD does not exceed DVDD inputs with minimum parasitic inductance. 47 µF is an appropriate by more than 0.3 V, and thus free from supply voltage induced value for the tantalum capacitor when used with one of the latch-up. Additionally, it is very insensitive to power supply recommended reference voltages: variations over a wide frequency range as shown in Figure 9. • The low noise, low temperature drift ADR421 and AD780 110 voltage reference 105 • The low power ADR291 voltage reference 100 • The low cost AD1582 voltage reference 95 90 For applications using multiple AD7663s, it is more effective to 85 buffer the reference voltage with a low noise, very stable op amp 80 like the AD8031. 75 Care should also be taken with the reference temperature coefficient 70 of the voltage reference that directly affects the full-scale accu- 65 racy if this parameter matters. For instance, a ±15 ppm/°C 60 tempco of the reference changes the full scale by ±1 LSB/°C. 55 Note that V , as mentioned in the Specification tables, could be REF 50 increased to AVDD – 1.85 V. The benefit here is the increased 1 10 100 1000 SNR obtained as a result of this increase. Since the input range is FREQUENCY – kHz defined in terms of V , this would essentially increase the ±REF REF Figure 9. PSRR vs. Frequency range from ±2.5 V to ±3 V and so on with an AVDD above 4.85 V. The theoretical improvement as a result of this increase POWER DISSIPATION in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical The AD7663 automatically reduces its power consumption at quantization noise, however, the observed improvement is approxi- the end of each conversion phase. During the acquisition phase, mately 1 dB. The AD780 can be selected with a 3 V reference the operating currents are very low, which allows a significant voltage. power savings when the conversion rate is reduced as shown in Scaler Reference Input (Bipolar Input Ranges) Figure 10. This feature makes the AD7663 ideal for very low When using the AD7663 with bipolar input ranges, the connection power battery applications. diagram in Figure 5 shows a reference buffer amplifier. This This does not take into account the power, if any, dissipated by buffer amplifier is required to isolate the REF pin from the signal the input resistive scaler that depends on the input voltage range dependent current in the INx pin. A high speed op amp, such as used and the analog input voltage even in power-down mode. the AD8031, can be used with a single 5 V power supply with- There is no power dissipated when the 0 V to 2.5 V is used or out degrading the performance of the AD7663. The buffer must when both the analog input voltage is 0V and a unipolar range, have good settling characteristics and provide low total noise 0V to 5 V or 0 V to 10 V, is used. within the input bandwidth of the AD7663. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V. REV. B –15– PSRR – dB AD7663 100k For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7663 controls 10k the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7663 keeps the conversion process running by itself. It should be noted that the 1k analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the 100 conversion process. In this mode, the AD7663 could sometimes run slightly faster than the guaranteed limit of 250 kSPS. 10 t 9 1 RESET 0.1 1 10 100 1k 10k 100k 1M SAMPLING RATE – SPS BUSY Figure 10. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion DATA BUS process. The AD7663 is controlled by the signal CNVST, which initiates conversion. Once initiated, it cannot be restarted or t 8 aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and CNVST RD signals. Figure 12. RESET Timing t 2 DIGITAL INTERFACE t 1 The AD7663 has a versatile digital interface; it can be interfaced CNVST with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7663 digital interface also accommodates both 3 V or 5 V BUSY logic by simply connecting the OVDD supply pin of the AD7663 t 4 to the host system interface digital supply. Finally, by using the t 3 t 6 OB/2C input pin, twos complement and straight binary coding t 5 can be used. MODE ACQUIRE CONVERT ACQUIRE CONVERT The two signals CS and RD control the interface. When at least t t one of these signals is HIGH, the interface outputs are in high 7 8 impedance. Usually, CS allows the selection of each AD7663 in Figure 11. Basic Conversion Timing multicircuit applications and is held LOW in a single AD7663 design. RD is generally used to enable the conversion result on For a true sampling application, the recommended operation of the data bus. the CNVST signal is the following. CNVST must be held HIGH from the previous falling edge of CS = RD = 0 BUSY and during a minimum delay corresponding to the acquisi- t 1 tion time t . Then, when CNVST is brought LOW, a conversion is 8 CNVST initiated and the BUSY signal goes HIGH until the completion of the conversion. Although CNVST is a digital signal, it should t 10 be designed with special care with fast, clean edges, and levels BUSY with minimum overshoot and undershoot or ringing. It is a good t 4 t 3 thing to shield the CNVST trace with ground and also to add a t 11 low value serial resistor (i.e., 50 W) termination close to the output of the component that drives this line. For applications where DATA BUS PREVIOUS CONVERSION DATA NEW DATA the SNR is critical, the CNVST signal should have a very low jitter. To achieve this, some use a dedicated oscillator for Figure 13. Master Parallel Data Timing for Reading CNVST generation, or at least to clock it with a high frequency, (Continuous Read) low jitter clock as shown in Figure 5. –16– REV. B POWER DISSIPATION – �W AD7663 PARALLEL INTERFACE CS The AD7663 is configured to use the parallel interface when the SER/PAR is held LOW. The data can be read either after RD each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figures 14 and 15. When the data is read during the conversion, BYTE however, it is recommended that it be read-only during the first half of the conversion phase. That avoids any potential HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE feedthrough between voltage transients on the digital interface and t t t the most critical analog conversion circuitry. 12 12 13 HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE CS Figure 16. 8-Bit Parallel Interface RD SERIAL INTERFACE The AD7663 is configured to use the serial interface when the SER/PAR is held HIGH. The AD7663 outputs 16 bits of data, BUSY MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data CURRENT DATA BUS CONVERSION is valid on both the rising and falling edge of the data clock. t t 12 13 MASTER SERIAL INTERFACE Figure 14. Slave Parallel Data Timing for Reading (Read Internal Clock after Convert) The AD7663 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. It also generates a SYNC signal to indicate to the host when the serial data is valid. CS = 0 The serial clock SCLK and the SYNC signal can be inverted if t desired. Depending on RDC/SDIN input, the data can be read 1 CNVST, after each conversion or during the following conversion. Figures 17 RD and 18 show the detailed timing diagrams of these two modes. Usually, because the AD7663 has a longer acquisition phase BUSY t 4 than the conversion phase, the data is read immediately after t conversion. That makes the mode master, read after conversion, 3 the most recommended Serial Mode when it can be used. PREVIOUS In Read-during-Conversion Mode, the serial clock and data DATA BUS CONVERSION toggle at appropriate instants that minimize potential feedthrough t t 12 13 between digital activity and the critical conversion decisions. In Read-after-Conversion Mode, it should be noted that unlike Figure 15. Slave Parallel Data Timing for Reading (Read in other modes, the signal BUSY returns LOW after the 16 data during Convert) bits are pulsed out and not at the end of the conversion phase, The BYTESWAP pin allows a glueless interface to an 8-bit bus. which results in a longer BUSY width. In this mode, if neces- As shown in Figure 16, the LSB byte is output on D[7:0] and sary, the internal clock can be slowed down by a ratio selected the MSB is output on D[15:8] when BYTESWAP is LOW. by the DIVSCLK inputs according to Table II. When BYTESWAP is HIGH, the LSB and MSB are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16 data bits can be read in two bytes on either D[15:8] or D[7:0]. REV. B –17– AD7663 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 17. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) –18– REV. B AD7663 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 14 15 16 17 18 t 31 t 32 X SDOUT D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 19. Slave Serial Data Timing for Reading (Read after Convert) SLAVE SERIAL INTERFACE Another advantage is to be able to read the data at any speed up External Clock to 40 MHz, which accommodates both slow digital host interface The AD7663 is configured to accept an externally supplied and the fastest serial reading. serial data clock on the SCLK pin when the EXT/INT pin is Finally, in this mode only, the AD7663 provides a “daisy-chain” held HIGH. In this mode, several methods can be used to read feature using the RDC/SDIN input pin for cascading multiple the data. The external serial clock is gated by CS and the data converters together. This feature is useful for reducing component are output when both CS and RD are LOW. Thus, depending count and wiring connections when desired as, for instance, in on CS, the data can be read after each conversion or during the isolated multiconverter applications. following conversion. The external clock can be either a continu- An example of the concatenation of two devices is shown in ous or discontinuous clock. A discontinuous clock can be either Figure 20. Simultaneous sampling is possible by using a com- normally high or normally low when inactive. Figures 19 and 21 mon CNVST signal. It should be noted that the RDC/SDIN show the detailed timing diagrams of these methods. input is latched on the opposite edge of SCLK of the one used While the AD7663 is performing a bit decision, it is important to shift out the data on SDOUT. Therefore, the MSB of the that voltage transients not occur on digital input/output pins or “upstream” converter just follows the LSB of the “downstream” degradation of the conversion result could occur. This is par- converter on the next SCLK cycle. ticularly important during the second half of the conversion phase because the AD7663 provides error correction circuitry BUSY OUT that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended BUSY BUSY that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is LOW or, more AD7663 AD7663 #2 #1 importantly, that does not transition during the latter half of (UPSTREAM) (DOWNSTREAM) BUSY HIGH. DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT External Discontinuous Clock Data Read after Conversion CNVST CNVST This mode is the most recommended of the serial slave modes. CS CS Figure 19 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning SCLK SCLK LOW, the result of this conversion can be read while both CS and RD are LOW. The data is shifted out, MSB first, with 16 clock SCLK IN pulses and is valid on both the rising and falling edge of the clock. CS IN CNVST IN Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the Figure 20. Two AD7663s in a Daisy-Chain Configuration digital interface during the conversion process. REV. B –19– AD7663 INVSCLK = 0 EXT/INT = 1 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 X D15 D14 D13 D1 D0 SDOUT t 16 Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion peripheral interface (SPI) on the MC68HC11 is configured for Figure 21 shows the detailed timing diagrams of this method. Master Mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock During a conversion, while both CS and RD are LOW, the result Phase Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1 of the previous conversion can be read. The data is shifted out by writing to the SPI Control Register (SPCR). The IRQ is MSB first with 16 clock pulses, and is valid on both the rising and configured for edge-sensitive-only operation (IRQE = 1 in the falling edge of the clock. The 16 bits have to be read before OPTION register). the current conversion is complete. If that is not done, RDERROR is pulsed HIGH and can be used to interrupt the host interface DVDD AD7663* MC68HC11* to prevent an incomplete data reading. There is no daisy-chain feature in this mode, and RDC/SDIN input should always be SER/PAR tied either HIGH or LOW. EXT/INT CS To reduce performance degradation due to digital activity, a RD BUSY IRQ fast discontinuous clock of at least 25 MHz is recommended to SDOUT MISO/SDI ensure that all the bits are read during the first half of the conver- SCLK SCK sion phase. INVSCLK CNVST I/O PORT *ADDITIONAL PINS OMITTED FOR CLARITY MICROPROCESSOR INTERFACING The AD7663 is ideally suited for traditional dc measurement Figure 22. Interfacing the AD7663 to SPI Interface applications supporting a microprocessor and ac signal processing applications interfacing to a digital signal processor. The ADSP-21065L in Master Serial Interface AD7663 is designed to interface with either a parallel 8-bit or As shown in Figure 23, the AD7663 can be interfaced to the 16-bit wide interface or with a general-purpose Serial Port or I/O ADSP-21065L using the serial interface in Master Mode without Ports on a microcontroller. A variety of external buffers can be any glue logic required. This mode combines the advantages of used with the AD7663 to prevent digital noise from coupling into reducing the wire connections and being able to read the data during the ADC. The following sections illustrate the use of the AD7663 or after conversion at maximum speed transfer (DIVSCLK[0:1] with an SPI equipped microcontroller, the ADSP-21065L and both low. ADSP-218x signal processors. The AD7663 is configured for the Internal Clock Mode (EXT/INT SPI Interface (MC68HC11) low) and acts therefore as the master device. The convert com- Figure 22 shows an interface diagram between the AD7663 and an mand can be generated by an external low jitter oscillator or, as SPI-equipped microcontroller, such as the MC68HC11. To shown, by a FLAG output of the ADSP-21065L, or by a frame accommodate the slower speed of the microcontroller, the AD7663 output TFS of one Serial Port of the ADSP-21065L that can be used acts as a slave device and data must be read after conversion. This like a timer. The Serial Port on the ADSP-21065L is configured mode also allows the daisy-chain feature. The convert command for external clock (IRFS = 0), rising edge active (CKRE = 1), could be initiated in response to an internal timer interrupt. The external late framed sync signals (IRFS = 0, LAFS = 1, reading of output data, one byte at a time if necessary, could be RFSR = 1), and active HIGH (LRFS = 0). The Serial Port of initiated in response to the end-of-conversion signal (BUSY going the ADSP-21065L is configured by writing to its receive control LOW) using an interrupt line of the microcontroller. The serial register (SRCTL)—see ADSP-2106x SHARC User’s Manual. –20– REV. B AD7663 Because the Serial Port within the ADSP-21065L will be seeing a on different but close layers of the board should run at right discontinuous clock, an initial word reading has to be done after angles to each other. This will reduce the effect of feedthrough the ADSP-21065L has been reset to ensure that the Serial Port through the board. is properly synchronized to this clock during each following data The power supply lines to the AD7663 should use as large a trace read operation. as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also impor- DVDD tant to lower the supplies’ impedance presented to the AD7663 AD7663* ADSP-21065L* and to reduce the magnitude of the supply spikes. Decoupling SHARC SER/PAR ceramic capacitors, typically 100 nF, should be placed on all of RDC/SDIN the power supply pins AVDD, DVDD, and OVDD close to, and RD ideally right up against these pins and their corresponding ground EXT/INT SYNC RFS pins. Additionally, low ESR 10 µF capacitors should be located CS SDOUT DR in the vicinity of the ADC to further reduce low frequency ripple. INVSYNC SCLK RCLK INVSCLK CNVST FLAG OR TFS The DVDD supply of the AD7663 can be either a separate supply or come from the analog supply, AVDD, or from the *ADDITIONAL PINS OMITTED FOR CLARITY digital interface supply, OVDD. When the system digital supply is noisy or fast switching digital signals are present, it is recom- Figure 23. Interfacing to the ADSP-21065L Using the mended, if no separate supply is available, to connect the DVDD Serial Master Mode digital supply to the analog supply, AVDD, through an RC filter as shown in Figure 5, and to connect the system supply to the APPLICATION HINTS interface digital supply OVDD and the remaining digital circuitry. Layout When DVDD is powered from the system supply, it is useful to The AD7663 has very good immunity to noise on the power insert a bead to further reduce high frequency spikes. supplies as can be seen in Figure 9. However, care should still be taken with regard to grounding layout. The AD7663 has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the The printed circuit board that houses the AD7663 should be analog input signal. REFGND senses the reference voltage and designed so the analog and digital sections are separated and con- should be a low impedance return to the reference because it fined to certain areas of the board. This facilitates the use of carries pulsed currents. AGND is the ground to which most internal ground planes that can be easily separated. Digital and analog ADC analog signals are referenced. This ground must be con- ground planes should be joined in only one place, preferably nected with the least resistance to the analog ground plane. DGND underneath the AD7663 or at least as close as possible to the must be tied to the analog or digital ground plane depending on AD7663. If the AD7663 is in a system where multiple devices the configuration. OGND is connected to the digital system ground. require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that The layout of the decoupling of the reference voltage is important. should be established as close as possible to the AD7663. The decoupling capacitor should be close to the ADC and con- nected with short and large traces to minimize parasitic inductances. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane Evaluating the AD7663 Performance should be allowed to run under the AD7663 to avoid noise cou- A recommended layout for the AD7663 is outlined in the evalu- pling. Fast switching signals like CNVST or clocks should be ation board for the AD7663. The evaluation board package includes shielded with digital ground to avoid radiating noise to other a fully assembled and tested evaluation board, documentation, sections of the board and should never run near analog signal paths. and software for controlling the board from a PC via the Eval- Crossover of digital and analog signals should be avoided. Traces Control Board. REV. B –21– AD7663 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 48 37 1 36 PIN 1 SEATING 10� PLANE 7.00 1.45 6� TOP VIEW 0.20 (PINS DOWN) BSC SQ 2� 1.40 0.09 1.35 VIEW A 7� 3.5� 12 25 0.15 0� 13 24 SEATING 0.05 0.10 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90� CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 TOP BOTTOM BSC SQ 5.10 SQ VIEW VIEW 4.95 0.50 25 12 0.40 13 24 0.30 5.50 0.80 MAX REF 1.00 12� MAX PADDLE CONNECTED TO AGND. 0.65 NOM 0.90 THIS CONNECTION IS NOT 0.05 MAX REQUIRED TO MEET THE 0.80 ELECTRICAL PERFORMANCES 0.02 NOM 0.20 0.50 BSC COPLANARITY REF SEATING 0.08 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 –22– REV. B AD7663 Revision History Location Page 4/03—Data Sheet changed from REV. A to REV. B. Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5/02—Data Sheet changed from REV. 0 to REV. A. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Chart added to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Voltage Reference Input and Power Supply sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to ADSP-21065L in Master Serial Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 New Package Outline Added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REV. B –23– –24– C01845–0–5/03(B)