ANALOG DEVICES AD7660

® 16-Bit, 100 kSPS PulSAR a Unipolar CMOS ADC * AD7660 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: 100 kSPS AVDD AGND REF REFGND DVDD DGND INL: �3 LSB Max (�0.0046% of Full-Scale) 16-Bit Resolution with No Missing Codes OVDD AD7660 S/(N+D): 87 dB Min @ 10 kHz, 90 dB Typ @ 45 kHz OGND SERIAL THD: –96 dB Max @ 10 kHz PORT IN SWITCHED Analog Input Voltage Range: 0 V to 2.5 V 16 CAP DAC INGND D[15:0] Both AC and DC Specifications No Pipeline Delay BUSY PARALLEL Parallel and Serial 5 V/3 V Interface INTERFACE RD ® CLOCK SPI /QSPI™/MICROWIRE™/DSP Compatible PD CS Single 5 V Supply Operation RESET CONTROL LOGIC AND SER/PAR CALIBRATION CIRCUITRY 21 mW Typical Power Dissipation, 21 �W @ 100 SPS OB/2C Power-Down Mode: 7 �W Max Package: 48-Lead Quad Flatpack (LQFP) CNVST 48-Lead Chip Scale Package (LFCSP) Pin-to-Pin Compatible with the AD7664 Table I. PulSAR Selection APPLICATIONS Data Acquisition Type/kSPS 100–250 500–570 800–1000 Battery-Powered Systems Pseudo AD7651 AD7650/AD7652 AD7653 PCMCIA Instrumentation Differential AD7660/AD7661 AD7664/AD7666 AD7667 Automatic Test Equipment True Bipolar AD7663 AD7665 AD7671 Scanners True AD7675 AD7676 AD7677 Medical Instruments Differential Process Control 18-Bit AD7678 AD7679 AD7674 GENERAL DESCRIPTION Simultaneous/ AD7654 The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR, Multichannel AD7655 analog-to-digital converter that operates from a single 5 V power supply. The part contains an internal conversion clock, error cor- PRODUCT HIGHLIGHTS rection circuits, and both serial and parallel system interface ports. 1. Fast Throughput The AD7660 is hardware factory-calibrated and is comprehen- The AD7660 is a 100 kSPS, charge redistribution, 16-bit sively tested to ensure ac parameters such as signal-to-noise ratio SAR ADC with internal error correction circuitry. (SNR) and total harmonic distortion (THD), in addition to the 2. Superior INL more traditional dc parameters of gain, offset, and linearity. The AD7660 has a maximum integral nonlinearity of 3 LSBs It is fabricated using Analog Devices’ high performance, with no missing 16-bit code. 0.6 micron CMOS process with correspondingly low cost and is 3. Single-Supply Operation available in a 48-lead LQFP and a tiny 48-lead LFCSP with The AD7660 operates from a single 5 V supply and only operation specified from –40∞C to +85∞C. dissipates 21 mW typical. Its power dissipation decreases with the throughput to, for instance, only 21 mW at a 100 SPS throughput. It consumes 7 mW maximum when in power-down. 4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement com- patible with both 3 V or 5 V logic. *Patent pending REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. AD7660–SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V 0V V IN INGND REF Operating Input Voltage V –0.1 +3 V IN V –0.1 +0.5 V INGND Analog Input CMRR f = 25 kHz 70 dB IN Input Current 100 kSPS Throughput 325 nA Input Impedance See Analog Input Section THROUGHPUT SPEED Complete Cycle 10 ms Throughput Rate 0 100 kSPS DC ACCURACY 1 Integral Linearity Error –3 +3 LSB Differential Linearity Error –1 +1.75 LSB No Missing Codes 16 Bits 2 Transition Noise 0.75 LSB 3 Full-Scale Error REF = 2.5 V ±0.045 ±0.08 % of FSR 3 Unipolar Zero Error ±1 ±5 LSB Power Supply Sensitivity AVDD = 5 V ±5% ±3 LSB AC ACCURACY 4 Signal-to-Noise f = 10 kHz 87 90 dB IN f = 45 kHz 90 dB IN Spurious-Free Dynamic Range f = 10 kHz 96 dB IN f = 45 kHz 100 dB IN Total Harmonic Distortion f = 10 kHz –96 dB IN f = 45 kHz –100 dB IN Signal-to-(Noise+Distortion) f = 10 kHz 87 dB IN f = 45 kHz 90 dB IN –60 dB Input 30 dB –3 dB Input Bandwidth 820 kHz SAMPLING DYNAMICS Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 8 ms REFERENCE External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 100 kSPS Throughput 22 mA POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V Operating Current 100 kSPS Throughput AVDD 3.2 mA 5 DVDD 1mA 5 OVDD 10 mA 5 Power Dissipation 100 kSPS Throughput 21 25 mW 100 SPS Throughput 21 mW 5, 6 in Power-Down Mode 7 mW DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V +2.0 OVDD + 0.3 V IH I –1 +1 mA IL I –1 +1 mA IH DIGITAL OUTPUTS Data Format Parallel or Serial 16-Bit Pipeline Delay Conversion Results Available Immediately after Completed Conversion V I = 1.6 mA 0.4 V OL SINK V I = –500 mA OVDD – 0.6 V OH SOURCE REV. D –2– AD7660 Parameter Conditions Min Typ Max Unit TEMPERATURE RANGE Specified Performance T to T –40 +85 ∞C MIN MAX NOTES 1 LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 mV. 2 Typical rms noise at worst-case transitions and temperatures. 3 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 5 Tested in Parallel Reading Mode. 6 With all digital inputs forced to DVDD or DGND respectively. Specifications subject to change without notice. TIMING SPECIFICATIONS (–40�C to +85�C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit REFER TO FIGURES 11 AND 12 Convert Pulsewidth t 5ns 1 Time between Conversions t 10 ms 2 CNVST LOW to BUSY HIGH Delay t 15 ns 3 BUSY HIGH All Modes Except in t 2 ms 4 Master Serial Read after Convert Mode Aperture Delay t 2ns 5 End of Conversion to BUSY LOW Delay t 10 ns 6 Conversion Time t 2 ms 7 Acquisition Time t 8 ms 8 RESET Pulsewidth t 10 ns 9 REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t 2 ms 10 DATA Valid to BUSY LOW Delay t 45 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 515ns 13 1 REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 10 ns CS LOW to Internal SCLK Valid Delay t 15 CS LOW to SDOUT Delay t 10 ns 16 500 ns CNVST LOW to SYNC Delay t 17 SYNC Asserted to SCLK First Edge Delay t 4ns 18 40 75 ns Internal SCLK Period t 19 2 Internal SCLK HIGH (INVSCLK Low) t 30 ns 20 2 t 9.5 ns Internal SCLK LOW (INVSCLK Low) 21 SDOUT Valid Setup Time t 4.5 ns 22 3ns SDOUT Valid Hold Time t 23 SCLK Last Edge to SYNC Delay t 3 24 10 ns CS HIGH to SYNC HI-Z t 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 10 ns CS HIGH to SDOUT HI-Z t 27 BUSY HIGH in Master Serial Read after Convert t 3.2 ms 28 1.5 ms CNVST LOW to SYNC Asserted Delay t 29 SYNC Deasserted to BUSY LOW Delay t 50 ns 30 1 REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes) External SCLK Setup Time t 5ns 31 External SCLK Active Edge to SDOUT Delay t 316ns 32 SDIN Setup Time t 5ns 33 SDIN Hold Time t 5ns 34 External SCLK Period t 25 ns 35 External SCLK HIGH t 10 ns 36 External SCLK LOW t 10 ns 37 NOTES 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 2 If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice. REV. D –3– AD7660 1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Analog Inputs 2 IN , REF, INGND, REFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V 48 47 46 45 44 43 42 41 40 39 38 37 Supply Voltages AGND 1 36 AGND PIN 1 AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD 2 IDENTIFIER 35 CNVST NC 3 AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V 34 PD DGND 4 33 RESET DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V OB/2C 5 32 CS Digital Inputs AD7660 NC 6 31 RD TOP VIEW Except the Databus D(7:4) . . . –0.3 V to DVDD + 0.3 V 7 NC 30 DGND (Not to Scale) Databus Inputs D(7:4) . . . . . . –0.3 V to OVDD + 0.3 V SER/PAR 8 29 BUSY 3 D0 9 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . 700 mW 28 D15 4 10 D1 27 D14 Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 2.5 W D2 11 26 D13 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C D3 12 25 D12 Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C 13 14 15 16 17 18 21 22 23 24 19 20 Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational NC = NO CONNECT section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: q = 91∞C/W, q = 30∞C/W. JA JC 4 Specification is for device in free air: 48-Lead LFCSP: q = 26∞C/W. JA 1.6mA I OL TO OUTPUT 1.4V PIN C L * 60pF 2V I 500�A OH 0.8V t t DELAY DELAY *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 2V 2V SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD 0.8V 0.8V C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Voltage Reference Levels for Timings Figure 1. Load Circuit for Digital Interface Timing ORDERING GUIDE Model Temperature Range Package Description Package Option AD7660AST –40∞C to +85∞C Quad Flatpack (LQFP) ST-48 AD7660ASTRL –40∞C to +85∞C Quad Flatpack (LQFP) ST-48 AD7660ACP –40∞C to +85∞CChip Scale (LFCSP) CP-48 AD7660ACPRL –40∞C to +85∞CChip Scale (LFCSP) CP-48 1 EVAL-AD7660CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. –4– REV. D D4/EXT/INT NC D5/INVSYNC NC D6/INVSCLK NC D7/RDC/SDIN NC OGND NC OVDD IN DVDD NC DGND NC D8/SDOUT NC D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF AD7660 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 6, 7, NC No Connect 40–42, 44–48 4 DGND DI Must Be Tied to Digital Ground 5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a twos complement output from its internal shift register. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port. 9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 13 D4 DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 DI/O When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 DI/O When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Modes. 16 D7 DI/O When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input or a Read Mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground 21 D8 DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. REV. D –5– AD7660 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Type Description 22 D9 DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D11 DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard- less of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal. 30 DGND P Must Be Tied to Digital Ground 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver- sions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t ) is complete, the next 8 falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t ) is complete, the internal sample-and-hold is put into the 8 hold state and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground 37 REF AI Reference Input Voltage 38 REFGND AI Reference Input Analog Ground 39 INGND AI Analog Input Ground 43 IN AI Primary Analog Input with a Range of 0 V to V REF NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power –6– REV. D AD7660 DEFINITION OF SPECIFICATIONS Total Harmonic Distortion (THD) Integral Nonlinearity Error (INL) THD is the ratio of the rms sum of the first five harmonic Linearity error refers to the deviation of each individual code from components to the rms value of a full-scale input signal and is a line drawn from “negative full scale” through “positive full expressed in decibels. scale.” The point used as negative full scale occurs 1/2 LSB before Signal-to-Noise Ratio (SNR) the first code transition. Positive full scale is defined as a level SNR is the ratio of the rms value of the actual input signal to the 1 1/2 LSB beyond the last code transition. The deviation is mea- rms sum of all other spectral components below the Nyquist sured from the middle of each code to the true straight line. frequency, excluding harmonics and dc. The value for SNR is Differential Nonlinearity Error (DNL) expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-(Noise + Distortion) Ratio (S/[N+D]) nonlinearity is the maximum deviation from this ideal value. It is S/(N+D) is the ratio of the rms value of the actual input signal often specified in terms of resolution for which no missing codes to the rms sum of all other spectral components below the are guaranteed. Nyquist frequency, including harmonics but excluding dc. The Full-Scale Error value for S/(N+D) is expressed in decibels. The last transition (from 011 . . . 10 to 011 . . . 11 in twos Aperture Delay complement coding) should occur for an analog voltage 1 1/2 LSB Aperture delay is a measure of the acquisition performance and below the nominal full scale (2.49994278 V for the 0 V–2.5 V is measured from the falling edge of the CNVST input to when range). The full-scale error is the deviation of the actual level of the input signal is held for a conversion. the last transition from the ideal level. Transient Response Unipolar Zero Error The time required for the AD7660 to achieve its rated accuracy The first transition should occur at a level 1/2 LSB above analog after a full-scale step function is applied to its input. ground (19.073 mV for the 0 V–2.5 V range). Unipolar zero error is Overvoltage Recovery the deviation of the actual transition from that point. The time required for the ADC to recover to full accuracy after Spurious-Free Dynamic Range (SFDR) an analog input signal 150% of full-scale is reduced to 50% of The difference, in decibels (dB), between the rms amplitude of the full-scale value. the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/[N+D] by the following formula: ENOB = S/ N + D –. 176/6.02 [] () dB and is expressed in bits. REV. D –7– AD7660–Typical Performance Characteristics 8000 3 30 7219 7051 7000 2 25 6000 1 20 5000 4000 0 15 3000 –1 10 2000 1213 –2 5 879 1000 0 013 9 0 0 0 –3 0 8008 800A 800C 800E 8010 0 16384 32768 49152 65536 0 0.6 1.2 1.8 2.4 3.0 8009 800B 800D 800F 8011 CODE POSITIVE INL – LSB CODE – Hex TPC 1. Integral Nonlinearity TPC 2. Typical Positive INL TPC 3. Histogram of 16,384 vs. Code Distribution (350 Units) Conversions of a DC Input at the Code Transition 1.75 35 10000 1.50 9026 30 1.25 8000 1.00 25 0.75 6000 20 0.50 0.25 15 4000 0.00 3489 3520 10 –0.25 2000 –0.50 5 –0.75 161 188 0 0 00 –1.00 0 0 0 16384 32768 49152 65536 –3.0 –2.4 –1.8 –1.2 –0.6 0 8009 800B 800D 800F 8011 CODE 800A 800C 800E 8010 NEGATIVE INL – LSB CODE – Hex TPC 4. Differential Nonlinearity TPC 5. Typical Negative INL TPC 6. Histogram of 16,384 vs. Code Distribution (350 Units) Conversions of a DC Input at the Code Center 0 –60 120 –60 4096 POINT FFT –20 f = 100kHz –70 –70 S 110 f = 45kHz –40 IN SFDR –80 SNR = 90.14dB –80 SINAD = 89.94dB –60 100 THD = –101.37dB –90 SFDR = 110dB –90 –80 90 –100 –100 –100 SECOND HARMONIC THD –110 –120 80 THD SECOND HARMONIC –110 –120 –140 70 –120 –160 –130 THIRD HARMONIC THIRD HARMONIC 60 –180 –130 –140 1 10 100 1000 010 20 3040 50 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 FREQUENCY – kHz FREQUENCY – kHz INPUT LEVEL – dB TPC 7. FFT Plot TPC 8. THD, Harmonics, and SFDR TPC 9. THD, Harmonics vs. vs. Frequency Input Level –8– REV. D AMPLITUDE – dB of Full Scale DNL – LSB INL – LSB THD, HARMONICS – dB NUMBER OF UNITS NUMBER OF UNITS SFDR – dB THD, HARMONICS – dB COUNTS COUNTS AD7660 92 50 100 16.0 15.5 95 40 OVDD @ 2.7V, 85�C SNR 90 15.0 90 S/(N+D) 30 OVDD @ 2.7V, 25�C ENOB 85 14.5 20 88 OVDD @ 5V, 85�C 80 14.0 10 13.5 75 OVDD @ 5V, 25�C 13.0 86 0 70 –50 –40 –30 –20 –10 0 0 50 100 150 200 1 10 100 1k C – pF FREQUENCY – Hz INPUT LEVEL – dB L TPC 12. Typical Delay vs. Load TPC 10. SNR, S/(N+D), and ENOB TPC 11. SNR vs. Input Level Capacitance C vs. Frequency L (Referred to Full Scale) 100 10M 12 90 10 AVDD 1M 80 8 FULL SCALE ERROR DVDD 6 70 100k 4 60 10k 2 50 DVDD 0 OVDD 40 ZERO ERROR 1k –2 30 –4 100 20 AVDD –6 10 –8 10 0 OVDD –10 1 –10 –12 0.1 110 100 1k 10k 100k 1M –40 –15 10 35 60 85 110 –55 –35 –15 5 25 45 65 85 105 125 SAMPLING RATE – SPS TEMPERATURE (�C) TEMPERATURE – �C TPC 15. Zero Error, Full Scale vs. TPC 14. Power-Down Operating TPC 13. Operating Currents Temperature Currents vs. Temperature vs. Sample Rate REV. D –9– SNR AND S/(N+D) – dB OPERATING CURRENTS – nA ENOB – Bits POWER-DOWN OPERATING CURRENTS – nA SNR (REFERRED TO FULL SCALE) – dB t DELAY – ns ZERO ERROR, FULL SCALE ERROR (LSB) 12 AD7660 CIRCUIT INFORMATION During the acquisition phase, the common terminal of the array The AD7660 is a fast, low power, single-supply, precise 16-bit tied to the comparator’s positive input is connected to AGND analog-to-digital converter (ADC). The AD7660 is capable of via SW . All independent switches are connected to the analog A converting 100,000 samples per second (100 kSPS) and allows input IN. Thus, the capacitor array is used as a sampling capaci- power saving between conversions. When operating at 100 SPS, tor and acquires the analog signal on IN input. Similarly, the for example, it consumes typically only 21 mW. This feature dummy capacitor acquires the analog signal on the INGND input. makes the AD7660 ideal for battery-powered applications. When the acquisition phase is complete and the CNVST input The AD7660 provides the user with an on-chip track-and- goes or is LOW, a conversion phase is initiated. When the con- hold, successive-approximation ADC that does not exhibit any version phase begins, SW and SW are opened first. The A B pipeline or latency, making it ideal for multiple multiplexed capacitor array and the dummy capacitor are then disconnected channel applications. from the inputs and connected to the REFGND input. There- fore, the differential voltage between IN and INGND captured The AD7660 can be operated from a single 5 V supply and be at the end of the acquisition phase is applied to the comparator interfaced to either 5 V or 3 V digital logic. It is housed in a inputs, causing the comparator to become unbalanced. 48-lead LQFP package or a 48-lead LFCSP package that com- bines space savings and allows flexible configurations as either By switching each element of the capacitor array between REFGND serial or parallel interface. The AD7660 is pin-to-pin compatible or REF, the comparator input varies by binary weighted voltage with the AD7664. steps (V /2, V /4 . . . V /65536). The control logic toggles REF REF REF these switches, starting with the MSB first, in order to bring the CONVERTER OPERATION comparator back into a balanced condition. After the comple- The AD7660 is a successive-approximation analog-to-digital tion of this process, the control logic generates the ADC output converter based on a charge redistribution DAC. Figure 3 shows code and brings BUSY output LOW. the simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional LSB capacitor. The comparator’s negative input is connected to a “dummy” capacitor of the same value as the capacitive DAC array. IN REF REFGND SWITCHES CONTROL SW MSB LSB LSB A 16384C 4C 2C C C 32768C BUSY CONTROL COMP LOGIC OUTPUT INGND CODE 65536C SW B CNVST Figure 3. ADC Simplified Schematic –10– REV. D AD7660 Transfer Functions Table II. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7660 offers two output Digital Output Code (Hex) codings: straight binary and twos complement. The LSB size is Analog Straight Twos V /65536, which is about 38.15 mV. The ideal transfer charac- REF Description Input Binary Complement teristic for the AD7660 is shown in Figure 4 and Table II. 1 1 FSR – 1 LSB 2.499962 V FFFF 7FFF FSR – 2 LSB 2.499923 V FFFE 7FFE 1 LSB = V /65536 REF Midscale + 1 LSB 1.250038 V 8001 0001 111...111 Midscale 1.25 V 8000 0000 111...110 Midscale – 1 LSB 1.249962 V 7FFF FFFF 111...101 –FSR + 1 LSB 38 mV 0001 8001 2 2 –FSR 0 V 0000 8000 NOTES 1 This is also the code for overrange analog input (V – V above IN INGND V – V ). REF REFGND 2 This is also the code for underrange analog input (V below V ). IN INGND 000...010 000...001 TYPICAL CONNECTION DIAGRAM 000...000 Figure 5 shows a typical connection diagram for the AD7660. 0V 1 LSB V –1 LSB REF 0.5 LSB V –1.5 LSB REF ANALOG INPUT Figure 4. ADC Ideal Transfer Function ANALOG 100� DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) 100nF 100nF 100nF 10�F 10�F 10�F AVDD AGND DGND DVDD OVDD OGND SERIAL PORT 2.5V REF REF SCLK NOTE 1 C REF NOTE 1 SDOUT REFGND BUSY AD7660 �C/�P/DSP D NOTE 2 U1 IN CNVST NOTE 3 ANALOG INPUT (0V TO 2.5V) OB/2C INGND SER/PAR DVDD CS RD PD RESET CLOCK NOTES 1. WITH THE AD780 OR THE ADR291 VOLTAGE REFERENCE, C IS 47�F, REF SEE VOLTAGE REFERENCE INPUT SECTION. 2. THE OP184 IS RECOMMENDED. 3. OPTIONAL LOW JITTER CNVST. Figure 5. Typical Connection Diagram REV. D –11– ADC CODE – Straight Binary AD7660 Analog Input When the source impedance of the driving circuit is low, the Figure 6 shows an equivalent circuit of the input structure of the AD7660 can be driven directly. Large source impedances will AD7660. significantly affect the ac performances, especially the total harmonic distortion (THD). The maximum source impedance AVDD depends on the amount of THD that can be tolerated. The D1 C2 R1 THD degrades in function of the source impedance and the IN OR INGND maximum input frequency as shown in Figure 8. C1 D2 AGND –70 R = 500� S –75 Figure 6. Equivalent Analog Input Circuit The two diodes D1 and D2 provide ESD protection for the –80 analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than R = 100� S –85 0.3 V. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward- R = 50� S biased current of 100 mA maximum. For instance, these –90 conditions could eventually occur when the input buffer’s (U1) R = 20� S supplies are different from AVDD. In such cases, an input buffer –95 with a short circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential –100 1 10 100 signal between IN and INGND. Unlike other converters, the INPUT FREQUENCY – kHz INGND input is sampled at the same time as the IN input. By Figure 8. THD vs. Analog Input Frequency and using this differential input, small signals common to both inputs Source Resistance are rejected as shown in Figure 7, which represents the typical CMRR over frequency. For instance, by using INGND to sense Driver Amplifier Choice a remote signal ground, difference of ground potentials between Although the AD7660 is easy to drive, the driver amplifier needs the sensor and the local ADC ground is eliminated. to meet at least the following requirements: • The driver amplifier and the AD7660 analog input circuit 85 must be able, together, to settle for a full-scale step of 80 the capacitor array at a 16-bit level (0.0015%). For instance, operation at the maximum throughput of 100 kSPS 75 requires a minimum gain bandwidth product of 5 MHz. 70 • The noise generated by the driver amplifier needs to be 65 kept as low as possible in order to preserve the SNR and transition noise performance of the AD7660. The noise 60 coming from the driver is filtered by the AD7660 analog 55 input circuit one-pole low-pass filter made by R1 and C2. For instance, a driver with an equivalent input noise of 50 4 nV/÷Hz like the OP184 and configured as a buffer, thus 45 with a noise gain of +1, degrades the SNR by only 0.1 dB. 40 • The driver needs to have a THD performance suitable to 1k 10k 100k 1M 10M FREQUENCY – Hz that of the AD7660. TPC 8 gives the THD versus frequency that the driver should preferably exceed. Figure 7. Analog Input CMRR vs. Frequency The SNR degradation due to the amplifier is: During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and Ê ˆ the network formed by the series connection of R1 and C2. Á ˜ 28 Capacitor C1 is primarily the pin capacitance. The resistor R1 is SNR = 20log Á ˜ LOSS typically 3242 W and is a lumped component made up of some p Á ˜ 2 Á 784 + fN()e ˜ –3dB N serial resistors and the on resistance of the switches. The capacitor Ë ¯ 2 C2 is typically 60 pF and is mainly the ADC sampling capacitor. where: During the conversion phase, where the switches are opened, the input impedance is limited to C1. It has to be noted that the input f is the –3 dB input bandwidth in MHz of the AD7660 –3 dB impedance of the AD7660, unlike other SAR ADCs, is not a pure (0.82 MHz) or the cutoff frequency of the input filter if any capacitance and thus, inherently reduces the kickback transient at are used. the beginning of the acquisition phase. The R1, C2 makes a one- N is the noise factor of the amplifier (1 if in buffer configuration). pole low-pass filter with a typical cutoff frequency of 820 kHz that reduces undesirable aliasing effect and limits the noise. e is the equivalent input noise voltage of the op amp in N nV/÷Hz. –12– REV. D CMRR – dB THD – dB AD7660 The AD8519, OP162, or the OP184 meet these requirements of power supply sequencing and thus free from supply voltage and are usually appropriate for almost all applications. As an induced latch-up. Additionally, it is very insensitive to power supply alternative, in very high speed and noise-sensitive applications, variations over a wide frequency range, as shown in Figure 9. the AD8021 with an external compensation capacitor of 10 pF or the AD829 with an external compensation capacitor of 82 pF –50 can be used. This capacitor should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting –55 +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. –60 Voltage Reference Input The AD7660 uses an external 2.5 V voltage reference. –65 The voltage reference input REF of the AD7660 has a dynamic input impedance; it should therefore be driven by a low impedance –70 source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage –75 reference but usually consists of a 1 mF ceramic capacitor and a low ESR tantalum capacitor connected to the REF and REFGND –80 1k 10k 100k 1M inputs with minimum parasitic inductance. 47 mF is an appropriate INPUT FREQUENCY – Hz value for the tantalum capacitor when used with one of the recommended reference voltages: Figure 9. PSRR vs. Frequency ∑ The low noise, low temperature drift ADR421 and AD780 POWER DISSIPATION VS. THROUGHPUT voltage references The AD7660 automatically reduces its power consumption at ∑ The low power ADR291 voltage reference the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant ∑ The low cost AD1582 voltage reference power saving when the conversion rate is reduced, as shown in For applications using multiple AD7660s, it is more effective to Figure 10. This feature makes the AD7660 ideal for very low buffer the reference voltage with a low noise, very stable op amp power battery applications. It should be noted that the digital like the AD8031. interface remains active even during the acquisition phase. To Care should also be taken with the reference temperature coeffi- reduce the operating digital supply currents even further, the cient of the voltage reference that directly affects the full-scale digital inputs need to be driven close to the power rails (i.e., accuracy if this parameter matters. For instance, a ±15 ppm/∞C DVDD and DGND for all inputs except EXT/INT, INVSYNC, tempco of the reference changes the full scale by ±1 LSB/∞C. INVSCLK, RDC/SDIN, and OVDD or OGND for the last four inputs. V , as mentioned in the specification table, could be increased REF to AVDD – 1.85 V. The benefit here is the increased SNR 100000 obtained as a result of this increase. Since the input range is defined in terms of V , this would essentially increase the REF range to make it a ±3 V input range with an AVDD above 4.85 V. 10000 The theoretical improvement as a result of this increase in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical 1000 quantization noise, however, the observed improvement is approximately 1 dB. The AD780 can be selected with a 3 V reference voltage. 100 Power Supply The AD7660 uses three sets of power supply pins: an analog 5 V 10 supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. 1 10 100 1000 10000 100000 To reduce the number of supplies needed, the digital core THROUGHPUT – SPS (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 5. The AD7660 is independent Figure 10. Power Dissipation vs. Sample Rate REV. D –13– POWER DISSIPATION – �W PSRR – dB AD7660 CONVERSION CONTROL DIGITAL INTERFACE Figure 11 shows the detailed timing diagrams of the conversion The AD7660 has a versatile digital interface; it can be interfaced process. The AD7660 is controlled by the signal CNVST, which with the host system by using either a serial or parallel interface. initiates conversion. Once initiated, it cannot be restarted or The serial interface is multiplexed on the parallel data bus. The aborted, even by the power-down input PD, until the conver- AD7660 digital interface also accommodates both 3 V or 5 V sion is complete. The CNVST signal operates independently of logic by simply connecting the OVDD supply pin of the AD7660 CS and RD signals. to the host system interface digital supply. Finally, by using the OB/2C input pin, both twos complement or straight binary coding can be used. t 2 t 1 The two signals CS and RD control the interface. CS and RD have a similar effect because they are together internally. When CNVST at least one of these signals is HIGH, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7660 in multicircuit applications and is held LOW in a BUSY single AD7660 design. RD is generally used to enable the con- t 4 version result on the data bus. t 3 t 6 t 5 CS = RD = 0 MODE ACQUIRE CONVERT ACQUIRE CONVERT t 1 t t CNVST 7 8 t Figure 11. Basic Conversion Timing 10 BUSY For a true sampling application, the recommended operation of t 4 the CNVST signal is the following: t 3 t 11 CNVST must be held HIGH from the previous falling edge DATA BUS of BUSY, and during a minimum delay corresponding to the PREVIOUS CONVERSION DATA NEW DATA acquisition time t ; then, when CNVST is brought LOW, a 8 conversion is initiated and the BUSY signal goes HIGH until Figure 13. Master Parallel Data Timing for Reading the completion of the conversion. Although CNVST is a digital (Continuous Read) signal, it should be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or PARALLEL INTERFACE ringing. For applications where the SNR is critical, the CNVST The AD7660 is configured to use the parallel interface when the signal should have a very low jitter. This may be achieved by SER/PAR is held LOW. The data can be read either after each using a dedicated oscillator for CNVST generation or, at least, conversion, which is during the next acquisition phase, or during to clock it with a high frequency low jitter clock, as shown in the following conversion as shown, respectively, in Figures 14 and Figure 5. 15. When the data is read during the conversion, however, it is recommended that it is read-only during the first half of the t 9 conversion phase. This avoids any potential feedthrough between RESET voltage transients on the digital interface and the most critical analog conversion circuitry. BUSY CS DATABUS t 8 RD CNVST Figure 12. RESET Timing BUSY For other applications, conversions can be automatically initiated. If CNVST is held LOW when BUSY is LOW, the AD7660 controls the acquisition phase and then automatically initiates a CURRENT DATA BUS CONVERSION new conversion. By keeping CNVST LOW, the AD7660 keeps the conversion process running by itself. It should be noted that t t 12 13 the analog input has to be settled when BUSY goes LOW. Also, at power-up, CNVST should be brought LOW once to initiate Figure 14. Slave Parallel Data Timing for Reading the conversion process. In this mode, the AD7660 could some- (Read after Convert) times run slightly faster than the guaranteed limit of 100 kSPS. –14– REV. D AD7660 CS = 0 SERIAL INTERFACE t 1 The AD7660 is configured to use the serial interface when the CNVST, SER/PAR is held HIGH. The AD7660 outputs 16 bits of data, RD MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. BUSY t 4 MASTER SERIAL INTERFACE Internal Clock t 3 The AD7660 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. The AD7660 PREVIOUS DATA BUS CONVERSION also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal t t 12 13 can be inverted if desired. The output data is valid on both the Figure 15. Slave Parallel Data Timing for Reading rising and falling edge of the data clock. Depending on RDC/ (Read during Convert) SDIN input, the data can be read after each conversion or during the following conversion. Figures 16 and 17 show the detailed timing diagrams of these two modes. EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 16. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) REV. D –15– AD7660 CS EXT/INT = 1 INVSCLK = 0 RD = 0 BUSY t 35 t t 36 37 SCLK 12 3 14 15 1617 18 t 31 t 32 X SDOUT D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 18. Slave Serial Data Timing for Reading (Read after Convert) the result of this conversion can be read while both CS and RD are Usually, because the AD7660 has a longer acquisition phase LOW. The data is shifted out, MSB first, with 16 clock pulses and than the conversion phase, the data is read immediately after is valid on both the rising and falling edge of the clock. conversion. This makes the Master Read after conversion the most recommended Serial Mode when it can be used. In this Among the advantages of this method, the conversion performance mode, it should be noted that, unlike in other modes, the signal is not degraded because there are no voltage transients on the BUSY returns LOW after the 16 data bits are pulsed out and digital interface during the conversion process. not at the end of the conversion phase, which results in a longer Another advantage is the ability to read the data at any speed up BUSY width. to 40 MHz, which accommodates both slow digital host inter- In Read-during-Conversion Mode, the serial clock and data face and the fastest serial reading. toggle at appropriate instants, which minimizes potential Finally, in this mode only, the AD7660 provides a “daisy-chain” feedthrough between digital activity and the critical conversion feature using the RDC/SDIN input pin for cascading multiple decisions. converters together. This feature is useful for reducing component count and wiring connections when it is desired as it is, for SLAVE SERIAL INTERFACE instance, in isolated multiconverter applications. External Clock The AD7660 is configured to accept an externally supplied serial An example of the concatenation of two devices is shown in data clock on the SCLK pin when the EXT/INT pin is held Figure 19. Simultaneous sampling is possible by using a common HIGH. In this mode, several methods can be used to read the CNVST signal. It should be noted that the RDC/SDIN input is data. When CS and RD are both LOW, the data can be read latched on the opposite edge of SCLK of the one used to shift out after each conversion or during the following conversion. The the data on SDOUT. Therefore, the MSB of the “upstream” external clock can be either a continuous or discontinuous clock. converter just follows the LSB of the “downstream” converter on A discontinuous clock can be either normally HIGH or normally the next SCLK cycle. Up to 20 AD7660s running at 100 kSPS LOW when inactive. Figures 18 and 20 show the detailed timing can be daisy-chained using this method. diagrams of these methods. Usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data are BUSY OUT read immediately after conversion. BUSY BUSY While the AD7660 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or AD7660 AD7660 degradation of the conversion result could occur. This is par- #2 #1 (UPSTREAM) (DOWNSTREAM) ticularly important during the second half of the conversion DATA OUT RDC/SDIN SDOUT RDC/SDIN SDOUT phase because the AD7660 provides error correction circuitry that can correct for an improper bit decision made during the first half CNVST CNVST of the conversion phase. For this reason, it is recommended CS CS that when an external clock is being provided, it is a discon- SCLK SCLK tinuous clock that is toggling only when BUSY is LOW or, more importantly, that it does not transition during the latter half of BUSY HIGH. SCLK IN CS IN External Discontinuous Clock Data Read after Conversion CNVST IN This mode is the most recommended of the serial slave modes. Figure 18 shows the detailed timing diagrams of this method. After Figure 19. Two AD7660s in a Daisy-Chain Configuration a conversion is complete, indicated by BUSY returning LOW, –16– REV. D AD7660 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 X D1 SDOUT D15 D14 D13 D0 t 16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) External Clock Data Read during Conversion SPI Interface (ADSP-219x) Figure 20 shows the detailed timing diagrams of this method. Figure 21 shows an interface diagram between the AD7660 and During a conversion, while both CS and RD are LOW, the an SPI-equipped ADSP-219x. To accommodate the slower result of the previous conversion can be read. The data is shifted speed of the DSP, the AD7660 acts as a slave device and data out, MSB first, with 16 clock pulses, and is valid on both the must be read after conversion. This mode also allows the daisy- rising and falling edges of the clock. The 16 bits have to be read chain feature. The convert command can be initiated in response before the current conversion is complete; this, otherwise, to an internal timer interrupt. The reading process cab be initi- RDERROR is pulsed HIGH and can be used to interrupt the host ated in response to the end-of-conversion signal (BUSY going interface to prevent incomplete data reading. There is no daisy- LOW) using an interrupt line of the DSP. The serial interface chain feature in this mode, and RDC/SDIN input should always (SPI) on the ADSP-219x is configured for master mode— be tied either HIGH or LOW. (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00— by To reduce performance degradation due to digital activity, a fast writing to the SPI control register (SPICLTx). To meet all discontinuous clock of at least 18 MHz is recommended to ensure timing requirements, the SPI clock should be limited to 17 that all the bits are read during the first half of the conversion Mbps, which allows it to read an ADC result in less than 1 ms. phase. For this reason, this mode is more difficult to use. When a higher sampling rate is desired, use of one of the paral- lel interface modes is recommended. MICROPROCESSOR INTERFACING The AD7660 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal pro- DVDD AD7660* ADSP-219x* cessing applications interfacing to a digital signal processor. SER/PAR The AD7660 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O EXT/INT BUSY PFx ports on a microcontroller. A variety of external buffers can be SPIxSEL (PFx) CS used with the AD7660 to prevent digital noise from coupling RD SDOUT MISOx into the ADC. The following section discusses the use of an INVSCLK SCLK SCKx AD7660 with an ADSP-219x SPI equipped DSP. CNVST PFx or TFSx *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. Interfacing the AD7660 to an SPI Interface REV. D –17– AD7660 APPLICATION HINTS It is recommended to avoid running digital lines under the device Bipolar and Wider Input Ranges as these will couple noise onto the die. The analog ground plane In some applications, it is desired to use a bipolar or wider should be allowed to run under the AD7660 to avoid noise analog input range like, for instance, ±10 V, ±5 V, or 0 V to coupling. Fast switching signals like CNVST or clocks should 5 V. Although the AD7660 has only one unipolar range, by simple be shielded with digital ground to avoid radiating noise to other modifications of the input driver circuitry, bipolar and wider sections of the board and should never run near analog signal input ranges can be used without any performance degradation. paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right Figure 22 shows a connection diagram that allows this. Compo- angles to each other. This will reduce the effect of feedthrough nent values required and resulting full-scale ranges are shown in through the board. Table III. The power supply lines to the AD7660 should use as large a C F trace as possible to provide low impedance paths and reduce the R1 effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the R2 ANALOG AD7660 and to reduce the magnitude of the supply spikes. INPUT IN U1 Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply pins AVDD, DVDD, and OVDD close to, AD7660 and ideally right up against, these pins and their corresponding U2 100nF R3 R4 ground pins. Additionally, low ESR 10 mF capacitors should be located in the vicinity of the ADC to further reduce low INGND frequency ripple. 2.5V REF REF The DVDD supply of the AD7660 can be either a separate C 100nF REF supply or come from the analog supply, AVDD, or from the REFGND digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recom- Figure 22. Using the AD7660 in 16-Bit Bipolar and/or mended if no separate supply is available, to connect the DVDD Wider Input Ranges digital supply to the analog supply AVDD through an RC filter as shown in Figure 6 and to connect the system supply to the interface Table III. Component Values and Input Ranges digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert Input Range R1 (kW) R2 (kW) R3 (kW) R4 (kW) a bead to further reduce high frequency spikes. ±10 V 1 8 10 8 The AD7660 has five different ground pins: INGND, REFGND, ±5 V 1 4 10 6.67 AGND, DGND, and OGND. INGND is used to sense the 0 V to –5 V 1 2 None 0 analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it For bipolar range applications where accurate gain and offset carries pulsed currents. AGND is the ground to which most are desired, they can be calibrated by acquiring a ground and a internal ADC analog signals are referenced. This ground must be voltage reference using an analog multiplexer U2, as shown in connected with the least resistance to the analog ground plane. Figure 22. Also, C can be used as a one-pole antialiasing filter. F DGND must be tied to the analog or digital ground plane depend- Layout ing on the configuration. OGND is connected to the digital The AD7660 has very good immunity to noise on the power system ground. supplies as can be seen in Figure 9. However, care should still Evaluating the AD7660 Performance be taken with regard to grounding layout. A recommended layout for the AD7660 is outlined in the The printed circuit board that houses the AD7660 should be EVAL-AD7660 evaluation board for the AD7660. The evaluation designed so the analog and digital sections are separated and board package includes a fully assembled and tested evaluation confined to certain areas of the board. This facilitates the use of board, documentation, and software for controlling the board ground planes that can be easily separated. Digital and ana- from a PC via the EVAL-CONTROL-BRD2. log ground planes should be joined in only one place, preferably underneath the AD7660, or, at least, as close as possible to the AD7660. If the AD7660 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7660. –18– REV. D AD7660 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 48 37 1 36 PIN 1 SEATING 10� PLANE 7.00 1.45 6� TOP VIEW 0.20 BSC SQ (PINS DOWN) 2� 1.40 0.09 1.35 VIEW A 7� 3.5� 12 25 0.15 0� 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90� CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC 48-Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 TOP BOTTOM BSC SQ 5.10 SQ VIEW VIEW 4.95 0.50 25 12 0.40 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12� MAX PADDLE CONNECTED TO AGND. 0.65 TYP THIS CONNECTION IS NOT 0.85 0.05 MAX REQUIRED TO MEET THE 0.80 ELECTRICAL PERFORMANCES 0.02 NOM 0.50 BSC COPLANARITY 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 REV. D –19– AD7660 Revision History Location Page 10/03—Data Sheet changed from REV. C to REV. D. Update format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Added Overvoltage Recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Added TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Renamed Table I to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 5 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to Driver Amplifier Choise section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Replaced Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to DIGITAL INTERFACE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Replaced Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Deleted Figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Replaced MICROPROCESSOR INTERFACING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes in Bipolar and Wider Input Ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Added CP-48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1/02—Data Sheet changed from REV. B to REV. C. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Edits to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 New Voltage Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to DIGITAL INTERFACE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 New ST-48 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9/01—Data Sheet changed from REV. A to REV. B. Edit to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edit to Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to TYPICAL PERFORMANCE CHARACTERISTICS graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10 Edit to DRIVER AMPLIFIER CHOICE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edit to Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Edit to Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Edit to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Edit to Bipolar and Wider Input Ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REV. D –20– C01928–0–10/03(D)