ANALOG DEVICES AD7657-1

250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar, 16-/14-/12-Bit ADC Data Sheet AD7656-1/AD7657-1/AD7658-1 FEATURES FUNCTIONAL BLOCK DIAGRAM V CONVST A CONVST B CONVST C AV DV DD CC CC Pin and software compatible with AD7656/AD7657/AD7658 featuring reduced decoupling requirements CS 6 independent ADCs CLK REF CONTROL SER/PAR SEL OSC True bipolar analog inputs LOGIC V DRIVE Pin-/software-selectable ranges: ±10 V, ±5 V STBY BUF Fast throughput rate: 250 kSPS OUTPUT 16-/14-/ DB8/DOUT A DRIVERS V1 T/H iCMOS process technology 12-BIT SAR Low power DB6/SCLK 16-/14-/ 140 mW at 250 kSPS with 5 V supplies V2 T/H 12-BIT SAR High noise performance with wide bandwidth OUTPUT DB9/DOUT B BUF DRIVERS 88 dB SNR at 10 kHz input frequency 16-/14-/ V3 T/H 12-BIT SAR OUTPUT On-chip reference and reference buffers DRIVERS DB10/DOUT C High speed parallel, serial, and daisy-chain interface modes 16-/14-/ V4 T/H High speed serial interface 12-BIT SAR DATA/ OUTPUT CONTROL DRIVERS SPI/QSPI™/MICROWIRE™/DSP compatible BUF LINES 16-/14-/ Standby mode: 315 µW maximum V5 T/H 12-BIT SAR RD 64-lead LQFP WR/REF EN/DIS 16-/14-/ V6 T/H APPLICATIONS 12-BIT SAR AD7656-1/AD7657-1/AD7658-1 Power line monitoring and measuring systems Instrumentation and control systems V AGND DGND SS Multiaxis positioning systems Figure 1. GENERAL DESCRIPTION 1 The AD7656-1/AD7657-1/AD7658-1 are reduced decoupling pin- The conversion process and data acquisition are controlled and software-compatible versions of AD7656/AD7657/AD7658. using the CONVST signals and an internal oscillator. Three The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/ CONVST pins (CONVST A, CONVST B, and CONVST C) 14-/12-bit, fast, low power successive approximation ADCs in allow independent, simultaneous sampling of the three ADC a package designed on the iCMOS® process (industrial CMOS). pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed iCMOS is a process combining high voltage silicon with submicron parallel and serial interface, allowing the devices to interface with CMOS and complementary bipolar technologies. It enables the microprocessors or DSPs. When the serial interface is selected, development of a wide range of high performance analog ICs each part has a daisy-chain feature that allows multiple ADCs to capable of 33 V operation in a footprint that no previous generation connect to a single serial interface. The AD7656-1/AD7657-1/ of high voltage parts could achieve. Unlike analog ICs using conven- AD7658-1 can accommodate true bipolar input signals in the tional CMOS processes, iCMOS components can accept bipolar ±4 × V and ±2 × V ranges. Each AD7656-1/AD7657-1/ REF REF input signals while providing increased performance, which AD7658-1 also contains an on-chip 2.5 V reference. dramatically reduces power consumption and package size. PRODUCT HIGHLIGHTS The AD7656-1/AD7657-1/AD7658-1 feature throughput rates 1. Six 16-/14-/12-bit, 250 kSPS ADCs on board. of up to 250 kSPS. The parts contain low noise, wide bandwidth 2. Six true bipolar, high impedance analog inputs. track-and-hold amplifiers that can handle input frequencies 3. High speed parallel and serial interfaces. up to 4.5 MHz. 4. Reduced decoupling requirements and reduced bill of materials cost compared with the AD7656/AD7657/ AD7658 devices. 1 Protected by U.S. Patent No. 6,731,232. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. 07017-001 AD7656-1/AD7657-1/AD7658-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 20 Applications ....................................................................................... 1 Converter Details ....................................................................... 20 Functional Block Diagram .............................................................. 1 ADC Transfer Function ............................................................. 21 General Description ......................................................................... 1 Internal/External Reference ...................................................... 21 Product Highlights ........................................................................... 1 Typical Connection Diagram ................................................... 21 Revision History ............................................................................... 2 Driving the Analog Inputs ........................................................ 22 Specifications ..................................................................................... 3 Interface Options ........................................................................ 22 AD7656-1 ...................................................................................... 3 Software Selection of ADCs ...................................................... 24 AD7657-1 ...................................................................................... 5 Changing the Analog Input Range (H/S SEL = 0) ................ 25 AD7658-1 ...................................................................................... 7 Changing the Analog Input Range (H/S SEL = 1) ................ 25 Timing Specifications .................................................................. 9 Serial Read Operation ................................................................ 25 Absolute Maximum Ratings .......................................................... 10 PAR Daisy-Chain Mode (DCEN = 1, SER/ SEL = 1) ............. 27 Thermal Resistance .................................................................... 10 Application Hints ........................................................................... 29 ESD Caution ................................................................................ 10 Layout .......................................................................................... 29 Pin Configuration and Function Descriptions ........................... 11 Power Supply Configuration..................................................... 29 Typical Performance Characteristics ........................................... 14 Outline Dimensions ....................................................................... 30 Terminology .................................................................................... 18 Ordering Guide .......................................................................... 30 REVISION HISTORY 3/12—Rev. C to Rev. D Changes to Table 3 ............................................................................. 7 Changes to Figure 28 ...................................................................... 22 Changes to Table 4 ............................................................................. 9 Changes to Absolute Maximum Ratings Table .......................... 10 Changes to Pin Functions Description Table ............................. 11 11/10—Rev. B to Rev. C Added Power Supply Configuration Section .............................. 29 Changes to Figure 9 ........................................................................ 14 Added Figure 39 .............................................................................. 29 Changes to Converter Details Section ......................................... 20 Changes to Internal/External Reference Section ....................... 21 6/10—Rev. A to Rev. B Changes to Interface Options Section ......................................... 22 Changes to DC Accuracy Parameter, Table 1 ............................... 3 Changes to Parallel Interface Section .......................................... 22 Changes to DC Accuracy Parameter, Table 2 ............................... 5 Changes to Serial Interface (SER/ SEL = 1) Section .......... 25 PAR Change to DC Accuracy Parameter, Table 3 ................................. 7 Changes to Daisy-Chain Mode (DCEN = 1, SER/PAR SEL = 1) .. 27 Added %FSR to Terminology Section ......................................... 19 Changes to Layout Section ............................................................ 30 Updated Outline Dimension ........................................................ 31 3/09—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 31 Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 3 7/08—Revision 0: Initial Version Changes to Table 2 ............................................................................ 5 Rev. D | Page 2 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 SPECIFICATIONS AD7656-1 V = 2.5 V internal/external, AV = 4.75 V to 5.25 V, DV = 4.75 V to 5.25 V, V = 2.7 V to 5.25 V; for the ±4 × V range, V = REF CC CC DRIVE REF DD 10 V to 16.5 V, V = −10 V to −16.5 V; for the ±2 × V range, V = 5 V to 16.5 V, V = −5 V to −16.5 V; f = 250 kSPS, T = T to SS REF DD SS SAMPLE A MIN TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 10 kHz sine wave IN 1 Signal-to-(Noise + Distortion) (SINAD) 88 dB 1 Signal-to-Noise Ratio (SNR) 88 dB 1 Total Harmonic Distortion (THD) −90 dB −105 dB VDD/VSS = ±5 V to ±16.5 V 1 Peak Harmonic or Spurious Noise (SFDR) −100 dB 1 Intermodulation Distortion (IMD) fa = 10.5 kHz, fb = 9.5 kHz Second-Order Terms −112 dB Third-Order Terms −107 dB Aperture Delay 10 ns Aperture Delay Matching 4 ns Aperture Jitter 35 ps 1 Channel-to-Channel Isolation −100 dB f on unselected channels up to 100 kHz IN Full-Power Bandwidth 4.5 MHz @ −3 dB 2.2 MHz @ −0.1 dB DC ACCURACY Resolution 16 Bits No Missing Codes B Version 15 Bits Y Version 14 Bits 1 Integral Nonlinearity ±3 LSB ±1 LSB 1 Positive Full-Scale Error ±0.8 % FSR ±0.381% FSR typical 1 Positive Full-Scale Error Matching ±0.35 % FSR 1 Bipolar Zero-Scale Error ±0.0137% FSR typical B Version ±0.048 % FSR Y Version ±0.048 %F SR 1 Bipolar Zero-Scale Error Matching ±0.038 % FSR 1 Negative Full-Scale Error ±0.8 % FSR ±0.381% FSR typical 1 Negative Full-Scale Error Matching ±0.35 % FSR ANALOG INPUT See Table 8 for minimum VDD/VSS for each range Input Voltage Ranges −4 × VREF +4 × VREF V RNGx bits or RANGE pin = 0 −2 × VREF +2 × VREF V RNGx bits or RANGE pin = 1 DC Leakage Current ±1 µA 2 Input Capacitance 10 pF ±4 × V range when in track REF 14 pF ±2 × V range when in track REF REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5 2.5 V DC Leakage Current ±1 µA 2 Input Capacitance 18.5 pF REF DIS = 1 EN/ Reference Output Voltage 2.49 2.51 V Long-Term Stability 150 ppm 1000 hours Reference Temperature Coefficient 25 ppm/°C 6 ppm/°C Rev. D | Page 3 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (I ) ±10 µA Typically 10 nA, V = 0 V or V IN IN DRIVE 2 Input Capacitance (C ) 10 pF IN LOGIC OUTPUTS Output High Voltage (V ) V − 0.2 V I = 200 µA OH DRIVE SOURCE Output Low Voltage (V ) 0.2 V I = 200 µA OL SINK Floating-State Leakage Current ±10 µA 2 Floating-State Output Capacitance 10 pF Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 µs 1, 2 Track-and-Hold Acquisition Time 550 ns Throughput Rate 250 kSPS Parallel interface mode only POWER REQUIREMENTS V −5 +16.5 V For the 4 × V range, V = 10 V to 16.5 V DD REF DD V −5 −16.5 V For the 4 × V range, V = −10 V to −16.5 V SS REF SS AVCC 4.75 5.25 V DVCC 4.75 5.25 V VDRIVE 2.7 5.25 V 3 I Digital inputs = 0 V or V TOTAL DRIVE Normal Mode—Static 18 mA AV = DV = V = +5.25 V, V = +16.5 V, CC CC DRIVE DD V = −16.5 V SS Normal Mode—Operational 26 mA fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V ISS (Operational) 0.25 mA VSS = −16.5 V, fSAMPLE = 250 kSPS I (Operational) 0.25 mA V = +16.5 V, f = 250 kSPS DD DD SAMPLE Partial Power-Down Mode 7 mA AV = DV = V = +5.25 V, V = +16.5 V, CC CC DRIVE DD VSS = −16.5 V Full Power-Down Mode (STBY Pin) 60 µA SCLK on or off, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Power Dissipation AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, V = −16.5 V SS Normal Mode—Static 94 mW Normal Mode—Operational 140 mW fSAMPLE = 250 kSPS Partial Power-Down Mode 40 mW Full Power-Down Mode (STBY Pin) 315 µW 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. Rev. D | Page 4 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 AD7657-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for the ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for the ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to T , unless otherwise noted. MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 10 kHz sine wave Signal-to-(Noise + Distortion) 82.5 dB 1 (SINAD) 1 Signal-to-Noise Ratio (SNR) 83.5 dB 1 Total Harmonic Distortion (THD) −90 dB −105 dB Peak Harmonic or Spurious Noise −100 dB 1 (SFDR) 1 Intermodulation Distortion (IMD) fa = 10.5 kHz, fb = 9.5 kHz Second-Order Terms −109 dB Third-Order Terms −104 dB Aperture Delay 10 ns Aperture Delay Matching 4 ns Aperture Jitter 35 ps 1 Channel-to-Channel Isolation −100 dB f on unselected channels up to 100 kHz IN Full-Power Bandwidth 4.5 MHz @ −3 dB 2.2 MHz @ −0.1 dB DC ACCURACY Resolution 14 Bits No Missing Codes 14 Bits 1 Integral Nonlinearity ±1 LSB ±1 1 Positive Full-Scale Error ±0.95 % FSR ±0.27% FSR typical 1 Positive Full-Scale Error Matching ±0.366 % FSR 1 Bipolar Zero-Scale Error ±0.04 % FSR ±0.016% FSR typical 1 Bipolar Zero-Scale Error Matching ±0.0427 % FSR 1 Negative Full-Scale Error ±0.95 % FSR ±0.27% FSR typical 1 Negative Full-Scale Error Matching ±0.366 % FSR ANALOG INPUT See Table 8 for minimum VDD/VSS for each range Input Voltage Ranges −4 × VREF +4 × VREF V RNGx bits or RANGE pin = 0 −2 × V +2 × V V RNGx bits or RANGE pin = 1 REF REF DC Leakage Current ±1 µA 2 Input Capacitance 10 pF ±4 × V range when in track REF 14 pF ±2 × VREF range when in track REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5 2.5 V DC Leakage Current ±1 µA 2 Input Capacitance 18.5 pF REF = 1 EN/DIS Reference Output Voltage 2.49 2.51 V Long-Term Stability 150 ppm 1000 hours Reference Temperature Coefficient 25 ppm/°C 6 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (I ) ±10 µA Typically 10 nA, V = 0 V or V IN IN DRIVE 2 Input Capacitance (C ) 10 pF IN Rev. D | Page 5 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage (VOH) VDRIVE − 0.2 V ISOURCE = 200 µA Output Low Voltage (VOL) 0.2 V ISINK = 200 µA Floating-State Leakage Current ±10 µA 2 Floating-State Output Capacitance 10 pF Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 µs 1, 2 Track-and-Hold Acquisition Time 550 ns Throughput Rate 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD −5 +16.5 V For the 4 × VREF range, VDD = 10 V to 16.5 V VSS −5 −16.5 V For the 4 × VREF range, VSS= −10 V to −16.5 V AV 4.75 5.25 V CC DV 4.75 5.25 V CC V 2.7 5.25 V DRIVE 3 ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode—Static 18 mA AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, V = −16.5 V SS Normal Mode—Operational 26 mA f = 250 kSPS, AV = DV = V = +5.25 V, V = SAMPLE CC CC DRIVE DD +16.5 V, V = −16.5 V SS ISS (Operational) 0.25 mA VSS = −16.5 V, fSAMPLE = 250 kSPS IDD (Operational) 0.25 mA VDD = 16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 mA AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, V = −16.5 V SS Full Power-Down Mode (STBY Pin) 60 µA SCLK on or off, AV = DV = V = +5.25 V, CC CC DRIVE VDD = +16.5 V, VSS = −16.5 V Power Dissipation AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V Normal Mode—Static 94 mW Normal Mode—Operational 140 mW f = 250 kSPS SAMPLE Partial Power-Down Mode 40 mW Full Power-Down Mode 315 µW (STBY Pin) 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 Includes I , I , I , I , and I . AVCC VDD VSS VDRIVE DVCC Rev. D | Page 6 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 AD7658-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 10 kHz sine wave Signal-to-(Noise + Distortion) 73.5 dB 1 (SINAD) 73.5 dB 1 Total Harmonic Distortion (THD) −88 dB −100 dB Peak Harmonic or Spurious Noise −97 dB 1 (SFDR) 1 Intermodulation Distortion (IMD) fa = 10.5 kHz, fb = 9.5 kHz Second-Order Terms −106 dB Third-Order Terms −101 dB Aperture Delay 10 ns Aperture Delay Matching 4 ns Aperture Jitter 35 ps 1 Channel-to-Channel Isolation −100 dB f on unselected channels up to 100 kHz IN Full-Power Bandwidth 4.5 MHz @ −3 dB 2.2 MHz @ −0.1 dB DC ACCURACY Resolution 12 Bits No Missing Codes 12 Bits Differential Nonlinearity ±0.7 LSB 1 Integral Nonlinearity ±0.5 LSB 1 Positive Full-Scale Error ±0.95 % FSR ±0.317% FSR typical 1 Positive Full-Scale Error Matching ±0.366 % FSR 1 Bipolar Zero-Scale Error ±2 LSB ±0.0125% FSR typical 1 Bipolar Zero-Scale Error Matching ±2 LSB 1 Negative Full-Scale Error ±0.95 % FSR ±0.317% FSR typical 1 Negative Full-Scale Error Matching ±0.366 % FSR ANALOG INPUT See Table 8 for minimum VDD/VSS for each range Input Voltage Ranges −4 × VREF +4 × VREF V RNGx bits or RANGE pin = 0 −2 × V +2 × V V RNGx bits or RANGE pin = 1 REF REF DC Leakage Current ±1 µA 2 Input Capacitance 10 ±4 × V range when in track REF 14 pF ±2 × VREF range when in track REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5 2.5 V DC Leakage Current ±1 µA 2 Input Capacitance 18.5 pF REF = 1 EN/DIS Reference Output Voltage 2.49 2.51 V Long-Term Stability 150 ppm 1000 hours Reference Temperature Coefficient 25 ppm/°C 6 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (I ) ±10 µA Typically 10 nA, V = 0 V or V IN IN DRIVE 2 Input Capacitance (C ) 10 pF IN Rev. D | Page 7 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage (VOH) VDRIVE − 0.2 V ISOURCE = 200 µA Output Low Voltage (VOL) 0.2 V ISINK = 200 µA Floating-State Leakage Current ±10 µA Floating-State Output 10 pF 2 Capacitance Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 µs 1, 2 Track-and-Hold Acquisition Time 550 ns Throughput Rate 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD −5 +16.5 V For the 4 × VREF range, VDD = 10 V to 16.5 V V −5 −16.5 V For the 4 × V range, V = −10 V to −16.5 V SS REF SS AV 4.75 5.25 V CC DVCC 4.75 5.25 V VDRIVE 2.7 5.25 V 3 ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode—Static 18 mA AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, V =−16.5 V SS Normal Mode—Operational 26 mA f = 250 kSPS, AV = DV = V = +5.25 V, V = SAMPLE CC CC DRIVE DD +16.5 V, VSS = −16.5 V ISS (Operational) 0.25 mA VSS = −16.5 V, fSAMPLE = 250 kSPS IDD (Operational) 0.25 mA VDD = 16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 mA AV = DV = V = +5.25 V, V = +16.5 V, CC CC DRIVE DD V = −16.5 V SS Full Power-Down Mode ( Pin) 60 µA SCLK on or off, AV = DV = V = +5.25 V, STBY CC CC DRIVE VDD = +16.5 V, VSS = −16.5 V Power Dissipation AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, V = −16.5 V SS Normal Mode—Static 94 mW Normal Mode—Operational 140 mW f = 250 kSPS SAMPLE Partial Power-Down Mode 40 mW Full Power-Down Mode 315 µW (STBY Pin) 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. Rev. D | Page 8 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 TIMING SPECIFICATIONS AVCC and DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at tMIN, tMAX 1 Parameter V < 4.75 V V = 4.75 V to 5.25 V Unit Description DRIVE DRIVE PARALLEL INTERFACE t 3 3 µs typ Conversion time, internal clock CONVERT t 150 150 ns min Minimum quiet time required between bus QUIET relinquish and start of next conversion tACQ 550 550 ns min Acquisition time t10 25 25 ns min Minimum CONVST low pulse t1 60 60 ns max CONVST high to BUSY high t 2 2 ms max STBY rising edge to CONVST rising edge WAKE-UP 25 25 µs max Partial power-down mode PARALLEL READ OPERATION t 0 0 ns min BUSY to RD delay 2 t 0 0 ns min to setup time 3 CS RD t4 0 0 ns min CS to RD hold time t5 45 36 ns min RD pulse width t6 45 36 ns max Data access time after RD falling edge t 10 10 ns min Data hold time after RD rising edge 7 t 12 12 ns max Bus relinquish time after RD rising edge 8 t9 6 6 ns min Minimum time between reads PARALLEL WRITE OPERATION t 15 15 ns min pulse width 11 WR t12 0 0 ns min CS to WR setup time t13 5 5 ns min CS to WR hold time t14 5 5 ns min Data setup time before WR rising edge t 5 5 ns min Data hold after WR rising edge 15 SERIAL INTERFACE fSCLK 18 18 MHz max Frequency of serial read clock t 12 12 ns max Delay from CS until DOUTx three-state 16 disabled 2 t17 22 22 ns max Data access time after SCLK rising edge/CS falling edge t18 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t 0.4 × t 0.4 × t ns min SCLK high pulse width 19 SCLK SCLK t 10 10 ns min SCLK to data valid hold time after SCLK 20 falling edge t21 18 18 ns max CS rising edge to DOUTx high impedance 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DD 2 A buffer is used on the DOUTx pins (Pin 5 to Pin 7) for this measurement. 200µA I OL TO OUTPUT 1.6V PIN C L 25pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 9 of 32 07017-002 AD7656-1/AD7657-1/AD7658-1 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to AGND, DGND −0.3 V to +16.5 V DD section of this specification is not implied. Exposure to absolute V to AGND, DGND +0.3 V to −16.5 V SS maximum rating conditions for extended periods may affect VDD to AVCC VCC − 0.3 V to +16.5 V device reliability. AVCC to AGND, DGND −0.3 V to +7 V DV to AV −0.3 V to AV + 0.3 V THERMAL RESISTANCE CC CC CC DV to DGND, AGND −0.3 V to +7 V CC θ is specified for the worst-case conditions, that is, a device JA AGND to DGND −0.3 V to +0.3 V soldered in a circuit board for surface-mount packages. These VDRIVE to DGND −0.3 V to DVCC + 0.3 V specifications apply to a 4-layer board. 1 Analog Input Voltage to AGND VSS − 0.3 V to VDD + 0.3 V Table 6. Thermal Resistance Digital Input Voltage to DGND −0.3 V to VDRIVE + 0.3 V Package Type θ θ Unit Digital Output Voltage to DGND −0.3 V to V + 0.3 V JA JC DRIVE REFIN/REFOUT to AGND −0.3 V to AV + 0.3 V 64-Lead LQFP 45 11 °C/W CC Input Current to Any Pin Except 2 Supplies ±10 mA ESD CAUTION Operating Temperature Range B Version −40°C to +85°C Y Version −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/Sn Temperature, Soldering Reflow (10 sec to 30 sec) 240(+0)°C Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD 1.5 kV 1 If the analog inputs are driven from alternative VDD and VSS supply circuitry, a 240 Ω series resistor should be placed on the analog inputs and Schottky diodes should be placed in series with the VDD and VSS supplies of the AD7656-1/AD7657-1/AD7658-1. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. D | Page 10 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DB14/REFBUF V6 EN/DIS PIN 1 DB13 2 47 AV CC DB12 3 46 AV CC DB11 4 45 V5 DB10/DOUT C 5 44 AGND 6 43 DB9/DOUT B AGND AD7656-1/AD7657-1/AD7658-1 7 42 DB8/DOUT A V4 TOP VIEW 8 (Not to Scale) 41 DGND AV CC 9 40 V AV DRIVE CC DB7/HBEN/DCEN 10 39 V3 11 38 DB6/SCLK AGND DB5/DCIN A 12 37 AGND DB4/DCIN B 13 36 V2 DB3/DCIN C 14 35 AV CC 15 34 DB2/SEL C AV CC 16 33 DB1/SEL B V1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 54, 56, 58 REFCAPA, REFCAPB, Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are connected to these pins to decouple the reference buffer for each ADC pair. Decouple each REFCAP pin REFCAPC to AGND using a 1 µF capacitor. 33, 36, 39, V1 to V6 Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode, 42, 45, 48 the analog input range of these channels is determined by the RANGE pin. In software mode, it is determined by the RNGC to RNGA bits of the control register (see Table 11). 32, 37, 38, 43, AGND Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656-1/ 44, 49, 52, 53, AD7657-1/AD7658-1. Refer all analog input signals and external reference signals to this pin. 55, 57, 59 Connect all AGND pins to the AGND plane of the system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 26 DV Digital Power, 4.75 V to 5.25 V. The DV and AV voltages should ideally be at the same potential CC CC CC and must not be more than 0.3 V apart, even on a transient basis. Decouple this supply to DGND by placing a 1 µF decoupling capacitor on the DVCC pin. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface. 8, 25 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7656-1/AD7657-1/ AD7658-1. Connect both DGND pins to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 34, 35, 40, AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and 41, 46, 47, DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even 50, 60 on a transient basis. 21, 22, 23 CONVST C, Conversion Start Input A, Conversion Start Input B, and Conversion Start Input C. These logic inputs are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions CONVST B, CONVST A on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on V5 and V6. When one of these pins switches from low to high, the track-and-hold switch on the selected ADC pair switches from track to hold, and the conversion is initiated. These inputs can also be used to place the ADC pairs into partial power- down mode. Rev. D | Page 11 of 32 DB15 DB0/SEL A WR/REF BUSY EN/DIS H/S SEL CS SER/PAR SEL RD AV CONVST C CC AGND CONVST B REFCAPC CONVST A AGND STBY REFCAPB DGND AGND DV CC RANGE REFCAPA RESET AGND W/B AGND V REFIN/REFOUT SS V AV CC DD AGND AGND 07017-003 AD7656-1/AD7657-1/AD7658-1 Data Sheet Pin No. Mnemonic Description 19 CS Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and the parallel interface is selected, the output bus is enabled and the conversion result is output on the parallel data bus lines. If both CS and WR are logic low and the parallel interface is selected, DB[15:8] are used to write data to the on-chip control register. When the serial interface is selected, the CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 20 RD Read Data. If both CS and RD are logic low and the parallel interface is selected, the output bus is enabled. When the serial interface is selected, the RD line should be held low. 63 /REF Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are WR EN/DIS logic low, DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is DIS low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/ = 0, the internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When H/S SEL = 0 and REF = 1, the internal reference is enabled and the REFIN/REFOUT pin EN/ DIS should be decoupled. See the Internal/External Reference section. 18 BUSY Busy Output. This pin transitions to high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. A new conversion cannot be initiated on the AD7656-1/AD7657-1/AD7658-1 when the BUSY signal is high because any applied CONVST edges are ignored. 51 REFIN/REFOUT Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the internal reference can be disabled and an external reference can be applied to this input. See the Internal/External Reference section. When the internal reference is enabled, decouple this pin using at least a 1 µF decoupling capacitor. 61 SER/ SEL Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high, PAR the serial interface is selected. When the serial interface is selected, DB[10:8] function as DOUT[C:A], DB[0:2] function as DOUT, and DB7 functions as DCEN. When the serial interface is selected, tie DB15 and DB[13:11] to DGND. 17 DB0/SEL A Data Bit 0/Select DOUT A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL A and is used to configure the serial interface. If this pin is 1, the serial interface operates with one, two, or three DOUT output pins and enables DOUT A as a serial output. When the serial interface is selected, always set this pin to 1. 16 DB1/SEL B Data Bit 1/Select DOUT B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL B and is used to configure the serial interface. If this pin is 1, the serial interface operates with two or three DOUT output pins and enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected. 15 DB2/SEL C Data Bit 2/Select DOUT C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL C and is used to configure the serial interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Unused serial DOUT pins should be left unconnected. 14 DB3/DCIN C Data Bit 3/Daisy-Chain Input C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When the serial interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND. 13 DB4/DCIN B Data Bit 4/Daisy-Chain Input B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When the serial interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND. 12 DB5/DCIN A Data Bit 5/Daisy-Chain Input A. When SER/PAR SEL is low, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When the serial interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND. 11 DB6/SCLK Data Bit 6/Serial Clock. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/ SEL = 1, this pin functions as SCLK input and is the read serial clock for the serial transfer. PAR 10 DB7/HBEN/DCEN Data Bit 7/High Byte Enable/Daisy-Chain Enable. When the parallel interface is selected and the device is used in word mode (SER/PAR SEL = 0 and W/B = 0), this pin functions as Data Bit 7. When the parallel interface is selected and the device is used in byte mode (SER/PAR SEL = 0 and W/B = 1), this pin functions as HBEN. If the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. If the HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When the serial interface is selected (SER/PAR SEL = 1), this pin functions as DCEN. If the DCEN pin is logic high, the parts operate in daisy-chain mode with DB[5:3] functioning as DCIN[A:C]. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Rev. D | Page 12 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 Pin No. Mnemonic Description 7 DB8/DOUT A Data Bit 8/Serial Data Output A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL A = 1, this pin functions as DOUT A and outputs serial conversion data. 6 DB9/DOUT B Data Bit 9/Serial Data Output B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL B = 1, this pin functions as DOUT B and outputs serial conversion data. This configures the serial interface to have two DOUT output lines. 5 DB10/DOUT C Data Bit 10/Serial Data Output C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL C = 1, this pin functions as DOUT C and outputs serial conversion data. This configures the serial interface to have three DOUT output lines. 4 DB11 Data Bit 11/Digital Ground. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/ SEL = 1, tie this pin to DGND. PAR 2, 3, 64 DB13, DB12, DB15 Data Bit 12, Data Bit 13, Data Bit 15. When SER/PAR SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR SEL = 1, tie these pins to DGND. For the AD7657-1, DB15 contains a leading 0. For the AD7658-1, DB15, DB13, and DB12 contain leading 0s. 1 SEL = 0, this pin acts as a three- DB14/REFBUFEN/DIS Data Bit 14/Reference Buffer Enable and Disable. When SER/PAR state digital input/output pin. For the AD7657-1 and AD7658-1, DB14 contains a leading 0. When SER/PAR SEL = 1, this pin can be used to enable or disable the internal reference buffers. 28 RESET Reset Input. When set to logic high, this pin resets the AD7656-1/AD7657-1/AD7658-1. In software mode, the current conversion is aborted and the internal register is set to all 0s. In hardware mode, the AD7656-1/AD7657-1/AD7658-1 are configured depending on the logic levels on the hardware select pins. In all modes, the parts should receive a RESET pulse after power-up. The RESET high pulse should be typically 100 ns wide. The CONVST pin may be held high during the RESET pulse. However, if the CONVST pin is held low during the RESET pulse, then after the RESET pulse, the AD7656-1/AD7657-1 /AD7658-1 need to receive a complete CONVST pulse to initiate the first conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. In hardware mode, the user can initiate a RESET pulse between conversion cycles, that is, a 100 ns RESET pulse can be applied to the device after BUSY has transitioned from high to low and the data has been read. The RESET can then be issued prior to the next complete CONVST pulse. Ensure that in such a case, RESET has returned to logic low prior to the next complete CONVST pulse. 27 RANGE Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the next conversion is ±2 × V . When this pin is Logic 0 at the falling edge of BUSY, the range for the REF next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is determined by the RNGA, RNGB, and RNGC bits in the control register. 31 V Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. DD 30 V Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. SS 24 STBY Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is high for normal operation and low for standby operation. 62 H/S SEL Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656-1/AD7657-1/AD7658-1 operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the control register. When the serial interface is selected, CONVST A is used to initiate conversions on the selected ADC pairs. 29 W/B Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656-1/ AD7657-1/AD7658-1 using the parallel data lines DB[15:0]. When this pin is logic high and the parallel interface is selected, byte mode is enabled. In this mode, data is transferred using Data Lines DB[15:8], and DB 7 functions as HBEN. To obtain the 16-bit conversion result, 2-byte reads are required. When the serial interface is selected, tie this pin to DGND. Rev. D | Page 13 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 2.0 V /V = ±12V T = –40°C V /V = ±15V DD SS A DD SS AV /DV /V = 5V DNL WCP = 0.61LSB AV /DV /V = 5V CC CC DRIVE CC CC DRIVE –20 1.5 f = 250kSPS DNL WCN = –0.82LSB ±10V RANGE SAMPLE 2 × V RANGE INTERNAL REFERENCE REF –40 T = 25°C A 1.0 f = 250kSPS SAMPLE –60 f = 10kHz IN 0.5 SNR = 88.44dB SINAD = 88.43dB –80 THD = –111.66dB 0 –100 –0.5 –120 –1.0 –140 –1.5 –160 –2.0 –180 0 10k 20k 30k 40k 50k 60k 65535 0 20 40 60 80 100 120 CODE FREQUENCY (kHz) Figure 4. AD7656-1 FFT for ±5 V Range (V /V = ±15 V) DD SS Figure 7. AD7656-1 Typical DNL 0 2.0 V /V = ±12V V /V = ±12V DD SS DD SS AV /DV /V = 5V AV /DV /V = 5V CC CC DRIVE CC CC DRIVE 1.6 –20 f = 250kSPS ±5V RANGE SAMPLE INTERNAL REFERENCE ±5V RANGE 1.2 –40 T = 25°C A f = 250kSPS SAMPLE 0.8 –60 f = 10kHz IN SNR = 88.25dB 0.4 SINAD = 88.24dB –80 THD = –112.46dB 0 –100 –0.4 –120 –0.8 –140 –1.2 –160 –1.6 –2.0 –180 0 2000 4000 6000 8000 10000 12000 14000 16000 0 20 40 60 80 100 120 CODE FREQUENCY (kHz) Figure 5. AD7656-1 FFT for ±5 V Range (V /V = ±12 V) DD SS Figure 8. AD7657-1 Typical INL 2.0 2.0 V /V = ±12V T = –40°C V /V = ±12V DD SS A DD SS AV /DV /V = 5V INL WCP = 0.97LSB AV /DV /V = 5V CC CC DRIVE CC CC DRIVE 1.5 1.5 f = 250kSPS INL WCN = –0.72LSB f = 250kSPS SAMPLE SAMPLE 2 × V RANGE ±5V RANGE REF 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 0 10k 20k 30k 40k 50k 60k 65535 CODE CODE Figure 6. AD7656-1 Typical INL Figure 9. AD7657-1 Typical DNL Rev. D | Page 14 of 32 INL (LSB) AMPLITUDE (dB) AMPLITUDE (dB) 07017-006 07017-005 07017-004 DNL (LSB) DNL (LSB) INL (LSB) 07017-007 07017-009 07017-008 Data Sheet AD7656-1/AD7657-1/AD7658-1 1.0 –80 V /V = ±12V DD SS f = 250kSPS SAMPLE AV /DV /V = 5V CC CC DRIVE 0.8 T = 25°C A f = 250kSPS SAMPLE –85 INTERNAL REFERENCE ±5V RANGE 0.6 –90 0.4 0.2 –95 0 ±10V RANGE V /V = ±12V DD SS –100 –0.2 AV /DV /V = 5V CC CC DRIVE –0.4 –105 –0.6 –110 ±5V RANGE –0.8 V /V = ±12V DD SS AV /DV /V = 5V CC CC DRIVE –1.0 –115 0 500 1000 1500 2000 2500 3000 3500 4000 10 100 CODE ANALOG INPUT FREQUENCY (kHz) Figure 10. AD7658-1 Typical INL Figure 13. AD7656-1 THD vs. Analog Input Frequency 1.0 –80 V /V = ±12V V /V = ±16.5V DD SS DD SS AV /DV /V = 5V AV /DV /V = 5.25V 0.8 CC CC DRIVE CC CC DRIVE f = 250kSPS T = 25°C SAMPLE R = 1000Ω A SOURCE ±5V RANGE INTERNAL REFERENCE 0.6 ±4 × V RANGE –90 REF 0.4 0.2 R = 220Ω SOURCE 0 –100 R = 50Ω SOURCE –0.2 –0.4 –110 R = 100Ω SOURCE –0.6 R = 10Ω SOURCE –0.8 –1.0 –120 0 500 1000 1500 2000 2500 3000 3500 4000 10 100 CODE ANALOG INPUT FREQUENCY (kHz) Figure 11. AD7658-1 Typical DNL Figure 14. AD7656-1 THD vs. Analog Input Frequency for Various Source Impedances, ±4 × VREF Range 90 –80 V /V = ±12V f = 250kSPS DD SS SAMPLE AV /DV /V = 5V T = 25°C CC CC DRIVE A 89 ±10V RANGE –85 T = 25°C INTERNAL REFERENCE A V /V = ±12V INTERNAL REFERENCE DD SS AV /DV /V = 5V ±2 × V RANGE REF CC CC DRIVE 88 –90 87 –95 R = 1000Ω ±5V RANGE SOURCE V /V = ±12V DD SS AV /DV /V = 5V CC CC DRIVE 86 –100 R = 220Ω R = 100Ω SOURCE SOURCE 85 –105 R = 50Ω SOURCE R = 10Ω 84 –110 SOURCE 83 –115 10 100 10 100 ANALOG INPUT FREQUENCY (kHz) ANALOG INPUT FREQUENCY (kHz) Figure 12. AD7656-1 SINAD vs. Analog Input Frequency Figure 15. AD7656-1 THD vs. Analog Input Frequency for Various Source Impedances, ±2 × VREF Range Rev. D | Page 15 of 32 DNL (LSB) INL (LSB) SINAD (dB) 07017-012 07017-011 07017-010 THD (dB) THD (dB) THD (dB) 07017-015 07017-014 07017-013 AD7656-1/AD7657-1/AD7658-1 Data Sheet 2.510 100 f = 250kSPS AV /DV /V = 5V SAMPLE CC CC DRIVE ±2 × V RANGE V /V = ±12V REF DD SS 2.508 INTERNAL REFERENCE 90 T = 25°C A 2.506 f = 10kHz IN 100nF ON V AND V DD SS 2.504 80 2.502 70 2.500 V SS 2.498 60 V DD 2.496 50 2.494 40 2.492 –55 –35 –15 5 25 45 65 85 105 125 30 80 130 180 230 280 330 380 430 480 530 TEMPERATURE (°C) SUPPLY RIPPLE FREQUENCY (kHz) Figure 16. Reference Voltage vs. Temperature Figure 19. PSRR vs. Supply Ripple Frequency 3.20 90 AV /DV /V = 5V CC CC DRIVE V /V = ±12V 3.15 DD SS 3.10 89 ±10V RANGE AV /DV /V = 5.25V 3.05 CC CC DRIVE V /V = ±16.5V DD SS 3.00 88 ±5V RANGE 2.95 AV /DV /V = 5V CC CC DRIVE V /V = ±12V DD SS 2.90 87 2.85 2.80 86 f = 250kSPS SAMPLE 2.75 f = 10kHz IN INTERNAL REFERENCE 2.70 85 –55 –35 –15 5 25 45 65 85 105 125 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Conversion Time vs. Temperature Figure 20. AD7656-1 SNR vs. Temperature 3500 –90 3212 f = 250kSPS SAMPLE V /V = ±15V f = 10kHz DD SS IN 3000 AV /DV /V = 5V INTERNAL REFERENCE CC CC DRIVE 2806 –95 INTERNAL REFERENCE 8192 SAMPLES 2500 –100 2000 ±5V RANGE AV /DV /V = 5V CC CC DRIVE –105 V /V = ±12V 1532 DD SS 1500 –110 1000 ±10V RANGE –115 AV /DV /V = 5.25V CC CC DRIVE 500 392 V /V = ±16.5V DD SS 168 57 25 0 0 0 –120 –5 –4 –3 –2 –1 0 1 2 3 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 18. AD7656-1 Histogram of Codes Figure 21. AD7656-1 THD vs. Temperature Rev. D | Page 16 of 32 NUMBER OF OCCURRENCES CONVERSION TIME (µs) REFERENCE VOLTAGE (V) 07017-018 07017-017 07017-016 PSRR (dB) THD (dB) SNR (dB) 07017-021 07017-020 07017-019 Data Sheet AD7656-1/AD7657-1/AD7658-1 95 120 90 110 85 100 80 90 75 f = 250kSPS 80 SAMPLE ±2 × V RANGE AV /DV /V = 5V 70 REF CC CC DRIVE INTERNAL REFERENCE V /V = ±12V DD SS T = 25°C T = 25°C A A 70 65 f = 10kHz INTERNAL REFERENCE IN 1µF ON AV SUPPLY PIN ±2 × V RANGE CC REF ±100mV SUPPLY RIPPLE AMPLITUDE 30kHz ON SELECTED CHANNEL 60 60 0 20 40 60 80 100 120 140 30 70 110 150 190 230 FREQUENCY OF INPUT NOISE (kHz) SUPPLY RIPPLE FREQUENCY (kHz) Figure 22. Channel-to-Channel Isolation vs. Frequency of Input Noise Figure 24. PSRR vs. Supply Ripple Frequency for AV Supply CC 22 ±5V RANGE 20 ±10V RANGE 18 16 14 AV /DV /V = 5V CC CC DRIVE 12 f = 250kSPS SAMPLE FOR ±5V RANGE V /V = ±12V DD SS FOR ±10V RANGE V /V = ±16.5V DD SS 10 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 23. Dynamic Current vs. Temperature Rev. D | Page 17 of 32 CHANNEL-TO-CHANNEL ISOLATION (dB) DYNAMIC CURRENT (mA) 07017-023 07017-022 PSRR (dB) 07017-036 AD7656-1/AD7657-1/AD7658-1 Data Sheet TERMINOLOGY Total Harmonic Distortion (THD) Integral Nonlinearity (INL) The ratio of the rms sum of the harmonics to the fundamental. The maximum deviation from a straight line passing through For the AD7656-1/AD7657-1/AD7658-1, it is defined as the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at a ½ LSB below the first code 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 transition and full scale at ½ LSB above the last code transition. THD (dB)= 20 log V 1 Differential Nonlinearity (DNL) where: The difference between the measured and the ideal 1 LSB V1 is the rms amplitude of the fundamental. change between any two adjacent codes in the ADC. V2, V3, V4, V5, and V6 are the rms amplitudes of the second Bipolar Zero Scale Error through sixth harmonics. The deviation of the midscale transition (all 1s to all 0s) from Peak Harmonic or Spurious Noise the ideal VIN voltage, that is, AGND − 1 LSB. The ratio of the rms value of the next largest component in the Bipolar Zero Scale Error Matching ADC output spectrum (up to f /2, excluding dc) to the rms SAMPLE The difference in bipolar zero code error between any two input value of the fundamental. Normally, the value of this specification channels. is determined by the largest harmonic in the spectrum, but for Positive Full-Scale Error ADCs where the harmonics are buried in the noise floor, it is The deviation of the last code transition (011 … 110 to 011 … 111) determined by a noise peak. from the ideal (+4 × VREF − 1 LSB, +2 × VREF − 1 LSB) after Intermodulation Distortion (IMD) adjusting for the bipolar zero scale error. With inputs consisting of sine waves at two frequencies, fa and Positive Full-Scale Error Matching fb, any active device with nonlinearities create distortion The difference in positive full-scale error between any two input products at the sum and difference frequencies of mfa ± nfb, channels. where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the Negative Full-Scale Error second-order terms include (fa + fb) and (fa − fb), and the The deviation of the first code transition (10 … 000 to 10 … 001) third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and from the ideal (−4 × VREF + 1 LSB, −2 × VREF + 1 LSB) after (fa − 2fb). adjusting for the bipolar zero scale error. The AD7656-1/AD7657-1/AD7658-1 are tested using the CCIF Negative Full-Scale Error Matching standard in which two input frequencies near the maximum The difference in negative full-scale error between any two input bandwidth are used. In this case, the second-order terms input channels. are usually distanced in frequency from the original sine waves, Track-and-Hold Acquisition Time and the third-order terms are usually at a frequency close to the The track-and-hold amplifier returns to track mode at the end input frequencies. As a result, the second- and third-order terms of the conversion. The track-and-hold acquisition time is the are specified separately. The calculation of the intermodulation time required for the output of the track-and-hold amplifier to distortion is per the THD specification, where it is the ratio of reach its final value, within ±1 LSB, after the end of the conversion. the rms sum of the individual distortion products to the rms See the Track-and-Hold section for more details. amplitude of the sum of the fundamentals and is expressed in Signal-to-(Noise + Distortion) Ratio (SINAD) decibels. The measured ratio of signal-to-(noise + distortion) at the Channel-to-Channel Isolation output of the ADC. The signal is the rms amplitude of the Channel-to-channel isolation is a measure of the level of crosstalk fundamental. Noise is the sum of all nonfundamental signals up between any two channels. It is measured by applying a full-scale, to half the sampling frequency (fSAMPLE/2, excluding dc). 100 kHz sine wave signal to all unselected input channels and The ratio depends on the number of quantization levels in the determining the degree to which the signal attenuates in the digitization process: the more levels, the smaller the quantization selected channel with a 30 kHz signal. noise. The theoretical SINAD ratio for an ideal N-bit converter Power Supply Rejection (PSR) with a sine wave input is given by Variations in power supply affect the full-scale transition but SINAD = (6.02 N + 1.76) dB not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a Therefore, SINAD is 98 dB for a 16-bit converter, 86.04 dB for a change in power supply voltage from the nominal value. See the 14-bit converter, and 74 dB for a 12-bit converter. Typical Performance Characteristics section. Rev. D | Page 18 of 32 Data Sheet AD7656-1/AD7657-1/AD7658-1 Figure 19 shows the power supply rejection ratio vs. supply % FSR ripple frequency for the AD7656-1/AD7657-1/AD7658-1. The %FSR is calculated using the full theoretical span of the ADC. power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the VDD and VSS supplies of the ADC at a frequency sampled, fSAMPLE, as follows: PSRR (dB) = 10 log(Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. Pf is equal to the power at Frequency f coupled onto the S SAMPLE VDD and VSS supplies. Rev. D | Page 19 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet THEORY OF OPERATION and-hold amplifiers return to track mode and the acquisition CONVERTER DETAILS time begins. The AD7656-1/AD7657-1/AD7658-1 are pin- and software- Analog Input compatible, reduced decoupling versions of the AD7656/AD7657/ The AD7656-1/AD7657-1/AD7658-1 can handle true bipolar AD7658 devices. In addition, the AD7656-1/AD7657-1/AD7658-1 input voltages. The logic level on the RANGE pin or the value are high speed, low power converters that allow the simultaneous sampling of six on-chip ADCs. The analog inputs on the AD7656-1/ written to the RNGx bits in the control register determines the AD7657-1/AD7658-1 can accept true bipolar input signals. The analog input range on the AD7656-1/AD7657-1/AD7658-1 for RANGE pin or RNGx bits are used to select either ±4 × VREF or the next conversion. When the RANGE pin or RNGx bits are 1, ±2 × V as the input range for the next conversion. the analog input range for the next conversion is ±2 × VREF. REF When the RANGE pin or RNGx bits are 0, the analog input Each AD7656-1/AD7657-1/AD7658-1 contains six SAR ADCs, six range for the next conversion is ±4 × V . REF track-and-hold amplifiers, an on-chip 2.5 V reference, reference V DD buffers, and high speed parallel and serial interfaces. The parts allow the simultaneous sampling of all six ADCs when the three D1 C2 R1 V1 CONVST pins (CONVST A, CONVST B, and CONVST C) are C1 D2 tied together. Alternatively, the six ADCs can be grouped into three pairs. Each pair has an associated CONVST signal used to V SS initiate simultaneous sampling on each ADC pair, on four ADCs, Figure 25. Equivalent Analog Input Structure or on all six ADCs. CONVST A is used to initiate simultaneous Figure 25 shows an equivalent circuit of the analog input structure sampling on V1 and V2, CONVST B is used to initiate simul- of the AD7656-1/AD7657-1/AD7658-1. The two diodes, D1 and taneous sampling on V3 and V4, and CONVST C is used to D2, provide ESD protection for the analog inputs. Care must be initiate simultaneous sampling on V5 and V6. taken to ensure that the analog input signal never exceeds the A conversion is initiated on the AD7656-1/AD7657-1/AD7658-1 V and V supply rails by more than 300 mV. Signals exceeding DD SS by pulsing the CONVST input. On the rising edge of CONVST, this value cause these diodes to become forward-biased and to the track-and-hold amplifier of the selected ADC pair is placed start conducting current into the substrate. The maximum current into hold mode and the conversions are started. After the rising these diodes can conduct without causing irreversible damage edge of CONVST, the BUSY signal goes high to indicate that the to the parts is 10 mA. Capacitor C1 in Figure 25 is typically conversion is taking place. The conversion clock for the AD7656-1/ about 4 pF and can be attributed primarily to pin capacitance. AD7657-1/AD7658-1 is internally generated, and the conversion Resistor R1 is a lumped component made up of the on time for the parts is 3 µs. Any further CONVST rising edges on resistance of a switch (that is, a track-and-hold switch). This either CONVST A, CONVST B or CONVST C are ignored as long resistor is typically about 3.5 kΩ. Capacitor C2 is the ADC as BUSY is high. The BUSY signal returns low to indicate the end sampling capacitor and has a capacitance of 10 pF typically. of a conversion. On the falling edge of BUSY, the track-and-hold The AD7656-1/AD7657-1/AD7658-1 require VDD and VSS dual amplifier returns to track mode. Data can be read from the output supplies for the high voltage analog input structures. These supplies register via the parallel or serial interface. must be equal to or greater than the analog input range (see Table 8 Track-and-Hold Amplifiers for the requirements on these supplies for each analog input range). The track-and-hold amplifiers on the AD7656-1/AD7657-1/ The AD7656-1/AD7657-1/AD7658-1 require a low voltage AV CC AD7658-1 allow the ADCs to accurately convert an input supply of 4.75 V to 5.25 V to power the ADC core, a DV supply CC sine wave of full-scale amplitude to 16-/14-/12-bit resolution, of 4.75 V to 5.25 V for the digital power, and a V supply of DRIVE respectively. The input bandwidth of the track-and-hold amplifiers 2.7 V to 5.25 V for the interface power. is greater than the Nyquist rate of the ADC, even when the To meet the specified performance when using the minimum AD7656-1/AD7657-1/AD7658-1 are operating at the maximum supply voltage for the selected analog input range, it may be throughput rate. The parts can handle input frequencies of up necessary to reduce the throughput rate from the maximum to 4.5 MHz. throughput rate. The track-and-hold amplifiers sample their respective inputs Table 8. Minimum V /V Supply Voltage Requirements DD SS simultaneously on the rising edge of CONVST. The aperture time Analog Input Reference Full-Scale Minimum (that is, the delay time between the external CONVST signal Range (V) Voltage (V) Input (V) V /V (V) DD SS actually going into hold) for the track-and-hold amplifier is 10 ns. ±4 × V 2.5 ±10 ±10 REF This is well matched across all six track-and-hold amplifiers on one ±2 × V 2.5 ±5 ±5 REF device and from device to device. This allows more than six ADCs to be sampled simultaneously. The end of the conversion is signaled by the falling edge of BUSY, and it is at this point that the track- Rev. D | Page 20 of 32 07017-024 Data Sheet AD7656-1/AD7657-1/AD7658-1 The AD7656-1/AD7657-1/AD7658-1 each contain three on- ADC TRANSFER FUNCTION chip reference buffers as shown in Figure 27. Each of the three The output coding of the AD7656-1/AD7657-1/AD7658-1 is ADC pairs has an associated reference buffer. These reference twos complement. The designed code transitions occur midway buffers require external decoupling capacitors, using 1 µF between successive integer LSB values, that is, 1⁄2 LSB, 3⁄2 LSB. capacitors, on the REFCAPA, REFCAPB, and REFCAPC pins. The LSB size is FSR/65,536 for the AD7656-1, FSR/16,384 for The internal reference buffers can be disabled in software mode the AD7657-1, and FSR/4096 for the AD7658-1. The ideal by writing to Bit DB8 in the internal control register. If a serial transfer characteristic is shown in Figure 26. interface is selected, the internal reference buffers can be disabled in hardware mode by setting the DB14/REFBUFEN/DIS pin high. If 011 ... 111 011 ... 110 the internal reference and its buffers are disabled, apply an external buffered reference to the REFCAPx pins. 000 ... 001 REFCAPA 000 ... 000 111 ... 111 BUF SAR REFIN/ 100 ... 010 SAR REFOUT 100 ... 001 100 ... 000 REF BUF SAR AGND – 1LSB –FSR/2 + 1/2LSB +FSR/2 – 3/2LSB REFCAPB ANALOG INPUT SAR Figure 26. AD7656-1/AD7657-1/AD7658-1 Transfer Characteristic BUF SAR The LSB size is dependent on the analog input range selected SAR (see Table 9). REFCAPC INTERNAL/EXTERNAL REFERENCE Figure 27. Reference Circuit The REFIN/REFOUT pin allows access to the 2.5 V reference of TYPICAL CONNECTION DIAGRAM the AD7656-1/AD7657-1/AD7658-1, or it allows an external reference to be connected to provide the reference source for Figure 28 shows the typical connection diagram for the AD7656-1/ conversions. AD7657-1/AD7658-1, illustrating the reduction in the number and value of decoupling capacitors that are required. There are The AD7656-1/AD7657-1/AD7658-1 can each accommodate a eight AVCC supply pins on each part. The AVCC supplies are the 2.5 V external reference. When applying an external reference via supplies used for the AD7656-1/AD7657-1/AD7658-1 conversion the REFIN/REFOUT pin, the internal reference must be disabled process; therefore, they should be well decoupled. The AVCC supply and the reference buffers must be enabled. Alternatively, an external which is applied to eight AV pins can be decoupled using just one CC refernce can be applied via the REFCAPx pins, in which case the 1 µF capacitor. The AD7656-1/AD7657-1/AD7658-1 can operate internal reference should be disabled and it is recommended with the internal reference or an externally applied reference. In to disable the reference buffers to save power and minimize this configuration, the parts are configured to operate with the crosstalk. After a reset, the AD7656-1/AD7657-1/AD7658-1 external reference. The REFIN/REFOUT pin is decoupled with default to operating in external reference mode with the internal a 1 µF capacitor. The three internal reference buffers are enabled. reference disabled and the reference buffers enabled. Each of the REFCAPx pins is decoupled with a 1 µF capacitor. The internal reference can be enabled in either hardware or If the same supply is being used for the AVCC and DVCC supplies, software mode. To enable the internal reference in hardware mode, place a ferrite or small RC filter between the supply pins. set the H/S SEL pin to 0 and the REF pin to 1. To enable the EN/ DIS AGND pins are connected to the AGND plane of the system. internal reference in software mode, set H/S SEL to 1 and write to The DGND pins are connected to the digital ground plane in the control register to set DB9 of the register to 1. For the internal the system. Connect the AGND and DGND planes together at reference mode, decouple the REFIN/REFOUT pin using a 1 µF one place in the system. This connection should be as close as capacitor. possible to the AD7656-1/AD7657-1/AD7658-1 in the system. Table 9. LSB Size for Each Analog Input Range Input Range for AD7656-1 Input Range for AD7657-1 Input Range for AD7658-1 Parameter ±10 V ±5 V ±10 V ±5 V ±10 V ±5 V LSB Size 0.305 mV 0.152 mV 1.22 mV 0.610 mV 4.88 mV 2.44 mV FS Range 20 V/65,536 10 V/65,536 20 V/16,384 10 V/16,384 20 V/4096 10 V/4096 Rev. D | Page 21 of 32 ADC CODE 07017-025 07017-127 AD7656-1/AD7657-1/AD7658-1 Data Sheet DV CC DIGITAL SUPPLY VOLTAGE +3V OR +5V ANALOG SUPPLY VOLTAGE 5V + + + 1µF 1µF 1µF AGND AV DV DGND V DGND CC CC DRIVE 1 +9.5V TO +16.5V V DD SUPPLY + PARALLEL 1µF D0 TO D15 INTERFACE AGND µP/µC/DSP RESET REFCAPA, B, C + CS 1µF RD AGND BUSY AD7656-1/ 2.5V CONVST A, B, C AD7657-1/ REFIN/OUT REF + AD7658-1 1µF SER/PAR AGND H/S W/B SIX ANALOG RANGE INPUTS 1 –9.5V TO –16.5V V SS SUPPLY STBY V DRIVE 1µF + AGND 1 SEE POWER SUPPLY CONFIGURATION SECTION. Figure 28. Typical Connection Diagram supply is connected to the same supply as the example, consider the case where CONVST A and CONVST C The VDRIVE processor. The voltage on VDRIVE controls the voltage value of are toggled simultaneously but CONVST B is not used. At the output logic signals. end of the conversion process when BUSY goes low a read is implemented. Four read pulses (in parallel mode) are applied Decouple the VDD and VSS signals with a minimum 1 µF and data from V1, V2, V5, and V6 are output. Data from V3 decoupling capacitor. These supplies are used for the high voltage and V4 is not output since CONVST B was not toggled in this analog input structures on the AD7656-1/AD7657-1/AD7658-1 cycle. However, when in serial mode all zeros are output in analog inputs. place of the ADC result for ADCs not included in the conversion DRIVING THE ANALOG INPUTS cycle. See the Serial Interface section for more information. Together, the driver amplifier and the analog input circuit used Parallel Interface (SER/PAR SEL = 0) for the AD7656-1 must settle for a full-scale step input to a 16-bit The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/ level (0.0015%), which is within the specified 550 ns acquisition 12-bit ADCs, respectively. A simultaneous sample of all six time of the AD7656-1. The noise generated by the driver ADCs can be performed by connecting all three CONVST amplifier needs to be kept as low as possible to preserve the pins (CONVST A, CONVST B, and CONVST C) together. The SNR and transition noise performance of the AD7656-1. In AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse addition, the driver also needs to have a THD performance to initiate a conversion; this should consist of a falling CONVST suitable for the AD7656-1. edge followed by a rising CONVST edge. The rising edge of The AD8021 meets these requirements. The AD8021 needs an CONVST initiates simultaneous conversions on the selected external compensation capacitor of 10 pF. If a dual version of ADCs. The AD7656-1/AD7657-1/AD7658-1 each contain an the AD8021 is required, the AD8022 can be used. The AD8610 on-chip oscillator that is used to perform the conversions. The and the AD797 can also be used to drive the AD7656-1/AD7657-1/ conversion time, tCONV, is 3 µs. The BUSY signal goes low to AD7658-1. indicate the end of a conversion. The falling edge of the BUSY signal is used to place the track-and-hold amplifier into track mode. INTERFACE OPTIONS The AD7656-1/AD7657-1/AD7658-1 provide two interface The AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs options: a high speed parallel interface and a high speed serial to be converted simultaneously in pairs by pulsing the three CONVST pins independently. CONVST A is used to initiate interface. The required interface mode is selected via the SER/PAR SEL pin. The parallel interface can operate in word simultaneous conversions on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C (W/B = 0) or byte (W/B = 1) mode. When in serial mode, the is used to initiate simultaneous conversions on V5 and V6. The AD7656-1/AD7657-1/AD7658-1 can be configured into daisy- conversion results from the simultaneously sampled ADCs are chain mode. stored in the output data registers. Note that once a rising edge When in parallel mode, a read operation only accesses the occurs on any one CONVST pin to initiate a conversion, then any results related to conversions which have just occurred. For Rev. D | Page 22 of 32 07017-026 Data Sheet AD7656-1/AD7657-1/AD7658-1 further CONVST rising edges on any of the CONVST pins are occurs on any one CONVST pin to initiate a conversion then any ignored while BUSY is high. further CONVST rising edges on any of the CONVST pins are ignored while BUSY is high. Data can be read from the AD7656-1/AD7657-1/AD7658-1 via the parallel data bus with standard CS and RD signals (W/B = 0). Although a conversion can be initiated during a read sequence, it is not recommended practice, because doing so may affect the To read the data over the parallel bus, tie SER/PAR SEL low. The performance of the conversion. For the specified performance, CS and RD input signals are internally gated to enable the it is recommended to perform the read after the conversion. conversion result onto the data bus. The data lines DB0 to DB15 For unused input channel pairs, tie the associated CONVST pin CS RD leave their high impedance state when both and are to V . DRIVE logic low. If there is only an 8-bit bus available, the AD7656-1/AD7657-1/ The CS signal can be permanently tied low, and the RD signal AD7658-1 parallel interface can be configured to operate in byte can be used to access the conversion results. A read operation mode (W/B = 1). In this configuration, the DB7/HBEN/DCEN can take place after the BUSY signal goes low. The number of pin takes on its HBEN function. Each channel conversion result required read operations depends on the number of ADCs that from the AD7656-1/AD7657-1/AD7658-1 can be accessed in are simultaneously sampled (see Figure 29). If CONVST A two read operations, with eight bits of data provided on DB15 and CONVST B are simultaneously brought low, four read to DB8 for each of the read operations (see Figure 30). The operations are required to obtain the conversion results from HBEN pin determines whether the read operation first accesses V1, V2, V3, and V4. If CONVST A and CONVST C are the high byte or the low byte of the 16-bit conversion result. To simultaneously brought low, four read operations are required always access the low byte first on DB15 to DB8, tie the HBEN to obtain the conversion results from V1, V2, V5, and V6. pin low. To always access the high byte first on DB15 to DB8, tie The conversion results are output in ascending order. For the HBEN pin high. In byte mode when all three CONVST pins the AD7657-1, DB15 and DB14 contain two leading 0s, and are pulsed together to initiate simultaneous conversions on all six DB[13:0] output the 14-bit conversion result. For the AD7658-1, ADCs, 12 read operations are necessary to read back the six DB[15:12] contain four leading 0s, and DB[11:0] output the 16-/14-/12-bit conversion results. DB[6:0] should be left 12-bit conversion result. unconnected in byte mode. When using the three CONVST signals to independently initiate conversions on the three ADC pairs, once a rising edge t 10 CONVST A, CONVST B, CONVST C t t CONV ACQ BUSY t 4 CS t t 3 5 RD t 9 t t 2 7 t t 6 8 t QUIET DATA V1 V2 V3 V4 V5 V6 Figure 29. Parallel Interface Timing Diagram (W/B = 0) CS t t 4 3 t 9 t 5 RD t 8 t t 6 7 DB15 TO DB8 LOW BYTE HIGH BYTE W Figure 30. Parallel Interface—Read Cycle for Byte Mode of Operation ( /B = 1, HBEN = 0) Rev. D | Page 23 of 32 07017-028 07017-027 AD7656-1/AD7657-1/AD7658-1 Data Sheet SOFTWARE SELECTION OF ADCS Table 11. Control Register Bit Function Descriptions The H/S SEL pin determines the source of the combination of ADCs Bit Mnemonic Description H that are to be simultaneously sampled. When the /S SEL pin DB15 VC This bit is used to select the V5 and V6 is logic low, the combination of channels to be simultaneously analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are sampled is determined by the CONVST A, CONVST B, and simultaneously converted on the next H CONVST C pins. When the /S SEL pin is logic high, the CONVST A rising edge. combination of channels selected for simultaneous sampling DB14 VB This bit is used to select the V3 and V4 is determined by the contents of the DB15 to DB13 control analog inputs for the next conversion. registers. In this mode, a write to the control register is necessary. When this bit is set to 1, V3 and V4 are simultaneously converted on the next The control register is an 8-bit write-only register. Data is written CONVST A rising edge. CS WR to this register using the and pins and the DB[15:8] data DB13 VA This bit is used to select the V1 and V2 pins (see Figure 31). The control register is detailed in Table 10 analog inputs for the next conversion. and Table 11. To select an ADC pair to be simultaneously sampled, When this bit is set to 1, V1 and V2 are set the corresponding data line high during the write operation. simultaneously converted on the next CONVST A rising edge. CS DB12 RNGC This bit is used to select the analog input range for the V5 and V6 analog inputs. WR When this bit is set to 1, the ±2 × V range REF t t t 13 12 11 is selected for the next conversion. When t 15 this bit is set to 0, the ±4 × VREF range is t 14 selected for the next conversion. DB15 TO DB8 DATA DB11 RNGB This bit is used to select the analog input range for the V3 and V4 analog inputs. Figure 31. Parallel Interface—Write Cycle for Word Mode (W/B = 0) When this bit is set to 1, the ±2 × VREF range is selected for the next conversion. When The AD7656-1/AD7657-1/AD7658-1 control register allows this bit is set to 0, the ±4 × V range is REF individual ranges to be programmed on each ADC pair. DB12 selected for the next conversion. to DB10 in the control register are used to program the range DB10 RNGA This bit is used to select the analog input range for the V1 and V2 analog inputs. on each ADC pair. When this bit is set to 1, the ±2 × V range REF After a reset occurs on the AD7656-1/AD7657-1/AD7658-1, is selected for the next conversion. When the control register contains all 0s. this bit is set to 0, the ±4 × VREF range is selected for the next conversion. The CONVST A signal is used to initiate a simultaneous DB9 REFEN This bit is used to select the internal conversion on the combination of channels selected via the reference or an external reference. When control register. The CONVST B and CONVST C signals can be this bit is set to 0, the external reference tied low when operating in software mode (H/S SEL = 1). The mode is selected. When this bit is set to 1, the internal reference is selected. number of read pulses required depends on the number of ADCs selected in the control register and on whether the DB8 REFBUF This bit is used to select between using the internal reference buffers and choosing devices are operating in word or byte mode. The conversion to bypass these reference buffers. When results are output in ascending order. this bit is set to 0, the internal reference During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8 buffers are enabled and decoupling is required on the REFCAPx pins. When this are bidirectional and become inputs to the control register when bit is set to 1, the internal reference buffers RD is logic high and CS and WR are logic low. The logic state are disabled and a buffered reference on DB15 through DB8 is latched into the control register when should be applied to the REFCAPx pins. WR goes logic high. 1 Table 10. Control Register Bit Map DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 VC VB VA RNGC RNGB RNGA REFEN REFBUF 1 Default all 0s. Rev. D | Page 24 of 32 07017-029 Data Sheet AD7656-1/AD7657-1/AD7658-1 If it is required to clock conversion data out on two data output CHANGING THE ANALOG INPUT RANGE lines, use DOUT A and DOUT B. To enable DOUT A and (H/S SEL = 0) DOUT B, tie DB0/SEL A and DB1/SEL B to VDRIVE, and The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the DB2/SEL C should be tied low. When six simultaneous conversions user to select either ±2 × VREF or ±4 × VREF as the analog input are performed and only two DOUT lines are used, a 48-SCLK range for the six analog inputs. When the H/S SEL pin is low, transfer can be used to access the data from the AD7656-1/ the logic state of the RANGE pin is sampled on the falling edge of AD7657-1/AD7658-1. Any additional SCLKs applied after this the BUSY signal to determine the range for the next simultaneous result in an output of all zeros. The read sequence is shown in conversion. When the RANGE pin is logic high at the falling Figure 33 for a simultaneous conversion on all six ADCs using edge of the BUSY signal, the range for the next conversion is two DOUT lines. If a simultaneous conversion occurred on all ±2 × V . When the RANGE pin is logic low at the falling REF six ADCs, and only two DOUT lines are used to read the results edge of the BUSY signal, the range for the next conversion is from the AD7656-1/AD7657-1/AD7658-1, DOUT A clocks out ±4 × VREF. After a RESET pulse, the range is updated on the first the result from V1, V2, and V5, whereas DOUT B clocks out falling BUSY edge. the results from V3, V4, and V6. CHANGING THE ANALOG INPUT RANGE Data can also be clocked out using just one DOUT line, in which (H/S SEL = 1) case useDOUT A to access the conversion data. To configure the AD7656-1/AD7657-1/AD7658-1 to operate in this mode, H When the /S SEL pin is high, the range can be changed by tie DB0/SEL A to V , and tie DB1/SEL B and DB2/SEL C DRIVE writing to the control register. DB[12:10] in the control register low. The disadvantage of using only one DOUT line is that the are used to select the analog input ranges for the next conversion. throughput rate is reduced. Data can be accessed from the Each analog input pair has an associated range bit, allowing AD7656-1/AD7657-1/AD7658-1 using one 96-SCLK transfer, independent ranges to be programmed on each ADC pair. When three 32-SCLK individually framed transfers, or six 16-SCLK the RNGx bit is set to 1, the range for the next conversion is ±2 individually framed transfers. Any additional SCLKs applied × VREF. When the RNGx bit is set to 0, the range for the next after this result in an output of all zeros. When using the serial conversion is ±4 × VREF. interface, tie the RD signal low and leave the unused DOUT line(s) Serial Interface (SER/ SEL = 1) PAR unconnected. By pulsing one, two, or all three CONVST signals, the AD7656-1/ Whether one, two, or three data output lines are used, if a AD7657-1/AD7658-1 use their on-chip trimmed oscillator to particular CONVST pin is not used in the conversion cycle then simultaneously convert the selected channel pairs on the rising all zeros are output in place of the ADC result for the associated edge of CONVST. After the rising edge of CONVST, the BUSY ADCs even though they were not used in the conversion cycle. signal goes high to indicate that the conversion has started. It This means that if, for example, only CONVST B is pulsed and returns low when the conversion is complete, 3 µs later. Any one data output pin is in use, then 64 SCLKs are required to further CONVST rising edges on either CONVST A, CONVST B, access the results from V3 and V4, but only 32 SCLKs are or CONVST C are ignored as long as BUSY is high. The output required if two or three data output lines are in use. register is loaded with the new conversion results, and data can be read from the AD7656-1/AD7657-1/AD7658-1. To read the SERIAL READ OPERATION PAR data back from the parts over the serial interface, SER/ SEL Figure 34 shows the timing diagram for reading data from the should be tied high. The and SCLK signals are used to transfer CS AD7656-1/AD7657-1/AD7658-1 when the serial interface is data from the AD7656-1/AD7657-1/AD7658-1. The parts have selected. The SCLK input signal provides the clock source for three DOUT pins: DOUT A, DOUT B, and DOUT C. Data the serial interface. The CS signal goes low to access data from can be read back from each part using one, two, or all three the AD7656-1/AD7657-1/AD7658-1. The falling edge of CS DOUT lines. takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. The ADCs output 16 bits for each Figure 32 shows six simultaneous conversions and the read conversion result; the data stream of the AD7656-1 consists of sequence using three DOUT lines. Also in Figure 32, 32 SCLK 16 bits of conversion data, provided MSB first. The data stream transfers are used to access data from the AD7656-1/AD7657-1/ for the AD7657-1 consists of two leading 0s followed by 14 bits AD7658-1; however, two 16-SCLK individually framed transfers of conversion data, provided MSB first. The data stream for the CS with the signal can also be used to access the data on the AD7658-1 consists of four leading 0s and 12 bits of conversion three DOUT lines. Any additional SCLKs applied after this data, provided MSB first. result in an output of all zeros. When the serial interface is selected and conversion data is clocking out on all three DOUT lines, tie DB0/SEL A, DB1/SEL B, and DB2/SEL C to VDRIVE. These pins are used to enable the DOUT A to DOUT C lines, respectively. Rev. D | Page 25 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet The first bit of the conversion result is valid on the first SCLK 16 clock pulses must be provided to the AD7656-1/AD7657-1/ CS AD7658-1. Figure 34 shows how a 16-SCLK read is used to falling edge after the falling edge. The subsequent 15 data access the conversion results. bits are clocked out on the rising edge of the SCLK signal. Data is valid on the SCLK falling edge. To access each conversion result, CONVST A, CONVST B, t CONV t ACQ CONVST C BUSY CS 16 32 SCLK t QUIET DOUT A V1 V2 V4 DOUT B V3 DOUT C V5 V6 Figure 32. Serial Interface with Three DOUT Lines CS 48 SCLK DOUT A V1 V2 V5 DOUT B V3 V4 V6 Figure 33. Serial Interface with Two DOUT Lines t 1 CONVST A, t 10 CONVST B, t t ACQ CONV CONVST C t 2 BUSY ACQUISITION CONVERSION ACQUISITION CS t QUIET t t 19 18 SCLK t 16 t 17 t 20 DOUT A, t 21 DOUT B, DB15 DB14 DB13 DB1 DB0 DOUT C Figure 34. Serial Read Operation Rev. D | Page 26 of 32 07017-031 07017-030 07017-032 Data Sheet AD7656-1/AD7657-1/AD7658-1 The maximum number of devices in the chain is limited by the DAISY-CHAIN MODE (DCEN = 1, SER/PAR SEL = 1) throughput required per channel depending on the application When reading conversion data back from the AD7656-1/AD7657-1/ needs, the SCLK frequency used, and the number of serial data AD7658-1 using one/two/three DOUT pins, it is possible to lines used. configure the parts to operate in daisy-chain mode by using the Standby/Partial Power-Down Modes of Operation DCEN pin. This daisy-chain feature allows multiple AD7656-1/ PAR (SER/ SEL = 0 or 1) AD7657-1/AD7658-1 devices to be cascaded together and is useful for reducing the component count and wiring connections. Each ADC pair can be individually placed into partial power- An example connection of two devices is shown in Figure 36. down mode at the end of their conversion by bringing the This configuration shows two DOUT lines being used for each associated CONVST signal low before the falling edge of BUSY. device. Simultaneous sampling of the 12 analog inputs is possible If a CONVST pin is low when BUSY goes low, the associated by using a common CONVST signal. The DB5, DB4, and DB3 ADC pair only enters partial power-down mode if they were data pins are used as the DCIN[A:C] data input pins for the actually converting within that cycle, that is, if that particular daisy-chain mode. CONVST pin was used to trigger conversions. To power an ADC pair back up, the CONVST signal should be brought high The rising edge of CONVST is used to initiate a conversion on to tell the ADC pair to power up and place the track-and-hold the AD7656-1/AD7657-1/AD7658-1. After the BUSY signal has amplifier into track mode. After the power-up time from partial gone low to indicate that the conversion is complete, the user can power-down has elapsed, the CONVST signal can receive a begin to read the data from the two devices. Figure 37 shows the rising edge to initiate a valid conversion. In partial power-down serial timing diagram when operating two AD7656-1/AD7657-1/ mode, the reference buffers remain powered up. When an ADC AD7658-1 devices in daisy-chain mode. pair is in partial power-down mode, conversions can still occur CS The falling edge is used to frame the serial transfer from the on the other fully powered ADCs. In Figure 35 at Point A, ADC 1 AD7656-1/AD7657-1/AD7658-1 devices, to take the bus out of and ADC 2 enter partial power-down while ADC 3 to ADC 6 three-state, and to clock out the MSB of the first conversion remain fully powered. At Point B in Figure 35, ADC1 and ADC 2 result. In the example shown in Figure 37, all 12 ADC channels begin to power up. Once the required power up time has are simultaneously sampled. Two DOUT lines are used to read elapsed then a conversion can be initiated on the next CONVST the conversion results in this example. CS frames a 96-SCLK rising edge as shown. transfer. During the first 48 SCLKs, the conversion data is A B t transferred from Device 2 to Device 1. DOUT A on Device 2 WAKE-UP transfers conversion data from V1, V2, and V5 into DCIN A in CONVST A Device 1; DOUT B on Device 2 transfers conversion results from V3, V4, and V6 to DCIN B in Device 1. During the first 48 SCLKs, BUSY Device 1 transfers data into the digital host. DOUT A on Device 1 CONVST B transfers conversion data from V1, V2, and V5; DOUT B on Device 1 transfers conversion data from V3, V4, and V6. During CONVST C the last 48 SCLKs, Device 2 clocks out 0s, and Device 1 shifts the Figure 35. Entering and Exiting Partial Power-Down Mode data clocked in from Device 2 during the first 48 SCLKs into The AD7656-1/AD7657-1/AD7658-1 have a standby mode the digital host. This example can also be implemented using whereby the devices can be placed into a low power consumption six 16-SCLK individually framed transfers if DCEN remains mode (315 μW maximum). The AD7656-1/AD7657-1/AD7658-1 high during the transfers. STBY are placed into standby mode by bringing the input logic Figure 38 shows the timing if two AD7656-1/AD7657-1/AD7658- low and can be powered up again for normal operation by bringing 1 devices are configured in daisy-chain mode and are operating STBY logic high. The output data buffers are still operational with three DOUT lines. Assuming that a simultaneous sampling when the AD7656-1/AD7657-1/AD7658-1 are in standby of all 12 inputs occurs, the CS frames a 64 SCLK transfer during mode, meaning the user can continue to access the conversion the read operation. During the first 32 SCLKs of this transfer, results of the parts. This standby feature can be used to reduce the conversion results from Device 1 are clocked into the digital the average power consumed by the AD7656-1/AD7657-1/ host and the conversion results from Device 2 are clocked into AD7658-1 when operating at lower throughput rates. The parts Device 1. During the last 32 SCLKs of the transfer, the conversion can be placed into standby at the end of each conversion when results from Device 2 are clocked out of Device 1 and into the BUSY goes low and are taken out of standby mode prior to the digital host, and Device 2 clocks out 0s. next conversion. The time for the AD7656-1/AD7657-1/ AD7658-1 to come out of standby is called the wake-up time. The wake-up time limits the maximum throughput rate at which the AD7656-1/AD7657-1/AD7658-1 can operate when powering down between conversions. See the Specifications section. Rev. D | Page 27 of 32 07017-135 AD7656-1/AD7657-1/AD7658-1 Data Sheet CONVERT DIGITAL HOST CONVST CONVST DOUT A DCIN A DOUT A DATA IN1 AD7656-1/ AD7656-1/ AD7657-1/ DCIN B AD7657-1/ DOUT B DATA IN2 DOUT B AD7658-1 AD7658-1 SCLK CS SCLK CS CS SCLK DCEN = 0 DCEN = 1 DEVICE 2 DEVICE 1 Figure 36. Daisy-Chain Configuration CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 65 94 95 96 SCLK DEVICE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 Figure 37. Daisy-Chain Serial Interface Timing with Two DOUT Lines CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 SCLK DEVICE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 1, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 MSB V5 LSB V5 MSB V6 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 2, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 Figure 38. Daisy-Chain Serial Interface Timing with Three DOUT Lines Rev. D | Page 28 of 32 07017-033 07017-034 07017-035 Data Sheet AD7656-1/AD7657-1/AD7658-1 APPLICATION HINTS and each REFCAPx pin. Avoid sharing these capacitors between LAYOUT pins, and use vias to connect the capacitors to the power and Design the printed circuit board (PCB) that houses the AD7656-1/ ground planes. In addition, use wide, short traces between each AD7657-1/AD7658-1 so that the analog and digital sections are via and the capacitor pad, or place the vias adjacent to the capacitor separated and confined to different areas of the board. pad to minimize parasitic inductances. The AD7656-1/AD7657-1/ Use at least one ground plane. It can be common or split AD7658-1 offer the user a reduced decoupling solution that is pin between the digital and analog sections. In the case of the split and software compatible with AD7656/AD7657/AD7658. The plane, join the digital and analog ground in only one place, recommended reduced decoupling required for AD7656-1/ preferably underneath the AD7656-1/AD7657-1/AD7658-1, AD7657-1/AD7658-1 is outlined in Figure 28. or at least as close as possible to the part. POWER SUPPLY CONFIGURATION If the AD7656-1/AD7657-1/AD7658-1 are in a system where As outlined in the Absolute Maximum Ratings section, the multiple devices require analog-to-digital ground connections, analog inputs should not be applied to the AD7656-1/ the connection should still be made at only one point, a star AD7657-1/AD7658-1 until after the AD7656-1/AD7657-1/ ground point, established as close as possible to the AD7656-1/ AD7658-1 power supplies have been applied to the device. AD7657-1/AD7658-1. Make good connections to the ground However, if a condition exists where the system analog signal plane. Avoid sharing one connection for multiple ground pins. conditioning circuitry supplies are different to the V and DD Individual vias or multiple vias to the ground plane should be V supplies of the AD7656-1/AD7657-1/AD7658-1, or if the SS used for each ground pin. analog inputs may be applied prior to the AD7656-1/ Avoid running digital lines under the devices because doing so AD7657-1/AD7658-1 supplies being established, then an analog couples noise onto the die. Allow the analog ground plane to input series resister and Schottky diodes in series with the VDD run under the AD7656-1/AD7657-1/AD7658-1 to avoid noise and VSS supplies are recommended (see Figure 39). coupling. Shield fast-switching signals like CONVST or clocks This configuration should also be used if AVCC is applied to the with digital ground to avoid radiating noise to other sections of AD7656-1/AD7657-1/AD7658-1 prior to VDD and VSS being the board, and the fast switching signals should never run near applied. analog signal paths. Avoid crossover of digital and analog V DD signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. 240Ω V1 V DD The power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS pins V2 AD7656-1/ on the AD7656-1/AD7657-1/AD7658-1 should use as large a V3 ANALOG AD7657-1/ INPUTS V4 trace as possible to provide low impedance paths and reduce the AD7658-1 V5 effect of glitches on the power supply lines. Establish good V6 V SS connections between the AD7656-1/AD7657-1/AD7658-1 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. V SS Good decoupling is also important to lower the supply impedance Figure 39. Power Supply Configuration presented to the AD7656-1/AD7657-1/AD7658-1 and to reduce the magnitude of the supply spikes. Place the decoupling capacitors close to, ideally right up against, these pins and their corresponding ground pins. Additionally, place low ESR 1 μF capacitors on each of the supply pins, the REFIN/REFOUT pin, Rev. D | Page 29 of 32 07017-037 Data Sheet AD7656-1/AD7657-1/AD7658-1 OUTLINE DIMENSIONS 12.20 12.00 SQ 0.75 11.80 0.60 1.60 0.45 MAX 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 16 33 0.15 0° SEATING 17 32 0.05 0.08 PLANE VIEW A COPLANARITY 0.27 0.50 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 40. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Notes Temperature Range Package Description Package Option AD7656BSTZ-1 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656BSTZ-1-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656YSTZ-1 −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656YSTZ-1-RL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657BSTZ-1 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657BSTZ-1-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657YSTZ-1 −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657YSTZ-1-RL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658BSTZ-1 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658BSTZ-1-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658YSTZ-1 −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658YSTZ-1-RL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 2 EVAL-AD7656-1CBZ Evaluation Board 2 EVAL-AD7657-1CBZ Evaluation Board 2 EVAL-AD7658-1CBZ Evaluation Board 3 EVAL-CONTROL BRD2Z Controller Board 1 Z = RoHS Compliant Part. 2 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, for example, EVAL-AD7656-1/AD7657-1/AD7658-1CB, the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information. Rev. D | Page 30 of 32 051706-A Data Sheet AD7656-1/AD7657-1/AD7658-1 NOTES Rev. D | Page 31 of 32 AD7656-1/AD7657-1/AD7658-1 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07017-0-3/12(D) Rev. D | Page 32 of 32