ANALOG DEVICES AD7657

250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/12-Bit ADC Data Sheet AD7656/AD7657/AD7658 FEATURES FUNCTIONAL BLOCK DIAGRAM V CONVST A CONVST B CONVST C AV DV DD CC CC 6 independent ADCs True bipolar analog inputs CS Pin-/software-selectable ranges: ±10 V, ±5 V CLK REF SER/PAR CONTROL OSC Fast throughput rate: 250 kSPS LOGIC V DRIVE STBY iCMOS process technology BUF OUTPUT Low power DOUT A 16-/14-/12-BIT SAR DRIVERS V1 T/H 140 mW at 250 kSPS with 5 V supplies SCLK Wide input bandwidth V2 T/H 16-/14-/12-BIT SAR 86.5 dB SNR at 50 kHz input frequency OUTPUT DOUT B BUF DRIVERS On-chip reference and reference buffers V3 T/H 16-/14-/12-BIT SAR OUTPUT Parallel, serial, and daisy-chain interface modes DRIVERS DOUT C High speed serial interface V4 T/H 16-/14-/12-BIT SAR DATA/ SPI-/QSPI™-/MICROWIRE™-/DSP-compatible OUTPUT CONTROL DRIVERS BUF LINES Standby mode: 100 µW maximum V5 T/H 16-/14-/12-BIT SAR RD 64-lead LQFP WR T/H V6 16-/14-/12-BIT SAR APPLICATIONS AD7656/AD7657/AD7658 V AGND DGND Power line monitoring systems SS Instrumentation and control systems Figure 1. Multi-axis positioning systems GENERAL DESCRIPTION 1 The AD7656/AD7657/AD7658 contain six 16-/14-/12-bit, The conversion process and data acquisition are controlled fast, low power, successive approximation ADCs all in the one using CONVST signals and an internal oscillator. Three package that is designed on the iCMOS™ process (industrial CONVST pins allow independent, simultaneous sampling of CMOS). iCMOS is a process combining high voltage silicon the three ADC pairs. The AD7656/AD7657/AD7658 all have a high speed parallel and serial interface, allowing the devices with submicron CMOS and complementary bipolar technol- to interface with microprocessors or DSPs. In serial interface ogies. It enables the development of a wide range of high performance analog ICs, capable of 33 V operation in a mode, the parts have a daisy-chain feature that allows multiple footprint that no previous generation of high voltage parts ADCs to connect to a single serial interface. The AD7656/ could achieve. Unlike analog ICs using conventional CMOS AD7657/AD7658 can accommodate true bipolar input signals processes, iCMOS components can accept bipolar input signals in the ±4 × V range and ±2 × V range. The AD7656/ REF REF while providing increased performance, which dramatically AD7657/AD7658 also contain an on-chip 2.5 V reference. reduces power consumption and package size. PRODUCT HIGHLIGHTS The AD7656/AD7657/AD7658 feature throughput rates up 1. Six 16-/14-/12-bit, 250 kSPS ADCs on board. to 250 kSPS. The parts contain low noise, wide bandwidth, 2. Six true bipolar, high impedance analog inputs. track-and-hold amplifiers that can handle input frequencies 3. Parallel and high speed serial interfaces. up to 12 MHz. 1 Protected by U.S. Patent No. 6,731,232. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved. 05020-001 AD7656/AD7657/AD7658 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 14 Applications ....................................................................................... 1 Terminology .................................................................................... 18 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 20 General Description ......................................................................... 1 Converter Details ....................................................................... 20 Product Highlights ........................................................................... 1 ADC Transfer Function ............................................................. 21 Revision History ............................................................................... 2 Reference Section ....................................................................... 21 Specifications ..................................................................................... 3 Typical Connection Diagram ................................................... 21 AD7656 .......................................................................................... 3 Driving the Analog Inputs ........................................................ 22 AD7657 .......................................................................................... 5 Interface Section ......................................................................... 22 AD7658 .......................................................................................... 7 Application Hints ........................................................................... 29 Timing Specifications .................................................................. 9 Layout .......................................................................................... 29 Absolute Maximum Ratings .......................................................... 10 Power Supply Configuration..................................................... 29 Thermal Resistance .................................................................... 10 Outline Dimensions ....................................................................... 30 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 30 Pin Configuration and Function Descriptions ........................... 11 REVISION HISTORY 3/12—Rev. C to Rev D 4/06—Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 22 Added AD7657/AD7658 parts ......................................... Universal 8/10—Rev. B to Rev. C Changes to Table 1 ............................................................................. 3 Changes to t1 Unit in Table 4 ........................................................... 9 Changes to Table 5 .......................................................................... 10 Changes to VDD to AVCC Rating in Table 5 .................................. 10 3/06—Revision 0: Initial Version Added Power Supply Configuration Section .............................. 29 Added Figure 36 .............................................................................. 29 V to AV DD CC 1/10—Rev. A to Rev. B Changes to Unit of DC Accuracy Parameter, Table 1 .................. 3 Changes to DC Accuracy Parameter, Table 2 ............................... 5 Changes to DC Accuracy Parameter, Table 3 ............................... 7 Changes to Terminology Section.................................................. 18 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 Rev. D | Page 2 of 32 Data Sheet AD7656/AD7657/AD7658 SPECIFICATIONS AD7656 V = 2.5 V internal/external, AV = 4.75 V to 5.25 V, DV = 4.75 V to 5.25 V, V = 2.7 V to 5.25 V; REF CC CC DRIVE For ±4 × V range: V = 10 V to 16.5 V, V = −10 V to −16.5 V; For ±2 × V range: V = 5 V to 16.5 V, V = −5 V to −16.5 V; REF DD SS REF DD SS 1 fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 1 Parameter B Version Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN 2 Signal-to-Noise + Distortion (SINAD) 84 84 dB min 85.5 85.5 dB typ 2 Signal-to-Noise Ratio (SNR) 85 85 dB min 86.5 86.5 dB typ 2 Total Harmonic Distortion (THD) −90 −90 dB max −92 −92 dB typ V /V = ±5 V to ±10 V DD SS −100 −100 dB typ V /V = ±12 V to ±16.5 V DD SS 2 Peak Harmonic or Spurious Noise (SFDR) −100 −100 dB typ 2 Intermodulation Distortion (IMD) fa = 50 kHz, fb = 49 kHz Second-Order Terms −112 −112 dB typ Third-Order Terms −107 −107 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ 2 Channel-to-Channel Isolation −100 −100 dB typ fIN on unselected channels up to 100 kHz Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 16 16 Bits No Missing Codes 15 14 Bits min 16 16 Bits min @ 25°C 2 Integral Nonlinearity ±3 ±4.5 LSB max ±1 ±1 LSB typ 2 Positive Full-Scale Error ±0.75 ±0.75 % FSR max ±0.22% FSR typical 2 Positive Full-Scale Error Matching ±0.35 ±0.35 % FSR max 2 Bipolar Zero-Scale Error ±0.023 ±0.023 % FSR max ±0.004% FSR typical 2 Bipolar Zero-Scale Error Matching ±0.038 ±0.038 % FSR max 2 Negative Full-Scale Error ±0.75 ±0.75 % FSR max ±0.22% FSR typical 2 Negative Full-Scale Error Matching ±0.35 ±0.35 % FSR max ANALOG INPUT See Table 8 for min VDD/VSS for each range Input Voltage Ranges ±4 × VREF ±4 × VREF V RNG bit/RANGE pin = 0 ±2 × VREF ±2 × VREF V RNG bit/RANGE pin = 1 DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 10 10 pF typ ±4 × V range when in track REF 14 14 pF typ ±2 × V range when in track REF REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 18.5 18.5 pF typ REF DIS = 1 EN/ Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ Rev. D | Page 3 of 32 AD7656/AD7657/AD7658 Data Sheet 1 1 Parameter B Version Y Version Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE 0.7 × VDRIVE V min Input Low Voltage (VINL) 0.3 × VDRIVE 0.3 × VDRIVE V max Input Current (I ) ±1 ±1 µA max Typically 10 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance (C ) 10 10 pF max IN LOGIC OUTPUTS Output High Voltage (V ) V − 0.2 V − 0.2 V min I = 200 µA OH DRIVE DRIVE SOURCE Output Low Voltage (V ) 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±1 ±1 µA max 3 Floating-State Output Capacitance 10 10 pF max Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 3.1 µs max 2, 3 Track-and-Hold Acquisition Time 550 550 ns max Throughput Rate 250 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD 5/15 5/15 V nom min/max For 4 × VREF range, VDD = 10 V to 16.5 V V −5/−15 −5/−15 V nom min/max For 4 × V range, V = −10 V to −16.5 V SS REF DD AV 5 5 V nom CC DVCC 5 5 V nom VDRIVE 3/5 3/5 V nom min/max ITOTAL Digital I/PS = 0 V or VDRIVE Normal Mode (Static) 28 28 mA max AV = DV = V = 5.25 V, V = 16.5 V, CC CC DRIVE DD (Includes IAV , IV , IV , IV , IDV ) V = −16.5 V CC DD SS DRIVE CC SS Normal Mode (Operational) 26 26 mA max f = 250 kSPS, AV = DV = V = 5.25 V, SAMPLE CC CC DRIVE (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) VDD = 16.5 V, VSS = −16.5 V ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, fSAMPLE = 250 kSPS IDD (Operational) 0.25 0.25 mA max VDD = 16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 7 mA max AV = DV = V = 5.25 V, V = 16.5 V, CC CC DRIVE DD V = −16.5 V SS Full Power-Down Mode ( Pin) 80 80 µA max SCLK on or off, AV = DV = V = 5.25 V, STBY CC CC DRIVE VDD = 16.5 V, VSS = −16.5 V Power Dissipation AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, V = −16.5 V SS Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max f = 250 kSPS SAMPLE Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin) 100 100 µW max 1 Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. Rev. D | Page 4 of 32 Data Sheet AD7656/AD7657/AD7658 AD7657 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; For ±4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; 1 f = 250 kSPS, T = T to T , unless otherwise noted. SAMPLE A MIN MAX Table 2. 1 1 Parameter B Version Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 2 Signal-to-Noise + Distortion (SINAD) 81.5 81.5 dB min 2 Signal-to-Noise Ratio (SNR) 82.5 82.5 dB min 83.5 83.5 dB typ 2 Total Harmonic Distortion (THD) −90 −89 dB max −92 −92 dB typ 2 Peak Harmonic or Spurious Noise (SFDR) −100 −100 dB typ 2 Intermodulation Distortion (IMD) fa = 50 kHz, fb = 49 kHz Second-Order Terms −109 −109 dB typ Third-Order Terms −104 −104 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ 2 Channel-to-Channel Isolation −100 −100 dB typ f on unselected channels up to 100 kHz IN Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 14 14 Bits No Missing Codes 14 14 Bits min 2 Integral Nonlinearity ±1.5 ±1.5 LSB max ±1 ±1 LSB typ 2 Positive Full-Scale Error ±0.75 ±0.75 % FSR max ±0.183% FSR typical 2 Positive Full-Scale Error Matching ±0.3 ±0.3 % FSR max 2 Bipolar Zero-Scale Error ±0.0305 ±0.0305 % FSR max ±0.015 % FSR typical 2 Bipolar Zero-Scale Error Matching ±0.0427 ±0.0427 % FSR max 2 Negative Full-Scale Error ±0.75 ±0.75 % FSR max ±0.183% FSR typical 2 Negative Full-Scale Error Matching ±0.3 ±0.3 % FSR max ANALOG INPUT See Table 8 for min VDD/VSS for each range Input Voltage Ranges ±4 × VREF ±4 × VREF V RNG bit/RANGE pin = 0 ±2 × VREF ±2 × VREF V RNG bit/RANGE pin = 1 DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 10 10 pF typ ±4 × V range when in track REF 14 14 pF typ ±2 × VREF range when in track REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 18.5 18.5 pF typ REF DIS = 1 EN/ Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ LOGIC INPUTS Input High Voltage (V ) 0.7 × V 0.7 × V V min INH DRIVE DRIVE Input Low Voltage (VINL) 0.3 × VDRIVE 0.3 × VDRIVE V max Input Current (IIN) ±1 ±1 µA max Typically 10 nA, VIN = 0 V or VDRIVE 3 Input Capacitance (C ) 10 10 pF max IN Rev. D | Page 5 of 32 AD7656/AD7657/AD7658 Data Sheet 1 1 Parameter B Version Y Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage (VOH) VDRIVE − 0.2 VDRIVE − 0.2 V min ISOURCE = 200 µA Output Low Voltage (VOL) 0.2 0.2 V max ISINK = 200 µA Floating-State Leakage Current ±1 ±1 µA max 3 Floating-State Output Capacitance 10 10 pF max Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 3.1 µs max 2, 3 Track-and-Hold Acquisition Time 550 550 ns max Throughput Rate 250 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD 5/15 5/15 V nom min/max For 4 × VREF range, VDD = 10 V to 16.5 V VSS −5/−15 −5/−15 V nom min/max For 4 × VREF range, VDD = −10 V to −16.5 V AVCC 5 5 V nom DV 5 5 V nom CC V 3/5 3/5 V nom min/max DRIVE I Digital I/P = 0 V or V TOTAL S DRIVE Normal Mode (Static) 28 28 mA max AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) VSS = −16.5 V Normal Mode (Operational) 26 26 mA max f = 250 kSPS, AV = DV = V = 5.25 V, SAMPLE CC CC DRIVE (Includes IAV , IV , IV , IV , IDV ) V = 16.5 V, V = −16.5 V CC DD SS DRIVE CC DD SS I (Operational) 0.25 0.25 mA max V = −16.5 V, f = 250 kSPS SS SS SAMPLE IDD (Operational) 0.25 0.25 mA max VDD = 16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 7 mA max AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V Full Power-Down Mode (STBY Pin) 80 80 µA max SCLK on or off, AV = DV = V = 5.25 V, CC CC DRIVE V = 16.5 V, V = −16.5 V DD SS Power Dissipation AV = DV = V = 5.25 V, V = 16.5 V, CC CC DRIVE DD VSS = −16.5 V Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max fSAMPLE = 250 kSPS Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin) 100 100 µW max 1 Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. Rev. D | Page 6 of 32 Data Sheet AD7656/AD7657/AD7658 AD7658 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; For ±4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; 1 f = 250 kSPS, T = T to T , unless otherwise noted. SAMPLE A MIN MAX Table 3. 1 1 Parameter B Version Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 2 Signal-to-Noise + Distortion (SINAD) 73 73 dB min 73.5 73.5 dB typ 2 Total Harmonic Distortion (THD) −88 −88 dB max −92 −92 dB typ 2 Peak Harmonic or Spurious Noise (SFDR) −97 −97 dB typ 2 Intermodulation Distortion (IMD) fa = 50 kHz, fb = 49 kHz Second-Order Terms −106 −106 dB typ Third-Order Terms −101 −101 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ 2 Channel-to-Channel Isolation −100 −100 dB typ fIN on unselected channels up to 100 kHz Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB DC ACCURACY Resolution 12 12 Bits No Missing Codes 12 12 Bits min Differential Nonlinearity ±0.7 ±0.7 LSB max 2 Integral Nonlinearity ±1 ±1 LSB max 2 Positive Full-Scale Error ±0.75 ±0.75 % FSR max ±0.244% FSR typical 2 Positive Full-Scale Error Matching ±0.366 ±0.366 % FSR max 2 Bipolar Zero-Scale Error ±3 ±3 LSB max ±0.0488% FSR typical 2 Bipolar Zero-Scale Error Matching ±3 ±3 LSB max 2 Negative Full-Scale Error ±0.75 ±0.75 % FSR max ±0.244% FSR typical 2 Negative Full-Scale Error Matching ±0.366 ±0.366 % FSR max ANALOG INPUT See Table 8 for min V /V for each range DD SS Input Voltage Ranges ±4 × VREF ±4 × VREF V RNG bit/RANGE pin = 0 ±2 × VREF ±2 × VREF V RNG bit/RANGE pin = 1 DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 10 10 pF typ ±4 × V range when in track REF 14 14 pF typ ±2 × V range when in track REF REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 µA max 3 Input Capacitance 18.5 18.5 pF typ REFEN/DIS = 1 Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ LOGIC INPUTS Input High Voltage (V ) 0.7 × V 0.7 × V V min INH DRIVE DRIVE Input Low Voltage (V ) 0.3 × V 0.3 × V V max INL DRIVE DRIVE Input Current (I ) ±1 ±1 µA max Typically 10 nA, V = 0 V or V IN IN DRIVE 3 Input Capacitance (CIN) 10 10 pF max Rev. D | Page 7 of 32 AD7656/AD7657/AD7658 Data Sheet 1 1 Parameter B Version Y Version Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage (VOH) VDRIVE − 0.2 VDRIVE − 0.2 V min ISOURCE = 200 µA Output Low Voltage (VOL) 0.2 0.2 V max ISINK = 200 µA Floating-State Leakage Current ±1 ±1 µA max 3 Floating-State Output Capacitance 10 10 pF max Output Coding Twos complement CONVERSION RATE Conversion Time 3.1 3.1 µs max 2, 3 Track-and-Hold Acquisition Time 550 550 ns max Throughput Rate 250 250 kSPS Parallel interface mode only POWER REQUIREMENTS VDD 5/15 5/15 V nom min/max For 4 × VREF range, VDD = 10 V to 16.5 V VSS −5/−15 −5/−15 V nom min/max For 4 × VREF range, VDD = −10 V to −16.5 V AVCC 5 5 V nom DV 5 5 V nom CC V 3/5 3/5 V nom min/max DRIVE I Digital I/P = 0 V or V TOTAL S DRIVE Normal Mode (Static) 28 28 mA max AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) VSS = −16.5 V Normal Mode (Operational) 26 26 mA max f = 250 kSPS, AV = DV = V = 5.25 V, SAMPLE CC CC DRIVE (Includes IAV , IV , IV , IV , IDV ) V = 16.5 V, V = −16.5 V CC DD SS DRIVE CC DD SS I (Operational) 0.25 0.25 mA max V = −16.5 V, f = 250 kSPS SS SS SAMPLE IDD (Operational) 0.25 0.25 mA max VDD = 16.5 V, fSAMPLE = 250 kSPS Partial Power-Down Mode 7 7 mA max AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V Full Power-Down Mode (STBY Pin) 80 80 µA max SCLK on or off, AV = DV = V = 5.25 V, CC CC DRIVE V = 16.5 V, V = −16.5 V DD SS Power Dissipation AV = DV = V = 5.25 V, V = 16.5 V, CC CC DRIVE DD VSS = −16.5 V Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max fSAMPLE = 250 kSPS Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin) 100 100 µW max 1 Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. Rev. D | Page 8 of 32 Data Sheet AD7656/AD7657/AD7658 TIMING SPECIFICATIONS AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, 1 TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V Unit Description PARALLEL MODE tCONVERT 3 3 µs typ Conversion time, internal clock tQUIET 150 150 ns min Minimum quiet time required between bus relinquish and start of next conversion t 550 550 ns min Acquisition time ACQ t 25 25 ns min Minimum CONVST low pulse 10 t1 60 60 ns max CONVST high to BUSY high tWAKE-UP 2 2 ms max STBY rising edge to CONVST rising edge 25 25 µs max Partial power-down mode PARALLEL WRITE OPERATION t11 15 15 ns min WR pulse width t12 0 0 ns min CS to WR setup time t 5 5 ns min CS to WR hold time 13 t 5 5 ns min Data setup time before WR rising edge 14 t15 5 5 ns min Data hold after WR rising edge PARALLEL READ OPERATION t 0 0 ns min BUSY to RD delay 2 t3 0 0 ns min CS to RD setup time t4 0 0 ns min CS to RD hold time t5 45 36 ns min RD pulse width t6 45 36 ns max Data access time after RD falling edge t 10 10 ns min Data hold time after RD rising edge 7 t 12 12 ns max Bus relinquish time after rising edge 8 RD t9 6 6 ns min Minimum time between reads SERIAL INTERFACE f 18 18 MHz max Frequency of serial read clock SCLK t16 12 12 ns max Delay from CS until SDATA three-state disabled 2 t17 22 22 ns max Data access time after SCLK rising edge/CS falling edge t18 0.4 tSCLK 0.4 tSCLK ns min SCLK low pulse width t 0.4 t 0.4 t ns min SCLK high pulse width 19 SCLK SCLK t 10 10 ns min SCLK to data valid hold time after SCLK falling edge 20 t21 18 18 ns max CS rising edge to SDATA high impedance 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DD 2 A buffer is used on the data output pins for this measurement. 200µA I OL TO OUTPUT 1.6V PIN C L 25pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specification Rev. D | Page 9 of 32 05020-002 AD7656/AD7657/AD7658 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to AGND, DGND −0.3 V to +16.5 V DD other conditions above those indicated in the operational V to AGND, DGND +0.3 V to −16.5 V SS section of this specification is not implied. Exposure to absolute VDD to AVCC AVCC − 0.3 V to 16.5 V maximum rating conditions for extended periods may affect AVCC to AGND, DGND −0.3 V to +7 V device reliability. DVCC to AVCC −0.3 V to AVCC + 0.3 V DV to DGND, AGND −0.3 V to +7 V CC THERMAL RESISTANCE AGND to DGND −0.3 V to +0.3 V θ is specified for the worst-case conditions, that is, a device JA VDRIVE to DGND −0.3 V to DVCC + 0.3 V soldered in a circuit board for surface-mount packages. These 1 Analog Input Voltage to AGND VSS − 0.3 V to VDD + 0.3 V specifications apply to a four-layer board. Digital Input Voltage to DGND −0.3 V to VDRIVE + 0.3 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE Table 6. Thermal Resistance REFIN to AGND −0.3 V to AV + 0.3 V CC Package Type θJA θJC Unit Input Current to Any Pin Except 64-Lead LQFP 45 11 °C/W 2 Supplies ±10 mA Operating Temperature Range B Version −40°C to +85°C ESD CAUTION Y Version −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) 240(+0)°C Pb-Free Temperature, Soldering Reflow 260(+0)°C 1 If the analog inputs are being driven from alternative VDD and VSS supply circuitry, a 240 Ω series resistor should be placed on the analog inputs. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. D | Page 10 of 32 Data Sheet AD7656/AD7657/AD7658 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 DB14/REFBUF V6 EN/DIS PIN 1 DB13 2 47 AV CC DB12 3 46 AV CC DB11 4 45 V5 DB10/DOUT C 5 44 AGND 6 43 DB9/DOUT B AGND AD7656/AD7657/AD7658 7 42 DB8/DOUT A V4 TOP VIEW 8 (Not to Scale) 41 DGND AV CC 9 40 V AV DRIVE CC DB7/HBEN/DCEN 10 39 V3 11 38 DB6/SCLK AGND DB5/DCIN A 12 37 AGND DB4/DCIN B 13 36 V2 DB3/DCIN C 14 35 AV CC 15 34 DB2/SEL C AV CC 16 33 DB1/SEL B V1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 54, 56, 58 REFCAPA, REFCAPB, Decoupling capacitors are connected to these pins. This decouples the reference buffer for each REFCAPC ADC pair. Each REFCAP pin should be decoupled to AGND using 10 µF and 100 nF capacitors. 33, 36, 39, V1 to V6 Analog Input 1 to 6. These are six single-ended analog inputs. In hardware mode, the analog input 42, 45, 48 range on these channels is determined by the RANGE pin. In software mode, it is determined by Bit RNGC to Bit RNGA of the control register (see Table 10). 32, 37, 38, 43, AGND Analog Ground. Ground reference point for all analog circuitry on the AD7656/AD7657/AD7658. 44, 49, 52, 53, All analog input signals and any external reference signal should be referred to this AGND voltage. 55, 57, 59 All 11 of these AGND pins should be connected to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 26 DV Digital Power, 4.75 V to 5.25 V. The DV and AV voltages should ideally be at the same potential CC CC CC and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to DGND, and 10 µF and 100 nF decoupling capacitors should be placed on the DVCC pin. 9 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the interface. Nominally at the same supply as the supply of the host interface. This pin should be decoupled to DGND, and 10 µF and 100 nF decoupling capacitors should be placed on the V pin. DRIVE 8, 25 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7656/AD7657/AD7658. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 34, 35, 40, AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and 41, 46, 47, DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even 50, 60 on a transient basis. These supply pins should be decoupled to AGND, and 10 µF and 100 nF decoupling capacitors should be placed on the AV pins. CC 23, 22, 21 CONVST A, Conversion Start Input A, B, C. These logic inputs are used to initiate conversions on the ADC pairs. CONVST B, CONVST C CONVST A is used to initiate simultaneous conversions on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on V5 and V6. When CONVSTx switches from low to high, the track-and-hold switch on the selected ADC pair switches from track to hold and the conversion is initiated. These inputs can also be used to place the ADC pairs into partial power-down mode. Rev. D | Page 11 of 32 DB15 DB0/SEL A BUSY WR/REF EN/DIS H/S SEL CS SER/PAR/SEL RD AV CONVST C CC AGND CONVST B REFCAPC CONVST A AGND STBY REFCAPB DGND AGND DV CC REFCAPA RANGE AGND RESET AGND W/B REFIN/REFOUT V SS AV V CC DD AGND AGND 05020-003 AD7656/AD7657/AD7658 Data Sheet Pin No. Mnemonic Description 19 CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the output bus is enabled and the conversion result is output on the parallel data bus lines. When both CS and WR are logic low in parallel mode, DB[15:8] are used to write data to the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 20 RD Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, the RD line should be held low. 63 /REF Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low, WR EN/DIS DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When /S SEL = 0 and REF = 1, the internal reference is enabled and the REFIN/REFOUT pin should be H EN/DIS decoupled. See the Reference Section. 18 BUSY BUSY Output. This pin transitions high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. A new conversion should not be initiated on the AD7656/AD7657/AD7658 when the BUSY signal is high. 51 REFIN/REFOUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7656/AD7657/AD7658. Alternatively, the internal reference can be disabled and an external reference can be applied to this input. See the Reference Section. When the internal reference is enabled, this pin should be decoupled using at least a 10 µF decoupling capacitor. 61 SER/PAR/SEL Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high, the serial interface mode is selected. In serial mode, DB[10:8] take on their DOUT[C:A] function, DB[0:2] take on their DOUT select function, DB7 takes on its DCEN function. In serial mode, DB15 and DB[13:11] should be tied to DGND. 17 DB0/SEL A Data Bit 0/Select DOUT A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SEL A function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with one/two/three DOUT output pins and enables DOUT A as a serial output. When operating in serial mode, this pin should always be = 1. 16 DB1/SEL B Data Bit 1/Select DOUT B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SEL B function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with two/three DOUT output pins and enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected. 15 DB2/SEL C Data Bit 2/Select DOUT C. When SER/ = 0, this pin acts as a three-state parallel digital output pin. PAR When SER/PAR = 1, this pin takes on its SEL C function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Unused serial DOUT pins should be left unconnected. 14 DB3/DCIN C Data Bit 3/Daisy-Chain Input C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. 13 DB4/DCIN B Data Bit 4/Daisy-Chain Input B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. 12 DB5/DCIN A Data Bit 5/Daisy-Chain Input A. When SER/ is low, this pin acts as a three-state parallel digital PAR output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. 11 DB6/SCLK Data Bit 6/Serial Clock. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial transfer. 10 DB7/HBEN/DCEN Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode (SER/PAR = 0 and W/B = 0), this pin takes on its Data Bit 7 function. When operating in parallel byte mode (SER/PAR = 0 and W/B = 1), this pin takes on its HBEN function. When in this mode and the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. When the HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When operating in serial mode (SER/PAR = 1), this pin takes on its DCEN function. When the DCEN pin is logic high, the parts operate in daisy- chain mode with DB[5:3] taking on their DCIN[A:C] function. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. Rev. D | Page 12 of 32 Data Sheet AD7656/AD7657/AD7658 Pin No. Mnemonic Description 7 DB8/DOUT A Data Bit 8/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs serial conversion data. 6 DB9/DOUT B Data Bit 9/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL B = 1, this pin takes on its DOUT B function and outputs serial conversion data. This configures the serial interface to have two DOUT output lines. 5 DB10/DOUT C Data Bit 10/Serial Data Output C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs serial conversion data. This configures the serial interface to have three DOUT output lines. 4 DB11 Data Bit 11/Digital Ground. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/ = 1, this pin should be tied to DGND. PAR 3, 2, 64 DB12, DB13, DB15 Data Bit 12, Data Bit 13, Data Bit 15. When SER/PAR = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR = 1, these pins should be tied to DGND. For the AD7657, DB15 contains a leading zero. For the AD7658, DB15, DB13, and DB12 contain leading zeros. 1 /Disable. When SER/ = 0, this pin acts as a three-state digital input/ DB14/REFBUFEN/DIS Data Bit 14/REFBUF Enable PAR output pin. For the AD7657/AD7658, DB14 contains a leading zero. When SER/PAR = 1, this pin can be used to enable or disable the internal reference buffers. 28 RESET Reset Input. When set to logic high, this pin resets the AD7656/AD7657/AD7658. The current conversion, if any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656/AD7657/AD7658 are configured depending on the logic levels on the hardware select pins. In all modes, the parts should receive a RESET pulse after power-up. The reset high pulse should be typically 100 ns wide. After the RESET pulse, the AD7656/AD7657/AD7658 needs to see a valid CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse. 27 RANGE Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND and the input range is determined by the RNGA, RNGB, and RNGC bits in the control register. 31 V Positive Power Supply Voltage. This is the positive supply voltage for the analog input section, and DD 10 µF and 100 nF decoupling capacitors should be placed on the VDD pin. 30 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section, and 10 µF and 100 nF decoupling capacitors should be placed on the VSS pin. 24 STBY Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is high for normal operation and low for standby operation. 62 /S SEL /Software Select Input. Logic input. When /S SEL = 0, the AD7656/AD7657/AD7658 H Hardware H operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the control register. In serial mode, CONVST A is used to initiate conversions on the selected ADC pairs. 29 W/B Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656/AD7657/ AD7658 using the parallel data lines DB[15:0]. When this pin is logic high, byte mode is enabled. In this mode, data is transferred using data lines DB[15:8] and DB[7] takes on its HBEN function. To obtain the 16-bit conversion result, 2-byte reads are required. In serial mode, this pin should be tied to DGND. Rev. D | Page 13 of 32 AD7656/AD7657/AD7658 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 2.0 V /V = ±15V DD SS AV /DV /V = +5V CC CC DRIVE –20 1.5 INTERNAL REFERENCE ±10V RANGE T = 25°C –40 A 1.0 f = 250kSPS S f = 50kHz IN 0.5 –60 SNR = +87.33dB SINAD = +87.251dB THD = –104.32dB 0 –80 SFDR = –104.13dB –0.5 –100 AV /DV /V = +5V CC CC DRIVE –1.0 –120 V /V = ±12V DD SS f = 250kSPS SAMPLE 2 × V RANGE –1.5 REF –140 DNL WCP = 0.81LSB DNL WCN = –0.57LSB –160 –2.0 0 10k 20k 30k 40k 50k 60k 65535 0 25 50 75 100 125 CODE FREQUENCY (kHz) Figure 4. AD7656 FFT for ±10 V Range Figure 7. AD7656 Typical DNL 0 2.0 V /V = ±12V AV /DV /V = +5V DD SS CC CC DRIVE AV /DV /V = +5V 1.6 V /V = ±12V CC CC DRIVE DD SS –20 INTERNAL REFERENCE f = 250kSPS SAMPLE ±5V RANGE RANGE 2 × V 1.2 REF T = 25°C –40 A f = 250kSPS S 0.8 f = 50kHz IN –60 SNR = +86.252dB 0.4 SINAD = +86.196dB THD = –105.11dB –80 0 SFDR = –98.189dB –0.4 –100 –0.8 –120 –1.2 –140 –1.6 –160 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16383 0 25 50 75 100 125 CODE FREQUENCY (kHz) Figure 5. AD7656 FFT for ±5 V Range Figure 8. AD7657 Typical INL 2.0 2.0 AV /DV /V = +5V AV /DV /V = +5V CC CC DRIVE CC CC DRIVE V /V = ±12V V /V = ±12V DD SS DD SS 1.6 1.5 f = 250kSPS SAMPLE 2 × V RANGE REF 1.2 INL WCP = 0.64LSB 1.0 INL WCN = –0.76LSB 0.8 0.5 0.4 0 0 –0.4 –0.5 –0.8 –1.0 –1.2 –1.5 –1.6 –2.0 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16383 0 10k 20k 30k 40k 50k 60k 65535 CODE CODE Figure 6. AD7656 Typical INL Figure 9. AD7657 Typical DNL Rev. D | Page 14 of 32 INL (LSB) (dB) (dB) 05020-017 05020-031 05020-030 DNL (LSB) INL (LSB) DNL (LSB) 05020-034 05020-035 05020-016 Data Sheet AD7656/AD7657/AD7658 1.0 –60 f = 250kSPS SAMPLE INTERNAL REFERENCE AV /DV /V = +5V 0.8 CC CC DRIVE T = 25°C V /V = ±12V DD SS A –70 AV /DV /V = +5V CC CC DRIVE f = 250kSPS 0.6 SAMPLE V /V = ±5.25V DD SS 2 × V RANGE REF ±5V RANGE 0.4 AV /DV / –80 CC CC V = +4.75V DRIVE 0.2 V /V = ±10V DD SS ±10V RANGE AV /DV / CC CC 0 –90 V = +5V DRIVE V /V = ±12V DD SS –0.2 ±5V RANGE –100 –0.4 AV /DV / CC CC V = +5.25V DRIVE –0.6 V /V = ±16.5V DD SS –110 ±10V RANGE –0.8 –1.0 –120 0 500 1000 1500 2000 2500 3000 3500 4095 10 100 1000 CODE ANALOG INPUT FREQUENCY (kHz) Figure 10. AD7658 Typical INL Figure 13. AD7656 THD vs. Input Frequency 1.0 –60 V /V = ±16.5V DD SS AV /DV /V = +5V 0.8 CC CC DRIVE AV /DV /V = +5.25V CC CC DRIVE V /V = ±12V DD SS T = 25°C A f = 250kSPS –70 0.6 SAMPLE INTERNAL REFERENCE 2 × V RANGE REF ±4 × V RANGE REF 0.4 –80 0.2 R = 1000Ω SOURCE 0 –90 –0.2 R = 100Ω SOURCE R = 220Ω SOURCE –100 –0.4 –0.6 –110 R = 10Ω SOURCE –0.8 R = 50Ω SOURCE –1.0 –120 0 500 1000 1500 2000 2500 3000 3500 4095 10 100 CODE ANALOG INPUT FREQUENCY (kHz) Figure 11. AD7658 Typical DNL Figure 14. AD7656 THD vs. Input Frequency for Various Source Impedances, ±4 × VREF Range 90 –40 AV /DV /V = +5.25V CC CC DRIVE V /V = ±12V DD SS V /V = ±16.5V DD SS AV /DV /V = +5V CC CC DRIVE ±10V RANGE –50 T = 25°C A 85 INTERNAL REFERENCE AV /DV / CC CC ±2 × V RANGE V = +5V REF –60 DRIVE AV /DV / V /V = ±12V CC CC DD SS 80 V = +4.75 V ±5V RANGE DRIVE –70 V /V = ±10V DD SS ±10V RANGE 75 –80 R = 1000Ω SOURCE AV /DV / CC CC V = +5V –90 DRIVE R = 220Ω 70 SOURCE V /V = ±5.25V DD SS R = 100Ω ±5V RANGE SOURCE –100 65 f = 250kSPS SAMPLE –110 INTERNAL REFERENCE R = 50Ω R = 10Ω SOURCE T = 25°C SOURCE A 60 –120 10 100 1000 10 100 ANALOG INPUT FREQUENCY (kHz) ANALOG INPUT FREQUENCY (kHz) Figure 12. AD7656 SINAD vs. Input Frequency Figure 15. AD7656 THD vs. Input Frequency for Various Source Impedances, ±2 × VREF Range Rev. D | Page 15 of 32 SINAD (dB) DNL (LSB) INL (LSB) 05020-032 05020-033 05020-023 THD (dB) THD (dB) THD (dB) 05020-027 05020-026 05020-022 AD7656/AD7657/AD7658 Data Sheet 2.510 100 f = 250kSPS AV /DV /V = +5V SAMPLE CC CC DRIVE ±2 × V RANGE V /V = ±12V REF DD SS 2.508 INTERNAL REFERENCE 90 T = 25°C A 2.506 f = 10kHz IN 100nF ON V AND V DD SS 2.504 80 2.502 70 2.500 V SS 2.498 60 V DD 2.496 50 2.494 40 2.492 –55 –35 –15 5 25 45 65 85 105 125 30 80 130 180 230 280 330 380 430 480 530 TEMPERATURE (°C) SUPPLY RIPPLE FREQUENCY (kHz) Figure 16. Reference Voltage vs. Temperature Figure 19. PSRR vs. Supply Ripple Frequency 3.20 87.0 AV /DV /V = +5V CC CC DRIVE V /V = ±12V 3.15 DD SS 86.5 3.10 86.0 ±5V RANGE, 3.05 AV /DV /V = +5V CC CC DRIVE 85.5 ±10V RANGE, V /V = ±12V 3.00 DD SS AV /DV /V = +5.25V CC CC DRIVE V /V = ±16.5V DD SS 2.95 85.0 2.90 84.5 2.85 84.0 2.80 f = 250kSPS 83.5 SAMPLE 2.75 f = 50kHz IN INTERNAL REFERENCE 2.70 83.0 –55 –35 –15 5 25 45 65 85 105 125 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Conversion Time vs. Temperature Figure 20. AD7656 SNR vs. Temperature 3500 –100 f = 250kSPS SAMPLE 3212 f = 50kHz V /V = ±15V IN DD SS INTERNAL REFERENCE –101 3000 AV /DV /V = +5V CC CC DRIVE 2806 INTERNAL REFERENCE 8192 SAMPLES –102 2500 ±10V RANGE, 2000 –103 AV /DV /V = +5.25V CC CC DRIVE V /V = ±16.5V DD SS 1532 –104 1500 ±5V RANGE, 1000 –105 AV /DV /V = +5V CC CC DRIVE V /V = ±12V DD SS –106 500 392 168 57 25 0 0 0 –107 –5 –4 –3 –2 –1 0 1 2 3 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 21. AD7656 THD vs. Temperature Figure 18. AD7656 Histogram of Codes Rev. D | Page 16 of 32 NUMBER OF OCCURRENCES CONVERSION TIME (µs) REFERENCE VOLTAGE (V) 05020-029 05020-019 05020-018 THD (dB) SNR (dB) PSRR (dB) 05020-024 05020-025 05020-021 Data Sheet AD7656/AD7657/AD7658 30 120 25 110 ±10V RANGE 100 20 ±5V RANGE 90 15 80 10 AV /DV /V = 5V CC CC DRIVE V /V = ±12V DD SS AV /DV /V = +5V T = 25°C A CC CC DRIVE 70 5 f = 250kSPS INTERNAL REFERENCE SAMPLE FOR ±5V RANGE V /V = ±12V ±2 × V RANGE REF DD SS FOR ±10V RANGE V /V = ±16.5V 30kHz ON SELECTED CHANNEL DD SS 0 60 0 20 40 60 80 100 120 140 –40 –20 0 20 40 60 80 100 FREQUENCY OF INPUT NOISE (kHz) TEMPERATURE (°C) Figure 22. Channel-to-Channel Isolation Figure 23. Dynamic Current vs. Temperature Rev. D | Page 17 of 32 CHANNEL-TO-CHANNEL ISOLATION (dB) 05020-028 DYNAMIC CURRENT (mA) 05020-020 AD7656/AD7657/AD7658 Data Sheet TERMINOLOGY The ratio depends on the number of quantization levels in the Integral Nonlinearity digitization process: the more levels, the smaller the quantization The maximum deviation from a straight line passing through noise. The theoretical signal-to-(noise + distortion) ratio for an the endpoints of the ADC transfer function. The endpoints of ideal N-bit converter with a sine wave input is given by the transfer function are zero scale, a ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, this is 98 dB for a 16-bit converter, 86.04 dB for a 14-bit Differential Nonlinearity converter, and 74 dB for a 12-bit converter. The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. Bipolar Zero Code Error For the AD7656/AD7657/AD7658, it is defined as The deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, that is, AGND − 1 LSB. 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 THD(dB)= 20log V Bipolar Zero Code Error Matching 1 The difference in bipolar zero code error between any two input where: channels. V is the rms amplitude of the fundamental. 1 V2, V3, V4, V5, and V6 are the rms amplitudes of the second Positive Full-Scale Error through sixth harmonics. The deviation of the last code transition (011…110) to (011…111) from the ideal (+4 × VREF − 1 LSB, +2 × VREF − 1 LSB) after Peak Harmonic or Spurious Noise (SFDR) adjusting for the bipolar zero code error. The ratio of the rms value of the next largest component in the ADC output spectrum (up to f /2, excluding dc) to the rms value S Positive Full-Scale Error Matching of the fundamental. Normally, the value of this specification is The difference in positive full-scale error between any two input determined by the largest harmonic in the spectrum, but for channels. ADCs where the harmonics are buried in the noise floor, it is Negative Full-Scale Error determined by a noise peak. The deviation of the first code transition (10…000) to (10…001) Intermodulation Distortion (IMD) from the ideal (−4 × VREF + 1 LSB, −2 × VREF + 1 LSB) after With inputs consisting of sine waves at two frequencies, fa and adjusting for the bipolar zero code error. fb, any active device with nonlinearities create distortion Negative Full-Scale Error Matching products at sum and difference frequencies of mfa ± nfb, where The difference in negative full-scale error between any two m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for input channels. which neither m nor n are equal to 0. For example, the second- order terms include (fa + fb) and (fa − fb), and the third-order Track-and-Hold Acquisition Time terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The track-and-hold amplifier returns to track mode at the end The AD7656/AD7657/AD7658 are tested using the CCIF standard of the conversion. The track-and-hold acquisition time is the in which two input frequencies near the top end of the input time required for the output of the track-and-hold amplifier to bandwidth are used. In this case, the second-order terms are reach its final value, within ±1 LSB, after the end of the conversion. usually distanced in frequency from the original sine waves, See the Track-and-Hold Section for more details. and the third-order terms are usually at a frequency close to the Signal-to-Noise Ratio (SNR) input frequencies. As a result, the second- and third-order terms SNR is the ratio of the rms value of the measured output signal are specified separately. The calculation of the intermodulation to the rms sum of all other spectral components below the distortion is per the THD specification, where it is the ratio of Nyquist frequency. The value for SNR is expressed in decibels. the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) The measured ratio of signal-to-(noise + distortion) at the Power Supply Rejection (PSR) output of the ADC. The signal is the rms amplitude of the Variations in power supply affect the full-scale transition but fundamental. Noise is the sum of all nonfundamental signals up not the converter’s linearity. Power supply rejection is the to half the sampling frequency (f /2, excluding dc). maximum change in full-scale transition point due to a change S in power supply voltage from the nominal value. See the Typical Performance Characteristics section. Rev. D | Page 18 of 32 Data Sheet AD7656/AD7657/AD7658 Figure 19 shows the power supply rejection ratio vs. supply Channel-to-Channel Isolation ripple frequency for the AD7656/AD7657/AD7658. Channel-to-channel isolation is a measure of the level of crosstalk The power supply rejection ratio is defined as the ratio between any two channels. It is measured by applying a full-scale, of the power in the ADC output at full-scale frequency, f, 100 kHz sine wave signal to all unselected input channels and to the power of a 200 mV p-p sine wave applied to the determining the degree to which the signal attenuates in the ADC’s VDD and VSS supplies of frequency fS selected channel with a 30 kHz signal. PSRR (dB) = 10 log (Pf/PfS) % FSR where: %FSR is calculated using the full theoretical span of the ADC. Pf is equal to the power at frequency f in the ADC output. Pf is equal to the power at frequency f coupled onto the V S S DD and VSS supplies. Rev. D | Page 19 of 32 AD7656/AD7657/AD7658 Data Sheet THEORY OF OPERATION Analog Input Section CONVERTER DETAILS The AD7656/AD7657/AD7658 can handle true bipolar input The AD7656/AD7657/AD7658 are high speed, low power voltages. The logic level on the RANGE pin or the value written converters that allow the simultaneous sampling of six on-chip to the RNGx bits in the control register determines the analog ADCs. The analog inputs on the AD7656/AD7657/AD7658 can input range on the AD7656/AD7657/AD7658 for the next accept true bipolar input signals. The RANGE pin/RNG bits are conversion. When the RANGE pin/RNGx bit is 1, the analog used to select either ±4 × VREF or ±2 × VREF as the input range input range for the next conversion is ±2 × VREF. When the for the next conversion. RANGE pin/RNGx bit is 0, the analog input range for the next Each AD7656/AD7657/AD7658 contains six SAR ADCs, six conversion is ±4 × VREF. track-and-hold amplifiers, an on-chip 2.5 V reference, reference V DD buffers, and high speed parallel and serial interfaces. The parts allow the simultaneous sampling of all six ADCs when all three D1 C2 R1 V1 CONVST signals are tied together. Alternatively, the six ADCs C1 D2 can be grouped into three pairs. Each pair has an associated CONVST signal used to initiate simultaneous sampling on each V SS ADC pair, on four ADCs, or on all six ADCs. CONVST A is used Figure 24. Equivalent Analog Input Structure to initiate simultaneous sampling on V1 and V2, CONVST B is used to initiate simultaneous sampling on V3 and V4, and Figure 24 shows an equivalent circuit of the analog input structure CONVST C is used to initiate simultaneous sampling on V5 of the AD7656/AD7657/AD7658. The two diodes, D1 and D2, and V6. provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the A conversion is initiated on the AD7656/AD7657/AD7658 by VDD and VSS supply rails by more than 300 mV. Signals exceeding pulsing the CONVST x input. On the rising edge of CONVST x, this value cause these diodes to become forward-biased and to the track-and-hold of the selected ADC pair is placed into hold start conducting current into the substrate. The maximum mode and the conversions are started. After the rising edge of current these diodes can conduct without causing irreversible CONVST x, the BUSY signal goes high to indicate that the damage to the parts is 10 mA. Capacitor C1 in Figure 24 is conversion is taking place. The conversion clock for the typically about 4 pF and can be attributed primarily to pin AD7656/AD7657/AD7658 is internally generated, and the capacitance. Resistor R1 is a lumped component made up of conversion time for the parts is 3 µs. The BUSY signal returns the on resistance of a switch (track-and-hold switch). This low to indicate the end of conversion. On the falling edge of resistor is typically about 25 Ω. Capacitor C2 is the ADC BUSY, the track-and-hold returns to track mode. Data can be sampling capacitor and has a capacitance of 10 pF typically. read from the output register via the parallel or serial interface. The AD7656/AD7657/AD7658 require V and V dual DD SS Track-and-Hold Section supplies for the high voltage analog input structures. These The track-and-hold amplifiers on the AD7656/AD7657/AD7658 supplies must be equal to or greater than the analog input range allow the ADCs to accurately convert an input sine wave of full- (see Table 8 for the requirements on these supplies for each scale amplitude to 16-/14-/12-bit resolution, respectively. The analog input range). The AD7656/AD7657/AD7658 require a input bandwidth of the track-and-hold amplifiers is greater low voltage AVCC supply of 4.75 V to 5.25 V to power the ADC than the Nyquist rate of the ADC, even when the AD7656/ core, a DV supply of 4.75 V to 5.25 V for the digital power, CC AD7657/AD7658 are operating at its maximum throughput and a V supply of 2.7 V to 5.25 V for the interface power. DRIVE rate. The parts can handle input frequencies of up to 12 MHz. To meet the specified performance when using the minimum The track-and-hold amplifiers sample their respective inputs supply voltage for the selected analog input range, it can be simultaneously on the rising edge of CONVSTx. The aperture time necessary to reduce the throughput rate from the maximum for the track-and-hold (that is, the delay time between the external throughput rate. CONVSTx signal actually going into hold) is 10 ns. This is well matched across all six track-and-holds on one device and from Table 8. Minimum VDD/VSS Supply Voltage Requirements device to device. This allows more than six ADCs to be sampled Analog Input Reference Full-Scale Minimum simultaneously. The end of the conversion is signaled by the falling Range (V) Voltage (V) Input (V) V /V (V) DD SS edge of BUSY, and it is at this point that the track-and-holds return ±4 × VREF +2.5 ±10 ±10 to track mode and the acquisition time begins. ±4 × VREF +3.0 ±12 ±12 ±2 × V +2.5 ±5 ±5 REF ±2 × V +3.0 ±6 ±6 REF Rev. D | Page 20 of 32 05020-004 Data Sheet AD7656/AD7657/AD7658 the internal reference buffers can be disabled in hardware ADC TRANSFER FUNCTION mode by setting the DB14/REFBUF pin high. If the EN/DIS The output coding of the AD7656/AD7657/AD7658 is twos internal reference and its buffers are disabled, an external complement. The designed code transitions occur midway buffered reference should be applied to the REFCAP pins. between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/65536 for the AD7656, FSR/16384 for the TYPICAL CONNECTION DIAGRAM AD7657, and FSR/4096 for the AD7658. The ideal transfer Figure 26 shows the typical connection diagram for the characteristic is shown in Figure 25. AD7656/AD7657/AD7658. There are eight AVCC supply pins on the parts. The AVCC supply is the supply that is used for the 011...111 AD7656/AD7657/AD7658 conversion process; therefore, it 011...110 should be well decoupled. Each AVCC supply pin should be individually decoupled with a 10 µF tantalum capacitor and a 000...001 000...000 100 nF ceramic capacitor. The AD7656/AD7657/AD7658 can 111...111 operate with the internal reference or an externally applied reference. In this configuration, the parts are configured to 100...010 operate with the external reference. The REFIN/REFOUT pin 100...001 100...000 is decoupled with a 10 µF and 100 nF capacitor pair. The three AGND – 1LSB –FSR/2 + 1/2LSB +FSR/2 – 3/2LSB internal reference buffers are enabled. Each of the REFCAP ANALOG INPUT pins are decoupled with the 10 µF and 100 nF capacitor pair. Figure 25. AD7656/AD7657/AD7658 Transfer Characteristic Six of the AV supply pins are used as the supply to the six CC The LSB size is dependent on the analog input range selected ADC cores on the AD7656/AD7657/AD7658 and, as a result, (see Table 9). are used for the conversion process. Each analog input pin is surrounded by an AVCC supply pin and an AGND pin. These REFERENCE SECTION AVCC and AGND pins are the supply and ground for the indi- The RFIN/REFOUT pin either allows access to the AD7656/ vidual ADC cores. For example, Pin 33 is V1, Pin 34 is the AVCC AD7657/AD7658’s 2.5 V reference or it allows an external supply for ADC Core 1, and Pin 32 is the AGND for ADC Core reference to be connected, providing the reference source for 1. An alternative reduced decoupling solution is to group these each part’s conversions. The AD7656/AD7657/AD7658 can six AV supply pins into three pairs, Pin 34 and Pin 35, Pin 40 CC accommodate a 2.5 V to 3 V external reference range. When and Pin 41, and Pin 46 and Pin 47. using an external reference, the internal reference needs to be disabled. After a reset, the AD7656/AD7657/AD7658 default to For the AD7656, a 100 µF decoupling capacitor can be placed operating in external reference mode with the internal reference on each of the pin pairs. All of the other supply and reference buffers enabled. The internal reference can be enabled in either pins should be decoupled with a 10 µF decoupling capacitor. hardware or software mode. To enable the internal reference in When the AD7657 is configured in this reduced decoupling H hardware mode, the /S SEL pin = 0 and the REFEN/DIS pin = 1. To configuration, each of the three AV pin pairs should be CC decoupled with a 33 µF capacitor. When the AD7658 is con- H enable the internal reference in software mode, /S SEL = 1 and figured in this same configuration, each of the three AV CC a write to the control register is necessary to make DB9 of the pin pairs should be decoupled with a 22 µF capacitor. register = 1. For the internal reference mode, the REFIN/REFOUT pin should be decoupled using 10 µF and 100 nF capacitors. If the same supply is being used for the AVCC supply and DVCC supply, a ferrite or small RC filter should be placed between the The AD7656/AD7657/AD7658 contain three on-chip reference supply pins. buffers. Each of the three ADC pairs has an associated reference buffer. These reference buffers require external decoupling The AGND pins are connected to the AGND plane of the system. capacitors on REFCAPA, REFCAPB, and REFCAPC pins, The DGND pins are connected to the digital ground plane in and 10 µF and 100 nF decoupling capacitors should be placed the system. The AGND and DGND planes should be connected on these REFCAP pins. The internal reference buffers can be together at one place in the system. This connection should be disabled in software mode by writing to Bit DB8 in the internal made as close as possible to the AD7656/AD7657/AD7658 in control register. If operating the devices in serial mode, the system. Table 9. LSB Size for Each Analog Input Range Range AD7656 AD7657 AD7658 Input Range ±10 V ±5 V ±10 V ±5 V ±10 V ±5 V LSB Size 0.305 mV 0.152 mV 1.22 mV 0.610 mV 4.88 mV 2.44mV FS Range 20 V/65536 10 V/65536 20 V/16384 10 V/16384 20 V/4096 10 V/4096 Rev. D | Page 21 of 32 ADC CODE 05020-005 AD7656/AD7657/AD7658 Data Sheet DV CC DIGITAL SUPPLY VOLTAGE +3V OR +5V ANALOG SUPPLY 1 VOLTAGE 5V + + + 10µF 100nF 100nF 10µF 100nF 10µF AGND AV DV DGND V DGND CC CC DRIVE 2 +9.5V TO +16.5V V DD SUPPLY + PARALLEL 10µF 100nF D0 TO D15 INTERFACE AGND µP/µC/DSP CONVST A, B, C REFCAPA, B, C + CS 10µF 100nF RD AGND BUSY AD7656/AD7657/AD7658 2.5V RESET REFIN/OUT REF + 10µF 100nF SER/PAR AGND H/S W/B SIX ANALOG RANGE INPUTS 2 –9.5V TO –16.5V V SS SUPPLY STBY V DRIVE 10µF 100nF + AGND 1 DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN. CC CC 2 SEE POWER SUPPLY CONFIGURATION SECTION. Figure 26. Typical Connection Diagram Parallel Interface (SER/ = 0) The V supply is connected to the same supply as the PAR DRIVE processor. The voltage on V controls the voltage value DRIVE The AD7656/AD7657/AD7658 consist of six 16-/14-/12-bit of the output logic signals. ADCs, respectively. A simultaneous sample of all six ADCs can be performed by connecting all three CONVST pins together, The VDD and VSS signals should be decoupled with a minimum CONVST A, CONVST B, and CONVST C. The AD7656/AD7657/ 10 µF decoupling capacitor. These supplies are used for the high AD7658 need to see a CONVST pulse to initiate a conversion; voltage analog input structures on the AD7656/AD7657/AD7658 this should consist of a falling CONVST edge followed by a analog inputs. rising CONVST edge. The rising edge of CONVSTx initiates DRIVING THE ANALOG INPUTS simultaneous conversions on the selected ADCs. The AD7656/ AD7657/AD7658 contain an on-chip oscillator that is used to Together, the driver amplifier and the analog input circuit used perform the conversions. The conversion time, t , is 3 µs. CONV for the AD7656 must settle for a full-scale step input to a 16-bit The BUSY signal goes low to indicate the end of conversion. level (0.0015%), which is within the specified 550 ns acquisition The falling edge of the BUSY signal is used to place the track- time of the AD7656. The noise generated by the driver amplifier and-hold into track mode. The AD7656/AD7657/AD7658 also needs to be kept as low as possible to preserve the SNR and allow the six ADCs to be converted simultaneously in pairs by transition noise performance of the AD7656. pulsing the three CONVST pins independently. CONVST A is The driver also needs to have a THD performance suitable to used to initiate simultaneous conversions on V1 and V2, that of the AD7656. The AD8021 meets all these requirements. CONVST B is used to initiate simultaneous conversions on The AD8021 needs an external compensation capacitor of V3 and V4, and CONVST C is used to initiate simultaneous 10 pF. If a dual version of the AD8021 is required, the AD8022 conversions on V5 and V6. The conversion results from the can be used. The AD8610 and the AD797 can also be used to simultaneously sampled ADCs are stored in the output data drive the AD7656/AD7657/AD7658. registers. INTERFACE SECTION Data can be read from the AD7656/AD7657/AD7658 via the parallel data bus with standard CS RD W and signals ( /B = 0). The AD7656/AD7657/AD7658 provide two interface options, a PAR To read the data over the parallel bus, SER/ should be tied parallel interface and a high speed serial interface. The required CS RD PAR low. The and input signals are internally gated to enable interface mode is selected via the SER/ pin. The parallel the conversion result onto the data bus. The data lines DB0 to W W interface can operate in word ( /B = 0) or byte ( /B = 1) mode. DB15 leave their high impedance state when both CS and RD The interface modes are discussed in the following sections. are logic low. Rev. D | Page 22 of 32 05020-006 Data Sheet AD7656/AD7657/AD7658 CS RD can affect the performance of the conversion. For the specified The signal can be permanently tied low, and the signal performance, it is recommended to perform the read after the can be used to access the conversion results. A read operation conversion. For unused input channel pairs, the associated can take place after the BUSY signal goes low. The number of CONVSTx pin should be tied to VDRIVE. required read operations depends on the number of ADCs that are simultaneously sampled (see Figure 27). If CONVST A If there is only an 8-bit bus available, the AD7656/AD7657/ and CONVST B are simultaneously brought low, four read AD7658 interface can be configured to operate in byte mode operations are required to obtain the conversion results from W ( /B = 1). In this configuration, the DB7/HBEN/DCEN pin V1, V2, V3, and V4. If CONVST A and CONVST C are takes on its HBEN function. Each channel conversion result simultaneously brought low, four read operations are required from the AD7656/AD7657/AD7658 can be accessed in two to obtain the conversion results from V1, V2, V5, and V6. read operations, with 8 bits of data provided on DB15 to DB8 The conversion results are output in ascending order. For for each of the read operations (see Figure 28). The HBEN pin the AD7657, DB15 and DB14 contain two leading zeros and determines whether the read operation first accesses the high DB[13:0] output the 14-bit conversion result. For the AD7658, byte or the low byte of the 16-bit conversion result. To always DB[15:12] contain four leading zeros, and DB[11:0] output the access the low byte first on DB15 to DB8, the HBEN pin should 12-bit conversion result. be tied low. To always access the high byte first on DB15 to When using the three CONVST signals to independently DB8, the HBEN pin should be tied high. In byte mode when all initiate conversions on the three ADC pairs, care should be three CONVST pins are pulsed together to initiate simultaneous taken to ensure that a conversion is not initiated on a channel conversions on all six ADCs, 12 read operations are necessary pair when the BUSY signal is high. It is also recommended not to read back the six 16-/14-/12-bit conversion results. DB[6:0] to initiate a conversion during a read sequence because doing so should be left unconnected in byte mode. t 10 CONVST A, CONVST B, CONVST C t CONVERT t ACQ BUSY t 4 CS t 3 t 5 RD t 9 t 2 t 7 t 6 t 8 t QUIET DB0 TO DB15 V1 V2 V3 V4 V5 V6 Figure 27. Parallel Interface Timing Diagram (W/B = 0) CS t t 3 4 t 9 t 5 RD t 8 t t 6 7 DB15 TO DB8 LOW BYTE HIGH BYTE Figure 28. Parallel Interface—Read Cycle for Byte Mode of Operation (W/B = 1, HBEN = 0) Rev. D | Page 23 of 32 05020-008 05020-007 AD7656/AD7657/AD7658 Data Sheet Software Selection of ADCs Table 11. The H/S SEL pin determines the source of the combination of Bit Mnemonic Comment ADCs that are to be simultaneously sampled. When the H/S SEL DB15 VC This bit is used to select Analog Inputs V5 and V6 for the next conversion. pin is logic low, the combination of channels to be simultaneously When this bit = 1, V5 and V6 are sampled is determined by the CONVST A, CONVST B, and simultaneously converted on the H CONVST C pins. When the /S SEL pin is logic high, the next CONVST A rising edge. combination of channels selected for simultaneous sampling is DB14 VB This bit is used to select Analog Inputs determined by the contents of the Control Register DB15 to V3 and V4 for the next conversion. Control Register DB13. In this mode, a write to the control When this bit = 1, V3 and V4 are simultaneously converted on the register is necessary. next CONVST A rising edge. The control register is an 8-bit write-only register. Data is written DB13 VA This bit is used to select Analog Inputs CS WR V1 and V2 for the next conversion. to this register using the and pins and the DB[15:8] data When this bit = 1, V1 and V2 are pins (see Figure 29). The control register is shown in Table 10. simultaneously converted on the To select an ADC pair to be simultaneously sampled, set the next CONVST A rising edge. corresponding data line high during the write operation. DB12 RNGC This bit is used to select the analog input range for Analog Inputs V5 and V6. The AD7656/AD7657/AD7658 control register allows When this bit = 1, the ±2 × V mode is REF individual ranges to be programmed on each ADC pair. selected for the next conversion. DB12 to DB10 in the control register are used to program When this bit = 0, the ±4 × VREF mode is the range on each ADC pair. selected for the next conversion. DB11 RNGB This bit is used to select the analog input After a reset occurs on the AD7656/AD7657/AD7658, the range for Analog Inputs V3 and V4. control register contains all zeros. When this bit = 1, the ±2 × VREF mode is selected for the next conversion. The CONVST A signal is used to initiate a simultaneous When this bit = 0, the ±4 × V mode is REF conversion on the combination of channels selected via the selected for the next conversion. control register. The CONVST B and CONVST C signals can DB10 RNGA This bit is used to select the analog input range for Analog Inputs V1 and V2. be tied low when operating in software mode (H/S SEL = 1). When this bit = 1, the ±2 × V mode is REF The number of read pulses required depends on the number selected for the next conversion. of ADCs selected in the control register and on whether the When this bit = 0, the ±4 × VREF mode is devices are operating in word or byte mode. The conversion selected for the next conversion. results are output in ascending order. DB9 REFEN This bit is used to select the internal reference or an external reference. During the write operation, Data Bus Bit DB15 to Bit DB8 are When this bit = 0, the external reference bidirectional and become inputs to the control register when mode is selected. When this bit = 1, the internal reference is selected. RD is logic high and CS and WR are logic low. The logic state DB8 REFBUF This bit is used to select between using the on DB15 through DB8 is latched into the control register when internal reference buffers and choosing WR goes logic high. to bypass these reference buffers. When this bit = 0, the internal reference Table 10. Control Register Bit Function Descriptions buffers are enabled and decoupling is required on the REFCAP pins. When this (Default All 0s) bit = 1, the internal reference buffers are DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 disabled and a buffered reference should VC VB VA RNGC RNGB RNGA REFEN REFBUF be applied to the REFCAP pins. CS WR t t t 12 13 11 t 15 t 14 DB15 TO DB8 DATA W Figure 29. Parallel Interface—Write Cycle for Word Mode ( /B= 0) Rev. D | Page 24 of 32 05020-009 Data Sheet AD7656/AD7657/AD7658 If it is required to clock conversion data out on two data out Changing the Analog Input Range ( /S SEL = 0) H lines, DOUT A and DOUT B should be used. To enable DOUT A The AD7656/AD7657/AD7658 RANGE pin allows the user to and DOUT B, DB0/SEL A and DB1/SEL B should be tied to select either ±2 × V or ±4 × V as the analog input range for REF REF VDRIVE and DB2/SEL C should be tied low. When six simultaneous H the six analog inputs. When the /S SEL pin is low, the logic conversions are performed and only two DOUT lines are used, state of the RANGE pin is sampled on the falling edge of the a 48 SCLK transfer can be used to access the data from the BUSY signal to determine the range for the next simultaneous AD7656/AD7657/AD7658. The read sequence is shown in conversion. When the RANGE pin is logic high at the falling Figure 31 for a simultaneous conversion on all six ADCs using edge of the BUSY signal, the range for the next conversion is two DOUT lines. If a simultaneous conversion occurred on all ±2 × VREF. When the RANGE pin is logic low at the falling six ADCs, and only two DOUT lines are used to read the results edge of the BUSY signal, the range for the next conversion is from the AD7656/AD7657/AD7658. DOUT A clocks out the ±4 × V . After a RESET pulse, the range is updated on the first REF result from V1, V2, and V5, while DOUT B clocks out the falling BUSY edge after the RESET pulse. results from V3, V4, and V6. Changing the Analog Input Range ( /S SEL = 1) H Data can also be clocked out using just one DOUT line, in H which case, DOUT A should be used to access the conversion When the /S SEL pin is high, the range can be changed by data. To configure the AD7656/AD7657/AD7658 to operate in writing to the control register. DB[12:10] in the control register this mode, DB0/SEL A should be tied to V and DB1/SEL B DRIVE are used to select the analog input ranges for the next conversion. and DB2/SEL C should be tied low. The disadvantage of using Each analog input pair has an associated range bit, allowing just one DOUT line is that the throughput rate is reduced. Data independent ranges to be programmed on each ADC pair. can be accessed from the AD7656/AD7657/AD7658 using one When the RNGx bit = 1, the range for the next conversion 96 SCLK transfer, three 32 SCLK individually framed transfers, is ±2 × V . When the RNGx bit = 0, the range for the next REF or six 16 SCLK individually framed transfers. In serial mode, conversion is ±4 × V . REF RD the signal should be tied low. The unused DOUT line(s) Serial Interface (SER/ = 1) PAR should be left unconnected in serial mode. By pulsing one, two, or all three CONVST x signals, the Serial Read Operation AD7656/AD7657/AD7658 use their on-chip trimmed oscillator Figure 32 shows the timing diagram for reading data from the to simultaneously convert the selected channel pairs on the AD7656/AD7657/AD7658 in serial mode. The SCLK input signal rising edge of CONVST x. After the rising edge of CONVST x, CS provides the clock source for the serial interface. The signal the BUSY signal goes high to indicate that the conversion has goes low to access data from the AD7656/AD7657/AD7658. started. It returns low when the conversion is complete 3 µs CS later. The output register is loaded with the new conversion The falling edge of takes the bus out of three-state and results, and data can be read from the AD7656/AD7657/AD7658. clocks out the MSB of the 16-bit conversion result. The ADCs To read the data back from the parts over the serial interface, output 16 bits for each conversion result; the data stream of the PAR SER/ should be tied high. The CS and SCLK signals are AD7656 consists of 16 bits of conversion data provided MSB first. The data stream for the AD7657 consists of two leading used to transfer data from the AD7656/AD7657/AD7658. The zeros followed by 14 bits of conversion data MSB first. The data parts have three DOUT pins, DOUT A, DOUT B, and DOUT C. stream for the AD7658 consists of four leading zeros and 12 bits Data can be read back from each part using one, two, or all of conversion data provided MSB first. three DOUT lines. The first bit of the conversion result is valid on the first SCLK Figure 30 shows six simultaneous conversions and the read falling edge after the CS falling edge. The subsequent 15 data sequence using three DOUT lines. Also in Figure 30, 32 SCLK transfers are used to access data from the AD7656/AD7657/ bits are clocked out on the rising edge of the SCLK signal. Data AD7658; however, two 16 SCLK individually framed transfers is valid on the SCLK falling edge. To access each conversion result, 16 clock pulses must be provided to the AD7656/AD7657/ with the CS signal can also be used to access the data on the AD7658. Figure 32 shows how a 16 SCLK read is used to access three DOUT lines. When operating the AD7656/AD7657/AD7658 the conversion results. in serial mode with conversion data clocking out on all three DOUT lines, DB0/SEL A, DB1/SEL B, and DB2/SEL C should be tied to V . These pins are used to enable the DOUT A to DRIVE DOUT C lines, respectively. Rev. D | Page 25 of 32 AD7656/AD7657/AD7658 Data Sheet CONVST A, CONVST B, CONVST C t CONVERT t ACQ BUSY CS 16 32 SCLK t QUIET DOUT A V1 V2 DOUT B V3 V4 DOUT C V5 V6 Figure 30. Serial Interface with Three DOUT Lines CS 48 SCLK DOUT A V5 V1 V2 DOUT B V3 V4 V6 Figure 31. Serial Interface with Two DOUT Lines t 1 CONVST A, t 10 CONVST B, t t CONVERT ACQ CONVST C t 2 BUSY ACQUISITION CONVERSION ACQUISITION CS t QUIET t t 19 18 SCLK t 16 t 17 t 20 t 21 DB15 DB14 DB13 DB1 DB0 DOUT A, DOUT B, DOUT C Figure 32. Serial Read Operation Rev. D | Page 26 of 32 05020-011 05020-010 05020-012 Data Sheet AD7656/AD7657/AD7658 Figure 35 shows the timing if two AD7656/AD7657/AD7658 Daisy-Chain Mode (DCEN = 1, SER/ = 1) PAR devices are configured in daisy-chain mode and are operating When reading conversion data back from the AD7656/AD7657/ with three DOUT lines. Assuming a simultaneous sampling of AD7658 using their three/two/one DOUT pins, it is possible all 12 inputs occurs, the CS frames a 64 SCLK transfer during to configure the parts to operate in daisy-chain mode, using the read operation. During the first 32 SCLKs of this transfer, the DCEN pin. This daisy-chain feature allows multiple AD7656/ the conversion results from Device 1 are clocked into the digital AD7657/AD7658 devices to be cascaded together and is useful host and the conversion results from Device 2 are clocked into for reducing component count and wiring connections. An Device 1. During the last 32 SCLKs of the transfer, the conver- example connection of two devices is shown in Figure 33. This sion results from Device 2 are clocked out of Device 1 and into configuration shows two DOUT lines being used. Simultaneous the digital host. Device 2 clocks out zeros. sampling of the 12 analog inputs is possible by using a common CONVSTx signal. The DB5, DB4, and DB3 data pins are used Standby/Partial Power-Down Modes of Operation as data input pins DCIN [A:C] for the daisy-chain mode. Each ADC pair can be individually placed into partial power- down mode by bringing the CONVST x signal low before the The rising edge of CONVST is used to initiate a conversion on falling edge of BUSY. To power the ADC pair back up, the the AD7656/AD7657/AD7658. After the BUSY signal has gone CONVST x signal should be brought high to tell the ADC pair low to indicate that the conversion is complete, the user can to power up and place the track-and-hold into track mode. begin to read the data from the two devices. Figure 34 shows the After the power-up time from partial power-down has elapsed, serial timing diagram when operating two AD7656/AD7657/ the CONVST x signal should receive a rising edge to initiate a D7658 devices in daisy-chain mode. valid conversion. In partial power-down mode, the reference CS buffers remain powered up. While an ADC pair is in partial power- The falling edge is used to frame the serial transfer from the down mode, conversions can still occur on the other ADCs. AD7656/AD7657/AD7658 devices, to take the bus out of three- state, and to clock out the MSB of the first conversion result. In The AD7656/AD7657/AD7658 have a standby mode whereby the example shown in Figure 34, all 12 ADC channels are the devices can be placed into a low power consumption mode simultaneously sampled. Two DOUT lines are used to read the (100 µW maximum). The AD7656/AD7657/AD7658 are placed CS conversion results in this example. frames a 96 SCLK transfer. into standby mode by bringing the logic input STBY low and During the first 48 SCLKs, the conversion data is transferred can be powered up again for normal operation by bringing from Device 2 to Device 1. DOUT A on Device 2 transfers STBY logic high. The output data buffers are still operational conversion data from V1, V2, and V5 into DCIN A in Device 1. when the AD7656/AD7657/AD7658 are in standby mode, DOUT B on Device 2 transfers conversion results from V3, V4, meaning the user can continue to access the conversion results and V6 to DCIN B in Device 1. During the first 48 SCLKs, of the parts. This standby feature can be used to reduce the Device 1 transfers data into the digital host. DOUT A on average power consumed by the AD7656/AD7657/AD7658 Device 1 transfers conversion data from V1, V2, and V5. when operating at lower throughput rates. The parts can be DOUT B on Device 1 transfers conversion data from V3, V4, placed into standby at the end of each conversion when and V6. During the last 48 SCLKs, Device 2 clocks out zeros BUSY goes low and taken out of standby again prior to the and Device 1 shifts the data clocked in from Device 2 during next conversion. The time for the AD7656/AD7657/AD7658 the first 48 SCLKs into the digital host. This example can to come out of standby is called the wake-up time. The wake- also be implemented using six 16 SCLK individually framed up time limits the maximum throughput rate at which the transfers if DCEN remains high during the transfers. AD7656/AD7657/AD7658 can operate when powering down between conversions. See the Specifications section. Rev. D | Page 27 of 32 AD7656/AD7657/AD7658 Data Sheet CONVERT DIGITAL HOST CONVST CONVST DOUT A DCIN A DOUT A DATA IN1 DCIN B DOUT B DATA IN2 DOUT B AD7656/AD7657/AD7658 AD7656/AD7657/AD7658 SCLK CS SCLK CS CS SCLK DCEN = 0 DCEN = 1 DEVICE 2 DEVICE 1 Figure 33. Daisy-Chain Configuration CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 65 94 95 96 SCLK DEVICE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 Figure 34. Daisy-Chain Serial Interface Timing with Two DOUT Lines CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 SCLK DEVICE 1, DOUT A LSB V1 MSB V2 LSB V2 MSB V1 LSB V1 MSB V2 LSB V2 MSB V1 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 1, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 MSB V5 LSB V5 MSB V6 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 2, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 Figure 35. Daisy-Chain Serial Interface Timing with Three DOUT Lines Rev. D | Page 28 of 32 05020-013 05020-015 05020-014 Data Sheet AD7656/AD7657/AD7658 APPLICATION HINTS parasitic inductances. Recommended decoupling capacitors are LAYOUT 100 nF, low ESR, ceramic capacitors (Farnell 335-1816) and The printed circuit board that houses the AD7656/AD7657/ 10 μF, low ESR, tantalum capacitors (Farnell 197-130) for the AD7658 should be designed so that the analog and digital AVCC decoupling. A large tantalum decoupling capacitor should sections are separated and confined to certain areas of the board. be placed where the AV supply enters the board. CC At least one ground plane should be used. It could be common An alternative reduced decoupling arrangement is outlined in or split between the digital and analog sections. In the case of the Typical Connection Diagram section. This decoupling the split plane, the digital and analog ground planes should be arrangement groups the AV supply pins into pairs and allows CC joined in only one place, preferably underneath the AD7656/ the decoupling capacitors to be shared between the supply pairs. AD7657/AD7658, or at least as close as possible to each part. Group the six AVCC core supply pins into three pairs, Pin 34 and If the AD7656/AD7657/AD7658 are in a system where multiple Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the devices require analog-to-digital ground connections, the con- supply pins in each pair together; their location on the AD7656/ nection should still be made at only one point, a star ground AD7657/AD7658 pin configuration easily facilitates this. For point, which should be established as close as possible to the the AD7656, decouple each pair with a 100 µF capacitor; for the AD7656/AD7657/AD7658. Good connections should be made AD7657, decouple each pair with a 33 µF capacitor; for the to the ground plane. Avoid sharing one connection for multiple AD7658, decouple each pair with a 22 µF capacitor. For this ground pins. Individual vias or multiple vias to the ground minimum decoupling configuration, all other supply and plane should be used for each ground pin. reference pins should be decoupled with a 10 µF decoupling capacitor. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be POWER SUPPLY CONFIGURATION allowed to run under the AD7656/AD7657/AD7658 to avoid As outlined in the Absolute Maximum Ratings section, the noise coupling. Fast-switching signals like CONVST or clocks analog inputs should not be applied to the AD7656/AD7657/ should be shielded with digital ground to avoid radiating noise AD7658 until after the AD7656/AD7657/AD7658 power to other sections of the board, and they should never run near supplies have been applied to the device. However, if a analog signal paths. Crossover of digital and analog signals condition exists where the system analog signal conditioning should be avoided. Traces on different but close layers of the circuitry supplies are different to the V and V supplies of DD SS board should run at right angles to each other to reduce the the AD7656/AD7657/AD7658, or if the analog inputs may be effect of feedthrough through the board. applied prior to the AD7656/AD7657/AD7658 supplies being The power supply lines to the AV CC, DVCC, VDRIVE, VDD, and VSS established, then an analog input series resister and Schottky pins on the AD7656/AD7657/AD7658 should use as large a diodes in series with the VDD and VSS supplies are recom- trace as possible to provide low impedance paths and reduce the mended, see Figure 36. This configuration should also be effect of glitches on the power supply lines. Good connections used if AV is applied to the AD7656/AD7657/AD7658 CC should be made between the AD7656/AD7657/AD7658 supply prior to V and V . DD SS pins and the power tracks on the board; this should involve the V DD use of a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply 240Ω impedance presented to the AD7656/AD7657/AD7658 and to V1 V DD reduce the magnitude of the supply spikes. Decoupling ceramic V2 AD7656/ V3 ANALOG capacitors, typically 100 nF, should be placed on all of the power AD7657/ INPUTS V4 AD7658 supply pins, V , V , AV , DV , and V . These decoupling DD SS CC CC DRIVE V5 V6 V capacitors should be placed close to, ideally right up against, SS these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be placed on each of the supply pins. Avoid sharing these capacitors between pins. Use V SS big vias to connect the capacitors to the power and ground Figure 36. Power Supply Configuration planes. Use wide, short traces between the via and the capacitor pad, or place the via adjacent to the capacitor pad to minimize Rev. D | Page 29 of 32 05020-036 AD7656/AD7657/AD7658 Data Sheet OUTLINE DIMENSIONS 12.20 12.00 SQ 0.75 11.80 0.60 1.60 0.45 MAX 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 16 33 0.15 0° SEATING 17 32 0.05 0.08 PLANE VIEW A COPLANARITY 0.27 0.50 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 37. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option AD7656BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656YSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7656YSTZ-REEL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657YSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7657YSTZ-REEL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658YSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7658YSTZ-REEL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-AD7656CBZ Evaluation Board EVAL-AD7657CBZ Evaluation Board EVAL-AD7658CBZ Evaluation Board EVAL-CONTROL BRD2Z Controller Board 1 Z = RoHS Compliant Part. 2 The EVAL-CONTROL BRD2Z is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, for example, EVAL-AD7656/AD7657/AD7658CBZ, the EVAL-CONTROL BRD2Z and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information. Rev. D | Page 30 of 32 051706-A Data Sheet AD7656/AD7657/AD7658 NOTES Rev. D | Page 31 of 32 AD7656/AD7657/AD7658 Data Sheet NOTES ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05020-0-3/12(D) Rev. D | Page 32 of 32