ANALOG DEVICES AD7655

Low Cost, 4-Channel, 16-Bit 1 MSPS ® PulSAR ADC AD7655 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND REFGND REFx DVDD DGND 4-channel, 16-bit resolution ADC 2 track-and-hold amplifiers TRACK/HOLD OVDD ×2 Throughput INA1 SERIAL OGND PORT INAN MUX 16 1 MSPS (normal mode) D[15:0] INA2 888 kSPS (impulse mode) SWITCHED A0 MUX SER/PAR CAP DAC Analog input voltage range: 0 V to 5 V INB1 EOC INBN MUX No pipeline delay BUSY INB2 Parallel and serial 5 V/3 V interface CLOCK PARALLEL CS PD INTERFACE SPI®/QSPI™/MICROWIRE™/DSP compatible CONTROL LOGIC AND RD RESET CALIBRATION CIRCUITRY Single 5 V supply operation A/B AD7655 Power dissipation BYTESWAP 120 mW typical IMPULSE CNVST 2.6 mW @ 10 kSPS Package Figure 1. 48-lead quad flat package (LQFP) Table 1. PulSAR Selection 48-lead frame chip scale package (LFCSP) 800 to Pin-to-pin compatible with the AD7654 Type/kSPS 100 to 250 500 to 570 1000 >1000 Low cost AD7660/ AD7650/ AD7653 Pseudo AD7661 AD7652 AD7667 Differential AD7664/ APPLICATIONS AD7666 AC motor control AD7663 AD7665 AD7671 True Bipolar 3-phase power control AD7621 True 4-channel data acquisition AD7623 Differential AD7675 AD7676 AD7677 Uninterrupted power supplies 18 Bit AD7678 AD7679 AD7674 AD7641 Communications AD7654 AD7655 Multichannel/ Simultaneous GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. Multichannel ADC. The AD7655 is a low cost, simultaneous sampling, dual- The AD7655 features 4-channel inputs with two sample- channel, 16-bit, charge redistribution SAR, analog-to-digital and-hold circuits that allow simultaneous sampling. converter that operates from a single 5 V power supply. It contains two low noise, wide bandwidth, track-and-hold 2. Fast Throughput. amplifiers that allow simultaneous sampling, a high speed The AD7655 is a 1 MSPS, charge redistribution, 16-bit SAR 16-bit sampling ADC, an internal conversion clock, error ADC with internal error correction circuitry. correction circuits, and both serial and parallel system interface 3. Single-Supply Operation. ports. Each track-and-hold has a multiplexer in front to provide The AD7655 operates from a single 5 V supply. In impulse a 4-channel input ADC. The A0 multiplexer control input mode, its power dissipation decreases with throughput. allows the choice of simultaneously sampling input pairs 4. Serial or Parallel Interface. INA1/INB1 (A0 = low) or INA2/INB2 (A0 = high). The part Versatile parallel or 2-wire serial interface arrangements features a very high sampling rate mode (normal) and, for low are compatible with both 3 V and 5 V logic. power applications, a reduced power mode (impulse) where the power is scaled with the throughput. Operation is specified from −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03536-001 AD7655 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 17 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 17 General Description ......................................................................... 1 Power Dissipation....................................................................... 17 Product Highlights ........................................................................... 1 Conversion Control ................................................................... 18 Specifications..................................................................................... 3 Digital Interface.......................................................................... 18 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 18 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 20 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 20 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 22 Terminology .................................................................................... 11 Microprocessor Interfacing....................................................... 24 Typical Performance Characteristics ........................................... 12 SPI Interface (ADSP-219X) ....................................................... 24 Application Information................................................................ 14 Application Hints ........................................................................... 25 Circuit Information.................................................................... 14 Layout .......................................................................................... 25 Modes of Operation ................................................................... 14 Evaluating the AD7655 Performance ...................................... 25 Transfer Functions...................................................................... 14 Outline Dimensions ....................................................................... 26 Typical Connection Diagram ................................................... 16 Ordering Guide .......................................................................... 27 Analog Inputs.............................................................................. 16 Input Channel Multiplexer........................................................ 16 REVISION HISTORY 12/04—Rev. 0 to Rev. A Changes to Figure 17...................................................................... 15 9/05—Rev. A to Rev. B Changes to Figure 18...................................................................... 16 Changes to General Description .................................................... 1 Changes to Voltage Reference Input section .............................. 17 Changes to Specifications................................................................ 3 Changes to Conversion Control section ..................................... 18 Changes to Timing Specifications.................................................. 5 Changes to Digital Interface section............................................ 18 Changes to Typical Performance Characteristics....................... 13 Updated Outline Dimensions....................................................... 25 Changes to Figure 17...................................................................... 15 Added Table 8.................................................................................. 17 11/02—Revision 0: Initial Version Changes to Figure 28...................................................................... 21 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 Rev. B | Page 2 of 28 AD7655 SPECIFICATIONS AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V 0 2 V V INx INxN REF Common-Mode Input Voltage V −0.1 +0.5 V INxN Analog Input CMRR f = 100 kHz 55 dB IN Input Current 1 MSPS throughput 45 μA 1 Input Impedance THROUGHPUT SPEED Complete Cycle (2 Channels) Normal mode 2 μs Throughput Rate Normal mode 0 1 MSPS Complete Cycle (2 Channels) Impulse mode 2.25 μs Throughput Rate Impulse mode 0 888 kSPS DC ACCURACY 2 3 Integral Linearity Error −6 +6 LSB No Missing Codes 15 Bits Transition Noise 0.8 LSB 4 Full-Scale Error TMIN to TMAX ±0.25 ±0.5 % of FSR 4 Full-Scale Error Drift ±2 ppm/°C 4 Unipolar Zero Error TMIN to TMAX ±0.25 % of FSR 4 Unipolar Zero Error Drift ±0.8 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB AC ACCURACY 5 Signal-to-Noise f = 100 kHz 86 dB IN Spurious-Free Dynamic Range f = 100 kHz 98 dB IN Total Harmonic Distortion fIN = 100 kHz −96 dB Signal-to-Noise and Distortion fIN = 100 kHz 86 dB fIN = 100 kHz, −60 dB input 30 dB Channel-to-Channel Isolation f = 100 kHz −92 dB IN −3 dB Input Bandwidth 10 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Delay Matching 30 ps Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD/2 V External Reference Current Drain 1 MSPS throughput 180 μA DIGITAL INPUTS Logic Levels VIL −0.3 +0.8 V VIH +2.0 DVDD + 0.3 V I −1 +1 μA IL I −1 +1 μA IH DIGITAL OUTPUTS 6 Data Format 7 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK VOH ISOURCE = −500 μA OVDD − 0.2 V Rev. B | Page 3 of 28 AD7655 Parameter Conditions Min Typ Max Unit POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V 4.75 5 5.25 V DVDD 8 OVDD 2.7 5.25 V 9 Operating Current 1 MSPS throughput AVDD 15.5 mA DVDD 8.5 mA OVDD 100 μA 9 Power Dissipation 1 MSPS throughput 120 135 mW 10 20 kSPS throughput 2.6 mW 10 888 kSPS throughput 114 125 mW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. 3 LSB means least significant bit. With the 0 V to 5 V input range, 1 LSB is 76.294 μV. 4 See the Terminology section. These specifications do not include the error contribution from the external reference. 5 All specifications in dB are referred to as full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 6 Parallel or serial 16 bit. 7 Conversion results are available immediately after completed conversion. 8 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 9 In normal mode; tested in parallel reading mode. 10 In impulse mode; tested in parallel reading mode. 11 Consult sales for extended temperature range. Rev. B | Page 4 of 28 AD7655 TIMING SPECIFICATIONS AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 21 and Figure 22) Convert Pulse Width t 5 ns 1 Time Between Conversions (Normal Mode/Impulse Mode) t2 2/2.25 μs CNVST Low to BUSY High Delay t3 32 ns BUSY High All Modes Except in Master Serial Read After Convert Mode (Normal Mode/Impulse Mode) t 1.75/2 μs 4 Aperture Delay t5 2 ns End of Conversions to BUSY Low Delay t6 10 ns Conversion Time (Normal Mode/Impulse Mode) t 1.75/2 μs 7 Acquisition Time t 250 ns 8 RESET Pulse Width t 10 ns 9 CNVST Low to EOC High Delay t10 30 ns EOC High for Channel A Conversion (Normal Mode/Impulse Mode) t11 1/1.25 μs EOC Low after Channel A Conversion t 45 ns 12 EOC High for Channel B Conversion t 0.75 μs 13 Channel Selection Setup Time t 250 ns 14 Channel Selection Hold Time t15 30 ns PARALLEL INTERFACE MODES (See Figure 23 to Figure 27) CNVST Low to DATA Valid Delay t16 1.75/2 μs DATA Valid to BUSY Low Delay t17 14 ns Bus Access Request to DATA Valid t 40 ns 18 Bus Relinquish Time t 5 15 ns 19 A/B Low to Data Valid Delay t20 40 ns MASTER SERIAL INTERFACE MODES (See Figure 28 and Figure 29) CS Low to SYNC Valid Delay t 10 ns 21 1 CS Low to Internal SCLK Valid Delay t22 10 ns CS Low to SDOUT Delay t23 10 ns CNVST Low to SYNC Delay, Read During Convert (Normal Mode/Impulse Mode) t 250/500 ns 24 SYNC Asserted to SCLK First Edge Delay t 3 ns 25 2 Internal SCK Period t 23 40 ns 26 2 Internal SCLK High t27 12 ns 2 Internal SCLK Low t28 7 ns 2 SDOUT Valid Setup Time t 4 ns 29 2 SDOUT Valid Hold Time t 2 ns 30 2 SCLK Last Edge to SYNC Delay t 1 ns 31 CS High to SYNC HI-Z t32 10 ns CS High to Internal SCLK HI-Z t33 10 ns CS High to SDOUT HI-Z t34 10 ns 2 BUSY High in Master Serial Read after Convert t See Table 4 35 CNVST Low to SYNC Asserted Delay (Normal Mode/Impulse Mode) t 0.75/1 μs 36 SYNC Deasserted to BUSY Low Delay t37 25 ns Rev. B | Page 5 of 28 AD7655 Parameter Symbol Min Typ Max Unit SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32) External SCLK Setup Time t38 5 ns External SCLK Active Edge to SDOUT Delay t39 3 18 ns SDIN Setup Time t 5 ns 40 SDIN Hold Time t 5 ns 41 External SCLK Period t 25 ns 42 External SCLK High t43 10 ns External SCLK Low t44 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum. 2 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t25 3 17 17 17 ns Internal SCLK Period Minimum t26 25 50 100 200 ns Internal SCLK Period Typical t26 40 70 140 280 ns Internal SCLK High Minimum t 12 22 50 100 ns 27 Internal SCLK Low Minimum t 7 21 49 99 ns 28 SDOUT Valid Setup Time Minimum t 4 18 18 18 ns 29 SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t31 1 3 30 80 ns Busy High Width Maximum (Normal) t35 3.25 4.25 6.25 10.75 μs Busy High Width Maximum (Impulse) t 3.5 4.5 6.5 11 μs 35 Rev. B | Page 6 of 28 AD7655 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Values may cause permanent damage to the device. This is a stress Analog Input rating only; functional operation of the device at these or any 1 1 INAx , INBx , REFx, INxN, REFGND AVDD + 0.3 V to other conditions above those indicated in the operational AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD, OVDD –0.3 V to +7 V I 1.6mA OL AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD −0.3 V to +7 V TO OUTPUT Digital Inputs −0.3 V to DVDD + 0.3 V 1.4V PIN C L 2 Internal Power Dissipation 700 mW 60pF* 3 Internal Power Dissipation 2.5 W 500μA I Junction Temperature 150°C OH Storage Temperature Range −65°C to +150°C *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD Lead Temperature Range C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L (Soldering 10 sec) 300°C Figure 2. Load Circuit for Digital Interface Timing 1 See the Analog Inputs section. 2 Specification is for device in free air: 48-lead LQFP, θ = 91°C/W, JA θJC = 30°C/W. 3 Specification is for device in free air: 48-lead LFCSP, θ = 26°C/W. JA 2V 0.8V t DELAY t DELAY 2V 2V 0.8V 0.8V Figure 3. Voltage Reference Levels for Timing ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 28 03536-002 03536-003 AD7655 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 DVDD PIN 1 AVDD 2 35 CNVST A0 3 34 PD 4 33 BYTESWAP RESET 5 32 A/B CS AD7655 6 31 DGND RD TOP VIEW (Not to Scale) 7 IMPULSE 30 EOC SER/PAR 8 29 BUSY D0 9 28 D15 D1 10 27 D14 11 26 D2/DIVSCLK[0] D13 12 25 D3/DIVSCLK[1] D12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 47, 48 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3 A0 DI Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted. 4 BYTESWAP DI Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 A/B DI Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel B. When LOW, Channel B is output first followed by Channel A. 6, 20 DGND P Digital Power Ground. 7 IMPULSE DI Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 DI SER/PAR Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after convert mode. These inputs, part of the serial port, are used to slow down the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. 13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock called, respectively, master and slave mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. Rev. B | Page 8 of 28 AGND D4/EXT/INT D5/INVSYNC AGND INA1 D6/INVSCLK D7/RDC/SDIN INAN OGND INA2 OVDD REFA DVDD REFB DGND INB2 D8/SDOUT INBN D9/SCLK INB1 D10/SYNC REFGND D11/RDERROR REF 03536-004 AD7655 1 Pin No. Mnemonic Type Description 15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. 16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19, 36 DVDD P Digital Power. Nominally at 5 V. 21 D[8] DO PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/ or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depends upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH. 24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started but not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25 to 28 D[12:15] DO Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high impedance. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two conversions are complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. 30 EOC DO End of Convert Output. Goes LOW at each channel conversion. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current conversion is completed. Rev. B | Page 9 of 28 AD7655 1 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 37 REF AI This input pin is used to provide a reference to the converter. 38 REFGND AI Reference Input Analog Ground. 39, 41 INB1, INB2 AI Channel B Analog Inputs. 40, 45 INBN, INAN AI Analog Inputs Ground Senses. Allow to sense each channel ground independently. 42, 43 REFB, REFA AI These inputs are the references applied to Channel A and Channel B, respectively. 44, 46 INA2, INA1 AI Channel A Analog Inputs. 1 Al = input; DI = digital input; DO = digital output; DI/O = bidirectional digital; P = power. Rev. B | Page 10 of 28 AD7655 TERMINOLOGY Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal-to-Noise and Distortion Ratio (SINAD) 1½ LSBs beyond the last code transition. The deviation is SINAD is the ratio of the rms value of the actual input signal to measured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, including harmonics but excluding dc. The value for In an ideal ADC, code transitions are 1 LSB apart. Differential SINAD is expressed in decibels. nonlinearity is the maximum deviation from this ideal value, Spurious-Free Dynamic Range (SFDR) and is often specified in terms of resolution for which no The difference, in decibels, between the rms amplitude of the missing codes are guaranteed. input signal and the peak spurious signal. Full-Scale Error Effective Number of Bits (ENOB) The last transition (from 111. . .10 to 111. . .11) should occur for ENOB is a measurement of the resolution with a sine wave an analog voltage 1½ LSBs below the nominal full scale input. It is related to SINAD and expressed in bits by (4.999886 V for the 0 V to 5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal ENOB = (SINADdB − 1.76)/6.02 level. Aperture Delay Aperture delay is a measure of acquisition performance and is Unipolar Zero Error measured from the falling edge of the CNVST input to when The first transition should occur at a level ½ LSB above analog the input signals are held for a conversion. ground (76.29 μV for the 0 V to 5 V range). The unipolar zero error is the deviation of the actual transition from that point. Transient Response The time required for the AD7655 to achieve its rated accuracy Signal-to-Noise Ratio (SNR) after a full-scale step function is applied to its input. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. B | Page 11 of 28 AD7655 TYPICAL PERFORMANCE CHARACTERISTICS 5 3 4 2 3 2 1 1 0 0 –1 –1 –2 –3 –2 –4 –5 –3 0 32768 49152 65536 16384 0 16384 32768 49152 65536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 9000 8000 8480 7059 6894 8000 7000 7000 6000 6000 5000 5000 4000 4000 3505 3396 3000 3000 2000 2000 1230 1094 739 1000 1000 0 5 220 39 0 00 77 29 0 0 0 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 CODE IN HEX CODE IN HEX Figure 9. Histogram of 16,384 Conversions of a DC Input at the Figure 6. Histogram of 16,384 Conversions of a DC Input at the Code Center Code Transition 0 –90 96 8192 POINT FFT f = 500kHz S –20 f = 100kHz, –0.5dB IN SNR = 85.8dB –40 THD = –91.4dB 93 –94 SFDR = 93.6dB SINAD = 84.5dB –60 –80 90 –98 THD –100 –120 87 –102 –140 SNR –160 –180 84 –106 0 25 50 75 100 125 150 175 200 225 250 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 10. SNR, THD vs. Temperature Figure 7. FFT Plot Rev. B | Page 12 of 28 COUNTS INL (LSB) AMPLITUDE (dB of Full Scale) 03536-007 03536-006 03536-005 SNR (dB) DNL (LSB) COUNTS 03536-010 THD (dB) 03536-009 03536-008 AD7655 100 16.0 100 NORMAL AVDD 95 15.5 10 NORMAL DVDD 1 90 15.0 IMPULSE AVDD SNR IMPULSE DVDD 14.5 85 0.1 SINAD 14.0 0.01 80 ENOB 13.5 0.001 OVDD 2.7V 75 13.0 70 0.0001 1 10 100 1000 1 10 100 1000 FREQUENCY (kHz) SAMPLING RATE (kSPS) Figure 11. SNR, SINAD, and ENOB vs. Frequency Figure 14. Operating Currents vs. Sample Rate –75 50 105 OVDD = 2.7V @ 85°C –80 100 OVDD = 2.7V @ 25°C SFDR 40 –85 95 30 CROSSTALK B TO A –90 90 –95 85 OVDD = 5V @ 85°C CROSSTALK A TO B 20 THD OVDD = 5V @ 25°C –100 80 THIRD HARMONIC SECOND HARMONIC 10 –105 75 0 –110 70 0 50 100 150 200 1 10 100 1000 C (pF) L FREQUENCY (kHz) Figure 12. THD, Harmonics, Crosstalk, and SFDR vs. Frequency Figure 15. Typical Delay vs. Load Capacitance CL 5 4 3 FULL-SCALE ERROR 2 ZERO ERROR 1 0 –1 –2 –3 –4 –5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 13. Full-Scale Error and Zero Error vs. Temperature Rev. B | Page 13 of 28 THD, HARMONICS (dB) LSB SNR AND SINAD (dB) SFDR (dB) 03536-011 ENOB (Bits) 03536-013 03536-012 t DELAY (ns) OPERATING CURRENTS (mA) 18 03536-014 03536-015 AD7655 APPLICATION INFORMATION CIRCUIT INFORMATION TRANSFER FUNCTIONS The AD7655 is a very fast, low power, single-supply, precise The AD7655 data format is straight binary. The ideal transfer simultaneous sampling 16-bit ADC. characteristic for the AD7655 is shown in Figure 16 and Table 7. The LSB size is 2 × V /65536, which is about 76.3 μV. REF The AD7655 provides the user with two on-chip, track-and- hold, successive approximation ADCs that do not exhibit any pipeline or latency, making it ideal for multiple multiplexed 111...111 111...110 channel applications. The AD7655 can also be used as a 111...101 4-channel ADC with two pairs simultaneously sampled. The AD7655 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP or a tiny, 48-lead LFCSP that combines space savings and allows flexible configurations as either a serial or 000...010 parallel interface. The AD7655 is pin-to-pin compatible with 000...001 PulSAR ADCs. 000...000 –FS –FS + 1 LSB +FS – 1 LSB MODES OF OPERATION –FS + 0.5 LSB +FS – 1.5 LSB ANALOG INPUT The AD7655 features two modes of operation, normal mode and impulse mode. Each of these modes is suitable for specific Figure 16. ADC Ideal Transfer Function applications. Normal mode is the fastest mode (1 MSPS). Except when it is Table 7. Output Codes and Ideal Input Voltages powered down (PD = HIGH), the power dissipation is almost Analog Input independent of the sampling rate. Description V = 2.5 V Digital Output Code REF 1 FSR − 1 LSB 4.999924 V 0xFFFF Impulse mode, the lowest power dissipation mode, allows FSR − 2 LSB 4.999847 V 0xFFFE power saving between conversions. The maximum throughput Midscale + 1 LSB 2.500076 V 0x8001 in this mode is 888 kSPS. When operating at 20 kSPS, for Midscale 2.5 V 0x8000 example, it typically consumes only 2.6 mW. This feature makes Midscale − 1 LSB 2.499924 V 0x7FFF the AD7655 ideal for battery-powered applications. −FSR + 1 LSB −76.29 μV 0x0001 2 −FSR 0 V 0x0000 1 This is also the code for overrange analog input: (V – V above 2 × (V – V )). INx INxN REF REFGND 2 This is also the code for underrange analog input (VINx below VINxN). Rev. B | Page 14 of 28 ADC CODE (Straight Binary) 03536-016 AD7655 DVDD ANALOG 30Ω DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) NOTE 6 + + + 100nF 10μF 10μF 100nF 100nF 10μF AD780 AVDD AGND DGND OVDD OGND DVDD SERIAL PORT REF 2.5V REF SCLK REF A 1MΩ NOTE 1 C + REF REF B 50kΩ 1μF NOTE 1 100nF NOTE 2 SDOUT REFGND NOTE 3 50Ω BUSY μC/μP/ 50Ω - 10Ω DSP CNVST D NOTE 4 U1 INA1 ANALOG INPUT A1 + 2.7nF NOTE 7 C C NOTE 5 AD7655 A0 SER/PAR DVDD A/B 50Ω CS RD - 10Ω NOTE 4 U2 INA2 BYTESWAP CLOCK ANALOG INPUT A2 + RESET 2.7nF C C PD NOTE 5 INAN 50Ω - 10Ω NOTE 4 U3 INB1 ANALOG INPUT B1 + 2.7nF C C NOTE 5 50Ω - 10Ω NOTE 4 U4 INB2 ANALOG INPUT B2 + 2.7nF C C NOTE 5 INBN NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C IS 47μF. SEE VOLTAGE REFERENCE INPUT SECTION. REF 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. SEE ANALOG INPUTS SECTION. 6. OPTIONAL, SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION. Figure 17. Typical Connection Diagram (Serial Interface) Rev. B | Page 15 of 28 03536-017 AD7655 TYPICAL CONNECTION DIAGRAM Figure 17 shows a typical connection diagram for the AD7655. be kept low because it affects the ac performance, especially the Some of the circuitry shown in this diagram is optional and is total harmonic distortion. The maximum source impedance discussed in the following sections. depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades when the source ANALOG INPUTS impedance increases. Figure 18 shows a simplified analog input section of the INPUT CHANNEL MULTIPLEXER AD7655. The AD7655 allows the choice of simultaneously sampling the AVDD inputs pairs INA1/INB1 or INA2/INB2 with the A0 multiplexer input. When A0 is low, the input pairs INA1/INB1 are selected, A0 = L R and when A0 is high, the input pairs INA2/INB2 are selected. A INA1 A0 = H INA2 Note that INAx is always converted before INBx regardless of C S INAN the state of the digital interface channel selection A/B pin. INBN Also note that the channel selection control, A0, should not be A0 = L C S INB1 A0 = H changed during the acquisition phase of the converter. Refer to INB2 R B the Conversion Control section and Figure 21 for timing details. DRIVER AMPLIFIER CHOICE AGND A0 Although the AD7655 is easy to drive, the driver amplifier Figure 18. Simplified Analog Input needs to meet at least the following requirements: The diodes shown in Figure 18 provide ESD protection for • The noise generated by the driver amplifier needs to be the inputs. Care must be taken to ensure that the analog input kept as low as possible to preserve the SNR and transition signal never exceeds the absolute ratings on these inputs. noise performance of the AD7655. The noise coming from This causes the diodes to become forward biased and start the driver is filtered by the AD7655 analog input circuit conducting current. These diodes can handle a forward-biased one-pole, low-pass filter made by RA, RBB, and CS or by an current of 120 mA maximum. This condition can occur when external filter, if one is used. the input buffer (U1) or (U2) supplies are different from AVDD. • The driver needs to have a THD performance suitable to In such a case, an input buffer with a short-circuit current that of the AD7655. limitation can be used to protect the part. • For multichannel, multiplexed applications, the driver This analog input structure allows the sampling of the amplifier and the AD7655 analog input circuit together differential signal between INx and INxN. Unlike other must be able to settle for a full-scale step of the capacitor converters, the INxN is sampled at the same time as the INx array at a 16-bit level (0.0015%). In the data sheet for the input. By using differential inputs, small signals common to driver amplifier, the settling at 0.1% or 0.01% is more both inputs are rejected. commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified During the acquisition phase, for ac signals, the AD7655 prior to driver selection. behaves like a one-pole RC filter consisting of the equivalent resistance RA, RBB, and CS. The resistors RA and RBB are typically The AD8021 meets these requirements and, for almost all 500 Ω and are a lumped component made up of some serial applications, is usually appropriate. The AD8021 needs an resistors and the on resistance of the switches. The C capacitor S external compensation capacitor of 10 pF. This capacitor should is typically 32 pF and is mainly the ADC sampling capacitor. have good linearity as an NPO ceramic or mica type. The This one-pole filter with a typical −3 dB cutoff frequency of AD8022 can be used where a dual version is needed and a gain 10 MHz reduces undesirable aliasing effects and limits the of +1 is used. noise coming from the inputs. The AD829 is another alternative where high frequency (above Because the input impedance of the AD7655 is very high, the 100 kHz) performance is not required. In a gain of +1, it AD7655 can be driven directly by a low impedance source requires an 82 pF NPO or mica type compensation capacitor. without gain error. To further improve the noise filtering of the The AD8610 is another option where low bias current is needed AD7655 analog input circuit, an external, one-pole RC filter in low frequency applications. between the amplifier output and the ADC input, as shown in Figure 17, can be used. However, the source impedance has to Refer to Table 8 for some recommended op amps. Rev. B | Page 16 of 28 03536-018 AD7655 Table 8. Recommended Driver Amplifiers OVDD does not exceed DVDD by more than 0.3 V, and thus is Amplifier Typical Application free from supply voltage induced latch-up. Additionally, it is ADA4841 Very low noise, low distortion, low power, very insensitive to power supply variations over a wide low frequency frequency range, as shown in Figure 19. AD829 Very low noise, low frequency 70 AD8021 Very low noise, high frequency AD8022 Very low noise, high frequency, dual 65 AD8605/AD8606/ 5 V single supply, low power, AD8608/AD8615/ low frequency, single/dual/quad AD8616/ AD8618 60 AD8610/AD8620 Low bias current, low frequency, single/dual 55 50 VOLTAGE REFERENCE INPUT The AD7655 requires an external 2.5 V reference. The reference 45 input should be applied to REF, REFA, and REFB. The voltage reference input REF of the AD7655 has a dynamic input 40 10 1 100 1000 10000 impedance; it should therefore be driven by a low impedance FREQUENCY (kHz) source with an efficient decoupling. This decoupling depends on the choice of the voltage reference but usually consists of a Figure 19. PSRR vs. Frequency 1 μF ceramic capacitor and a low ESR tantalum capacitor POWER DISSIPATION connected to the REFA, REFB, and REFGND inputs with minimum parasitic inductance. A value of 47 μF is appropriate In impulse mode, the AD7655 automatically reduces its power for the tantalum capacitor when using one of the recommended consumption at the end of each conversion phase. During the reference voltages: acquisition phase, the operating currents are very low, which allows significant power savings when the conversion rate is • The low noise, low temperature drift AD780, ADR421, reduced, as shown in Figure 20. This feature makes the AD7655 and ADR431 voltage references ideal for very low power battery applications. • The low cost AD1582 voltage reference Note that the digital interface remains active even during the For applications using multiple AD7655s with one voltage acquisition phase. To reduce the operating digital supply reference source, it is recommended that the reference source currents even further, the digital inputs need to be driven close drives each ADC in a star configuration with individual to the power rails (that is, DVDD and DGND), and OVDD decoupling placed as close as possible to the REF/REFGND should not exceed DVDD by more than 0.3 V. inputs. Also, it is recommended that a buffer, such as the 1000 AD8031/AD8032, be used in this configuration. Care should be taken with the reference temperature coefficient NORMAL of the voltage reference, which directly affects the full-scale 100 accuracy if this parameter is applicable. For instance, a 15 ppm/°C tempco of the reference changes the full-scale IMPULSE 10 accuracy by 1 LSB/°C. POWER SUPPLY The AD7655 uses three sets of power supply pins: an analog 1 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD 0.1 supply allows direct interface with any logic working between 100 1000 1 10 2.7 V and DVDD + 0.3 V. To reduce the number of supplies SAMPLING RATE (kSPS) needed, the digital core (DVDD) can be supplied through a Figure 20. Power Dissipation vs. Sample Rate simple RC filter from the analog supply, as shown in Figure 17. The AD7655 is independent of power supply sequencing, once Rev. B | Page 17 of 28 POWER DISSIPATION (mW) PSRR (dB) 03536-020 03536-019 AD7655 CONVERSION CONTROL Figure 21 shows a detailed timing diagram of the conversion The two signals, CS and RD, control the interface. When at process. The AD7655 is controlled by the signal CNVST, least one of these signals is high, the interface outputs are in which initiates conversion. Once initiated, it cannot be high impedance. Usually allows the selection of each CS restarted or aborted, even by the power-down input, PD, AD7655 in multicircuit applications and is held low in a single until the conversion is complete. The CNVST signal operates AD7655 design. RD is generally used to enable the conversion independently of the CS and RD signals. result on the data bus. In parallel mode, signal A/ allows the B choice of reading either the output of Channel A or Channel B, t 2 whereas in serial mode, signal A/B controls which channel is t 1 output first. CNVST t 15 Figure 22 details the timing when using the RESET input. Note t 14 the current conversion, if any, is aborted and the data bus is A0 high impedance while RESET is high. BUSY t 3 t 9 t 4 RESET t 10 EOC t 13 t 11 t 12 t 6 BUSY t 5 MODE ACQUIRE CONVERT A CONVERT B ACQUIRE CONVERT DATA t t 7 8 BUS Figure 21. Basic Conversion Timing t 8 Although CNVST is a digital signal, it should be designed with CNVST special care with fast, clean edges and levels, and with minimum Figure 22. Reset Timing overshoot and undershoot or ringing. PARALLEL INTERFACE For applications where the SNR is critical, the CNVST signal should have very low jitter. One solution is to use a dedicated The AD7655 is configured to use the parallel interface when oscillator for generation or, at least, to clock it with a CNVST SER/PAR is held low. high frequency low jitter clock, as shown in Figure 17. Master Parallel Interface In impulse mode, conversions can be automatically initiated. If Data can be read continuously by tying and low, thus CS RD is held low when BUSY is low, the AD7655 controls the CNVST requiring minimal microprocessor connections. However, in acquisition phase and automatically initiates a new conversion. this mode the data bus is always driven and cannot be used in By keeping CNVST low, the AD7655 keeps the conversion shared bus applications (unless the device is held in RESET). process running by itself. Note that the analog input has to be Figure 23 details the timing for this mode. settled when BUSY goes low. Also, at power-up, should CNVST CS = RD = 0 be brought low once to initiate the conversion process. In this t 1 mode, the AD7655 can sometimes run slightly faster than the CNVST guaranteed limits of 888 kSPS in impulse mode. This feature does not exist in normal mode. t 16 BUSY DIGITAL INTERFACE t 4 The AD7655 has a versatile digital interface; it can be interfaced t 3 with the host system by using either a serial or parallel interface. EOC t 10 The serial interface is multiplexed on the parallel data bus. The t 17 AD7655 digital interface accommodates either 3 V or 5 V logic DATA PREVIOUS CHANNEL A PREVIOUS CHANNEL B NEW A when the OVDD supply pin of the AD7655 is connected to the BUS OR B OR NEW A OR B host system interface digital supply. Figure 23. Master Parallel Data Timing for Reading (Continuous Read) Rev. B | Page 18 of 28 03536-021 03536-023 03536-022 AD7655 Slave Parallel Interface 8-Bit Interface (Master or Slave) In slave parallel reading mode, the data can be read either after The BYTESWAP pin allows a glueless interface to an 8-bit bus. each conversion, which is during the next acquisition phase, or As shown in Figure 26, the LSB byte is output on D[7:0] and the during the other channel’s conversion, or during the following MSB is output on D[15:8] when BYTESWAP is low. When conversion, as shown in Figure 24 and Figure 25, respectively. BYTESWAP is high, the LSB and MSB bytes are swapped, the When the data is read during the conversion, however, it is LSB is output on D[15:8], and the MSB is output on D[7:0]. By recommended that it is read only during the first half of the connecting BYTESWAP to an address line, the 16-bit data can conversion phase. This avoids any potential feedthrough be read in 2 bytes on either D[15:8] or D[7:0]. between voltage transients on the digital interface and the most critical analog conversion circuitry. CS CS RD RD BYTESWAP BUSY HI-Z HI-Z HIGH BYTE LOW BYTE PINS D[15:8] CURRENT DATA BUS t t t CONVERSION 18 18 19 HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE t t 18 19 Figure 26. 8-Bit Parallel Interface Figure 24. Slave Parallel Data Timing for Reading (Read after Convert) Channel A/B Output CS = 0 t 1 The A/B input controls which channel’s conversion results CNVST, RD (INAx or INBx) are output on the data bus. The function-ality t 12 of A/ is detailed in Figure 27. When high, the data from t B 10 t t 13 11 Channel A is available on the data bus. When low, the data from EOC Channel B is available on the bus. Note that in parallel reading BUSY t 4 mode, Channel A can be read immediately after the end of conversion (EOC), while Channel B is still in its converting t 3 phase. However, in any of the serial reading modes Channel A data is updated only after Channel B conversion. PREVIOUS DATA BUS CONVERSION CS t t 18 19 RD Figure 25. Slave Parallel Data Timing for Reading (Read During Convert) A/B HI-Z HI-Z DATA BUS CHANNEL A CHANNEL B t 18 t 20 B Figure 27. A/ Channel Reading Rev. B | Page 19 of 28 03536-024 03536-025 03536-027 03536-026 AD7655 SERIAL INTERFACE The AD7655 is configured to use the serial interface when the Usually, because the AD7655 is used with a fast throughput, the SER/PAR is held high. The AD7655 outputs 32 bits of data, MSB master read during convert mode is the most recommended serial mode when it can be used. In this mode, the serial clock first, on the SDOUT pin. The order of the channels being output and data toggle at appropriate instants, which minimizes is also controlled by A/ . When high, Channel A is output first; B potential feed through between digital activity and the critical when low, Channel B is output first. This data is synchronized conversion decisions. The SYNC signal goes low after the LSB with the 32 clock pulses provided on the SCLK pin. of each channel has been output. Note that in this mode, the MASTER SERIAL INTERFACE SCLK period changes because the LSBs require more time to settle, and the SCLK is derived from the SAR conversion clock. Internal Clock The AD7655 is configured to generate and provide the serial Note that in master read after convert mode, unlike in other data clock SCLK when the EXT/ pin is held low. The INT modes, the BUSY signal returns low after the 32 bits of data are AD7655 also generates a SYNC signal to indicate to the host pulsed out and not at the end of the conversion phase, which when the serial data is valid. The serial clock SCLK and the results in a longer BUSY width. One advantage of using this SYNC signal can be inverted, if desired, using the INVSCLK mode is that it can accommodate slow digital hosts because the and INVSYNC inputs, respectively. The output data is valid on serial clock can be slowed down by using the DIVSCLK[1:0] both the rising and falling edge of the data clock. In this mode, inputs. Refer to Table 4 for the timing details. the D7/RDC/SDIN input is used to select between reading after conversion (RDC = low) or reading previous conversion results during conversion (RDC = high). Figure 28 and Figure 29 show the detailed timing diagrams of these two modes. Rev. B | Page 20 of 28 AD7655 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 A/B = 1 CS, RD CNVST BUSY t t 35 3 EOC t t t t 10 11 12 13 t 37 t 26 t 36 t 32 SYNC t t 26 t 25 21 t t t 28 27 31 t 33 12 16 17 31 32 SCLK t t 29 22 t 34 CH A CH A CH A CH B CH B CH B SDOUT X D15 D14 D0 D15 D1 D0 t t 23 30 Figure 28. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 INVSCLK = INVSYNC = 0 RDC/SDIN = 1 A/B = 1 CS, RD t 1 CNVST t 3 BUSY t 12 EOC t t 10 13 t 11 t 24 t 32 SYNC t t 21 26 t t 27 28 t 31 t 33 t 22 SCLK 12 16 1 2 16 t 25 t 34 CH B CH B CH A CH A SDOUT CH B D0 X CH A D0 D15 D14 D15 D14 t t 23 30 t 29 Figure 29. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 21 of 28 03536-028 03536-029 AD7655 SLAVE SERIAL INTERFACE An example of the concatenation of two devices is shown in Figure 30. Simultaneous sampling is possible by using a External Clock CNVST common signal. Note that the RDC/SDIN input is The AD7655 is configured to accept an externally supplied latched on the edge of SCLK opposite the one used to shift out serial data clock on the SCLK pin when the EXT/ pin is INT the data on SDOUT. Therefore, the MSB of the upstream held high. In this mode, several methods can be used to read converter follows the LSB of the downstream converter on the the data. The external serial clock is gated by CS. When both CS next SCLK cycle. The SDIN input should be tied either high or and are low, the data can be read after each conversion or RD low on the most upstream converter in the chain. during the following conversion. The external clock can be BUSY either a continuous or discontinuous clock. A discontinuous OUT clock can be either normally high or normally low when BUSY BUSY inactive. Figure 31 and Figure 32 show the detailed timing AD7655 AD7655 diagrams of these methods. #2 (UPSTREAM) #1 (DOWNSTREAM) While the AD7655 is performing a bit decision, it is important DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT that voltage transients do not occur on digital input/output pins CNVST CNVST or degradation of the conversion result could occur. This is CS CS particularly important during the second half of the conversion SCLK SCLK phase of each channel, because the AD7655 provides error SCLK IN correction circuitry that can correct for an improper bit CS IN CNVST IN decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is Figure 30. Two AD7655s in a Daisy-Chain Configuration provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of EOC high. External Clock Data Read (Previous) During Convert Figure 32 shows the detailed timing diagrams of this method. External Discontinuous Clock Data Read After Convert During a conversion, while both CS and RD are low, the result Although the maximum throughput cannot be achieved in this of the previous conversion can be read. The data is shifted out, mode, it is the most recommended of the serial slave modes. MSB first, with 32 clock pulses, and is valid on both the rising Figure 31 shows the detailed timing diagrams of this mode. and falling edges of the clock. The 32 bits have to be read before After a conversion is complete, indicated by BUSY returning the current conversion is completed; otherwise, RDERROR is low, the conversion results can be read while both and CS RD pulsed high and can be used to interrupt the host interface to are low. Data is shifted out from both channels’ MSB first, with prevent incomplete data reading. There is no daisy-chain 32 clock pulses, and is valid on both rising and falling edges of feature in this mode, and RDC/SDIN input should always be the clock. tied either high or low. Among the advantages of using this mode is that conversion To reduce performance degradation due to digital activity, a fast performance is not degraded because there are no voltage discontinuous clock (at least 32 MHz in impulse mode and transients on the digital interface during the conversion process. 40 MHz in normal mode) is recommended to ensure that all of Another advantage is the ability to read the data at any speed up the bits are read during the first half of each conversion phase to 40 MHz, which accommodates both slow digital host (EOC high, t11, t12). interface and the fastest serial reading. It is also possible to begin to read data after conversion and Finally, in this mode only, the AD7655 provides a daisy-chain continue to read the last bits after a new conversion has been feature using the RDC/SDIN (serial data in) input pin for initiated. This allows the use of a slower clock speed such as cascading multiple converters together. This feature is useful for 26 MHz in impulse mode and 30 MHz in normal mode. reducing component count and wiring connections when it is desired, as in isolated multiconverter applications. Rev. B | Page 22 of 28 03536-030 AD7655 EXT/INT = 1 INVSCLK = 0 RD = 0 A/B = 1 CS EOC BUSY t 42 t t 43 44 1 2 3 303132 33 34 SCLK t 38 t 39 CH A CH A CH A X CH A X CH A CH B D1 CH B D0 X SDOUT D15 D14 D13 D15 D14 t 23 t 41 X CH A X CH A X CH B X CH B Y CH A Y CH A X CH A SDIN D15 D14 D1 D0 D15 D14 D13 t 40 Figure 31. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 A/B = 1 CS t 10 CNVST t 12 t t 13 11 EOC BUSY t 3 t 42 t 43 t 44 SCLK 12 3 31 32 t 38 t 39 SDOUT X CH A D15 CH A D14 CH A D13 CH B D1 CH B D0 t 23 Figure 32. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 23 of 28 03536-031 03536-032 AD7655 MICROPROCESSOR INTERFACING The AD7655 is ideally suited for traditional dc measurement to the end of conversion signal (BUSY going low) using an applications supporting a microprocessor and for ac signal interrupt line of the DSP. The SPI on the ADSP-219x is processing applications interfacing to a digital signal processor. configured for master mode—(MSTR) = 1, Clock Polarity bit The AD7655 is designed to interface with either a parallel (CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt 8-bit-wide or 16-bit-wide interface, a general-purpose serial port, Enable (TIMOD) = 00—by writing to the SPI control register or I/O ports on a microcontroller. A variety of external buffers (SPICLTx). To meet all timing requirements, the SPI clock can be used with the AD7655 to prevent digital noise from should be limited to 17 Mbps, which allows it to read an ADC coupling into the ADC. The following section describes the use of result in less than 1 μs. When a higher sampling rate is desired, the AD7655 with an SPI-equipped DSP, the ADSP-219x. use of one of the parallel interface modes is recommended. DVDD SPI INTERFACE (ADSP-219X) AD7655* ADSP-219x* Figure 33 shows an interface diagram between the AD7655 and SER/PAR the SPI1-equipped ADSP-219x. To accommodate the slower EXT/INT speed of the DSP, the AD7655 acts as a slave device and data BUSY PFx must be read after conversion. This mode also allows the daisy- SPIxSEL (PFx) CS chain feature to be used. The convert command can be initiated SDOUT MISOx in response to an internal timer interrupt. The 32-bit output RD SCLK SCKx data is read with two serial peripheral interface (SPI) 16-bit PFx or TFSx INVSCLK CNVST wide accesses. The reading process can be initiated in response *ADDITIONAL PINS OMITTED FOR CLARITY Figure 33. Interfacing the AD7655 to SPI Interface Rev. B | Page 24 of 28 03536-033 AD7655 APPLICATION HINTS LAYOUT placed on each power supply pin—AVDD, DVDD, and OVDD—close to, and ideally right up against these pins and The AD7655 has very good immunity to noise on the power their corresponding ground pins. Additionally, low ESR 10 μF supplies. However, care should still be taken with regard to capacitors should be located near the ADC to further reduce grounding layout. low frequency ripple. The printed circuit board that houses the AD7655 should be The DVDD supply of the AD7655 can be a separate supply or designed so the analog and digital sections are separated and can come from the analog supply AVDD or the digital interface confined to certain areas of the board. This facilitates the use of supply OVDD. When the system digital supply is noisy or when ground planes that can be separated easily. Digital and analog fast switching digital signals are present, if no separate supply is ground planes should be joined in only one place, preferably available, the user should connect DVDD to AVDD through an underneath the AD7655, or as close as possible to the AD7655. RC filter (see Figure 17) and the system supply to OVDD and If the AD7655 is in a system where multiple devices require the remaining digital circuitry. When DVDD is powered from analog-to-digital ground connections, the connection should the system supply, it is useful to insert a bead to further reduce still be made at one point only, a star ground point that should high frequency spikes. be established as close as possible to the AD7655. The AD7655 has five ground pins: INGND, REFGND, AGND, Avoid unning digital lines under the device because these DGND, and OGND. INGND is used to sense the analog input couple noise onto the die. The analog ground plane should be signal. REFGND senses the reference voltage and, because it allowed to run under the AD7655 to avoid noise coupling. Fast carries pulsed currents, should be a low impedance return to switching signals such as or clocks should be shielded CNVST the reference. AGND is the ground to which most internal with digital ground to avoid radiating noise to other sections of ADC analog signals are referenced; it must be connected with the board and should never run near analog signal paths. the least resistance to the analog ground plane. DGND must be Crossover of digital and analog signals should be avoided. tied to the analog or digital ground plane depending on the Traces on different but close layers of the board should run at configuration. OGND is connected to the digital system right angles to each other. This reduces the effect of crosstalk ground. through the board. EVALUATING THE AD7655 PERFORMANCE The power supply lines to the AD7655 should use as large a A recommended layout for the AD7655 is outlined in the trace as possible to provide low impedance paths and reduce the EVAL-AD7655CB evaluation board documentation. The effect of glitches on the power supply lines. Good decoupling is evaluation board package includes a fully assembled and tested also important to lower the supply impedance presented to the evaluation board, documentation, and software for controlling AD7655 and to reduce the magnitude of the supply spikes. the board from a PC via the EVAL-CONTROL-BRD3. Decoupling ceramic capacitors, typically 100 nF, should be Rev. B | Page 25 of 28 PAD AD7655 OUTLINE DIMENSIONS 0.75 9.00 1.60 0.60 BSC SQ MAX 0.45 48 37 1 36 PIN 1 7.00 TOP VIEW BSC SQ 1.45 0.20 (PINS DOWN) 1.40 0.09 1.35 7° 3.5° 25 12 0.15 0° 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 0.40 12 24 13 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO GND. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP REQUIRED TO MEET THE 0.85 0.05 MAX ELECTRICAL PERFORMANCES 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 35. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters Rev. B | Page 26 of 28 AD7655 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7655ACP −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD7655ACPRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7655ACPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7655ACPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD7655AST −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 AD7655ASTRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7655ASTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7655ASTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7655CB Evaluation Board 3 EVAL-CONTROL-BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in CB designators. Rev. B | Page 27 of 28 AD7655 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03536-0-9/05(B) TTTT Rev. B | Page 28 of 28