ANALOG DEVICES AD7654

® 16-Bit, 500 kSPS PulSAR Dual, 2-Channel, Simultaneous Sampling ADC AD7654 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual, 16-bit, 2-channel simultaneous sampling ADC AVDD AGND REFGND REFx DVDD DGND 16-bit resolution with no missing codes TRACK/HOLD Throughput: OVDD ×2 INA1 SERIAL 500 kSPS (normal mode) OGND PORT INAN MUX 16 444 kSPS (impulse mode) D[15:0] INA2 INL: ±3.5 LSB max (±0.0053% of full scale) SWITCHED MUX A0 SER/PAR CAP DAC INB1 SNR: 89 dB typ @ 100 kHz EOC INBN MUX THD: −100 dB @ +100 kHz BUSY INB2 CLOCK PARALLEL CS Analog input voltage range: 0 V to 5 V PD INTERFACE CONTROL LOGIC AND RD No pipeline delay RESET CALIBRATION CIRCUITRY A/B Parallel and serial 5 V/3 V interface AD7654 BYTESWAP SPI®/QSPI™/MICROWIRE™/DSP compatible IMPULSE CNVST Single 5 V supply operation Power dissipation: Figure 1. 120 mW typical 2.6 mW @ 10 kSPS Packages: Table 1. PulSAR Selection 48-lead low profile quad flat package (LQFP) Type/kSPS 100 to 250 500 to 570 800 to 1000 >1000 48-lead lead frame chip scale package (LFCSP) Pseudo AD7660/ AD7650/ AD7667 Low cost Differential AD7661 AD7652 AD7653 AD7664/ AD7666 APPLICATIONS True Bipolar AD7663 AD7665 AD7671 AC motor control True Differential AD7675 AD7676 AD7677 AD7621 3-phase power control AD7623 4-channel data acquisition 18-Bit AD7678 AD7679 AD7674 AD7641 Uninterrupted power supplies Multichannel/ AD7654 AD7655 Communications Simultaneous GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7654 is a low cost, simultaneous sampling, dual- 1. Simultaneous Sampling. channel, 16-bit, charge redistribution SAR, analog-to-digital The AD7654 features two sample-and-hold circuits that converter that operates from a single 5 V power supply. It allow simultaneous sampling. It provides inputs for four contains two low noise, wide bandwidth, track-and-hold channels. amplifiers that allow simultaneous sampling, a high speed 2. Fast Throughput. 16-bit sampling ADC, an internal conversion clock, error The AD7654 is a 500 kSPS, charge redistribution, 16-bit correction circuits, and both serial and parallel system interface SAR ADC with internal error correction circuitry. ports. Each track-and-hold has a multiplexer in front to provide 3. Superior INL and No Missing Codes. a 4-channel input ADC. The A0 multiplexer control input The AD7654 has a maximum integral nonlinearity of allows the choice of simultaneously sampling input pairs 3.5 LSB with no missing 16-bit codes. INA1/INB1 (A0 = low) or INA2/INB2 (A0 = high). The part 4. Single-Supply Operation. features a very high sampling rate mode (normal) and, for low The AD7654 operates from a single 5 V supply. In impulse power applications, a reduced power mode (impulse) where the mode, its power dissipation decreases with throughput. power is scaled with the throughput. Operation is specified 5. Serial or Parallel Interface. from −40°C to +85°C. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03057-001 AD7654 TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Voltage Reference Input ............................................................ 17 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 17 General Description ......................................................................... 1 Power Dissipation....................................................................... 17 Product Highlights ........................................................................... 1 Conversion Control ................................................................... 18 Specifications..................................................................................... 3 Digital Interface.......................................................................... 18 Timing Specifications .................................................................. 5 Parallel Interface......................................................................... 18 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 20 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 20 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 22 Terminology .................................................................................... 11 Microprocessor Interfacing....................................................... 24 Typical Performance Characteristics ........................................... 12 SPI Interface (ADSP-219x) ....................................................... 24 Application Information................................................................ 14 Application Hints ........................................................................... 25 Circuit Information.................................................................... 14 Layout .......................................................................................... 25 Modes of Operation ................................................................... 14 Evaluating the AD7654 Performance ...................................... 25 Transfer Functions...................................................................... 14 Outline Dimensions....................................................................... 26 Typical Connection Diagram ................................................... 16 Ordering Guide .......................................................................... 27 Analog Inputs.............................................................................. 16 Input Channel Multiplexer........................................................ 16 REVISION HISTORY 11/05—Rev. A to Rev. B 11/04—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Changes to Figure 7........................................................................ 12 Changes to Timing Specifications.................................................. 5 Changes to Figure 18...................................................................... 15 Changes to Figure 16...................................................................... 13 Changes to Figure 19...................................................................... 16 Changes to Figure 18...................................................................... 15 Changes to Voltage Reference Input Section .............................. 17 Added Table 8.................................................................................. 17 Changes to Conversion Control Section..................................... 18 Changes to Figure 24...................................................................... 19 Changes to Digital Interface Section ........................................... 18 Changes to Figure 29...................................................................... 21 Updated Outline Dimensions...................................................... 25 Updated Outline Dimensions ....................................................... 26 11/02—Revision 0: Initial Version Changes to Ordering Guide .......................................................... 26 Rev. B | Page 2 of 28 AD7654 SPECIFICATIONS AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V – V 0 2 V V INx INxN REF Common-Mode Input Voltage V −0.1 +0.5 V INxN Analog Input CMRR f = 100 kHz 55 dB IN Input Current 500 kSPS throughput 45 μA 1 Input Impedance THROUGHPUT SPEED Complete Cycle In normal mode 2 μs Throughput Rate In normal mode 0 500 kSPS Complete Cycle In impulse mode 2.25 μs Throughput Rate In impulse mode 0 444 kSPS DC ACCURACY 2 3 Integral Linearity Error −3.5 +3.5 LSB No Missing Codes 16 Bits Transition Noise 0.7 LSB 4 Full-Scale Error TMIN to TMAX ±0.25 ±0.5 % of FSR 4 Full-Scale Error Drift ±2 ppm/°C 4 Unipolar Zero Error TMIN to TMAX ±0.25 % of FSR 4 Unipolar Zero Error Drift ±0.8 ppm/°C Power Supply Sensitivity AVDD = 5 V ±5% 0.8 LSB AC ACCURACY 5 Signal-to-Noise f = 20 kHz 88 90 dB IN f = 100 kHz 89 dB IN Spurious-Free Dynamic Range fIN = 100 kHz 105 dB Total Harmonic Distortion fIN = 100 kHz −100 dB Signal-to-Noise and Distortion fIN = 20 kHz 87.5 90 dB f = 100 kHz 88.5 dB IN f = 100 kHz, −60 dB Input 30 dB IN Channel-to-Channel Isolation f = 100 kHz −92 dB IN −3 dB Input Bandwidth 10 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Delay Matching 30 ps Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns REFERENCE External Reference Voltage Range 2.3 2.5 AVDD/2 V External Reference Current Drain 500 kSPS throughput 180 μA DIGITAL INPUTS Logic Levels V −0.3 +0.8 V IL V +2.0 DVDD + 0.3 V IH I −1 +1 μA IL IIH −1 +1 μA Rev. B | Page 3 of 28 AD7654 Parameter Conditions Min Typ Max Unit DIGITAL OUTPUTS 6 Data Format 7 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK V I = −500 μA OVDD − 0.2 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 8 OVDD 2.7 5.25 V 9 Operating Current 500 kSPS throughput AVDD 15.5 mA DVDD 8.5 mA OVDD 100 μA 9 Power Dissipation 500 kSPS throughput 120 135 mW 10 10 kSPS throughput 2.6 mW 10 444 kSPS throughput 114 125 mW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. 3 LSB means least significant bit. Within the 0 V to 5 V input range, one LSB is 76.294 μV. 4 See the Terminology section. These specifications do not include the error contribution from the external reference. 5 All specifications in dB are referred to as full-scale input, FS; tested with an input signal at 0.5 dB below full scale unless otherwise specified. 6 Parallel or serial 16-bit. 7 Conversion results are available immediately after completed conversion. 8 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 9 In normal mode; tested in parallel reading mode. 10 In impulse mode; tested in parallel reading mode. 11 Consult sales for extended temperature range. Rev. B | Page 4 of 28 AD7654 TIMING SPECIFICATIONS AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 22 and Figure 23) Convert Pulse Width t1 5 ns Time Between Conversions (Normal Mode/Impulse Mode) t2 2/2.25 μs CNVST Low to BUSY High Delay t 32 ns 3 BUSY High All Modes Except in Master Serial Read After Convert Mode (Normal Mode/Impulse Mode) t4 1.75/2 μs Aperture Delay t5 2 ns End of Conversions to BUSY Low Delay t6 10 ns Conversion Time (Normal Mode/Impulse Mode) t 1.75/2 μs 7 Acquisition Time t 250 ns 8 RESET Pulse Width t9 10 ns CNVST Low to EOC High Delay t10 30 ns EOC High for Channel A Conversion (Normal Mode/Impulse Mode) t 1/1.25 μs 11 EOC Low after Channel A Conversion t 45 ns 12 t 0.75 μs EOC High for Channel B Conversion 13 Channel Selection Setup Time t14 250 ns Channel Selection Hold Time t15 30 ns PARALLEL INTERFACE MODES (See Figure 24 to Figure 28) CNVST Low to DATA Valid Delay t16 1.75/2 μs DATA Valid to BUSY Low Delay t17 14 ns Bus Access Request to DATA Valid t 40 ns 18 Bus Relinquish Time t 5 15 ns 19 t 40 ns A/B Low to Data Valid Delay 20 MASTER SERIAL INTERFACE MODES (see Figure 29 and Figure 30) CS Low to SYNC Valid Delay t 10 ns 21 1 t 10 ns CS Low to Internal SCLK Valid Delay 22 CS Low to SDOUT Delay t23 10 ns CNVST Low to SYNC Delay (Read During Convert) (Normal Mode/Impulse Mode) t24 250/500 ns SYNC Asserted to SCLK First Edge Delay t 3 ns 25 2 Internal SCK Period t 23 40 ns 26 2 Internal SCLK High t27 12 ns 2 Internal SCLK Low t28 7 ns 2 SDOUT Valid Setup Time t29 4 ns 2 SDOUT Valid Hold Time t 2 ns 30 2 SCLK Last Edge to SYNC Delay t 1 ns 31 CS High to SYNC HI-Z t 10 ns 32 CS High to Internal SCLK HI-Z t33 10 ns CS High to SDOUT HI-Z t34 10 ns 2 BUSY High in Master Serial Read After Convert t35 See Table 4 CNVST Low to SYNC Asserted Delay (Normal Mode/Impulse Mode) t 0.75/1 μs 36 SYNC Deasserted to BUSY Low Delay t37 25 ns Rev. B | Page 5 of 28 AD7654 Parameter Symbol Min Typ Max Unit SLAVE SERIAL INTERFACE MODES (see Figure 32 and Figure 33) External SCLK Setup Time t38 5 ns External SCLK Active Edge to SDOUT Delay t39 3 18 ns SDIN Setup Time t 5 ns 40 SDIN Hold Time t 5 ns 41 External SCLK Period t 25 ns 42 External SCLK High t43 10 ns External SCLK Low t44 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum. 2 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert 0 0 1 1 DIVSCLK[1] DIVSCLK[0] Symbol 0 1 0 1 Unit t 3 17 17 17 ns 25 SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum t26 25 50 100 200 ns Internal SCLK Period Typical t 40 70 140 280 ns 26 Internal SCLK High Minimum t 12 22 50 100 ns 27 Internal SCLK Low Minimum t28 7 21 49 99 ns SDOUT Valid Setup Time Minimum t29 4 18 18 18 ns SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t 1 3 30 80 ns 31 Busy High Width Maximum (Normal) t 3.25 4.25 6.25 10.75 μs 35 Busy High Width Maximum (Impulse) t 3.5 4.5 6.5 11 μs 35 Rev. B | Page 6 of 28 AD7654 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Values may cause permanent damage to the device. This is a stress Analog Inputs rating only; functional operation of the device at these or any 1 1 INAx , INBx , REFx, INxN, AVDD + 0.3 V to other conditions above those indicated in the operational REFGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V I 1.6mA OL AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD −0.3 V to +7 V TO OUTPUT 1.4V Digital Inputs −0.3 V to DVDD + 0.3 V PIN C L 2 Internal Power Dissipation 700 mW 60pF* 3 Internal Power Dissipation 2.5 W I 500µA OH Junction Temperature 150°C Storage Temperature Range −65°C to +150°C *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD Lead Temperature Range C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L (Soldering 10 sec) 300°C Figure 2. Load Circuit for Digital Interface Timing 1 (SDOUT, SYNC, SCLK Outputs, CL = 10 pF) See Analog Inputs section. 2 Specification is for device in free air: 48-lead LQFP: θ = 91°C/W, θ = 30°C/W. JA JC 3 Specification is for device in free air: 48-lead LFCSP; θJA = 26°C/W. 2V 0.8V t DELAY t DELAY 2V 2V 0.8V 0.8V Figure 3. Voltage Reference Levels for Timing ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 28 03057-002 03057-003 AD7654 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 36 AGND DVDD PIN 1 AVDD 2 35 CNVST A0 3 34 PD 4 33 BYTESWAP RESET A/B 5 32 CS AD7654 6 31 DGND RD TOP VIEW 7 (Not to Scale) 30 IMPULSE EOC 8 SER/PAR 29 BUSY D0 9 28 D15 D1 10 27 D14 D2/DIVSCLK[0] 11 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 47, 48 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3 A0 DI Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted. 4 BYTESWAP DI Parallel Mode Selection (8 bit, 16 bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 A/B DI Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel B. When LOW, Channel B is output first followed by Channel A. 6, 20 DGND P Digital Power Ground. 7 IMPULSE DI Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after convert mode, these inputs, part of the serial port, are used to slow down if desired the internal serial clock that clocks the data output. In the other serial modes, these inputs are not used. 13 D[4] DI/O When SER/PARis LOW, this output is used as Bit 4 of the parallel port data output bus. or EXT/INT When SER/PARis HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. Rev. B | Page 8 of 28 AGND D4/EXT/INT D5/INVSYNC AGND INA1 D6/INVSCLK D7/RDC/SDIN INAN OGND INA2 OVDD REFA DVDD REFB DGND INB2 D8/SDOUT INBN D9/SCLK INB1 D10/SYNC REFGND D11/RDERROR REF 03057-004 AD7654 1 Pin No. Mnemonic Type Description 15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. 16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19, 36 DVDD P Digital Power. Nominally at 5 V. 21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel port data output bus. or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7654 provides the two conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH. 24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In Slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25 to 28 D[12:15] DO Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high impedance. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two conversions are complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. 30 EOC DO End of Convert Output. Goes LOW at each channel conversion. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7654. Current conversion if any is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Rev. B | Page 9 of 28 AD7654 1 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 37 REF AI This input pin is used to provide a reference to the converter. 38 REFGND AI Reference Input Analog Ground. 39, 41 INB1, INB2 AI Channel B Analog Inputs. 40, 45 INBN, INAN AI Analog Inputs Ground Senses. Allow to sense each channel ground independently. 42, 43 REFB, REFA AI These inputs are the references applied to Channel A and Channel B, respectively. 44, 46 INA2, INA1 AI Channel A Analog Inputs. 1 AI = analog input; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Rev. B | Page 10 of 28 AD7654 TERMINOLOGY Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal-to-Noise and Distortion Ratio (SINAD) 1½ LSB beyond the last code transition. The deviation is SINAD is the ratio of the rms value of the actual input signal to measured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, including harmonics but excluding dc. The value for In an ideal ADC, code transitions are 1 LSB apart. Differential SINAD is expressed in decibels. nonlinearity is the maximum deviation from this ideal value. It Spurious-Free Dynamic Range (SFDR) is often specified in terms of resolution for which no missing The difference, in decibels, between the rms amplitude of the codes are guaranteed. input signal and the peak spurious signal. Full-Scale Error Effective Number of Bits (ENOB) The last transition (from 111. . .10 to 111. . .11) should occur ENOB is a measurement of the resolution with a sine wave for an analog voltage 1½ LSB below the nominal full scale input. It is related to SINAD and expressed in bits by (4.999886 V for the 0 V to 5 V range). The full-scale error is the deviation of the actual level of the last transition from the ENOB = ((SINADdB − 1.76)/6.02) ideal level. and is expressed in bits. Unipolar Zero Error Aperture Delay The first transition should occur at a level ½ LSB above analog Aperture delay is a measure of acquisition performance and is ground (76.29 μV for the 0 V to 5 V range). The unipolar zero measured from the falling edge of the CNVST input to when error is the deviation of the actual transition from that point. the input signals are held for a conversion. Signal-to-Noise Ratio (SNR) Transient Response SNR is the ratio of the rms value of the actual input signal to the The time required for the AD7654 to achieve its rated accuracy rms sum of all other spectral components below the Nyquist after a full-scale step function is applied to its input. frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. B | Page 11 of 28 AD7654 TYPICAL PERFORMANCE CHARACTERISTICS 5 3 4 2 3 2 1 1 0 0 –1 –1 –2 –3 –2 –4 –5 –3 0 16384 32768 49152 65535 0 16384 32768 49152 65535 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 10000 8000 9366 7288 7220 9000 7000 8000 6000 7000 5000 6000 4000 5000 4000 3000 3411 3299 3000 2000 2000 953 903 1000 1000 176 0 0 14 6 0 0 0 0 132 00 0 0 7FBF 7FC0 7FC1 7FC2 7FC3 7FC4 7FC5 7FC6 7FC7 7FC8 7FBF 7FC0 7FC1 7FC2 7FC3 7FC4 7FC5 7FC6 7FC7 CODE IN HEX CODE IN HEX Figure 6. Histogram of 16,384 Conversions of a DC Input at the Figure 9. Histogram of 16,384 Conversions of a DC Input at the Code Transition Code Center 0 –98 96 8192 POINT FFT f = 500kHz –20 S f = 100kHz, –0.5dB IN SNR = 89.9dB –40 SINAD = 89.4dB 93 –100 THD = –99.3dB THD –60 –80 90 –102 SNR –100 –120 –104 87 –140 –160 –106 84 0 25 50 75 100 125 150 175 200 225 250 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 7. FFT Plot Figure 10. SNR, THD vs. Temperature Rev. B | Page 12 of 28 AMPLITUDE (dB of Full Scale) COUNTS INL (LSB) 03057-007 03057-006 03057-005 COUNTS SNR (dB) DNL (LSB) THD (dB) 03057-010 03057-009 03057-008 AD7654 100 16.0 10 8 95 15.5 6 SNR FULL-SCALE ERROR 4 90 15.0 SINAD 2 85 14.5 0 ENOB –2 ZERO ERROR 80 14.0 –4 –6 75 13.5 –8 70 13.0 –10 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 11. SNR, SINAD, and ENOB vs. Frequency Figure 14. Full-Scale Error and Zero Error vs. Temperature 100 92 NORMAL AVDD 10 NORMAL DVDD SNR 1 90 IMPULSE AVDD IMPULSE DVDD 0.1 SINAD 0.01 88 0.001 OVDD 2.7V 0.0001 86 1 10 –60 –50 –40 –30 –20 –10 0 100 1000 INPUT LEVEL (dB) SAMPLING RATE (kSPS) Figure 12. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 15. Operating Currents vs. Sample Rate –60 115 50 –65 110 OVDD = 2.7V @ 85°C SFDR –70 105 40 OVDD = 2.7V @ 25°C –75 100 –80 95 OVDD = 5V @ 85°C 30 –85 90 CROSSTALK B TO A –90 85 OVDD = 5V @ 25°C 20 –95 80 CROSSTALK A TO B THIRD HARMONIC –100 THD 75 10 –105 70 SECOND –110 65 HARMONIC –115 60 0 1 10 100 1000 0 50 100 150 200 C (pF) FREQUENCY (kHz) L Figure 13. THD, Harmonics, Crosstalk, and SFDR vs. Frequency Figure 16. Typical Delay vs. Load Capacitance C L Rev. B | Page 13 of 28 SNR, SINAD (dB) SNR, SINAD (dB) THD, HARMONICS, CROSSTALK (dB) SFDR (dB) 03057-013 03057-012 03057-011 ENOB (Bits) t DELAY (ns) OPERATING CURRENTS (mA) LSB 18 03057-015 03057-014 03057-016 AD7654 APPLICATION INFORMATION CIRCUIT INFORMATION TRANSFER FUNCTIONS The AD7654 is a very fast, low power, single-supply, precise, The AD7654 data format is straight binary. The ideal transfer simultaneous sampling 16-bit ADC. characteristic for the AD7654 is shown in Figure 17 and Table 7. The LSB size is 2*V /65536, which is about 76.3 μV. REF The AD7654 provides the user with two on-chip, track-and- hold, successive approximation ADCs that do not exhibit any pipeline or latency, making it ideal for multiple multiplexed 111...111 111...110 channel applications. The AD7654 can also be used as a 111...101 4-channel ADC with two pairs simultaneously sampled. The AD7654 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP or tiny 48-lead LFCSP that combines space savings and allows flexible configurations as either a serial or 000...010 parallel interface. The AD7654 is pin-to-pin compatible with 000...001 PulSAR ADCs. 000...000 –FS –FS + 1 LSB +FS – 1 LSB –FS + 0.5 LSB MODES OF OPERATION +FS – 1.5 LSB ANALOG INPUT The AD7654 features two modes of operation, normal and impulse. Each of these modes is more suitable for specific Figure 17. ADC Ideal Transfer Function applications. Table 7. Output Codes and Ideal Input Voltages Normal mode is the fastest mode (500 kSPS). Except when it is Description Analog Input Digital Output Code powered down (PD = HIGH), the power dissipation is almost VREF = 2.5 V independent of the sampling rate. 1 FSR − 1 LSB 4.999924 V 0xFFFF Impulse mode, the lowest power dissipation mode, allows FSR − 2 LSB 4.999847 V 0xFFFE power saving between conversions. The maximum Midscale + 1 LSB 2.500076 V 0x8001 throughput in this mode is 444 kSPS. When operating at Midscale 2.5 V 0x8000 10 kSPS, for example, it typically consumes only 2.6 mW. This Midscale − 1 LSB 2.499924 V 0x7FFF feature makes the AD7654 ideal for battery-powered −FSR + 1 LSB −76.29 μV 0x0001 2 applications. −FSR 0 V 0x0000 1 This is also the code for overrange analog input (V – V above 2 × (V − V )). INx INxN REF REFGND 2 This is also the code for underrange analog input (VINx below VINxN). Rev. B | Page 14 of 28 ADC CODE (Straight Binary) 03057-017 AD7654 DVDD ANALOG 30Ω DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) NOTE 6 + + + 100nF 10µF 10µF 100nF 100nF 10µF AD780 AVDD AGND DGND OVDD OGND DVDD SERIAL PORT REF 2.5V REF SCLK REF A 1MΩ NOTE 1 C + REF REF B 50kΩ 1µF NOTE 1 100nF NOTE 2 SDOUT REFGND NOTE 3 50Ω BUSY µC/µP/ 50Ω – 10Ω DSP CNVST D NOTE 4 U1 INA1 ANALOG INPUT A1 + 2.7nF NOTE 7 C C NOTE 5 AD7654 A0 SER/PAR DVDD A/B 50Ω CS RD – 10Ω NOTE 4 U2 INA2 BYTESWAP CLOCK ANALOG INPUT A2 + RESET 2.7nF CC PD NOTE 5 INAN 50Ω – 10Ω NOTE 4 U3 INB1 ANALOG INPUT B1 + 2.7nF C C NOTE 5 50Ω – 10Ω NOTE 4 U4 INB2 ANALOG INPUT B2 + 2.7nF C C NOTE 5 INBN NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C IS 47µF. SEE VOLTAGE REFERENCE INPUT SECTION. REF 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. SEE ANALOG INPUTS SECTION. 6. OPTIONAL, SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION. Figure 18. Typical Connection Diagram (Serial Interface) Rev. B | Page 15 of 28 03057-018 AD7654 TYPICAL CONNECTION DIAGRAM that can be tolerated. The THD degrades as the source Figure 18 shows a typical connection diagram for the AD7654. impedance increases. Different circuitry shown on this diagram is optional and is discussed in the following sections. INPUT CHANNEL MULTIPLEXER ANALOG INPUTS The AD7654 allows the choice of simultaneously sampling the inputs pairs INA1/INB1 or INA2/INB2 with the A0 multiplexer Figure 19 shows a simplified analog input section of the input. When A0 is low, the input pairs INA1/INB1 are selected, AD7654. AVDD and when A0 is high, the input pairs INA2/INB2 are selected. Note that INAx is always converted before INBx regardless of the state of the digital interface channel selection A/ pin. Also, B A0 = L R A INA1 note that the channel selection control A0 should not be A0 = H INA2 C S changed during the acquisition phase of the converter. Refer to INAN the Conversion Control section and Figure 22 for timing details. INBN A0 = L C S INB1 DRIVER AMPLIFIER CHOICE A0 = H INB2 R B Although the AD7654 is easy to drive, the driver amplifier needs to meet at least the following requirements: AGND A0 • For multichannel, multiplexed applications, the driver Figure 19. Simplified Analog Input amplifier and the AD7654 analog input circuit together The diodes shown in Figure 19 provide ESD protection for the must be able to settle for a full-scale step of the capacitor inputs. Care must be taken to ensure that the analog input array at a 16-bit level (0.0015%). In the amplifier’s data signal never exceeds the absolute ratings on these inputs. This sheet, the settling at 0.1% or 0.01% is more commonly causes these diodes to become forward biased and start specified. It could significantly differ from the settling time conducting current. These diodes can handle a forward-biased at a 16-bit level and, therefore, it should be verified prior to current of 120 mA maximum. This condition could eventually the driver selection. occur when the input buffers (U1) or (U2) supplies are different • The noise generated by the driver amplifier needs to be kept from AVDD. In such a case, an input buffer with a short-circuit as low as possible to preserve the SNR and transition noise current limitation can be used to protect the part. performance of the AD7654. The noise coming from the driver is filtered by the AD7654 analog input circuit one- This analog input structure allows the sampling of the pole low-pass filter made by R , R , and C . The SNR differential signal between INx and INxN. Unlike other A B S degradation due to the amplifier is converters, the INxN is sampled at the same time as the INx ⎛ ⎞ input. By using these differential inputs, small signals common ⎜ ⎟ 56 ⎜ ⎟ to both inputs are rejected. SNR = 20 log LOSS ⎜ ⎟ π 2 2 ⎜ 56 + f (Ne ) ⎟ −3dB N During the acquisition phase, for ac signals, the AD7654 2 ⎝ ⎠ behaves like a one-pole RC filter consisting of the equivalent where: resistance R , R , and C . The resistors R and R are typically A B S A B f is the –3 dB input bandwidth in MHz of the AD7654 –3 dB 500 Ω and are a lumped component made up of some serial (10 MHz) or the cutoff frequency of the input filter, if resistors and the on resistance of the switches. The capacitor C S any is used. is typically 32 pF and is mainly the ADC sampling capacitor. N is the noise factor of the amplifier (1 if in buffer This one-pole filter with a typical −3 dB cutoff frequency of configuration). 10 MHz reduces undesirable aliasing effects and limits the noise e is the equivalent input noise voltage of the N coming from the inputs. op amp in nV/√Hz. Because the input impedance of the AD7654 is very high, the For instance, a driver like the AD8021 with an equivalent AD7654 can be driven directly by a low impedance source input noise of 2 nV/√Hz, configured as a buffer, and thus without gain error. To further improve the noise filtering of the with a noise gain of +1, degrades the SNR by only 0.06 dB AD7654 analog input circuit, an external one-pole RC filter with the filter in Figure 18, and by 0.10 dB without. between the amplifier output and the ADC input, as shown in Figure 18, can be used. However, the source impedance has to • The driver needs to have a THD performance suitable to be kept low because it affects the ac performance, especially the that of the AD7654. total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) Rev. B | Page 16 of 28 03057-019 AD7654 The AD8021 meets these requirements and is usually appro- Care should be taken with the reference temperature coefficient priate for almost all applications. The AD8021 needs an of the voltage reference, which directly affects the full-scale external compensation capacitor of 10 pF. This capacitor should accuracy if this parameter is applicable. For instance, a have good linearity as an NPO ceramic or mica type. The 15 ppm/°C tempco of the reference changes the full-scale AD8022 could be used where a dual version is needed and a accuracy by 1 LSB/°C. gain of +1 is used. POWER SUPPLY The AD829 is another alternative where high frequency The AD7654 uses three sets of power supply pins: an analog (above 100 kHz) performance is not required. In a gain of +1, 5 V supply AVDD, a digital 5 V core supply DVDD, and a it requires an 82 pF compensation capacitor. digital input/output interface supply OVDD. The OVDD The AD8610 is another option where low bias current is needed supply allows direct interface with any logic working between in low frequency applications. 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a Refer to Table 8 for some recommended op amps. simple RC filter from the analog supply, as shown in Figure 18. The AD7654 is independent of power supply sequencing, once Table 8. Recommended Driver Amplifiers OVDD does not exceed DVDD by more than 0.3 V, and thus Amplifier Typical Application free from supply voltage induced latch-up. Additionally, it is ADA4841 Very low noise, low distortion, low power, low frequency very insensitive to power supply variations over a wide AD829 Very low noise, low frequency frequency range, as shown in Figure 20. AD8021 Very low noise, high frequency 70 AD8022 Very low noise, high frequency, dual AD8655/AD8656 Low noise, 5 V single supply, low power, 65 low frequency, single/dual AD8610/AD8620 Low bias current, low frequency, 60 single/dual 55 VOLTAGE REFERENCE INPUT 50 The AD7654 requires an external 2.5 V reference. The reference input should be applied to REF, REFA, and REFB. The voltage 45 reference input REF of the AD7654 has a dynamic input impedance; it should therefore be driven by a low impedance 40 source with an efficient decoupling. This decoupling depends 10 100 1000 10000 1 FREQUENCY (kHz) on the choice of the voltage reference but usually consists of a 1 μF ceramic capacitor and a low ESR tantalum capacitor Figure 20. PSRR vs. Frequency connected to the REFA, REFB, and REFGND inputs with minimum parasitic inductance. A value of 47 μF is an appro- POWER DISSIPATION priate value for the tantalum capacitor when using one of the In impulse mode, the AD7654 automatically reduces its power recommended reference voltages: consumption at the end of each conversion phase. During the • The low noise, low temperature drift AD780, AD361, acquisition phase, the operating currents are very low, which ADR421, and ADR431 voltage reference. allows significant power savings when the conversion rate is reduced, as shown in Figure 21. This feature makes the AD7654 • The low cost AD1582 voltage reference. ideal for very low power battery applications. For applications using multiple AD7654s with one voltage Note that the digital interface remains active even during the reference source, it is recommended that the reference source acquisition phase. To reduce the operating digital supply drives each ADC in a star configuration with individual currents even further, the digital inputs need to be driven close decoupling placed as close as possible to the REF/REFGND to the power rails (that is, DVDD and DGND), and OVDD inputs. Also, it is recommended that a buffer, such as the should not exceed DVDD by more than 0.3 V. AD8031/AD8032, be used in this configuration. Rev. B | Page 17 of 28 PSRR (dB) 03057-020 AD7654 1000 By keeping low, the AD7654 keeps the conversion CNVST process running by itself. Note that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should NORMAL 100 be brought low once to initiate the conversion process. In this mode, the AD7654 could sometimes run slightly faster than the IMPULSE guaranteed limits of 444 kSPS in impulse mode. This feature 10 does not exist in normal mode. DIGITAL INTERFACE 1 The AD7654 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The 0.1 1 10 100 1000 AD7654 digital interface accommodates either 3 V or 5 V logic SAMPLING RATE (kSPS) by simply connecting the OVDD supply pin of the AD7654 to the host system interface digital supply. Figure 21. Power Dissipation vs. Sample Rate The two signals and control the interface. When at least CS RD CONVERSION CONTROL one of these signals is high, the interface outputs are in high Figure 22 shows the detailed timing diagrams of the impedance. Usually, CS allows the selection of each AD7654 conversion process. The AD7654 is controlled by the signal in multicircuit applications and is held low in a single AD7654 , which initiates conversion. Once initiated, it cannot be CNVST design. is generally used to enable the conversion result on RD restarted or aborted, even by the power-down input, PD, until the data bus. In parallel mode, signal A/B allows the choice of the conversion is complete. The CNVST signal operates reading either the output of Channel A or Channel B, whereas independently of the CS and RD signals. in serial mode, signal A/ controls which channel is output first. B t 2 t Figure 23 details the timing when using the RESET input. Note 1 the current conversion, if any, is aborted and the data bus is CNVST high impedance while RESET is high. t 15 t 14 t A0 9 RESET BUSY t 3 t 4 BUSY t 10 EOC t t 13 11 t 12 t 6 DATA t 5 BUS MODE CONVERT A CONVERT ACQUIRE CONVERT B ACQUIRE t 8 t t 7 8 CNVST Figure 22. Basic Conversion Timing Figure 23. Reset Timing Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels, and with minimum PARALLEL INTERFACE overshoot and undershoot or ringing. The AD7654 is configured to use the parallel interface when SER/ is held low. PAR For applications where the SNR is critical, the CNVST signal should have very low jitter. Some solutions to achieve this are to Master Parallel Interface use a dedicated oscillator for generation or, at least, to CNVST Data can be read continuously by tying and low, thus CS RD clock it with a high frequency, low jitter clock, as shown in requiring minimal microprocessor connections. However, in Figure 18. this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in RESET). In impulse mode, conversions can be automatically initiated. If Figure 24 details the timing for this mode. is held low when BUSY is low, the AD7654 controls the CNVST acquisition phase and automatically initiates a new conversion. Rev. B | Page 18 of 28 POWER DISSIPATION (mW) 03057-021 03057-022 03057-023 AD7654 CS = RD = 0 8-Bit Interface (Master or Slave) t 1 The BYTESWAP pin allows a glueless interface to an 8-bit bus. CNVST As shown in Figure 27, the LSB byte is output on D[7:0] and the t MSB is output on D[15:8] when BYTESWAP is low. When 16 BYTESWAP is high, the LSB and MSB bytes are swapped, the BUSY t LSB is output on D[15:8], and the MSB is output on D[7:0]. By 4 t 3 connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. EOC t 10 t 17 DATA PREVIOUS CHANNEL B PREVIOUS CHANNEL A NEW A CS BUS OR NEW A OR B OR B RD Figure 24. Master Parallel Data Timing for Continuous Read Slave Parallel Interface BYTESWAP In slave parallel reading mode, the data can be read either after HI-Z HI-Z each conversion, which is during the next acquisition phase or PINS D[15:8] HIGH BYTE LOW BYTE during the other channel’s conversion, or during the following t t t 18 18 19 conversion, as shown in Figure 25 and Figure 26, respectively. HI-Z HI-Z LOW BYTE HIGH BYTE PINS D[7:0] When the data is read during the conversion, however, it is recommended that it is read only during the first half of the Figure 27. 8-Bit Parallel Interface conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most Channel A/ Output B critical analog conversion circuitry. The A/B input controls which channel’s conversion results (INAx or INBx) are output on the data bus. The functionality CS of A/B is detailed in Figure 28. When high, the data from Channel A is available on the data bus. When low, the data from RD Channel B is available on the bus. Note that Channel A can be read immediately after conversion is done ( ), while EOC BUSY Channel B is still in its converting phase. However, in any of the CURRENT serial reading modes, Channel A data is updated only after DATA BUS CONVERSION Channel B is converted. t t 18 19 CS Figure 25. Slave Parallel Data Timing for a Read After Conversion RD CS =0 A/B t 1 HI-Z HI-Z CNVST, RD DATA BUS CHANNEL A CHANNEL B t 12 t t 10 18 t 20 t t 13 11 EOC Figure 28. A/B Channel Reading BUSY t 4 t 3 PREVIOUS DATA BUS CONVERSION t t 18 19 Figure 26. Slave Parallel Data Timing for a Read During Conversion Rev. B | Page 19 of 28 03057-025 03057-026 03057-024 03057-028 03057-027 AD7654 SERIAL INTERFACE The AD7654 is configured to use the serial interface when the Usually, because the AD7654 is used with a fast throughput, the SER/PAR is held high. The AD7654 outputs 32 bits of data, master-read-during-convert mode is the most recommended serial mode when it can be used. In this mode, the serial clock MSB first, on the SDOUT pin. The order of the channels being and data toggle at appropriate instants, which minimizes output is also controlled by A/ . When high, Channel A is B potential feedthrough between digital activity and the critical output first; when low, Channel B is output first. This data conversion decisions. The SYNC signal goes low after the LSB is synchronized with the 32 clock pulses provided on the of each channel has been output. Note that in this mode, the SCLK pin. SCLK period changes because the LSBs require more time to MASTER SERIAL INTERFACE settle, and the SCLK is derived from the SAR conversion clock. Internal Clock Note that in the master-read-after-convert mode, unlike in The AD7654 is configured to generate and provide the serial other modes, the signal BUSY returns low after the 32 data bits data clock SCLK when the EXT/ pin is held low. The INT are pulsed out and not at the end of the conversion phase, AD7654 also generates a SYNC signal to indicate to the host which results in a longer BUSY width. One advantage of using when the serial data is valid. The serial clock SCLK and the this mode is that it can accommodate slow digital hosts because SYNC signal can be inverted if desired. The output data is valid the serial clock can be slowed down by using DIVSCLK[1:0] on both the rising and falling edge of the data clock. Depending inputs. Refer to Table 4 for the timing details. on RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 29 and Figure 30 show the detailed timing diagrams of these two modes. Rev. B | Page 20 of 28 AD7654 EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 A/B = 1 CS, RD CNVST BUSY t t 35 3 EOC t t t t 10 11 12 13 t 37 t 26 t 36 t 32 SYNC t 26 t t 25 21 t t t 28 27 31 t 33 12 16 17 31 32 SCLK t t 29 22 t 34 CH A CH A CH A CH B CH B CH B SDOUT X D15 D14 D0 D15 D1 D0 t t 23 30 Figure 29. Master Serial Data Timing for Reading (Read After Conversion) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 A/B = 1 CS, RD t 1 CNVST t 3 BUSY t 12 EOC t t 10 13 t 11 t 24 t 32 SYNC t t 21 26 t t 27 28 t 31 t 33 t 22 SCLK 12 16 1 2 16 t 25 t 34 CH A CH A CH B CH B SDOUT CH A D0 CH B D0 X D15 D14 D15 D14 t t 23 30 t 29 Figure 30. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 21 of 28 03057-029 03057-030 AD7654 SLAVE SERIAL INTERFACE External Clock The AD7654 is configured to accept an externally supplied An example of the concatenation of two devices is shown in serial data clock on the SCLK pin when the EXT/ pin is Figure 31. Simultaneous sampling is possible by using a INT common signal. Note that the RDC/SDIN input is CNVST held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When both CS latched on the edge of SCLK opposite the one used to shift out the data on SDOUT. Therefore, the MSB of the upstream and are low, the data can be read after each conversion or RD converter follows the LSB of the downstream converter on the during the following conversion. The external clock can be next SCLK cycle. The SDIN input should be tied either high or either a continuous or discontinuous clock. A discontinuous low on the most upstream converter in the chain. clock can be either normally high or normally low when inactive. Figure 32 and Figure 33 show the detailed timing BUSY OUT diagrams of these methods. BUSY BUSY While the AD7654 is performing a bit decision, it is important AD7654 AD7654 that voltage transients not occur on digital input/output pins or #2 (UPSTREAM) #1 (DOWNSTREAM) degradation of the conversion result could occur. This is DATA particularly important during the second half of the conversion RDC/SDIN SDOUT RDC/SDIN SDOUT OUT phase of each channel because the AD7654 provides error CNVST CNVST CS CS correction circuitry that can correct for an improper bit SCLK SCLK decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is SCLK IN CS IN provided, it is a discontinuous clock that toggles only when CNVST IN BUSY is low or, more importantly, that it does not transition Figure 31. Two AD7654s in a Daisy-Chain Configuration during the latter half of EOC high. External Discontinuous Clock Data Read After Convert External Clock Data Read Previous During Convert Although the maximum throughput cannot be achieved in this Figure 33 shows the detailed timing diagrams of this method. mode, it is the most recommended of the serial slave modes. During a conversion, while both and are low, the result CS RD Figure 32 shows the detailed timing diagrams of this method. of the previous conversion can be read. The data is shifted out After a conversion is complete, indicated by BUSY returning MSB first with 32 clock pulses and is valid on both the rising low, the conversion results can be read while both and CS RD and falling edges of the clock. The 32 bits have to be read before are low. Data is shifted out from both channels MSB first, with the current conversion is completed; otherwise, RDERROR is 32 clock pulses and is valid on both rising and falling edges of pulsed high and can be used to interrupt the host interface to the clock. prevent incomplete data reading. There is no daisy-chain feature in this mode, and RDC/SDIN input should always be One advantage of this method is that conversion performance is tied either high or low. not degraded because there are no voltage transients on the digital interface during the conversion process. Another To reduce performance degradation due to digital activity, a advantage is the ability to read the data at any speed up to 40 fast discontinuous clock (at least 32 MHz in impulse mode and MHz, which accommodates both a slow digital host interface 40 MHz in normal mode) is recommended to ensure that all of and the fastest serial reading. the bits are read during the first half of each conversion phase ( high, t , t ). EOC 11 12 Finally, in this mode only, the AD7654 provides a daisy-chain feature using the RDC/SDIN (serial data in) input pin for It is also possible to begin to read data after conversion and cascading multiple converters together. This feature is useful for continue to read the last bits after a new conversion has been reducing component count and wiring connections when it is initiated. This allows the use of a slower clock speed like desired, as in isolated multiconverter applications. 26 MHz in impulse mode and 30 MHz in normal mode. Rev. B | Page 22 of 28 03057-031 AD7654 EXT/INT = 1 INVSCLK = 0 RD = 0 A/B = 1 CS EOC BUSY t 42 t t 43 44 12 3 30 31 32 33 34 SCLK t 38 t 39 CH A CH A CH A XCHA XCHA CH B D1 CH B D0 SDOUT X D15 D14 D13 D15 D14 t 23 t 41 XCHA XCHA XCHA XCHB XCHB YCHA YCHA SDIN D15 D14 D13 D1 D0 D15 D14 t 40 Figure 32. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 A/B= 1 CS t 10 CNVST t 12 t t 11 13 EOC BUSY t 3 t 42 t 43 t 44 SCLK 12 3 31 32 t 38 t 39 SDOUT X CHAD15 CHAD14 CHAD13 CHBD1 CHBD0 t 23 Figure 33. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 23 of 28 03057-032 03057-033 AD7654 MICROPROCESSOR INTERFACING The AD7654 is ideally suited for traditional dc measurement end-of-conversion signal (BUSY going low) using an applications supporting a microprocessor and for ac signal interrupt line of the DSP. By writing to the SPI control register processing applications interfacing to a digital signal processor. (SPICLTx), the serial interface (SPI) on the ADSP-219x is The AD7654 is designed to interface with either a parallel 8-bit configured for master mode (MSTR) = 1, clock polarity bit wide or 16-bit wide interface, a general-purpose serial port, or (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt I/O ports on a microcontroller. A variety of external buffers can enable (TIMOD) = 00. To meet all timing requirements, the SPI be used with the AD7654 to prevent digital noise from coupling clock should be limited to 17 Mbps, which allows it to read an into the ADC. The following section illustrates the use of the ADC result in less than 1 μs. When a higher sampling rate is AD7654 with an SPI-equipped DSP, the ADSP-219x. desired, use of one of the parallel interface modes is recommended. SPI INTERFACE (ADSP-219X) DVDD Figure 34 shows an interface diagram between the AD7654 and AD7654* ADSP-219x* the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7654 acts as a slave device and data SER/PAR must be read after conversion. This mode also allows the daisy- EXT/INT chain feature. The convert command can be initiated in BUSY PFx response to an internal timer interrupt. The 32-bit output data CS SPIxSEL (PFx) MISOx SDOUT is read with two serial peripheral interface (SPI) 16-bit wide RD SCLK SCKx accesses. The reading process can be initiated in response to the PFx or TFSx INVSCLK CNVST *ADDITIONAL PINS OMITTED FOR CLARITY Figure 34. Interfacing the AD7654 to an SPI Interface Rev. B | Page 24 of 28 03057-034 AD7654 APPLICATION HINTS LAYOUT The AD7654 has very good immunity to noise on the power OVDD—close to, and ideally right up against these pins and supplies. However, care should still be taken with regard to their corresponding ground pins. Additionally, low ESR 10 μF grounding layout. capacitors should be located near the ADC to further reduce low frequency ripple. The printed circuit board that houses the AD7654 should be designed so the analog and digital sections are separated and The DVDD supply of the AD7654 can be a separate supply or confined to certain areas of the board. This facilitates the use of can come from the analog supply AVDD or the digital interface ground planes that can be separated easily. Digital and analog supply OVDD. When the system digital supply is noisy or when ground planes should be joined in only one place, preferably fast switching digital signals are present, if no separate supply is underneath the AD7654, or as close as possible to the AD7654. available, the user should connect DVDD to AVDD through an If the AD7654 is in a system where multiple devices require RC filter (see Figure 18) and the system supply to OVDD and analog-to-digital ground connections, the connection should the remaining digital circuitry. When DVDD is powered from still be made at only a star ground point established as close as the system supply, it is useful to insert a bead to further reduce possible to the AD7654. high frequency spikes. Running digital lines under the device should be avoided The AD7654 has five different ground pins: INGND, REFGND, because these couple noise onto the die. The analog ground AGND, DGND, and OGND. INGND is used to sense the plane should be allowed to run under the AD7654 to avoid analog input signal. REFGND senses the reference voltage and, noise coupling. Fast switching signals like or clocks because it carries pulsed currents, should be a low impedance CNVST return to the reference. AGND is the ground to which most should be shielded with digital ground to avoid radiating noise internal ADC analog signals are referenced; it must be to other sections of the board, and should never run near connected with the least resistance to the analog ground plane. analog signal paths. Crossover of digital and analog signals DGND must be tied to the analog or digital ground plane, should be avoided. Traces on different but close layers of the depending on the configuration. OGND is connected to the board should run at right angles to each other. This reduces the digital system ground. effect of crosstalk through the board. EVALUATING THE AD7654 PERFORMANCE The power supply lines to the AD7654 should use as large a trace as possible to provide low impedance paths and reduce the A recommended layout for the AD7654 is outlined in the effect of glitches on the power supply lines. Good decoupling is documentation of the evaluation board for the also important to lower the supply’s impedance presented to the EVAL-AD7654CB. The evaluation board package includes a AD7654 and to reduce the magnitude of the supply spikes. fully assembled and tested evaluation board, documentation, Decoupling ceramic capacitors, typically 100 nF, should be and software for controlling the board from a PC via the placed on each power supply pin—AVDD, DVDD, and EVAL-CONTROL-BRD3. Rev. B | Page 25 of 28 AD7654 OUTLINE DIMENSIONS 0.75 9.00 1.60 0.60 BSC SQ MAX 0.45 48 37 36 1 PIN 1 7.00 TOP VIEW BSC SQ 1.45 (PINS DOWN) 0.20 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 35. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED 5.25 6.75 PAD TOP BSC SQ 5.10 SQ VIEW (BOTTOM VIEW) 4.95 0.50 25 0.40 12 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 PADDLE CONNECTED TO AGND. 12° MAX 0.65 TYP THIS CONNECTION IS NOT 0.85 REQUIRED TO MEET THE 0.05 MAX 0.80 ELECTRICAL PERFORMANCES 0.02 NOM 0.50 BSC COPLANARITY 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 36. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm (CP-48-1) Dimensions shown in millimeters Rev. B | Page 26 of 28 AD7654 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7654ACP –40°C to +85°C Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 AD7654ACPRL –40°C to +85°C Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7654ACPZ –40°C to +85°C Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7654ACPZRL –40°C to +85°C Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 AD7654AST –40°C to +85°C Low Profile Quad Flat Package [LQFP] ST-48 AD7654ASTRL –40°C to +85°C Low Profile Quad Flat Package [LQFP] ST-48 1 AD7654ASTZ –40°C to +85°C Low Profile Quad Flat Package [LQFP] ST-48 1 AD7654ASTZRL –40°C to +85°C Low Profile Quad Flat Package [LQFP] ST-48 2 EVAL-AD7654CB Evaluation Board 3 EVAL-CONTROL BRD2 Controller Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL-BRD2/EVAL-CONTROL-BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. Rev. B | Page 27 of 28 AD7654 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03057–0–11/05(B) Rev. B | Page 28 of 28