ANALOG DEVICES AD7653

TM 16-Bit 1 MSPS PulSAR Unipolar ADC with Reference AD7653 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: REFBUFIN REF REFGND DVDD DGND 1 MSPS (Warp mode) OVDD AGND AD7653 800 kSPS (Normal mode) AVDD SERIAL OGND REF 666 kSPS (Impulse mode) PORT 16-bit resolution 16 IN SWITCHED DATA[15:0] Analog input voltage range: 0 V to 2.5 V CAP DAC INGND BUSY No pipeline delay PARALLEL PDREF INTERFACE RD Parallel and serial 5 V/3 V interface PDBUF CLOCK CS TM TM PD SPI®/QSPI /MICROWIRE /DSP compatible CONTROL LOGIC AND SER/PAR RESET CALIBRATION CIRCUITRY Single 5 V supply operation OB/2C Power dissipation BYTESWAP 92 mW typ @ 666 kSPS, 138 μW @ 1 kSPS without REF WARP IMPULSE CNVST 02966-0-001 128 mW typ @ 1 MSPS with REF 48-lead LQFP and 48-lead LFCSP packages Figure 1. Pin-to-pin compatible with PulSAR ADCs Table 1. PulSAR Selection 800– APPLICATIONS Type/kSPS 100–250 500–570 1000 Data acquisition Pseudo- AD7651 AD7650/AD7652 AD7653 Instrumentation Differential AD7660/AD7661 AD7664/AD7666 AD7667 Digital signal processing True Bipolar AD7663 AD7665 AD7671 Spectrum analysis True AD7675 AD7676 AD7677 Medical instruments Differential Battery-powered systems 18-Bit AD7678 AD7679 AD7674 Process control Multichannel/ AD7654 Simultaneous AD7655 GENERAL DESCRIPTION The AD7653 is a 16-bit, 1 MSPS, charge redistribution SAR PRODUCT HIGHLIGHTS analog-to-digital converter that operates from a single 5 V 1. Fast Throughput. power supply. The part contains a high speed 16-bit sampling The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR ADC, internal conversion clock, internal reference, error ADC with internal error correction circuitry. correction circuits, and both serial and parallel system interface ports. It features a very high sampling rate mode (Warp), a fast 2. Internal Reference. mode (Normal) for asynchronous conversion rate applications, The AD7653 has an internal reference with a typical and a reduced power mode (Impulse) for low power applica- temperature drift of 7 ppm/°C. tions where power is scaled with the throughput. The AD7653 is 3. Single-Supply Operation. fabricated using Analog Devices’ high performance, 0.6 micron The AD7653 operates from a single 5 V supply. In Impulse CMOS process, with correspondingly low cost. It is available in mode, its power dissipation decreases with the throughput. a 48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40°C to +85°C. 4. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. AD7653 TABLE OF CONTENTS Specifications..................................................................................... 3 Parallel Interface......................................................................... 20 Timing Specifications....................................................................... 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings............................................................ 7 Master Serial Interface............................................................... 21 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 22 Definitions of Specifications ......................................................... 11 Microprocessor Interfacing....................................................... 24 Typical Performance Characteristics ........................................... 12 Application Hints............................................................................ 25 Circuit Information ........................................................................ 15 Bipolar and Wider Input Ranges .............................................. 25 Converter Operation.................................................................. 15 Layout .......................................................................................... 25 Typical Connection Diagram.................................................... 17 Evaluating the AD7653’s Performance .................................... 25 Power Dissipation vs. Throughput........................................... 19 Outline Dimensions ....................................................................... 26 Conversion Control.................................................................... 19 Ordering Guide........................................................................... 26 Digital Interface .......................................................................... 20 REVISION HISTORY Location Page 9/03—Data Sheet Changed from Rev. 0 to Rev. A Change to Product Highlights .................................................... 1 Changes to Specifications ............................................................ 3 Changes to Absolute Maximum Ratings ................................... 7 Changes to Figure 15.................................................................. 13 Changes to Figure 22.................................................................. 16 Changes to Voltage Reference Input section........................... 18 Changes to Figure 31.................................................................. 20 Rev. A | Page 2 of 28 AD7653 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN – VINGND 0 VREF V Operating Input Voltage VIN –0.1 +3 V VINGND –0.1 +0.5 V Analog Input CMRR f = 10 kHz 65 dB IN Input Current 1 MSPS Throughput 12 µA 1 Input Impedance THROUGHPUT SPEED Complete Cycle In Warp Mode 1 µs Throughput Rate In Warp Mode 1 1000 kSPS Time between Conversions In Warp Mode 1 ms Complete Cycle In Normal Mode 1.25 µs Throughput Rate In Normal Mode 0 800 kSPS Complete Cycle In Impulse Mode 1.5 µs Throughput Rate In Impulse Mode 0 666 kSPS DC ACCURACY 2 Integral Linearity Error –6 +6 LSB No Missing Codes 15 Bits Differential Linearity Error –2 +3 LSB Transition Noise 0.7 LSB 3 Unipolar Zero Error, TMIN to TMAX ±25 LSB Unipolar Zero Error Temperature Drift ±0.2 ppm/°C 3 Full-Scale Error, T to T REF = 2.5 V ±0.12 % of FSR MIN MAX ±0.4 Full-Scale Error Temperature Drift ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5%, with REF ±2 LSB AC ACCURACY 4 Signal-to-Noise fIN = 100 kHz 86 dB Spurious Free Dynamic Range f = 100 kHz 98 dB IN Total Harmonic Distortion f = 45 kHz –98 dB IN fIN = 100 kHz –96 dB Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB –60 dB Input, f = 100 kHz 30 dB IN –3 dB Input Bandwidth 12 MHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 250 ns REFERENCE Internal Reference Voltage VREF @ 25°C 2.48 2.50 2.52 V Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C AVDD = 5 V ± 5% Line Regulation ±24 ppm/V Turn-On Settling Time C = 10 µF 5 ms REF Temperature Pin Voltage Output @ 25°C 300 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.3 kΩ External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 1 MSPS Throughput 300 µA Rev. A | Page 3 of 28 AD7653 Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V VIH 2.0 DVDD + 0.3 V I –1 +1 µA IL I –1 +1 µA IH DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK VOH ISOURCE = –500 µA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 5.25 V 8 Operating Current 1 MSPS Throughput 9 AVDD With Reference and Buffer 18.7 mA 10 AVDD Reference and Buffer Alone 3 mA 11 DVDD 6.7 mA 11 OVDD 200 µA 11 Power Dissipation without REF 666 kSPS Throughput 92 115 mW 11 1 kSPS Throughput 138 µW 8 Power Dissipation with REF 1 MSPS Throughput 128 145 mW 12 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Input section. 2 LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. 3 See Definitions of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or serial 16-bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 In Warp mode. 9 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 10 With PDREF, PDBUF LOW and PD HIGH. 11 Impulse Mode. Tested in Parallel Reading mode. 12 Consult factory for extended temperature range. Rev. A | Page 4 of 28 AD7653 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit Refer to Figure 26 and Figure 27 Convert Pulse Width t1 10 ns 1 Time between Conversions (Warp Mode/Normal Mode/Impulse Mode) t2 1/1.25/1.5 µs CNVST LOW to BUSY HIGH Delay t 35 ns 3 BUSY HIGH All Modes Except Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) t4 0.75/1/1.25 µs Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t 0.75/1/1.25 µs 7 t Acquisition Time 8 250 ns RESET Pulse Width t9 10 ns Refer to Figure 28, Figure 29, and Figure 30 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) t 0.75/1/1.25 µs 10 DATA Valid to BUSY LOW Delay t 12 ns 11 Bus Access Request to DATA Valid t12 45 ns Bus Relinquish Time t13 5 15 ns 2 Refer to Figure 32 and Figure 33 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t 10 ns 14 2 CS LOW to Internal SCLK Valid Delay t 10 ns 15 CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t17 25/275/525 ns SYNC Asserted to SCLK First Edge Delay t 3 ns 18 3 Internal SCLK Period t 25 40 ns 19 3 Internal SCLK HIGH t20 12 ns 3 Internal SCLK LOW t21 7 ns 3 SDOUT Valid Setup Time t 4 ns 22 3 SDOUT Valid Hold Time t 2 ns 23 3 SCLK Last Edge to SYNC Delay t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t 10 ns 27 3 BUSY HIGH in Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) t28 See Table 4 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) t 0.75/1/1.25 µs 29 SYNC Deasserted to BUSY LOW Delay t 25 ns 30 2 Refer to Figure 34 and Figure 35 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t 5 ns 33 SDIN Hold Time t 5 ns 34 External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t 10 ns 37 1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 3 In Serial Master Read during Convert Mode. See Table 4 for Serial Master Read after Convert mode. Rev. A | Page 5 of 28 AD7653 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t 3 17 17 17 ns 18 Internal SCLK Period Minimum t 25 50 100 200 ns 19 Internal SCLK Period Maximum t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t 7 21 49 99 ns 21 SDOUT Valid Setup Time Minimum t 4 18 18 18 ns 22 SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns BUSY HIGH Width Maximum (Warp) t 1.5 2 3 5.25 µs 28 BUSY HIGH Width Maximum (Normal) t 1.75 2.25 3.25 5.55 µs 28 BUSY HIGH Width Maximum (Impulse) t28 2 2.5 3.5 5.75 µs Rev. A | Page 6 of 28 AD7653 ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7653 Absolute Maximum Ratings 1.6mA I OL Parameter Rating 2 2 IN , TEMP ,REF, REFBUFIN, AVDD + 0.3 V to TO OUTPUT INGND, REFGND to AGND AGND – 0.3 V 1.4V PIN C L Ground Voltage Differences 60pF* AGND, DGND, OGND ±0.3 V I 500µA OH Supply Voltages *IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND AVDD, DVDD, OVDD –0.3 V to +7 V SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. AVDD to DVDD, AVDD to OVDD ±7 V L 02966-0-006 DVDD to OVDD –0.3 V to +7 V Digital Inputs –0.3 V to DVDD + 0.3 V Figure 2. Load Circuit for Digital Interface Timing, 3 SDOUT, SYNC, SCLK Outputs CL = 10 pF PDREF, PDBUF ±20 mA 4 Internal Power Dissipation 700 mW 5 2V Internal Power Dissipation 2.5 W 0.8V Junction Temperature 150°C t t DELAY DELAY Storage Temperature Range –65°C to +150°C 2V 2V Lead Temperature Range 300°C 0.8V 0.8V (Soldering 10 sec) 02966-0-007 Figure 3. Voltage Reference Levels for Timing 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 See Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W 5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 28 AD7653 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 2 IDENTIFIER AVDD 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7653 WARP 6 31 RD TOP VIEW IMPULSE 7 30 DGND (Not to Scale) SER/PAR 8 29 BUSY D0 9 28 D15 10 D1 27 D14 11 D2/DIVSCLK0 26 D13 12 D3/DIVSCLK1 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT 02966-0-002 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 40 NC No Connect. 4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. 13 D4 or DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. INT EXT/ When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choos- ing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. Rev. A | Page 8 of 28 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN DVDD AGND DGND AGND D8/SDOUT NC D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF AD7653 1 Pin No. Mnemonic Type Description 15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. 16 D7 or DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. RDC/SDIN is HIGH, this input, part of the serial port, is used as either an external data input or a When SER/PAR read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D8 or DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchro- nized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D9 or DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 or DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. 24 D11 or DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When RDERROR SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the acquisition phase (t ) is complete, the internal sample/hold is put into the hold state and a 8 conversion is immediately started. Rev. A | Page 9 of 28 AD7653 1 Pin No. Mnemonic Type Description 37 REF AI/O Reference Input Voltage. On-chip reference output voltage. 38 REFGND AI Reference Input Analog Ground. 39 INGND AI Analog Input Ground. 43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V. 45 TEMP AO Temperature Sensor Voltage Output. 46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input. 47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used. 48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer. When LOW, the buffer is selected. When HIGH, the buffer is switched off. 1 AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Rev. A | Page 10 of 28 AD7653 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Signal-to-Noise Ratio (SNR) Linearity error refers to the deviation of each individual code SNR is the ratio of the rms value of the actual input signal to the from a line drawn from negative full scale through positive full rms sum of all other spectral components below the Nyquist scale. The point used as negative full scale occurs ½ LSB before frequency, excluding harmonics and dc. The value for SNR is the first code transition. Positive full scale is defined as a level expressed in decibels. 1½ LSB beyond the last code transition. The deviation is Signal-to-(Noise + Distortion) Ratio (S/[N+D]) measured from the middle of each code to the true straight line. S/(N+D) is the ratio of the rms value of the actual input signal Differential Nonlinearity Error (DNL) to the rms sum of all other spectral components below the In an ideal ADC, code transitions are 1 LSB apart. Differential Nyquist frequency, including harmonics but excluding dc. The nonlinearity is the maximum deviation from this ideal value. It value for S/(N+D) is expressed in decibels. is often specified in terms of resolution for which no missing Aperture Delay codes are guaranteed. Aperture delay is a measure of the acquisition performance and Full-Scale Error is measured from the falling edge of the input to when CNVST The last transition (from 011…10 to 011…11 in twos the input signal is held for a conversion. complement coding) should occur for an analog voltage 1½ LSB Transient Response below the nominal full scale (2.49994278 V for the 0 V to 2.5 V Transient response is the time required for the AD7653 to range). The full-scale error is the deviation of the actual level of achieve its rated accuracy after a full-scale step function is the last transition from the ideal level. applied to its input. Unipolar Zero Error Overvoltage Recovery The first transition should occur at a level ½ LSB above analog Overvoltage recovery is the time required for the ADC to ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero recover to full accuracy after an analog input signal 150% of the error is the deviation of the actual transition from that point. full-scale value is reduced to 50% of the full-scale value. Spurious-Free Dynamic Range (SFDR) Reference Voltage Temperature Coefficient SFDR is the difference, in decibels (dB), between the rms Reference voltage temperature coefficient is the change of amplitude of the input signal and the peak spurious signal. internal reference voltage output voltage V over the operating Effective Number of Bits (ENOB) temperature range and normalized by the output voltage at ENOB is a measurement of the resolution with a sine wave 25°C, expressed in ppm/°C. The equation follows: input. It is related to S/(N+D) by the following formula: V(T 2) –V(T1) 6 TCV(ppm/°C)= ×10 ENOB = (S/[N+D]dB – 1.76)/6.02 V(25°C)×(T 2 –T1) where: and is expressed in bits. V(25°C) = V at +25°C Total Harmonic Distortion (THD) V(T2) = V at Temperature 2 (+85°C) THD is the ratio of the rms sum of the first five harmonic V(T1) = V at Temperature 1 (–40°C) components to the rms value of a full-scale input signal, and is expressed in decibels. Rev. A | Page 11 of 28 AD7653 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 4 3 1.5 2 1.0 1 0.5 0 –1 0 –2 –0.5 –3 –1.0 –4 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE 02966-0-023 02966-0-026 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 160000 140000 146148 114641 140000 120000 112516 120000 100000 100000 80000 80000 60000 60000 54482 54473 40000 40000 17001 15906 20000 20000 3099 2856 679 53 00 377 0 0 0 90 0 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX CODE IN HEX 02966-0-028 02966-0-027 Figure 6. Histogram of 261,120 Conversions of a Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Transition DC Input at the Code Center 15.0 90 0 f = 1000kSPS S f = 101kHz –20 IN SNR = 86.0dB 14.5 87 THD = 90.3dB –40 SFDR = 91.5dB S/[N+D] = 84.8dB SNR 14.0 –60 84 –80 13.5 81 S/[N+D] –100 78 13.0 –120 ENOB –140 75 12.5 –160 72 12.0 –180 0 100 200 300 400 500 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) 02966-0-030 02966-0-029 Figure 7. FFT Plot Figure 10. SNR, S/(N+D), and ENOB vs. Frequency Rev. A | Page 12 of 28 COUNTS AMPLITUDE (dB of Full Scale) INL (LSB) COUNTS SNR, S/[N+D] (dB) DNL (LSB) ENOB (Bits) AD7653 –50 120 –95 SFDR –60 100 SECOND –70 THD HARMONIC –105 80 –80 THIRD 60 HARMONIC –90 THD 40 –115 –100 THIRD HARMONIC 20 –110 SECOND HARMONIC –120 0 –125 –55 –35 –1558 25 45 655 105 125 1 10 100 1000 FREQUENCY (kHz) TEMPERATURE (°C) 02966-0-034 02966-0-031 Figure 14. THD and Harmonics vs. Temperature Figure 11. THD, Harmonics, and SFDR vs. Frequency 92 100000 AVDD, WARP/NORMAL 91 10000 DVDD, WARP/NORMAL 90 1000 89 SNR 100 88 DVDD, IMPULSE AVDD, IMPULSE 87 10 S/[N+D] 86 1 OVDD, ALL MODES 85 0.1 84 0.01 83 PDREF = PDBUF = HIGH 0.001 82 1000 –60 –50 –40 –30 –20 –10 0 10 100 10000 100000 1000000 SAMPLE RATE (SPS) INPUT LEVEL (dB) 02966-A-032 02966-0-036 Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) Figure 15. Operating Current vs. Sample Rate 89 14.75 6 5 4 3 88 14.50 SNR 2 S[N+D] FULL SCALE 1 0 87 14.25 ENOB –1 ZERO ERROR –2 –3 86 14.00 –4 –5 13.75 –6 85 –55 –35 5 25 45 65 85 105 125 –55 –35 –1558 25 45 655 105 125 –15 TEMPERATURE (°C) TEMPERATURE (°C) 02966-0-033 02966-0-040 Figure 16. Zero Error, Full Scale with Reference vs. Temperature Figure 13. SNR, S/(N+D), and ENOB vs. Temperature Rev. A | Page 13 of 28 THD, HARMONICS (dB) SNR, S/[N+D] (dB) SNR, S/[N+D] REFERRED TO FULL SCALE (dB) SFDR (dB) ENOB (Bits) OPERATING CURRENT (µA) THD, HARMONICS (dB) ZERO ERROR, FULL SCALE (LSB) AD7653 2.5020 50 OVDD = 2.7V @ 85°C 2.5019 2.5018 40 2.5017 OVDD = 2.7V @ 25°C 2.5016 30 2.5015 2.5014 OVDD = 5V @ 85°C 2.5013 20 OVDD = 5V @ 25°C 2.5012 2.5011 10 2.5010 2.5009 2.5008 0 –40 –20 0 20 40 60 80 100 120 0 50 100 150 200 TEMPERATURE (°C) C (pF) L 02966-0-038 02966-0-035 Figure 17. Typical Reference Output Voltage vs. Temperature Figure 19. Typical Delay vs. Load Capacitance C L 90 80 70 60 50 40 30 20 10 0 –30 –26 –22 –18 –14 –10 –6 –2 2 6 10 14 18 22 26 30 REFERENCE DRIFT (ppm/°C) 02966-0-039 Figure 18. Reference Voltage Temperature Coefficient Distribution (335 Units) Rev. A | Page 14 of 28 VREF (V) NUMBER OF UNITS t DELAY (ns) 12 AD7653 CIRCUIT INFORMATION IN REF REFGND SWITCHES CONTROL SW MSB LSB A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC INGND OUTPUT 65,536C CODE SW B CNVST 02966-0-005 Figure 20. ADC Simplified Schematic The AD7653 is a very fast, low power, single supply, precise from the inputs and connected to REFGND. Therefore, the 16-bit analog-to-digital converter (ADC). The AD7653 features differential voltage between IN and INGND captured at the end different modes to optimize performance according to the of the acquisition phase is applied to the comparator inputs, application. In Warp mode, the part can convert 1 million causing the comparator to become unbalanced. By switching samples per second. each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps The AD7653 provides the user with an on-chip track/hold, (VREF/2, VREF/4, …VREF/65536). The control logic toggles successive approximation ADC that does not exhibit any these switches, starting with the MSB, to bring the comparator pipeline or latency, making it ideal for multiple multiplexed back into a balanced condition. channel applications. After this process is completed, the control logic generates the The AD7653 can be operated from a single 5 V supply and can ADC output code and brings the BUSY output LOW. be interfaced to either 5 V or 3 V digital logic. It is housed in Modes of Operation either a 48-lead LQFP or a 48-lead LFCSP that saves space and The AD7653 features three modes of operations: Warp, Normal, allows flexible configurations as either a serial or a parallel and Impulse. Each mode is best suited for specific applications. interface. The AD7653 is a pin-to-pin compatible upgrade of the AD7651/AD7652. Warp mode allows the fastest conversion rate up to 1 MSPS. CONVERTER OPERATION However in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions The AD7653 is a successive approximation ADC based on a does not exceed 1 ms. If the time between two consecutive charge redistribution DAC. Figure 20 shows a simplified conversions is longer than 1 ms (e.g., after power-up), the first schematic of the ADC. The capacitive DAC consists of an array conversion result should be ignored. This mode makes the of 16 binary weighted capacitors and an additional LSB AD7653 ideal for applications where both high accuracy and capacitor. The comparator’s negative input is connected to a fast sample rate are required. dummy capacitor of the same value as the capacitive DAC array. Normal mode is the fastest mode (800 kSPS) without any During the acquisition phase, the common terminal of the array limitations on the time between conversions. This mode makes tied to the comparator’s positive input is connected to AGND the AD7653 ideal for asynchronous applications such as data via SWA. All independent switches are connected to the analog acquisition systems, where both high accuracy and fast sample input IN. Thus, the capacitor array is used as a sampling rate are required. capacitor and acquires the analog signal on IN. Similarly, the dummy capacitor acquires the analog signal on INGND. Impulse mode, the lowest power dissipation mode, allows power saving between conversions. When operating at 1 kSPS, for When CNVST goes LOW, a conversion phase is initiated. When example, it typically consumes only 138 µW. This feature makes the conversion phase begins, SWA and SWB are opened. The the AD7653 ideal for battery-powered applications. capacitor array and dummy capacitor are then disconnected Rev. A | Page 15 of 28 AD7653 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Digital Output Code (Hex) 2C Using the OB/ digital input, the AD7653 offers two output Analog Straight Twos codings: straight binary and twos complement. The LSB size is Description Input Binary Complement V /65536, which is about 38.15 µV. The AD7653’s ideal REF 1 FSR – 1 LSB 2.499962 V FFFF 7FFF1 transfer characteristic is shown in Figure 21 and Table 7. FSR – 2 LSB 2.499923 V FFFE 7FFE Midscale + 1 LSB 1.250038 V 8001 0001 1 LSB = V /65536 REF Midscale 1.25 V 8000 0000 111...111 Midscale – 1 LSB 1.249962 V 7FFF FFFF 111...110 –FSR + 1 LSB 38 µV 0001 8001 111...101 2 2 –FSR 0 V 0000 8000 1 This is also the code for overrange analog input (V – V above IN INGND VREF – VREFGND). 2 This is also the code for underrange analog input (V below V ). IN INGND 000...010 000...001 000...000 0V 1LSB V – 1 LSB REF 0.5 LSB V – 1.5 LSB REF ANALOG INPUT 02966-0-003 Figure 21. ADC Ideal Transfer Function ANALOG 20Ω DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) + + + 100nF 100nF 100nF 10µF 10µF 10µF AVDD GND DGND DVDD OVDD OGND SERIAL PORT SCLK REF SDOUT 4 1 C REFBUFIN R 100nF µC/µP/DSP REFGND BUSY AD7653 3 CNVST D 15Ω 2 U1 IN OB/2C ANALOG INPUT (0VTO 2.5V) DVDD SER/PAR C 2.7nF C WARP BYTESWAP INGND IMPULSE PD PDBUF RESET CS RD PDREF CLOCK NOTES 1 THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER. 2 THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3 OPTIONAL LOW JITTER. 4 A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 02966-A-004 Figure 22. Typical Connection Diagram Rev. A | Page 16 of 28 ADC CODE (Straight Binary) AD7653 when the switches are opened, the input impedance is limited to TYPICAL CONNECTION DIAGRAM C1. R1 and C2 make a 1-pole low-pass filter that reduces Figure 22 shows a typical connection diagram for the AD7653. undesirable aliasing effects and limits the noise. Analog Input When the source impedance of the driving circuit is low, the Figure 23 shows an equivalent circuit of the input structure of AD7653 can be driven directly. Large source impedances will the AD7653. significantly affect the ac performance, especially total The two diodes, D1 and D2, provide ESD protection for the harmonic distortion. analog inputs IN and INGND. Care must be taken to ensure Driver Amplifier Choice that the analog input signal never exceeds the supply rails by Although the AD7653 is easy to drive, the driver amplifier needs more than 0.3 V. This will cause these diodes to become to meet the following requirements: forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For • The driver amplifier and the AD7653 analog input circuit instance, these conditions could eventually occur when the must be able to settle for a full-scale step of the capacitor input buffer’s (U1) supplies are different from AVDD. In such a array at a 16-bit level (0.0015%). In the amplifier’s data case, an input buffer with a short-circuit current limitation can sheet, settling at 0.1% to 0.01% is more commonly be used to protect the part. specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver AVDD selection. The tiny op amp AD8021, which combines D1 C2 R1 ultralow noise and high gain-bandwidth, meets this settling IN OR INGND C1 time requirement even when used with gains up to 13. D2 AGND • The noise generated by the driver amplifier needs to be 02966-0-008 kept as low as possible in order to preserve the SNR and transition noise performance of the AD7653. The noise Figure 23. Equivalent Analog Input Circuit coming from the driver is filtered by the AD7653 analog input circuit 1-pole low-pass filter made by R1 and C2 or This analog input structure allows the sampling of the different- by the external filter, if one is used. tial signal between IN and INGND. Unlike other converters, INGND is sampled at the same time as IN. By using this differ- • The driver needs to have a THD performance suitable to ential input, small signals common to both inputs are rejected. that of the AD7653. For instance, by using INGND to sense a remote signal ground, The AD8021 meets these requirements and is appropriate for ground potential differences between the sensor and the local almost all applications. The AD8021 needs a 10 pF external ADC ground are eliminated. compensation capacitor that should have good linearity as an During the acquisition phase, the impedance of the analog input NPO ceramic or mica type. IN can be modeled as a parallel combination of capacitor C1 The AD8022 could also be used if a dual version is needed and and the network formed by the series connection of R1 and C2. gain of 1 is present. The AD829 is an alternative in applications C1 is primarily the pin capacitance. R1 is typically 168 Ω and is where high frequency (above 100 kHz) performance is not a lumped component made up of some serial resistors and the required. In gain of 1 applications, it requires an 82 pF on resistance of the switches. C2 is typically 60 pF and is mainly compensation capacitor. The AD8610 is an option when low the ADC sampling capacitor. During the conversion phase, bias current is needed in low frequency applications. Rev. A | Page 17 of 28 AD7653 Voltage Reference Input The AD7653 allows the choice of either a very low temperature For applications that use multiple AD7653s, it is more effective drift internal voltage reference or an external 2.5 V reference. to use the internal buffer to buffer the reference voltage. Unlike many ADCs with internal references, the internal Care should be taken with the voltage reference’s temperature reference of the AD7653 provides excellent performance and coefficient, which directly affects the full-scale accuracy, if this can be used in almost all applications. parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. To use the internal reference along with the internal buffer, PDREF and PDBUF should both be LOW. This will produce a Note that VREF can be increased to AVDD – 1.85 V. Since the 1.207 V voltage on REFBUFIN which, amplified by the buffer, input range is defined in terms of VREF, this would essentially will result in a 2.5 V reference on the REF pin. increase the range to 0 V to 3 V with an AVDD above 4.85 V. The AD780 can be selected with a 3 V reference voltage. The output impedance of REFBUFIN is 11 kΩ (minimum) when the reference is enabled. It is useful to decouple REFBUFIN with The TEMP pin, which measures the temperature of the AD7653, a 100 nF ceramic capacitor. Thus, the 100 nF capacitor provides can be used as shown in Figure 24. The output of the TEMP pin an RC filter for noise reduction. is applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own To use an external reference along with the internal buffer, temperature. This configuration is very useful for improving the PDREF should be HIGH and PDBUF should be LOW. This calibration accuracy over the temperature range. powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN. TEMP ADG779 To use an external reference directly on the REF pin, PDREF TEMPERATURE and PDBUF should both be HIGH. SENSOR IN ANALOG INPUT (UNIPOLAR) AD7653 C AD8021 C PDREF and PDBUF, respectively, power down the internal 02966-0-024 reference and the internal reference. Note that the PDREF and Figure 24. Temperature Sensor Connection Diagram PDBUF input current should never exceed 20 mA. This could eventually occur when input voltage is above AVDD (for Power Supply instance at power-up). In this case, a 100 Ω series resistor is recommended. The AD7653 uses three power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital The internal reference is temperature compensated to 2.5 V ± input/output interface supply OVDD. OVDD allows direct 20 mV. The reference is trimmed to provide a typical drift of 7 interface with any logic between 2.7 V and DVDD + 0.3 V. To ppm/°C. This typical drift characteristic is shown in Figure 17. reduce the supplies needed, the digital core (DVDD) can be For improved drift performance, an external reference such as supplied through a simple RC filter from the analog supply, as the AD780 can be used. shown in Figure 22. The AD7653 is independent of power supply sequencing once OVDD does not exceed DVDD by The AD7653 voltage reference input REF has a dynamic input more than 0.3 V, and is thus free of supply voltage induced impedance; it should, therefore, be driven by a low impedance latch-up. source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 • The low power ADR291 • The low cost AD1582 Rev. A | Page 18 of 28 AD7653 The CNVST trace should be shielded with ground and a low POWER DISSIPATION VS. THROUGHPUT value serial resistor (i.e., 50 Ω) termination should be added Operating currents are very low during the acquisition phase, close to the output of the component that drives this line. allowing significant power savings when the conversion rate is reduced (see Figure 25). This power savings depends on the For applications where SNR is critical, the signal should CNVST mode used. In Impulse mode, the AD7653 automatically have very low jitter. This may be achieved by using a dedicated reduces power consumption at the end of each conversion oscillator for CNVST generation, or to clock CNVST with a phase. This makes the part ideal for very low power battery high frequency, low jitter clock, as shown in Figure 22. applications. The digital interface and the reference remain active even during the acquisition phase. To reduce operating t 2 digital supply currents even further, digital inputs need to be t 1 driven close to the power supply rails (i.e., DVDD or DGND), CNVST and OVDD should not exceed DVDD by more than 0.3 V. 1000000 BUSY t 4 t 3 WARP MODE POWER t 100000 6 t 5 MODE ACQUIRE CONVERT ACQUIRE CONVERT 10000 t t 7 8 02966-0-011 1000 Figure 26. Basic Conversion Timing IMPULSE MODE POWER 100 t 9 RESET PDREF = PDBUF = HIGH 10 1000 10 100 10000 100000 1000000 BUSY SAMPLE RATE (SPS) 02966-0-041 Figure 25. Power Dissipation vs. Sampling Rate DATA t 8 CONVERSION CONTROL CNVST Figure 26 shows the detailed timing diagrams of the conversion process. The AD7653 is controlled by the CNVST signal, which 02966-0-011 initiates conversion. Once initiated, it cannot be restarted or Figure 27. RESET Timing aborted, even by the power-down input PD, until the conversion is complete. operates independently of and . CNVST CS RD CS = RD = 0 t In Impulse mode, conversions can be automatically initiated. If 1 CNVST CNVST is held LOW when BUSY is LOW, the AD7653 controls the acquisition phase and automatically initiates a new con- t 10 version. By keeping CNVST LOW, the AD7653 keeps the BUSY conversion process running by itself. It should be noted that the t 4 t 3 analog input must be settled when BUSY goes low. Also, at t 11 power-up, should be brought LOW once to initiate the CNVST DATA PREVIOUS CONVERSION DATA NEW DATA conversion process. In this mode, the AD7653 can run slightly BUS faster than the guaranteed 666 kSPS limits in Impulse mode. 02966-0-012 This feature does not exist in Warp and Normal modes. Figure 28. Master Parallel Data Timing for Reading (Continuous Read) Although is a digital signal, it should be designed with CNVST special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. Rev. A | Page 19 of 28 POWER DISSIPATION (µW) AD7653 DIGITAL INTERFACE CS The AD7653 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel inter- RD face. The serial interface is multiplexed on the parallel data bus. The AD7653 digital interface also accommodates both 3 V and 5 V logic by simply connecting the OVDD supply pin of the AD7653 to the host system interface digital supply. Finally, by BUSY using the OB/2C input pin, both twos complement and straight binary coding can be used. DATA CURRENT BUS CONVERSION The two signals, and , control the interface. and CS RD CS RD t t 12 13 have a similar effect because they are OR’d together internally. 02966-0-013 When at least one of these signals is HIGH, the interface outputs are in high impedance. Usually allows the selection CS Figure 29. Slave Parallel Data Timing for Reading (Read after Convert Mode) of each AD7653 in multicircuit applications and is held LOW in a single AD7653 design. RD is generally used to enable the conversion result on the data bus. CS = 0 CNVST, t 1 RD PARALLEL INTERFACE The AD7653 is configured to use the parallel interface when SER/ is held LOW. The data can be read either after each PAR conversion, which is during the next acquisition phase, or BUSY t 4 during the following conversion, as shown in Figure 29 and t 3 Figure 30, respectively. When the data is read during the conversion, however, it is recommended that it is read only DATA PREVIOUS during the first half of the conversion phase. This avoids any CONVERSION BUS t potential feedthrough between voltage transients on the digital t 12 13 02966-0-014 interface and the most critical analog conversion circuitry. Figure 30. Slave Parallel Data Timing for Reading The BYTESWAP pin allows a glueless interface to an 8-bit bus. (Read during Convert Mode) As shown in Figure 31, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is LOW. When BYTESWAP is HIGH, the LSB and MSB bytes are swapped and CS the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data RD can be read in two bytes on either D[15:8] or D[7:0]. BYTESWAP SERIAL INTERFACE The AD7653 is configured to use the serial interface when HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE SER/PAR is held HIGH. The AD7653 outputs 16 bits of data, t t t 12 12 13 MSB first, on the SDOUT pin. This data is synchronized with HI-Z HI-Z LOW BYTE HIGH BYTE the 16 clock pulses provided on the SCLK pin. The output data PINS D[7:0] is valid on both the rising and falling edges of the data clock. 02966-A-025 Figure 31. 8-Bit Parallel Interface Rev. A | Page 20 of 28 AD7653 Usually, because the AD7653 is used with a fast throughput, the MASTER SERIAL INTERFACE Master Read During Conversion mode is the most Internal Clock recommended serial mode. In this mode, the serial clock and The AD7653 is configured to generate and provide the serial data toggle at appropriate instants, minimizing potential data clock SCLK when the EXT/INT pin is held LOW. The feedthrough between digital activity and critical conversion AD7653 also generates a SYNC signal to indicate to the host decisions. when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted, if desired. Depending on the In Read After Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns LOW after the 16 data RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 32 and Figure 33 show bits are pulsed out and not at the end of the conversion phase, the detailed timing diagrams of these two modes. which results in a longer BUSY width. EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 02966-0-015 Figure 32. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 02966-0-016 Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. A | Page 21 of 28 AD7653 While the AD7653 is performing a bit decision, it is important SLAVE SERIAL INTERFACE External Clock that voltage transients be avoided on digital input/output pins, or degradation of the conversion result could occur. This is The AD7653 is configured to accept an externally supplied particularly important during the second half of the conversion serial data clock on the SCLK pin when the EXT/INT pin is held phase because the AD7653 provides error correction circuitry HIGH. In this mode, several methods can be used to read the that can correct for an improper bit decision made during the data. The external serial clock is gated by . When and CS CS RD first half of the conversion phase. For this reason, it is recom- are both LOW, the data can be read after each conversion or mended that when an external clock is being provided, it is a during the following conversion. The external clock can be discontinuous clock that is toggling only when BUSY is LOW, either a continuous or a discontinuous clock. A discontinuous or, more importantly, that it does not transition during the latter clock can be either normally HIGH or normally LOW when half of BUSY HIGH. inactive. Figure 34 and Figure 35 show the detailed timing diagrams of these methods. RD = 0 EXT/INT = 1 INVSCLK = 0 RD BUSY t 35 t t 36 37 SCLK 1 2 3 14 151617 18 t 31 t 32 X D15 D14 D13 D1 X15 X14 SDOUT D0 t t 16 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 02966-0-017 Figure 34. Slave Serial Data Timing for Reading (Read after Convert) RD = 0 EXT/INT = 1 INVSCLK = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 X D1 SDOUT D15 D14 D13 D0 t 02966-0-018 16 Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. A | Page 22 of 28 AD7653 External Discontinuous Clock Data Read After External Clock Data Read During Conversion Conversion Figure 35 shows the detailed timing diagrams of this method. Though the maximum throughput cannot be achieved using During a conversion, while both and are both LOW, the CS RD this mode, it is the most recommended of the serial slave modes. result of the previous conversion can be read. The data is shifted Figure 34 shows the detailed timing diagrams of this method. out MSB first with 16 clock pulses, and is valid on both the After a conversion is complete, indicated by BUSY returning rising and falling edges of the clock. The 16 bits must be read LOW, the conversion’s result can be read while both CS and RD before the current conversion is complete; otherwise, are LOW. Data is shifted out MSB first with 16 clock pulses and RDERROR is pulsed HIGH and can be used to interrupt the is valid on the rising and falling edges of the clock. host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode, and the RDC/SDIN input Among the advantages of this method is the fact that conversion should always be tied either HIGH or LOW. performance is not degraded because there are no voltage transients on the digital interface during the conversion process. To reduce performance degradation due to digital activity, a fast Another advantage is the ability to read the data at any speed up discontinuous clock (at least 18 MHz when Impulse mode is to 40 MHz, which accommodates both the slow digital host used, 25 MHz when Normal mode is used, or 40 MHz when interface and the fastest serial reading. Warp mode is used) is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also Finally, in this mode only, the AD7653 provides a daisy-chain possible to begin to read data after conversion and continue to feature using the RDC/SDIN pin for cascading multiple read the last bits after a new conversion has been initiated. This converters together. This feature is useful for reducing compo- allows the use of a slower clock speed like 14 MHz in Impulse nent count and wiring connections when desired, as, for mode, 18 MHz in Normal mode, and 25 MHz in Warp mode. instance, in isolated multiconverter applications. The concatenation of two devices is shown in Figure 36. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite the one used to shift out the data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7653 AD7653 #2 #1 (UPSTREAM) (DOWNSTREAM) DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 02966-0-019 Figure 36. Two AD7653s in a Daisy-Chain Configuration Rev. A | Page 23 of 28 AD7653 face (SPI) on the ADSP-219x is configured for master mode— MICROPROCESSOR INTERFACING (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit The AD7653 is ideally suited for traditional dc measurement (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by applications supporting a microprocessor, and for ac signal writing to the SPI control register (SPICLTx). To meet all timing processing applications interfacing to a digital signal processor. requirements, the SPI clock should be limited to 17 Mbps, which The AD7653 is designed to interface either with a parallel 8-bit allows it to read an ADC result in less than 1 µs. When a higher or 16-bit wide interface, or with a general-purpose serial port or sampling rate is desired, use of one of the parallel interface I/O ports on a microcontroller. A variety of external buffers can modes is recommended. be used with the AD7653 to prevent digital noise from coupling DVDD into the ADC. The following section discusses the use of an ADSP-219x* AD7653* AD7653 with an ADSP-219x SPI equipped DSP. SER/PAR SPI Interface (ADSP-219x) EXT/INT Figure 37 shows an interface diagram between the AD7653 and BUSY PFx the SPI equipped ADSP-219x. To accommodate the slower CS SPIxSEL (PFx) RD speed of the DSP, the AD7653 acts as a slave device and data SDOUT MISOx INVSCLK SCLK SCKx must be read after conversion. This mode also allows the daisy- CNVST PFx or TFSx chain feature. The convert command can be initiated in response to an internal timer interrupt. The reading process can *ADDITIONAL PINS OMITTED FOR CLARITY 02966-0-021 be initiated in response to the end-of-conversion signal (BUSY Figure 37. Interfacing the AD7653 to an SPI Interface going LOW) using an interrupt line of the DSP. The serial inter- Rev. A | Page 24 of 28 AD7653 APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES Running digital lines under the device should be avoided since these will couple noise onto the die. The analog ground plane In some applications, it is desirable to use a bipolar or wider should be allowed to run under the AD7653 to avoid noise analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although coupling. Fast switching signals like or clocks should be CNVST the AD7653 has only one unipolar range, simple modifications shielded with digital ground to avoid radiating noise to other of input driver circuitry allow bipolar and wider input ranges to sections of the board, and should never run near analog signal be used without any performance degradation. Figure 38 shows paths. Crossover of digital and analog signals should be avoided. a connection diagram that allows this. Component values Traces on different but close layers of the board should run at required and resulting full-scale ranges are shown in Table 8. right angles to each other to will reduce the effect of crosstalk When desired, accurate gain and offset can be calibrated by through the board. acquiring a ground and voltage reference using an analog The power supply lines to the AD7653 should use as large a multiplexer (U2) as shown in Figure 38. trace as possible to provide low impedance paths and to reduce C F the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance R1 presented to the AD7653, and to reduce the magnitude of the R2 ANALOG supply spikes. Decoupling ceramic capacitors, typically 100 nF, 15Ω INPUT IN U1 should be placed on each power supply pin—AVDD, DVDD, 2.7nF and OVDD—close to, and ideally right up against these pins AD7653 and their corresponding ground pins. Additionally, low ESR U2 100nF R3 R4 10 µF capacitors should be located near the ADC to further INGND reduce low frequency ripple. REF The DVDD supply of the AD7653 can be a separate supply or C REF can come from the analog supply AVDD or the digital interface REFGND supply OVDD. When the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is 02966-0-022 available, the user should connect DVDD to AVDD through an RC filter (see Figure 22), and the system supply to OVDD and Figure 38. Using the AD7653 in 16-Bit Bipolar and/or Wider Input Ranges the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce Table 8. Component Values and Input Ranges high frequency spikes. Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ) ±10 V 500 4 2.5 2 The AD7653 has five different ground pins: INGND, REFGND, ±5 V 500 2 2.5 1.67 AGND, DGND, and OGND. INGND is used to sense the analog 0 V to –5 V 500 1 None 0 input signal. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to LAYOUT the reference. AGND is the ground to which most internal ADC The AD7653 has very good immunity to noise on the power analog signals are referenced; it must be connected with the supplies. However, care should still be taken with regard to least resistance to the analog ground plane. DGND must be tied grounding layout. to the analog or digital ground plane depending on the config- uration. OGND is connected to the digital system ground. The printed circuit board that houses the AD7653 should be designed so that the analog and digital sections are separated EVALUATING THE AD7653’S PERFORMANCE and confined to certain areas of the board. This facilitates the A recommended layout for the AD7653 is outlined in the use of ground planes that can be separated easily. Digital and EVAL-AD7653 evaluation board for the AD7653. The analog ground planes should be joined in only one place, evaluation board package includes a fully assembled and tested preferably underneath the AD7653, or as close as possible to the evaluation board, documentation, and software for controlling AD7653. If the AD7653 is in a system where multiple devices the board from a PC via the EVAL-CONTROL BRD2. require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7653. Rev. A | Page 25 of 28 AD7653 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 37 48 36 1 PIN 1 SEATING PLANE 10° TOP VIEW 7.00 1.45 6° (PINS DOWN) BSC SQ 0.20 1.40 2° 0.09 1.35 VIEW A 7° ° 12 25 3.5 13 24 0° 0.15 SEATING 0.05 0.08 MAX 0.27 0.50 PLANE COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 39. 48-Lead Quad Flatpack (LQFP)(ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 6.75 5.25 BOTTOM TOP BSC SQ VIEW 5.10 SQ VIEW 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 PADDLE CONNECTED TO AGND. 12° MAX 0.65 TYP THIS CONNECTION IS NOT 0.85 REQUIRED TO MEET THE 0.05 MAX 0.80 ELECTRICAL PERFORMANCES 0.02 NOM 0.50 BSC COPLANARITY 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) (CP-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7653AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7653ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7653ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 AD7653ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 1 EVAL-AD7653CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. A | Page 26 of 28 AD7653 NOTES Rev. A | Page 27 of 28 AD7653 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02966–0–9/03(A) Rev. A | Page 28 of 28