ANALOG DEVICES AD7651

TM 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference AD7651 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: 100 kSPS REFBUFIN REF REFGND DVDD DGND 16-bit resolution OVDD AGND AD7651 Analog input voltage range: 0 V to 2.5 V AVDD SERIAL OGND REF No pipeline delay PORT Parallel and serial 5 V/3 V interface 16 IN SWITCHED DATA[15:0] TM TM CAP DAC SPI®/QSPI /MICROWIRE /DSP compatible INGND BUSY PARALLEL Single 5 V supply operation PDREF INTERFACE RD PDBUF Power dissipation CLOCK CS PD 16 mW typ, 160 µW @ 1 kSPS without REF CONTROL LOGIC AND SER/PA R RESET CALIBRATION CIRCUITRY 38 mW typ with REF OB/2C 48-lead LQFP and 48-lead LFCSP packages BYTESWAP Pin-to-pin compatible with PulSAR ADCs CNVST 02964-0-001 APPLICATIONS Figure 1. Functional Block Diagram Data acquisition Table 1. PulSAR Selection Instrumentation 800– Digital signal processing Type/kSPS 100–250 500–570 1000 Spectrum analysis Pseudo- AD7651 AD7650/AD7652 AD7653 Medical instruments Differential AD7660/AD7661 AD7664/AD7666 AD7667 Battery-powered systems True Bipolar AD7663 AD7665 AD7671 Process control True AD7675 AD7676 AD7677 Differential GENERAL DESCRIPTION 18-Bit AD7678 AD7679 AD7674 The AD7651 is a 16-bit, 100 kSPS, charge redistribution SAR Multichannel/ AD7654 analog-to-digital converter that operates from a single 5 V Simultaneous AD7655 power supply. The part contains a high speed 16-bit sampling ADC, an internal conversion clock, internal reference, error PRODUCT HIGHLIGHTS correction circuits, and both serial and parallel system inter- 1. Fast Throughput. face ports. The AD7651 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. The AD7651 is fabricated using Analog Devices’ high perform- ance, 0.6 micron CMOS process, with correspondingly low cost, 2. Internal Reference. and is available in a 48-lead LQFP and a tiny 48-lead LFCSP The AD7651 has an internal reference with a typical with operation specified from –40°C to +85°C. temperature drift of 7 ppm/°C. 3. Single-Supply Operation. The AD7651 operates from a single 5 V supply. Its power dissipation decreases with throughput. 4. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. AD7651 TABLE OF CONTENTS Specifications..................................................................................... 3 Parallel Interface......................................................................... 20 Timing Specifications....................................................................... 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings............................................................ 7 Master Serial Interface............................................................... 21 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 22 Definitions of Specifications ......................................................... 11 Microprocessor Interfacing....................................................... 24 Typical Performance Characteristics ........................................... 12 Application Hints............................................................................ 25 Circuit Information ........................................................................ 15 Bipolar and Wider Input Ranges .............................................. 25 Converter Operation.................................................................. 15 Layout .......................................................................................... 25 Typical Connection Diagram.................................................... 17 Evaluating the AD7651’s Performance .................................... 25 Power Dissipation versus Throughput .................................... 19 Outline Dimensions ....................................................................... 26 Conversion Control.................................................................... 19 Ordering Guide........................................................................... 26 Digital Interface .......................................................................... 20 REVISION HISTORY Revision 0, Initial Version. Rev. 0 | Page 2 of 28 AD7651 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN – VINGND 0 VREF V Operating Input Voltage VIN –0.1 +3 V VINGND –0.1 +0.5 V Analog Input CMRR f = 10 kHz 65 dB IN Input Current 100 kSPS Throughput 1.1 µA 1 Input Impedance THROUGHPUT SPEED Complete Cycle 10 µs Throughput Rate 0 100 kSPS DC ACCURACY 2 Integral Linearity Error –6 +6 LSB No Missing Codes 15 Bits Differential Linearity Error –2 +3 LSB Transition Noise 0.7 LSB 3 Unipolar Zero Error, T to T ±5 LSB MIN MAX 3 Unipolar Zero Error Temperature Drift ±0.25 ppm/°C 3 Full-Scale Error, TMIN to TMAX REF = 2.5 V ±0.12 % of FSR Full-Scale Error Temperature Drift ±0.6 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB AC ACCURACY 4 Signal-to-Noise fIN = 45 kHz 86 dB Spurious Free Dynamic Range fIN = 45 kHz 98 dB Total Harmonic Distortion f = 10 kHz –98 dB IN f = 45 kHz –98 dB IN Signal-to-(Noise + Distortion) fIN = 45 kHz 86 dB –60 dB Input, fIN = 45 kHz 30 dB –3 dB Input Bandwidth 800 kHz SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 8.75 µs REFERENCE Internal Reference Voltage V @ 25°C 2.48 2.5 2.52 V REF Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C AVDD = 5 V ± 5% Line Regulation ±24 ppm/V Turn-On Settling Time CREF = 10 µF 5 ms Temperature Pin Voltage Output @ 25°C 300 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.3 kΩ External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 100 kSPS Throughput 35 µA Rev. 0 | Page 3 of 28 AD7651 Parameter Conditions Min Typ Max Unit DIGITAL INPUTS Logic Levels V –0.3 +0.8 V IL V 2.0 DVDD + 0.3 V IH IIL –1 +1 µA IIH –1 +1 µA DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay V I = 1.6 mA 0.4 V OL SINK VOH ISOURCE = –500 µA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V 7 OVDD 2.7 5.25 V Operating Current 100 kSPS Throughput 8 AVDD With Reference and Buffer 6.2 mA 9 AVDD Reference and Buffer Alone 3 mA 10 DVDD 1.5 mA 10 OVDD 18 µA 10 Power Dissipation without REF 100 kSPS Throughput 16 25 mW 1 kSPS Throughput 160 µW 10 Power Dissipation with REF 100 kSPS Throughput 38 45 mW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Input section. 2 LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. 3 See Definitions of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or Serial 16-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 9 With PDREF, PDBUF LOW and PD HIGH. 10 Tested in Parallel Reading Mode 11 Consult factory for extended temperature range. Rev. 0 | Page 4 of 28 AD7651 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit Refer to Figure 26 and Figure 27 Convert Pulse Width t1 10 ns Time between Conversions t2 10 µs CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t 1.25 µs 4 t Aperture Delay 5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.25 µs Acquisition Time t 8.75 µs 8 RESET Pulse Width t 10 ns 9 Refer to Figure 28, Figure 29, and Figure 30 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 12 ns Bus Access Request to DATA Valid t 45 ns 12 Bus Relinquish Time t 5 15 ns 13 1 Refer to Figure 32 and Figure 33 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay t14 10 ns 1 CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t 10 ns 16 CNVST LOW to SYNC Delay t 525 ns 17 SYNC Asserted to SCLK First Edge Delay t18 3 ns 2 Internal SCLK Period t19 25 40 ns 2 Internal SCLK HIGH t20 12 ns 2 Internal SCLK LOW t 7 ns 21 2 t SDOUT Valid Setup Time 22 4 ns 2 SDOUT Valid Hold Time t23 2 ns 2 SCLK Last Edge to SYNC Delay t24 3 ns CS HIGH to SYNC HI-Z t 10 ns 25 CS HIGH to Internal SCLK HI-Z t 10 ns 26 CS HIGH to SDOUT HI-Z t27 10 ns 2 BUSY HIGH in Master Serial Read after Convert t28 See Table 4 CNVST LOW to SYNC Asserted Delay t29 1.25 µs SYNC Deasserted to BUSY LOW Delay t 25 ns 30 1 Refer to Figure 34 and Figure 35 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t 5 ns 33 SDIN Hold Time t 5 ns 34 External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 2 In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode. Rev. 0 | Page 5 of 28 AD7651 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t 3 17 17 17 ns 18 Internal SCLK Period Minimum t 25 50 100 200 ns 19 Internal SCLK Period Maximum t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t 7 21 49 99 ns 21 SDOUT Valid Setup Time Minimum t 4 18 18 18 ns 22 SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns BUSY HIGH Width Maximum t 2 2.5 3.5 5.75 µs 24 Rev. 0 | Page 6 of 28 AD7651 ABSOLUTE MAXIMUM RATINGS 1 Table 5. AD7651 Stress Ratings 1.6mA I 2 2 OL IN , TEMP ,REF, REFBUFIN, AVDD + 0.3 V to INGND, REFGND to AGND AGND – 0.3 V TO OUTPUT Ground Voltage Differences 1.4V PIN C L AGND, DGND, OGND ±0.3 V 60pF* Supply Voltages I 500µA OH AVDD, DVDD, OVDD –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V *IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD DVDD to OVDD –0.3 V to +7 V C OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. L 02964-0-006 Digital Inputs –0.3 V to DVDD + 0.3 V 3 PDREF, PDBUF ±20 mA Figure 2. Load Circuit for Digital Interface Timing, 4 SDOUT, SYNC, SCLK Outputs CL = 10 pF Internal Power Dissipation 700 mW 5 Internal Power Dissipation 2.5 W Junction Temperature 150°C 2V 0.8V Storage Temperature Range –65°C to +150°C t t DELAY DELAY Lead Temperature Range 300°C 2V 2V (Soldering 10 sec) 0.8V 0.8V 02965-0-007 1 Stresses above those listed under Absolute Maximum Ratings may cause Figure 3. Voltage Reference Levels for Timing permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 See Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W 5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD7651 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 2 IDENTIFIER AVDD 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7651 NC 6 31 RD TOP VIEW NC 7 30 DGND (Not to Scale) SER/PAR 8 29 BUSY D0 9 28 D15 10 D1 27 D14 11 D2/DIVSCLK0 26 D13 12 D3/DIVSCLK1 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT 02965-0-002 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 6, NC No Connect. 7, 40 4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 8 DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial SER/PAR interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. 13 D4 or DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. Rev. 0 | Page 8 of 28 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN DVDD AGND DGND AGND D8/SDOUT NC D9/SCLK INGND D10/SYNC REFGND D11/RDERROR REF AD7651 1 Pin No. Mnemonic Type Description 16 D7 or DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. 21 D8 or DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7651 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D9 or DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 or DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. 24 D11 or DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When RDERROR SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7651 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t ) is 8 complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 37 REF AI/O Reference Input Voltage. On-chip reference output voltage. 38 REFGND AI Reference Input Analog Ground. 39 INGND AI Analog Input Ground. Rev. 0 | Page 9 of 28 AD7651 1 Pin No. Mnemonic Type Description 43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V. 45 TEMP AO Temperature Sensor Voltage Output. 46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input. 47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used. 48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer. When LOW, the buffer is selected. When HIGH, the buffer is switched off. 1 AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Rev. 0 | Page 10 of 28 AD7651 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal, and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal-to-Noise Ratio (SNR) 1½ LSB beyond the last code transition. The deviation is SNR is the ratio of the rms value of the actual input signal to the measured from the middle of each code to the true straight line. rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, excluding harmonics and dc. The value for SNR is In an ideal ADC, code transitions are 1 LSB apart. Differential expressed in decibels. nonlinearity is the maximum deviation from this ideal value. It Signal-to-(Noise + Distortion) Ratio (S/[N+D]) is often specified in terms of resolution for which no missing S/(N+D) is the ratio of the rms value of the actual input signal codes are guaranteed. to the rms sum of all other spectral components below the Full-Scale Error Nyquist frequency, including harmonics but excluding dc. The The last transition (from 011…10 to 011…11 in twos value for S/(N+D) is expressed in decibels. complement coding) should occur for an analog voltage 1½ LSB Aperture Delay below the nominal full scale (2.49994278 V for the 0 V to 2.5 V Aperture delay is a measure of the acquisition performance and range). The full-scale error is the deviation of the actual level of is measured from the falling edge of the input to when CNVST the last transition from the ideal level. the input signal is held for a conversion. Unipolar Zero Error Transient Response The first transition should occur at a level ½ LSB above analog Transient response is the time required for the AD7651 to ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero achieve its rated accuracy after a full-scale step function is error is the deviation of the actual transition from that point. applied to its input. Spurious-Free Dynamic Range (SFDR) Overvoltage Recovery SFDR is the difference, in decibels (dB), between the rms Overvoltage recovery is the time required for the ADC to amplitude of the input signal and the peak spurious signal. recover to full accuracy after an analog input signal 150% of the Effective Number Of Bits (ENOB) full-scale value is reduced to 50% of the full-scale value. ENOB is a measurement of the resolution with a sine wave Reference Voltage Temperature Coefficient input. It is related to S/(N+D) by the following formula: Reference voltage temperature coefficient is the change of ENOB = (S/[N+D]dB – 1.76)/6.02 internal reference voltage output voltage V over the operating temperature range and normalized by the output voltage at and is expressed in bits. 25°C, expressed in ppm/°C. The equation follows: V(T 2) –V(T1) 6 TCV(ppm/°C)= ×10 V(25°C)×(T 2 –T1) where: V(25°C) = V at +25°C V(T2) = V at Temperature 2 (+85°C) V(T1) = V at Temperature 1 (–40°C) Rev. 0 | Page 11 of 28 AD7651 TYPICAL PERFORMANCE CHARACTERISTICS 4 2.0 3 1.5 2 1.0 1 0 0.5 –1 0 –2 –0.5 –3 –4 –1.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE 02964-0-026 02964-0-023 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 140000 180000 155528 160000 120000 114156 114686 140000 100000 120000 80000 100000 80000 60000 60000 51585 49184 40000 40000 20890 20000 10822 20000 479 2896 1903 00 137 0 0 019 50 0 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX CODE IN HEX 02964-0-027 02964-0-028 Figure 6. Histogram of 261,120 Conversions of a Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Transition DC Input at the Code Center 15.5 0 90 f = 100kSPS S 89 –20 f = 45.7kHz IN SNR = 86.7dB 88 15.0 THD = 102.5dB –40 SFDR = 103.6dB S/[N+D] = 86.6dB 87 –60 86 14.5 –80 SNR 85 –100 14.0 84 S/[N+D] –120 83 ENOB –140 82 13.5 –160 81 –180 80 13.0 0 10 20 30 40 50 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) 02964-0-029 02964-0-030 Figure 7. FFT Plot Figure 10. SNR, S/(N+D), and ENOB vs. Frequency Rev. 0 | Page 12 of 28 COUNTS AMPLITUDE (dB of Full Scale) INL (LSB) COUNTS SNR, S/[N+D] (dB) DNL (LSB) ENOB (Bits) AD7651 –70 120 –100 110 –75 SFDR 100 –80 –105 –85 90 THD 80 –90 70 –110 –95 –100 60 SECOND THD THIRD HARMONIC –105 50 HARMONIC SECOND –115 HARMONIC 40 –110 THIRD HARMONIC –115 30 –120 20 –120 –55 –35 –1558 25 45 655 105 125 1 10 100 1000 FREQUENCY (kHz) TEMPERATURE (°C) 02964-0-034 02964-0-031 Figure 14. THD and Harmonics vs. Temperature Figure 11. THD, Harmonics, and SFDR vs. Frequency 90 10000 AVDD 1000 89 DVDD 100 88 10 SNR 1 87 OVDD S/[N+D] 0.1 86 0.01 PDREF = PDBUF = HIGH 0.001 85 10 100 1000 10000 100000 –60 –50 –40 –30 –20 –10 0 INPUT LEVEL (dB) SAMPLE RATE (SPS) 02964-0-032 02964-0-035 Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) Figure 15. Operating Current vs. Sample Rate 89 15.5 6 5 4 88 3 15.0 FULL SCALE 2 1 87 SNR 14.5 0 –1 86 ZERO ERROR S/[N+D] –2 14.0 –3 85 –4 –5 13.5 –6 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (dB) TEMPERATURE (°C) 02964-0-036 02964-0-033 Figure 16. Zero Error, Full Scale with Reference vs. Temperature Figure 13. SNR, S/(N+D), and ENOB vs. Temperature Rev. 0 | Page 13 of 28 THD, HARMONICS (dB) SNR, S/[N+D] (dB) SNR, S/[N+D] REFERRED TO FULL SCALE (dB) ENOB (Bits) SFDR (dB) OPERATING CURRENT (µA) THD, HARMONICS (dB) ZERO ERROR, FULL SCALE (LSB) AD7651 2.5042 50 OVDD = 2.7V @ 85°C 2.5040 40 OVDD = 2.7V @ 25°C 2.5038 30 2.5036 OVDD = 5V @ 85°C 2.5034 20 OVDD = 5V @ 25°C 2.5032 10 2.5030 2.5028 0 –40 –20 020 40 60 80 100 120 0 50 100 150 200 TEMPERATURE (°C) C (pF) L 02964-0-037 02964-0-039 Figure 17. Typical Reference Output Voltage vs. Temperature Figure 19. Typical Delay vs. Load Capacitance C L 25 20 15 10 5 0 –30 –26 –22 –18 –14 –10 –6 –2 2 6 10 14 18 22 26 30 REFERENCE DRIFT (ppm/°C) 02965-0-040 Figure 18. Reference Voltage Temperature Coefficient Distribution (100 Units) Rev. 0 | Page 14 of 28 VREF (V) NUMBER OF UNITS t DELAY (ns) 12 AD7651 CIRCUIT INFORMATION IN REF REFGND SWITCHES CONTROL SW MSB LSB A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC INGND OUTPUT 65,536C CODE SW B CNVST 02964-0-005 Figure 20. ADC Simplified Schematic The AD7651 is a very fast, low power, single supply, precise During the acquisition phase, the common terminal of the array 16-bit analog-to-digital converter (ADC). tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the analog The AD7651 provides the user with an on-chip track/hold, input IN. Thus, the capacitor array is used as a sampling successive approximation ADC that does not exhibit any capacitor and acquires the analog signal on IN. Similarly, the pipeline or latency, making it ideal for multiple multiplexed dummy capacitor acquires the analog signal on INGND. channel applications. When goes LOW, a conversion phase is initiated. When CNVST The AD7651 can be operated from a single 5 V supply and can the conversion phase begins, SWA and SWB are opened. The be interfaced to either 5 V or 3 V digital logic. It is housed in capacitor array and dummy capacitor are then disconnected either a 48-lead LQFP or a 48-lead LFCSP that saves space and from the inputs and connected to REFGND. Therefore, the allows flexible configurations as either a serial or parallel inter- differential voltage between IN and INGND captured at the end face. The AD7651 is pin-to-pin compatible with PulSAR ADCs. of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching CONVERTER OPERATION each element of the capacitor array between REFGND and REF, The AD7651 is a successive-approximation ADC based on a the comparator input varies by binary weighted voltage steps charge redistribution DAC. Figure 20 shows a simplified sche- (VREF/2, VREF/4, …VREF/65536). The control logic toggles these matic of the ADC. The capacitive DAC consists of an array of 16 switches, starting with the MSB, to bring the comparator back binary weighted capacitors and an additional LSB capacitor. The into a balanced condition. comparator’s negative input is connected to a dummy capacitor of the same value as the capacitive DAC array. After this process is completed, the control logic generates the ADC output code and brings the BUSY output LOW. Rev. 0 | Page 15 of 28 AD7651 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Digital Output Code (Hex) 2C Using the OB/ digital input, the AD7651 offers two output Analog Straight Twos codings: straight binary and twos complement. The LSB size is Description Input Binary Complement V /65536, which is about 38.15 µV. The AD7651’s ideal REF 1 FSR –1 LSB 2.499962 V FFFF 7FFF1 transfer characteristic is shown in Figure 21 and Table 7. FSR – 2 LSB 2.499923 V FFFE 7FFE Midscale + 1 LSB 1.250038 V 8001 0001 1 LSB = V /65536 REF Midscale 1.25 V 8000 0000 111...111 Midscale – 1 LSB 1.249962 V 7FFF FFFF 111...110 –FSR + 1 LSB 38 µV 0001 8001 111...101 2 2 –FSR 0 V 0000 8000 1 This is also the code for overrange analog input (VIN – VINGND above V – V ). REF REFGND 2 This is also the code for underrange analog input (V below V ). IN INGND 000...010 000...001 000...000 0V 1LSB V – 1 LSB REF 0.5 LSB V – 1.5 LSB REF ANALOG INPUT 02964-0-003 Figure 21. ADC Ideal Transfer Function ANALOG 20Ω DIGITAL SUPPLY SUPPLY (3.3V OR 5V) (5V) + + + 100nF 100nF 100nF 10µF 10µF 10µF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT SCLK REF SDOUT 4 1 C REFBUFIN R 100nF µC/µP/DSP REFGND BUSY AD7651 3 CNVST D 2 U1 IN OB/2C ANALOG INPUT (0VTO 2.5V) DVDD SER/PAR C C INGND CS RD BYTESWAP PDREF PD PDBUF RESET CLOCK NOTES 1 THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER. 2 THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3 OPTIONAL LOW JITTER. 4 A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 02964-0-004 Figure 22. Typical Connection Diagram Rev. 0 | Page 16 of 28 ADC CODE (Straight Binary) AD7651 Driver Amplifier Choice TYPICAL CONNECTION DIAGRAM Although the AD7651 is easy to drive, the driver amplifier needs Figure 22 shows a typical connection diagram for the AD7651. to meet the following requirements: Analog Input Figure 23 shows an equivalent circuit of the input structure of • The driver amplifier and the AD7651 analog input circuit the AD7651. must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data The two diodes, D1 and D2, provide ESD protection for the sheet, settling at 0.1% to 0.01% is more commonly speci- analog inputs IN and INGND. Care must be taken to ensure fied. This could differ significantly from the settling time at that the analog input signal never exceeds the supply rails by a 16-bit level and should be verified prior to driver more than 0.3 V. This will cause these diodes to become selection. The tiny op amp OP184, which combines ultra forward-biased and start conducting current. These diodes can low noise and high gain-bandwidth, meets this settling handle a forward-biased current of 100 mA maximum. For time requirement. instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from AVDD. In such a • The noise generated by the driver amplifier needs to be case, an input buffer with a short-circuit current limitation can kept as low as possible in order to preserve the SNR and be used to protect the part. transition noise performance of the AD7651. The noise coming from the driver is filtered by the AD7651 analog AVDD input circuit 1-pole low-pass filter made by R1 and C2 or D1 C2 R1 by the external filter, if one is used. IN OR INGND C1 D2 • The driver needs to have a THD performance suitable to AGND that of the AD7651. 02965-0-008 The OP184, OP162 or AD8519 meet these requirements and are Figure 23. Equivalent Analog Input Circuit usually appropriate for almost all applications. As an alternative, in very high speed and noise-sensitive applications, the AD8021 with an external 10 pF compensation capacitor can be used. This analog input structure allows the sampling of the This capacitor should have good linearity as an NPO ceramic or differential signal between IN and INGND. Unlike other mica type. Moreover, the use of a noninverting +1 gain converters, INGND is sampled at the same time as IN. By using arrangement is recommended and helps to obtain the best this differential input, small signals common to both inputs are signal-to-noise ratio. rejected. For instance, by using INGND to sense a remote signal ground, ground potential differences between the sensor and The AD8022 could also be used if a dual version is needed and the local ADC ground are eliminated. gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not During the acquisition phase, the impedance of the analog input required. In gain of 1 applications, it requires an 82 pF IN can be modeled as a parallel combination of capacitor C1 compensation capacitor. The AD8610 is an option when low and the network formed by the series connection of R1 and C2. bias current is needed in low frequency applications. C1 is primarily the pin capacitance. R1 is typically 3250 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 60 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. R1 and C2 make a 1-pole low-pass filter that reduces undesirable aliasing effect and limits the noise. When the source impedance of the driving circuit is low, the AD7651 can be driven directly. Large source impedances will significantly affect the ac performance, especially total harmonic distortion. Rev. 0 | Page 17 of 28 AD7651 Voltage Reference Input The AD7651 allows the choice of either a very low temperature For applications that use multiple AD7651s, it is more effective drift internal voltage reference or an external 2.5 V reference. to use the internal buffer to buffer the reference voltage. Unlike many ADCs with internal references, the internal Care should be taken with the voltage reference’s temperature reference of the AD7651 provides excellent performance and coefficient, which directly affects the full-scale accuracy if this can be used in almost all applications. parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. To use the internal reference along with the internal buffer, PDREF and PDBUF should both be LOW. This will produce a Note that VREF can be increased to AVDD – 1.85 V. Since the 1.207 V voltage on REFBUFIN which, amplified by the buffer, input range is defined in terms of VREF, this would essentially will result in a 2.5 V reference on the REF pin. increase the range to 0 V to 3 V with an AVDD above 4.85 V. The AD780 can be selected with a 3 V reference voltage. The output impedance of REFBUFIN is 11 kΩ (minimum) when the internal reference is enabled. It is useful to decouple The TEMP pin, which measures the temperature of the AD7651, REFBUFIN with a 100 nF ceramic capacitor. Thus, the 100 nF can be used as shown in Figure 24. The output of TEMP pin is capacitor provides an RC filter for noise reduction. applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own temperature. This To use an external reference along with the internal buffer, configuration is very useful for improving the calibration PDREF should be HIGH and PDBUF should be LOW. This accuracy over the temperature range. powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN. TEMP ADG779 To use an external reference directly on REF pin, PDREF and TEMPERATURE PDBUF should both be HIGH. SENSOR ANALOG INPUT IN (UNIPOLAR) AD7651 C AD8021 C PDREF and PDBUF respectively power down the internal 02964-0-024 reference and the internal reference buffer. Note that the PDREF Figure 24. Temperature Sensor Connection Diagram and PDBUF input current should never exceed 20 mA. This could eventually occur when input voltage is above AVDD (for Power Supply instance at power up). In this case, a 100 Ω series resistor is The AD7651 uses three power supply pins: an analog 5 V supply recommended. AVDD, a digital 5 V core supply DVDD, and a digital input/ The internal reference is temperature compensated to 2.5 V ± output interface supply OVDD. OVDD allows direct interface 20 mV. The reference is trimmed to provide a typical drift of 7 with any logic between 2.7 V and DVDD + 0.3 V. To reduce the ppm/°C. This typical drift characteristic is shown in Figure 17. supplies needed, the digital core (DVDD) can be supplied For improved drift performance, an external reference such as through a simple RC filter from the analog supply, as shown in the AD780 can be used. Figure 22. The AD7651 is independent of power supply sequencing once OVDD does not exceed DVDD by more than The AD7651 voltage reference input REF has a dynamic input 0.3 V, and is thus free of supply voltage induced latch-up. impedance; it should therefore be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR tantalum capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 • The low power ADR291 • The low cost AD1582 Rev. 0 | Page 18 of 28 AD7651 POWER DISSIPATION VERSUS THROUGHPUT The trace should be shielded with ground and a low CNVST Operating currents are very low during the acquisition phase, value serial resistor (i.e., 50 Ω) termination should be added allowing significant power savings when the conversion rate is close to the output of the component that drives this line. reduced (see Figure 25). The AD7651 automatically reduces its power consumption at the end of each conversion phase. This For applications where SNR is critical, the CNVST signal should makes the part ideal for very low power battery applications. have very low jitter. This may be achieved by using a dedicated The digital interface and the reference remain active even oscillator for CNVST generation, or to clock CNVST with a during the acquisition phase. To reduce operating digital supply high frequency, low jitter clock, as shown in Figure 22. currents even further, digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND), and OVDD should not exceed DVDD by more than 0.3 V. t 2 t 1 CNVST 100000 BUSY 10000 t 4 t 3 t 6 t 5 MODE ACQUIRE CONVERT ACQUIRE CONVERT 1000 t t 7 8 02964-0-011 100 Figure 26. Basic Conversion Timing t 9 PDREF = PDBUF = PDHIGH 10 RESET 10 100 1k 10k 100k SAMPLING RATE (SPS) 02964-0-038 BUSY Figure 25. Power Dissipation vs. Sampling Rate DATA CONVERSION CONTROL t 8 Figure 26 shows the detailed timing diagrams of the conversion process. The AD7651 is controlled by the CNVST signal, which CNVST initiates conversion. Once initiated, it cannot be restarted or 02964-0-011 aborted, even by the power-down input PD, until the conversion is complete. CNVST operates independently of CS and RD. Figure 27. RESET Timing Conversions can be automatically initiated with the AD7651. If CS = RD = 0 is held LOW when BUSY is LOW, the AD7651 controls CNVST t 1 the acquisition phase and automatically initiates a new CNVST conversion. By keeping CNVST LOW, the AD7651 keeps the t 10 conversion process running by itself. It should be noted that the BUSY analog input must be settled when BUSY goes LOW. Also, at t 4 power-up, CNVST should be brought LOW once to initiate the t 3 t 11 conversion process. In this mode, the AD7651 can run slightly DATA faster than the guaranteed 100 kSPS. PREVIOUS CONVERSION DATA NEW DATA BUS 02964-0-012 Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum Figure 28. Master Parallel Data Timing for Reading (Continuous Read) overshoot and undershoot or ringing. Rev. 0 | Page 19 of 28 POWER DISSIPATION (µW) AD7651 DIGITAL INTERFACE CS The AD7651 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel RD interface. The serial interface is multiplexed on the parallel data bus. The AD7651 digital interface also accommodates both 3 V and 5 V logic by simply connecting the OVDD supply pin of the AD7651 to the host system interface digital supply. Finally, by BUSY using the OB/2C input pin, both twos complement or straight binary coding can be used. DATA CURRENT BUS CONVERSION The two signals, CS and RD, control the interface. CS and RD t t 12 13 have a similar effect because they are OR’d together internally. 02964-0-013 When at least one of these signals is HIGH, the interface outputs are in high impedance. Usually allows the selection CS Figure 29. Slave Parallel Data Timing for Reading (Read after Convert) of each AD7651 in multicircuit applications and is held low in a single AD7651 design. RD is generally used to enable the CS = 0 conversion result on the data bus. CNVST, t 1 RD PARALLEL INTERFACE The AD7651 is configured to use the parallel interface when SER/ is held LOW. The data can be read either after each PAR BUSY t 4 conversion, which is during the next acquisition phase, or t 3 during the following conversion, as shown in Figure 29 and Figure 30, respectively. When the data is read during the DATA PREVIOUS conversion, however, it is recommended that it is read only CONVERSION BUS during the first half of the conversion phase. This avoids any t t 12 13 02964-0-014 potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. Figure 30. Slave Parallel Data Timing for Reading (Read during Convert) The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 31, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is LOW. When CS BYTESWAP is HIGH, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. RD By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. BYTESWAP SERIAL INTERFACE HI-Z HI-Z HIGH BYTE LOW BYTE PINS D[15:8] The AD7651 is configured to use the serial interface when SER/ is held HIGH. The AD7651 outputs 16 bits of data, t t t PAR 12 12 13 HI-Z HI-Z MSB first, on the SDOUT pin. This data is synchronized with PINS D[7:0] LOW BYTE HIGH BYTE the 16 clock pulses provided on the SCLK pin. The output data 02964-0-025 is valid on both the rising and falling edges of the data clock. Figure 31. 8-Bit Parallel Interface Rev. 0 | Page 20 of 28 AD7651 Usually, because the AD7651 has a longer acquisition phase than MASTER SERIAL INTERFACE Internal Clock the conversion phase, the data is read immediately after conversion. This makes the Master Read After Conversion the most recom- The AD7651 is configured to generate and provide the serial data mended serial mode when it can be used. In this mode, it should be clock SCLK when the EXT/INT pin is held LOW. The AD7651 also noted that unlike in other modes, the BUSY signal returns LOW generates a SYNC signal to indicate to the host when the serial data after the 16 data bits are pulsed out and not at the end of the is valid. The serial clock SCLK and the SYNC signal can be inverted conversion phase, which results in a longer BUSY width. if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 32 In the Read During Conversion mode, the serial clock and data and Figure 33 show detailed timing diagrams of these two modes. toggle at appropriate instants, which minimize potential feed- through between digital activity and critical conversion decisions RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 14 18 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 02964-0-015 Figure 32. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 02964-0-016 Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 21 of 28 AD7651 SLAVE SERIAL INTERFACE External Clock While the AD7651 is performing a bit decision, it is important The AD7651 is configured to accept an externally supplied that voltage transients be avoided on digital input/output pins or serial data clock on the SCLK pin when the EXT/INT pin is held degradation of the conversion result could occur. This is HIGH. In this mode, several methods can be used to read the particularly important during the second half of the conversion data. The external serial clock is gated by . When and CS CS RD phase because the AD7651 provides error correction circuitry are both LOW, the data can be read after each conversion or that can correct for an improper bit decision made during the during the following conversion. The external clock can be first half of the conversion phase. For this reason, it is either a continuous or a discontinuous clock. A discontinuous recommended that when an external clock is being provided, it clock can be either normally HIGH or normally LOW when is a discontinuous clock that is toggling only when BUSY is inactive. Figure 34 and Figure 35 show the detailed timing LOW, or, more importantly, that it does not transition during the diagrams of these methods. Usually, because the AD7651 has a latter half of BUSY HIGH. longer acquisition phase than conversion phase, the data are read immediately after conversion. EXT/INT = 1 RD = 0 INVSCLK = 0 RD BUSY t 35 t t 36 37 SCLK 1 2 3 14 151617 18 t 31 t 32 X SDOUT D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 02964-0-017 Figure 34. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 SDOUT X D15 D14 D13 D1 D0 t 02965-0-018 16 Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 22 of 28 AD7651 External Discontinuous Clock Data Read After External Clock Data Read During Conversion Conversion Figure 35 shows the detailed timing diagrams of this method. Though the maximum throughput cannot be achieved using During a conversion, while both and are LOW, the result CS RD this mode, it is the most recommended of the serial slave modes. of the previous conversion can be read. The data is shifted out Figure 34 shows the detailed timing diagrams of this method. MSB first with 16 clock pulses, and is valid on both the rising After a conversion is complete, indicated by BUSY returning and falling edges of the clock. The 16 bits must be read before LOW, the conversion’s result can be read while both CS and RD the current conversion is complete; otherwise, RDERROR is are LOW. Data is shifted out MSB first with 16 clock pulses and pulsed HIGH and can be used to interrupt the host interface to is valid on the rising and falling edges of the clock. prevent incomplete data reading. There is no daisy-chain feature in this mode and the RDC/SDIN input should always be tied Among the advantages of this method is the fact that conversion either HIGH or LOW. performance is not degraded because there are no voltage transients on the digital interface during the conversion process. To reduce performance degradation due to digital activity, a fast Another advantage is the ability to read the data at any speed up discontinuous clock of at least 18 MHz is recommended to to 40 MHz, which accommodates both the slow digital host ensure that all the bits are read during the first half of the interface and the fastest serial reading. conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new Finally, in this mode only, the AD7651 provides a daisy-chain conversion has been initiated. This allows the use of a slower feature using the RDC/SDIN pin for cascading multiple con- clock speed like 14 MHz. verters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 36. Simultaneous sampling is possible by using a common signal. It should be noted that the RDC/SDIN CNVST input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7651 AD7651 #2 #1 (UPSTREAM) (DOWNSTREAM) DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT CNVST CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 02964-0-019 Figure 36. Two AD7651s in a Daisy-Chain Configuration Rev. 0 | Page 23 of 28 AD7651 (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit MICROPROCESSOR INTERFACING (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by The AD7651 is ideally suited for traditional dc measurement writing to the SPI control register (SPICLTx). To meet all timing applications supporting a microprocessor, and for ac signal requirements, the SPI clock should be limited to 17 Mbps, which processing applications interfacing to a digital signal processor. allows it to read an ADC result in less than 1 µs. When a higher The AD7651 is designed to interface either with a parallel 8-bit sampling rate is desired, use of one of the parallel interface or 16-bit wide interface, or with a general-purpose serial port or modes is recommended. I/O ports on a microcontroller. A variety of external buffers can be used with the AD7651 to prevent digital noise from coupling DVDD into the ADC. The following section discusses the use of an ADSP-219x* AD7651* AD7651 with an ADSP-219x SPI equipped DSP. SER/PAR SPI Interface (ADSP-219x) EXT/INT Figure 37 shows an interface diagram between the AD7651 and BUSY PFx CS SPIxSEL (PFx) the SPI equipped ADSP-219x. To accommodate the slower RD SDOUT MISOx speed of the DSP, the AD7651 acts as a slave device and data INVSCLK SCLK SCKx must be read after conversion. This mode also allows the daisy- CNVST PFx or TFSx chain feature. The convert command can be initiated in *ADDITIONAL PINS OMITTED FOR CLARITY response to an internal timer interrupt. The reading process can 02964-0-021 be initiated in response to the end-of-conversion signal (BUSY Figure 37. Interfacing the AD7651 to an SPI Interfac going LOW) using an interrupt line of the DSP. The serial inter- face (SPI) on the ADSP-219x is configured for master mode— Rev. 0 | Page 24 of 28 AD7651 APPLICATION HINTS be established as close as possible to the AD7651. BIPOLAR AND WIDER INPUT RANGES In some applications, it is desirable to use a bipolar or wider Running digital lines under the device should be avoided since analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although these will couple noise onto the die. The analog ground plane the AD7651 has only one unipolar range, simple modifications should be allowed to run under the AD7651 to avoid noise of input driver circuitry allow bipolar and wider input ranges to coupling. Fast switching signals like or clocks should be CNVST be used without any performance degradation. Figure 38 shows shielded with digital ground to avoid radiating noise to other a connection diagram that allows this. Component values sections of the board, and should never run near analog signal required and resulting full-scale ranges are shown in Table 8. paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at When desired, accurate gain and offset can be calibrated by right angles to each other. This will reduce the effect of crosstalk acquiring a ground and voltage reference using an analog through the board. multiplexer (U2), as shown in Figure 38. The power supply lines to the AD7651 should use as large a C F trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is R1 also important to lower the supply’s impedance presented to the AD7651 and to reduce the magnitude of the supply spikes. R2 ANALOG INPUT Decoupling ceramic capacitors, typically 100 nF, should be U1 IN placed on each power supply pin—AVDD, DVDD, and OVDD—close to, and ideally right up against these pins and AD7651 U2 R3 R4 100nF their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located near the ADC to further reduce INGND low frequency ripple. REF C REF The DVDD supply of the AD7651 can be a separate supply or can come from the analog supply AVDD or the digital interface REFGND supply OVDD. When the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is 02964-0-022 available, the user should connect DVDD to AVDD through an Figure 38. Using the AD7651 in 16-Bit Bipolar and/or Wider Input Ranges RC filter (see Figure 22) and the system supply to OVDD and the remaining digital circuitry. When DVDD is powered from Table 8. Component Values and Input Ranges the system supply, it is useful to insert a bead to further reduce Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ) high frequency spikes. ±10 V 500 4 2.5 2 ±5 V 500 2 2.5 1.67 The AD7651 has five different ground pins: INGND, REFGND, 0 V to –5 V 500 1 None 0 AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and, because LAYOUT it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC The AD7651 has very good immunity to noise on the power analog signals are referenced; it must be connected with the supplies. However, care should still be taken with regard to least resistance to the analog ground plane. DGND must be tied grounding layout. to the analog or digital ground plane depending on the The printed circuit board that houses the AD7651 should be configuration. OGND is connected to the digital system designed so the analog and digital sections are separated and ground. confined to certain areas of the board. This facilitates the use of EVALUATING THE AD7651’S PERFORMANCE ground planes that can be separated easily. Digital and analog A recommended layout for the AD7651 is outlined in the ground planes should be joined in only one place, preferably EVAL-AD7651 evaluation board for the AD7651. The underneath the AD7651, or as close as possible to the AD7651. evaluation board package includes a fully assembled and tested If the AD7651 is in a system where multiple devices require evaluation board, documentation, and software for controlling analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should the board from a PC via the EVAL-CONTROL BRD2. Rev. 0 | Page 25 of 28 AD7651 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 37 48 1 36 PIN 1 SEATING 10° PLANE TOP VIEW 7.00 1.45 6° 0.20 (PINS DOWN ) BSC SQ 2° 1.40 0.09 1.35 VIEW A 7° 3.5° 12 25 0.15 0° 24 13 SEATING 0.05 0.10 MAX 0.27 PLANE 0.50 COPLANARITY 0.22 BSC VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 39. 48-Lead Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR 5.25 6.75 BOTTOM TOP BSC SQ 5.10 SQ VIEW VIEW 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 PADDLE CONNECTED TO AGND.
12° MAX 0.65 TYP THIS CONNECTION IS NOT 0.85 REQUIRED TO MEET THE 0.05 MAX 0.80 ELECTRICAL PERFORMANCES 0.02 NOM COPLANARITY 0.50 BSC 0.20 REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48] Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7651AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7651ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7651ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 AD7651ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48 1 EVAL-AD7651CB Evaluation Board 2 EVAL-CONTROL BRD2 Controller Board 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. 0 | Page 26 of 28 AD7651 NOTES Rev. 0 | Page 27 of 28 AD7651 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C02964–0–9/03(0) Rev. 0 | Page 28 of 28