ANALOG DEVICES AD7643

® 18-Bit, 1.25 MSPS PulSAR ADC AD7643 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND Throughput: 1.25 MSPS INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale) AGND 18-bit resolution with no missing codes OVDD AD7643 AVDD OGND Dynamic range: 95 dB typical REF REF AMP SINAD: 93.5 dB typical @ 20 kHz (VREF = 2.5 V) SERIAL PORT THD: −113 dB typical @ 20 kHz (V = 2.5 V) 18 REF IN+ SWITCHED D[17:0] CAP DAC 2.048 V internal reference: typical drift 8 ppm/°C; TEMP output IN– MODE0 PARALLEL Differential input range: ±VREF (VREF up to 2.5 V) INTERFACE MODE1 No pipeline delay (SAR architecture) PDREF BUSY CLOCK Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface PDBUF RD CONTROL LOGIC AND PD CS SPI®/QSPI™/MICROWIRE™/DSP compatible CALIBRATION CIRCUITRY RESET D0/OB/2C Single 2.5 V supply operation Power dissipation CNVST 65 mW typical @ 1.25 MSPS with internal REF Figure 1. 2 μW in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Table 1. PulSAR 48-Lead Selection Pin compatible with the AD7641 and other PulSAR ADC’s 100 to 500 to 650 to Type/kSPS 250 570 1000 >1000 APPLICATIONS Pseudo AD7651, AD7650, AD7653, AD7660, AD7652, AD7667 Differential Medical instruments AD7661 AD7664, High speed data acquisition/high dynamic data acquisition AD7666 Digital signal processing True Bipolar AD7610, AD7665 AD7612, Spectrum analysis AD7663 AD7671 Instrumentation True AD7675 AD7676 AD7677 AD7621, Communications Differential AD7622, AD7623 ATE 18-Bit AD7631, AD7679 AD7634, AD7641, Multichannel/ AD7678 AD7674 AD7643 GENERAL DESCRIPTION Simultaneous AD7654 AD7655 The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that PRODUCT HIGHLIGHTS operates from a single 2.5 V power supply. The part contains a 1. Fast Throughput. high speed, 18-bit sampling ADC, an internal conversion clock, The AD7643 is a 1.25 MSPS, charge redistribution, an internal reference (and buffer), error correction circuits, and 18-bit SAR ADC. both serial and parallel system interface ports. The part has no 2. Superior Linearity. latency and can be used in asynchronous rate applications. The The AD7643 has no missing 18-bit code. AD7643 is hardware factory calibrated and tested to ensure ac 3. Internal Reference. parameters, such as signal-to-noise ratio (SNR), in addition to The AD7643 has a 2.048 V internal reference with a typical the more traditional dc parameters of gain, offset, and linearity. drift of ±8 ppm/°C and an on-chip TEMP sensor. The AD7643 is only available in Pb-free packages with 4. Single-Supply Operation. operation specified from −40°C to +85°C. The AD7643 operates from a 2.5 V single supply. 5. Serial or Parallel Interface. Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 V, 3.3 V, or 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06024-001 AD7643 TABLE OF CONTENTS Features .............................................................................................. 1 Multiplexed Inputs ..................................................................... 17 Applications....................................................................................... 1 Driver Amplifier Choice ........................................................... 18 General Description ......................................................................... 1 Voltage Reference Input ............................................................ 18 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 20 Product Highlights ........................................................................... 1 Conversion Control ................................................................... 20 Revision History ............................................................................... 2 Interfaces.......................................................................................... 21 Specifications..................................................................................... 3 Digital Interface.......................................................................... 21 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Serial interface ............................................................................ 22 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 22 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 24 Terminology .................................................................................... 11 Microprocessor Interfacing....................................................... 26 Typical Performance Characteristics ........................................... 12 Application Hints ........................................................................... 27 Applications Information .............................................................. 15 Layout .......................................................................................... 27 Circuit Information.................................................................... 15 Evaluating the AD7643 Performance ...................................... 27 Converter Operation.................................................................. 15 Outline Dimensions ....................................................................... 28 Transfer Functions...................................................................... 16 Ordering Guide .......................................................................... 28 Typical Connection Diagram........................................................ 17 Analog Inputs.............................................................................. 17 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7643 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range V − V −V +V V IN+ IN− REF REF 1 Operating Input Voltage V , V to AGND −0.1 AVDD V IN+ IN− Analog Input CMRR f = 100 kHz 58 dB IN Input Current 1.25 MSPS throughput 2.5 μA 2 Input Impedance THROUGHPUT SPEED Complete Cycle 800 ns Throughput Rate 1.25 MSPS DC ACCURACY 3 4 Integral Linearity Error −3 ±1.5 +3 LSB No Missing Codes 18 Bits Differential Linearity Error −1 +1.25 LSB Transition Noise V = 2.5 V 1.7 LSB REF V = 2.048 V 2.0 LSB REF 5 Zero Error, TMIN to TMAX −16 +16 LSB Zero Error Temperature Drift ±1 ppm/°C 5 Gain Error, TMIN to TMAX −22 +22 LSB Gain Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB AC ACCURACY 6 Dynamic Range V = 2.5 V 95 dB REF Signal-to-Noise f = 1 kHz, V = 2.5 V 93.5 dB IN REF fIN = 20 kHz, VREF = 2.5 V 93.5 dB fIN = 20 kHz, VREF = 2.048 V 92 dB fIN = 100 kHz, VREF = 2.5 V 93 dB Spurious-Free Dynamic Range f = 1 kHz, V = 2.5 V 118 dB IN REF f = 20 kHz, V = 2.5 V 114 dB IN REF f = 20 kHz, V = 2.048 V 111 dB IN REF fIN = 100 kHz, VREF = 2.5 V 108 dB Total Harmonic Distortion fIN = 1 kHz, VREF = 2.5 V −114 dB fIN = 20 kHz, VREF = 2.5 V −113 dB f = 20 kHz, V = 2.048 V −109 dB IN REF f = 100 kHz, V = 2.5 V −105 dB IN REF Signal-to-(Noise + Distortion) f = 1 kHz, V = 2.5 V 93.5 dB IN REF fIN = 20 kHz, VREF = 2.5 V 93.5 dB fIN = 20 kHz, VREF = 2.048 V 91.8 dB f = 100 kHz, V = 2.5 V 92.5 dB IN REF −3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±8 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Rev. 0 | Page 3 of 28 AD7643 Parameter Conditions Min Typ Max Unit Turn-On Settling Time CREF = 10 μF 5 ms REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 1.8 2.5 AVDD + 0.1 V Current Drain 1.25 MSPS throughput 100 μA REFERENCE BUFFER PDREF = high, PDBUF = low REFBUFIN Input Voltage Range REF = 2.048 V typical 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA TEMPERATURE PIN Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL V 1.7 5.25 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS 7 Data Format 8 Pipeline Delay VOL ISINK = 500 μA 0.4 V V I = −500 μA OVDD − 0.3 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V 9 OVDD 2.30 3.6 V 10 Operating Current 1.25 MSPS throughput 11 AVDD With internal reference 24 mA DVDD 1.5 mA 12 OVDD 0.5 mA 10, 11 Power Dissipation With Internal Reference 1.25 MSPS throughput 65 80 mW With External Reference 1.25 MSPS throughput 60 75 mW 12 In Power-Down Mode PD = high 2 μW 13 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF. 2 See Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV. 5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 18-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; with external reference, PDREF and PDBUF are high. 12 With all digital inputs forced to OVDD. 13 Consult sales for extended temperature range. Rev. 0 | Page 4 of 28 AD7643 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (Refer to Figure 30 and Figure 31) 1 Convert Pulse Width t 15 70 ns 1 Time Between Conversions t2 800 ns CNVST t3 23 ns Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) t4 550 ns Aperture Delay t 1 ns 5 End of Conversion to BUSY Low Delay t 10 ns 6 Conversion Time t7 550 ns Acquisition Time t8 250 ns RESET Pulse Width t9 15 ns 2 RESET Low to BUSY High Delay t 10 ns 38 2 BUSY High Time from RESET Low t 500 ns 39 PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 ) CNVST t 550 ns Low to Data Valid Delay 10 Data Valid to BUSY Low Delay t 2 ns 11 Bus Access Request to Data Valid t 20 ns 12 Bus Relinquish Time t13 2 15 ns 3 MASTER SERIAL INTERFACE MODES (Refer to Figure 36 and Figure 37) CS t14 10 ns Low to SYNC Valid Delay 3 CS t15 10 ns Low to Internal SCLK Valid Delay CS t16 10 ns Low to SDOUT Delay CNVST t 135 ns Low to SYNC Delay 17 SYNC Asserted to SCLK First Edge Delay t 2 ns 18 4 Internal SCLK Period t19 8 20 ns 4 Internal SCLK High t20 2 ns 4 Internal SCLK Low t21 2 ns 4 SDOUT Valid Setup Time t 1 ns 22 4 SDOUT Valid Hold Time t 0 ns 23 4 SCLK Last Edge to SYNC Delay t 0 ns 24 CS t25 10 ns High to SYNC Hi-Z CS t26 10 ns High to Internal SCLK Hi-Z CS t 10 ns High to SDOUT Hi-Z 27 4 BUSY High in Master Serial Read After Convert t See Table 4 ns 28 t 508 ns CNVST 29 Low to SYNC Asserted Delay SYNC Deasserted to BUSY Low Delay t30 13 ns SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40) External SCLK Set-Up Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Set-Up Time t33 5 ns SDIN Hold Time t 5 ns 34 External SCLK Period t 12.5 ns 35 External SCLK High t 5 ns 36 External SCLK Low t37 5 ns 1 See the Conversion Control section. 2 See the Digital Interface section and the RESET section. 3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. Rev. 0 | Page 5 of 28 AD7643 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 1 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t 20 40 70 135 ns 19 Internal SCLK High Minimum t 2 8 16 32 ns 20 Internal SCLK Low Minimum t 2 8 16 32 ns 21 SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 30 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t 0.84 1.14 1.72 2.88 μs 28 500µA I OL TO OUTPUT 1.4V PIN C L 50pF 2V 0.8V 500µA I OH t t DELAY DELAY NOTE 2V 2V IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 0.8V 0.8V SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 3. Voltage Reference Levels for Timing Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, C = 10 pF L Rev. 0 | Page 6 of 28 06024-002 06024-003 AD7643 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 IN+ , IN−, REF, REFBUFIN, TEMP, AVDD + 0.3 V to other conditions above those indicated in the operational INGND, REFGND to AGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD, DVDD to OVDD −3.8 V to +2.8 V Digital Inputs −0.3 V to +5.5 V 2 PDREF, PDBUF ±20 mA 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C 1 See Analog Inputs section. 2 See Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, θ = 30°C/W. JA JC 4 Specification is for the device in free air: 48-Lead LFCSP; θ = 26°C/W. JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD7643 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 36 AGND AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST 3 MODE0 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS AD7643 DGND 6 31 RD TOP VIEW DGND 7 30 DGND (Not to Scale) D1/A0 8 29 BUSY 9 D2/A1 28 D17 10 D3 27 D16 11 D4/DIVSCLK[0] 26 D15 12 D5/DIVSCLK[1] 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin 1 No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI Data Output Interface Mode Selection. Interface MODE# MODE1 MODE0 Description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface 5 D0/OB/2C DI/O When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight 2C binary/twos complement. When OB/ is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6, 7 DGND P Connect to Digital Ground. 8 D1/A0 DI/O When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. or DIVSCLK[0:1] When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. or EXT/INT When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. Rev. 0 | Page 8 of 28 D6/EXT/INT PDBUF D7/INVSYNC PDREF D8/INVSCLK REFBUFIN D9/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND AGND D10/SDOUT NC D11/SCLK IN– D12/SYNC REFGND REF D13/RDERROR 06024-004 AD7643 Pin 1 No. Mnemonic Type Description 14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK When MODE[1:0] = 3 (serial mode), invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. 16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. or RDC When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. or SDIN When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). 19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. or SDOUT When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. or SCLK When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. or SYNC When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. 24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. or RDERROR When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 to D[14:17] DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of 28 the interface mode. 29 BUSY DO Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. 30 DGND P Digital Power Ground. Rev. 0 | Page 9 of 28 AD7643 Pin 1 No. Mnemonic Type Description 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. 33 RESET DI Reset Input. When high, resets the AD7643. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. 34 PD DI Power-Down Input. When high, powers down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. 38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 40 NC No Connect. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient of 1 mV/°C. This pin can be used to measure the temperature of the AD7643. See the Temperature Sensor section. 46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048 V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Table 7. Data Bus Interface Definition MODE MODE1 MODE0 2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description D0/OB/ 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel 1 0 1 2C A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word OB/ 1 0 1 A0 = 1 R[0] R[1] All Zeros 16-Bit Low Word 2C OB/ 2 1 0 2C A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte OB/ 2 1 0 2C A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte OB/ 2 1 0 2C A0 = 1 A1 = 0 All Hi-Z R[0:1] All Zeros 8-Bit Low Byte OB/ 2 1 0 2C A0 = 1 A1 = 1 All Hi-Z All Zeros R[0:1] 8-Bit Low Byte OB/ 3 1 1 2C All Hi-Z Serial Interface Serial Interface OB/ Rev. 0 | Page 10 of 28 AD7643 TERMINOLOGY Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal to (Noise + Distortion) Ratio (SINAD) 1½ LSB beyond the last code transition. The deviation is SINAD is the ratio of the rms value of the actual input signal to measured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, including harmonics but excluding dc. The value for In an ideal ADC, code transitions are 1 LSB apart. Differential SINAD is expressed in decibels. nonlinearity is the maximum deviation from this ideal value. It Spurious-Free Dynamic Range (SFDR) is often specified in terms of resolution for which no missing The difference, in decibels (dB), between the rms amplitude of codes are guaranteed. the input signal and the peak spurious signal. Gain Error Effective Number of Bits (ENOB) The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by (−2.0479922 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage ENOB = [(SINADdB − 1.76)/6.02] 1½ LSB below the nominal full scale (+2.0479766 V for the ±2.048 V range). The gain error is the deviation of the Aperture Delay difference between the actual level of the last transition and the Aperture delay is a measure of the acquisition performance and actual level of the first transition from the difference between is measured from the falling edge of the CNVST input to when the ideal levels. the input signal is held for a conversion. Zero Error Transient Response The zero error is the difference between the ideal midscale The time required for the AD7643 to achieve its rated accuracy input voltage (0 V) and the actual voltage producing the after a full-scale step function is applied to its input. midscale output code. Reference Voltage Temperature Coefficient Dynamic Range It is derived from the typical shift of output voltage at 25°C on a It is the ratio of the rms value of the full scale to the rms noise sample of parts maximum and minimum reference output measured with the inputs shorted together. The value for voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is dynamic range is expressed in decibels. expressed in ppm/°C using Signal-to-Noise Ratio (SNR) V() Max −V (Min) 6 REF REF TCV() ppm/°C = ×10 REF SNR is the ratio of the rms value of the actual input signal to the V() 25°C×() T −T REF MAX MIN rms sum of all other spectral components below the Nyquist where: frequency, excluding harmonics and dc. The value for SNR is V (Max) = Maximum V at T , T(25°C), or T expressed in decibels. REF REF MIN MAX VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Rev. 0 | Page 11 of 28 AD7643 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.25 2.5 1.0 2.0 1.5 1.0 0.5 0.5 0 0 –0.5 –1.0 –1.5 –0.5 –2.0 –2.5 –3.0 –1.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 40000 35000 σ = 1.67 σ = 2.04 V = 2.5V REF V = 2.048V REF 35000 33606 30000 28621 30000 24350 26875 25000 25000 23521 20000 18613 20000 16141 15505 17320 15000 15000 13376 10173 10000 10000 6371 5401 4726 4848 5000 3807 5000 3062 2306 1295 488 665 305 297 01 3 59 16 30 108 228 21 28 32 0 0 CODE IN HEX CODE IN HEX Figure 6. Histogram of 131,072 Conversions of a DC Input at Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Center (External Reference) the Code Center (Internal Reference) 2.0486 12 10 2.0484 GAIN ERROR 8 2.0482 6 4 2.0480 2 2.0478 0 ZERO ERROR –2 2.0476 –4 2.0474 –6 –8 2.0472 –10 2.0470 –12 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Typical Reference Voltage Output vs. Temperature (2 Units) Figure 10. Zero Error, Gain Error vs. Temperature Rev. 0 | Page 12 of 28 COUNTS INL (LSB) V (V) REF 1FFEE 1FFEF 1FFF0 1FFF1 1FFF2 1FFF3 1FFF4 1FFF5 1FFF6 1FFF7 1FFF8 1FFF9 1FFFA 1FFFB 1FFFC 1FFFD 1FFFE 1FFFF 06024-007 06024-006 06024-005 DNL (LSB) COUNTS ZERO ERROR, GAIN ERROR (LSB) 20027 20028 20029 2002A 2002B 2002C 2002D 2002E 2002F 20030 20031 20032 20033 20034 20035 20036 20037 20038 06024-010 06024-009 06024-008 AD7643 0 0 f = 1.25MSPS f = 1.25MSPS S S f = 20.03kHz f = 100.03kHz –20 IN –20 IN SNR = 93.4dB SNR = 93dB THD = –113dB THD = –106dB –40 –40 SFDR = 108dB SFDR = 109dB SINAD = 93.4dB SINAD = 92.8dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 06 100 200 300 400 50000 06 100 200 300 400 50000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. FFT 100 kHz Figure 11. FFT 20 kHz 95 16.0 95 19 93 15.6 SNR 91 SNR 15.2 94 18 89 14.8 SINAD 87 14.4 93 17 SINAD ENOB 85 14.0 92 16 83 13.6 81 13.2 ENOB 79 12.8 91 15 77 12.4 75 12.0 90 14 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 12. SNR, SINAD, and ENOB vs. Frequency Figure 15. SNR, SINAD, and ENOB vs. Temperature –70 120 –85 120 SFDR –90 110 SFDR –80 –95 110 100 –100 –90 90 –105 100 THD 80 –110 –100 THD 70 –115 90 THIRD –110 –120 HARMONIC 60 –125 80 50 –120 THIRD HARMONIC SECOND –130 HARMONIC 40 SECOND HARMONIC –135 70 –130 30 –140 –140 20 –145 60 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 13. THD, Harmonics, and SFDR vs. Frequency Figure 16. THD, Harmonics, and SFDR vs. Temperature Rev. 0 | Page 13 of 28 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full Scale) 06024-011 SFDR (dB) ENOB (Bits) 06024-013 06024-012 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full Scale) 06024-014 ENOB (Bits) SFDR (dB) 06024-015 06024-016 AD7643 96.0 100k AVDD 10k 95.5 1k 95.0 DVDD SNR 100 94.5 OVDD = 3.3V SINAD 10 94.0 1 OVDD = 2.5V 93.5 0.1 PDREF = PDBUF = HIGH 93.0 0.01 –60 –50 –40 –30 –20 –10 0 10 100 1k 10k 100k 1M 10M INPUT LEVEL (dB) SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sampling Rate 16 20 14 18 OVDD = 2.5V @ 85°C 12 16 OVDD = 2.5V @ 25°C 10 14 DVDD 8 12 OVDD, 3.3V 6 10 OVDD = 3.3V @ 25°C OVDD, 2.5V 4 8 OVDD = 3.3V @ 85°C 2 6 AVDD 0 4 –55 –35 –15 5 25 456585 105 125 0 50 100 150 200 TEMPERATURE (°C) C (pF) L Figure 20. Typical Delay vs. Load Capacitance CL Figure 18. Power-Down Operating Currents vs. Temperature Rev. 0 | Page 14 of 28 OPERATING CURRENTS (µA) SNR, SINAD REFERRED TO FULL SCALE (dB) 06024-018 06024-017 OPERATING CURRENTS (µA) t DELAY (ns) 12 06024-020 06024-019 AD7643 APPLICATIONS INFORMATION IN+ AGND SWITCHES CONTROL LSB SW+ MSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 131,072C 4C 2C C C 65,536C SW– MSB LSB CNVST AGND IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7643 is a very fast, low power, single-supply, precise During the acquisition phase, terminals of the array tied to the 18-bit ADC using successive approximation architecture. The comparator’s input are connected to AGND via SW+ and SW−. AD7643 is capable of converting 1,250,000 samples per second All independent switches are connected to the analog inputs. (1.25 MSPS). Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A The AD7643 provides the user with an on-chip, track-and-hold, conversion phase is initiated once the acquisition phase is complete successive approximation ADC that does not exhibit any CNVST and the input goes low. When the conversion phase pipeline or latency, making it ideal for multiple multiplexed begins, SW+ and SW− are opened first. The two capacitor channel applications. arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between The AD7643 can operate from a single 2.5 V supply and the inputs (IN+ and IN−) captured at the end of the acquisition interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed phase is applied to the comparator inputs, causing the in a Pb-free, 48-lead LQFP package or a tiny 48-lead LFCSP comparator to become unbalanced. By switching each element package, which combines space savings with flexibility and of the capacitor array between REFGND and REF, the comparator allows the AD7643 to be configured as either a serial or a input varies by binary weighted voltage steps (VREF/2, VREF/4 parallel interface. The AD7643 is pin-to-pin compatible with throughVREF/262144). The control logic toggles these switches, the AD7641 and is a speed upgrade of the AD7674, AD7678, starting with the MSB first, to bring the comparator back into a and AD7679. balanced condition. After the completion of this process, the CONVERTER OPERATION control logic generates the ADC output code and brings BUSY output low. The AD7643 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. Rev. 0 | Page 15 of 28 06024-021 AD7643 TRANSFER FUNCTIONS Using the OB/2C digital input, except in 18-bit interface mode, Table 8. Output Codes and Ideal Input Voltages the AD7643 offers two output codings: straight binary and twos Digital Output Code (Hex) complement. The LSB size with V = 2.048 V is 2 × V / REF REF Analog Input Straight Twos Description V = 2.048 V Binary Complement 262,144, which is 15.623 μV. Refer to Figure 22 and Table 8 for REF 1 1 the ideal transfer characteristic. FSR −1 LSB +2.0479844 V 0x3FFFF 0x1FFFF FSR − 2 LSB +2.0479688 V 0x3FFFE 0x1FFFE Midscale + 1 LSB +15.625 μV 0x20001 0x00001 111...111 Midscale 0 V 0x20000 0x00000 111...110 111...101 Midscale − 1 LSB −15.625 μV 0x1FFFF 0x3FFFF −FSR + 1 LSB −2.0479844 V 0x00001 0x20001 2 2 −FSR −2.048 V 0x00000 0x20000 1 This is also the code for overrange analog input (VIN+ − VIN− above +V − V ). REF REFGND 2 This is also the code for underrange analog input (VIN+ − VIN− below −V + V ). REF REFGND 000...010 000...001 000...000 –FSR + 1 LSB +FSR – 1 LSB –FSR –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (2.5V) (2.5V OR 3.3V) 100nF 10µF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT REF NOTE 3 SCLK C REF REFBUFIN 10µF 100nF SDOUT REFGND NOTE 4 BUSY NOTE 2 NOTE 7 MICROCONVERTER/ 50Ω MICROPROCESSOR/ 15Ω D CNVST DSP U1 IN+ 50pF ANALOG INPUT + AD7643 D0/OB/2C C 2.7nF C MODE0 NOTE 1 MODE1 OVDD NOTE 2 CS 15Ω CLOCK U2 IN– ANALOG RD INPUT – NOTE 3 C C 2.7nF 50pF PDREF PDBUF PD RESET NOTE 1 10kΩ NOTE 6 1. SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER-UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram Rev. 0 | Page 16 of 28 ADC CODE (Straight Binary) 06024-022 06024-023 AD7643 TYPICAL CONNECTION DIAGRAM switches. CIN is typically 12 pF and is mainly the ADC sampling Figure 23 shows a typical connection diagram for the AD7643. capacitor. During the conversion phase, when the switches are Different circuitry shown in this diagram is optional and is opened, the input impedance is limited to CPIN. RIN and CIN discussed in the following sections. make a 1-pole, low-pass filter that has a typical −3 dB cutoff ANALOG INPUTS frequency of 50 MHz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. Figure 24 shows an equivalent circuit of the input structure of the AD7643. Because the input impedance of the AD7643 is very high, the AD7643 can be driven directly by a low impedance source The two diodes, D1 and D2, provide ESD protection for the without gain error. To further improve the noise filtering achieved analog inputs IN+ and IN−. Care must be taken to ensure that by the AD7643’s analog input circuit, an external 1-pole RC the analog input signal never exceeds the supply rails by more filter between the amplifier’s outputs and the ADC analog than 0.3 V, because this causes the diodes to become forward- inputs can be used, as shown in Figure 23. However, large source biased and to start conducting current. These diodes can handle impedances significantly affect the ac performance, especially a forward-biased current of 100 mA maximum. For instance, the total harmonic distortion (THD). The maximum source these conditions could eventually occur when the input buffer’s impedance depends on the amount of THD that can be U1 or U2 supplies are different from AVDD. In such a case, an tolerated. The THD degrades as a function of the source input buffer with a short-circuit current limitation can be used impedance and the maximum input frequency, as shown in to protect the part. Figure 26. AVDD –70 D 1 R C IN IN IN+ OR IN– –75 R = 500Ω S C PIN D 2 –80 AGND –85 R = 100Ω S Figure 24. AD7643 Simplified Analog Input –90 The analog input of the AD7643 is a true differential structure. R = 50Ω S –95 By using this differential input, small signals common to both –100 inputs are rejected, as shown in Figure 25, representing the typical CMRR over frequency with internal and external references. –105 R = 10Ω S 65 –110 1 10 100 1000 INPUT FREQUENCY (kHz) 60 Figure 26. THD vs. Analog Input Frequency and Source Resistance INT REF MULTIPLEXED INPUTS EXT REF 55 When using the full 1.25 MSPS throughput in multiplexed applications for a full-scale step, the RC filter, as shown in Figure 23, does not settle in the required acquisition time, t8. 50 These values are chosen to optimize the best SNR performance of the AD7643. To use the full 1.25 MSPS throughput in multiplexed applications, the RC should be adjusted to satisfy t 8 45 (which is ~ 8.5 × RC time constant). However, lowering R and C 1 10 100 1000 10000 increases the RC filter bandwidth and allows more noise into the FREQUENCY (kHz) AD7643, which degrades SNR. To preserve the SNR performance Figure 25. Analog Input CMRR vs. Frequency in these applications using the RC filter shown in Figure 23, During the acquisition phase for ac signals, the impedance of the AD7643 should be run with t8 > 350 ns; or approximately the analog inputs, IN+ and IN−, can be modeled as a parallel 1/(t7 + t8) ~ 1.12 MSPS. combination of capacitor C and the network formed by the PIN series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 175 Ω and is a lumped component comprised of some serial resistors and the on resistance of the Rev. 0 | Page 17 of 28 CMRR (dB) 06024-024 06024-025 THD (dB) 06024-026 AD7643 The AD8021 meets these requirements and is appropriate for DRIVER AMPLIFIER CHOICE almost all applications. The AD8021 needs a 10 pF external Although the AD7643 is easy to drive, the driver amplifier compensation capacitor that should have good linearity as an needs to meet the following requirements: NPO ceramic or mica type. Moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the • For multichannel, multiplexed applications, the driver best signal-to-noise ratio. amplifier and the AD7643 analog input circuit must be able to settle for a full-scale step of the capacitor array at an The AD8022 can also be used when a dual version is needed 18-bit level (0.0004%). In the amplifier’s data sheet, settling and a gain of 1 is present. The AD829 is an alternative in at 0.1% to 0.01% is more commonly specified. This could applications where high frequency (above 100 kHz) performance is differ significantly from the settling time at an 18-bit level not required. In applications with a gain of 1, an 82 pF and should be verified prior to driver selection. The compensation capacitor is required. The AD8610 is an option AD8021 op amp, which combines ultralow noise and high when low bias current is needed in low frequency applications. gain bandwidth, meets this settling time requirement even when used with gains up to 13. Single-to-Differential Driver For applications using unipolar analog signals, a single-ended- • The noise generated by the driver amplifier needs to be to-differential driver, as shown in Figure 27, allows for a kept as low as possible to preserve the SNR and transition differential input into the part. This configuration, when noise performance of the AD7643. The noise coming from , produces a differential provided an input signal of 0 to VREF the driver is filtered by the AD7643 analog input circuit ±VREF with midscale at VREF/2. The 1-pole filter using R = 15 Ω 1-pole, low-pass filter made by RIN and CIN or by the and C = 2.7 nF provides a corner frequency of 3.9 MHz. external filter, if one is used. The SNR degradation due to the amplifier is If the application can tolerate more noise, the AD8139 differential driver can be used. ⎛ ⎞ ⎜ ⎟ 30 ⎜ ⎟ SNR = 20log LOSS ⎜ ⎟ πf πf 2 2 −3dB −3dB U1 ⎜ ⎟ 900+ () Ne + () Ne ⎜ N+ N− ⎟ AD8021 2 2 ⎝ ⎠ ANALOG INPUT (UNIPOLAR 0V TO 2.048V) 10pF 590Ω 15Ω where: IN+ 590Ω 2.7nF f–3dB is the input bandwidth of the AD7643 (50 MHz) or AD7643 the cutoff frequency of the input RC filter shown in Figure 23 15Ω IN– U2 (3.9 MHz), if one is used. 5kΩ REF AD8021 2.7nF N is the noise factor of the amplifier (1 in buffer 5kΩ 100nF 10pF 10µF configuration). e and e are the equivalent input voltage noise densities N+ N− Figure 27. Single-Ended-to-Differential Driver Circuit of the op amps connected to IN+ and IN−, in nV/√Hz. (Internal Reference Buffer Used) This approximation can be used when the resistances used VOLTAGE REFERENCE INPUT around the amplifier are small. If larger resistances are used, their noise contributions should also be root-sum The AD7643 allows the choice of either a very low temperature squared. drift internal voltage reference, an external 1.2 V reference that can be buffered using the internal reference buffer, or an For instance, when using op amps with an equivalent input external reference. noise density of 2.1 nV/√Hz, such as the AD8021, with a noise gain of 1 when configured as a buffer, degrades the Unlike many ADCs with internal references, the internal SNR by only 0.25 dB when using the RC filter in Figure 23, reference of the AD7643 provides excellent performance and and by 2.5 dB without it. can be used in almost all applications. • The driver needs to have a THD performance suitable to that of the AD7643. Figure 13 gives the THD vs. frequency that the driver should exceed. Rev. 0 | Page 18 of 28 06024-027 AD7643 Internal Reference (PDBUF = Low, PDREF = Low) occur when the driving voltage is above AVDD (for instance, at power-up). In this case, a 125 Ω series resistor is recommended. To use the internal reference, the PDREF and PDBUF inputs must both be low. This produces a 1.2 V band gap output on Reference Decoupling REFBUFIN, which is amplified by the internal buffer and Whether using an internal or external reference, the AD7643 results in a 2.048 V reference on the REF pin. voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with The internal reference is temperature compensated to 2.048 V ± efficient decoupling between the REF and REFGND inputs. 10 mV. The reference is trimmed to provide a typical drift of This decoupling depends on the choice of the voltage reference 8 ppm/°C. This typical drift characteristic is shown in Figure 7. but usually consists of a low ESR capacitor connected to REF The output resistance of REFBUFIN is 6.33 kΩ (minimum) and REFGND with minimum parasitic inductance. when the internal reference is enabled. It is necessary to A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF decouple this with a ceramic capacitor greater than 100 nF. tantalum capacitor) is appropriate when using either the Therefore, the capacitor provides an RC filter for noise reduction. internal reference or one of the recommended reference voltages. Because the output impedance of REFBUFIN is typically The placement of the reference decoupling is also important to 6.33 kΩ, relative humidity (among other industrial contaminates) the performance of the AD7643. The decoupling capacitor can directly affect the drift characteristics of the reference. should be mounted on the same side as the ADC right at the Typically, a guard ring is used to reduce the effects of drift REF pin with a thick PCB trace. The REFGND should also connect under such circumstances. However, because the AD7643 has a to the reference decoupling capacitor with the shortest distance. fine lead pitch, guarding this node is not practical. Therefore, in these industrial and other types of applications, it is recommended For applications that use multiple AD7643 devices, it is more to use a conformal coating, such as Dow Corning® 1-2577 or effective to use an external reference with the internal reference HumiSeal® 1B73. buffer to buffer the reference voltage. However, because the External 1.2 V Reference and Internal Buffer (PDBUF = reference buffers are not unity gain, ratiometric, simultaneously Low, PDREF = High) sampled designs should use an external reference and external buffer, such as the AD8031/AD8032; therefore, preserving the To use an external reference along with the internal buffer, same reference level for all converters. PDREF should be high and PDBUF should be low. This powers down the internal reference and allows an external 1.2 V The voltage reference temperature coefficient (TC) directly reference to be applied to REFBUFIN, producing 2.048 V impacts full scale; therefore, in applications where full-scale (typically) on the REF pin. accuracy matters, care must be taken with the TC. For instance, a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. External 2.5 V Reference (PDBUF = High, PDREF = High) To use an external 2.5 V reference directly on the REF pin, Note that V can be increased to AVDD + 0.1 V. Because the REF PDREF and PDBUF should both be high. input range is defined in terms of V , this would essentially REF increase the range to 0 V to 2.8 V with an AVDD = 2.7 V. For improved drift performance, an external reference, such as the AD780 or ADR431, can be used. The advantages of directly Temperature Sensor using the external voltage reference are: The TEMP pin measures the temperature of the AD7643. To improve the calibration accuracy over the temperature range, • The SNR and dynamic range improvement (about 1.7 dB) the output of the TEMP pin is applied to one of the inputs of resulting from the use of a reference voltage very close to the analog switch (such as, ADG779), and the ADC itself is the supply (2.5 V) instead of a typical 2.048 V reference used to measure its own temperature. This configuration is when the internal reference is used. This is calculated by shown in Figure 28. 2.048 ⎛ ⎞ SNR= 20log ⎜ ⎟ TEMP 2.50 ⎝ ⎠ ADG779 • The power savings when the internal reference is powered TEMPERATURE IN+ ANALOG INPUT SENSOR down (PDREF high). (UNIPOLAR) AD7643 C AD8021 C PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. The input current Figure 28. Use of the Temperature Sensor of PDREF and PDBUF should never exceed 20 mA. This can Rev. 0 | Page 19 of 28 06024-028 AD7643 POWER SUPPLY It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital The AD7643 uses three sets of power supply pins: an analog supply currents even further, drive the digital inputs close to 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a the power rails (that is, OVDD and OGND). digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V CONVERSION CONTROL and 5.25 V. To reduce the number of supplies needed, the digital CNVST core (DVDD) can be supplied through a simple RC filter from The AD7643 is controlled by the input. A falling edge Figure 23. CNVST the analog supply, as shown in on is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown Power Sequencing in Figure 30. Once initiated, it cannot be restarted or aborted, The AD7643 is independent of power supply sequencing and even by the power-down input, PD, until the conversion is thus free from supply induced voltage latch-up. In addition, it is complete. The CNVST signal operates independently of CS and insensitive to power supply variations over a wide frequency RD signals. range, as shown in Figure 29. t 2 65.0 t 1 62.5 CNVST 60.0 57.5 EXT REF BUSY t 4 55.0 t 3 t 6 t 5 52.5 INT REF MODE ACQUIRE CONVERT ACQUIRE CONVERT 50.0 t t 7 8 47.5 Figure 30. Basic Conversion Timing 45.0 1 10 100 1000 10000 For optimal performance, the rising edge of CNVST should not FREQUENCY (kHz) occur after the maximum CNVST low time, t , or until the end 1 Figure 29. PSRR vs. Frequency of conversion. Power-Up Although is a digital signal, it should be designed with CNVST At power-up, or when returning to operational mode from the special care with fast, clean edges and levels with minimum power-down mode (PD = high), the AD7643 engages an overshoot and undershoot or ringing. initialization process. During this time, the first 128 conversions The CNVST trace should be shielded with ground and a low should be ignored or the RESET input could be pulsed to value serial resistor (for example, 50 Ω) termination should be engage a faster initialization process. Refer to the Digital added close to the output of the component that drives this line. Interface section for RESET and timing details. In addition, a 50 pF capacitor is recommended to further reduce A simple power-on reset circuit, as shown in Figure 23, can be the effects of overshoot and undershoot as shown in Figure 23. used to minimize the digital interface. As OVDD powers up, the For applications where SNR is critical, the CNVST signal should capacitor is shorted and brings RESET high; it is then charged returning RESET to low. However, this circuit only works when have very low jitter. This can be achieved by using a dedicated powering up the AD7643 because the power-down mode oscillator for generation, or by clocking with a CNVST CNVST (PD = high) does not power down any of the supplies and as a high frequency, low jitter clock, as shown in Figure 23. result, RESET is low. Rev. 0 | Page 20 of 28 PSRR (dB) 06024-029 06024-030 AD7643 INTERFACES CS = RD = 0 DIGITAL INTERFACE t 1 CNVST The AD7643 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7643 BUSY digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic t 4 t 3 with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic t 11 high output voltage. In most applications, the OVDD supply pin DATA PREVIOUS CONVERSION DATA NEW DATA of the AD7643 is connected to the host system interface 2.5 V BUS 2C or 3.3 V digital supply. By using the D0/OB/ input pin, either Figure 32. Master Parallel Data Timing for Reading (Continuous Read) twos complement or straight binary coding can be used. Slave Parallel Interface CS RD The two signals and control the interface. When at least In slave parallel reading mode, the data can be read either after one of these signals is high, the interface outputs are in high each conversion, which is during the next acquisition phase, or impedance. Usually, CS allows the selection of each AD7643 in during the following conversion, as shown in Figure 33 and multicircuit applications and is held low in a single AD7643 Figure 34, respectively. When the data is read during the design. RD is generally used to enable the conversion result on conversion, it is recommended that it is read-only during the the data bus. first half of the conversion phase. This avoids any potential RESET feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. The RESET input is used to reset the AD7643 and generate a fast initialization. A rising edge on RESET aborts the current CS conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high. Conversions can take place RD after the falling edge of BUSY. Refer to Figure 31 for the RESET timing details. t 9 BUSY RESET CNVST DATA CURRENT BUS CONVERSION DATA t t 12 13 Figure 33. Slave Parallel Data Timing for Reading (Read After Convert) BUSY t t t 38 39 8 CS = 0 Figure 31. RESET Timing CNVST, t 1 RD PARALLEL INTERFACE BUSY t 4 The AD7643 is configured to use the parallel interface for an 18-bit, 16-bit, or 8-bit bus width according to Table 7. t 3 Master Parallel Interface DATA PREVIOUS BUS CONVERSION Data can be continuously read by tying CS and RD low, thus t t requiring minimal microprocessor connections. However, in 12 13 this mode, the data bus is always driven and cannot be used in Figure 34. Slave Parallel Data Timing for Reading (Read During Convert) shared bus applications, unless the device is held in RESET. Figure 32 details the timing for this mode. Rev. 0 | Page 21 of 28 06024-031 06024-033 06024-034 06024-032 AD7643 16-Bit and 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2) Internal Clock interfaces, the A0/A1 pins allow a glueless interface to a 16- or The AD7643 is configured to generate and provide the serial 8-bit bus, as shown in Figure 35. By connecting A0/A1 to an data clock SCLK when the EXT/ pin is held low. The INT address line(s), the data can be read in two words for a 16-bit AD7643 also generates a SYNC signal to indicate to the host interface, or three bytes for an 8-bit interface. This interface can when the serial data is valid. The serial clock SCLK and the be used in both master and slave parallel reading modes. Refer SYNC signal can be inverted. Depending on the read during to Table 7 for the full details of the interface. convert input, RDC/SDIN, the data can be read after each conversion or during the following conversion. Figure 36 and CS, RD Figure 37 show detailed timing diagrams of these two modes. Usually, because the AD7643 is used with a fast throughput, the A1 master read during conversion mode is the most recommended A0 serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between HI-Z HI-Z digital activity and critical conversion decisions. In this mode, HIGH LOW D[17:2] WORD WORD the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. HI-Z HI-Z HIGH MID LOW D[17:10] BYTE BYTE BYTE In read after conversion mode, it should be noted that unlike t t t t 12 12 12 13 other modes, the BUSY signal returns low after the 18 data bits Figure 35. 8-Bit and 16-Bit Parallel Interface are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width. As a result, the maximum SERIAL INTERFACE throughput cannot be achieved in this mode. The AD7643 is configured to use the serial interface when MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first, In addition, in read after convert mode, the SCLK frequency on the SDOUT pin. This data is synchronized with the 18 clock can be slowed down to accommodate different hosts using the pulses provided on the SCLK pin. The output data is valid on DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing both the rising and falling edge of the data clock. details when using these inputs. Rev. 0 | Page 22 of 28 06024-035 AD7643 INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0 EXT/INT = 0 RDC/SDIN = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SCLK t 15 t 27 SDOUT D17 D16 D2 D1 D0 X t t 16 23 t 22 Figure 36. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 19 14 t t 20 21 t 24 t 26 t 15 SCLK 12 3 16 17 18 t 18 t 27 SDOUT X D17 D16 D2 D1 D0 t t 16 23 t 22 Figure 37. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 28 06024-037 06024-036 AD7643 SLAVE SERIAL INTERFACE External Clock Finally, in this mode only, the AD7643 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters The AD7643 is configured to accept an externally supplied together. This feature is useful for reducing component count serial data clock on the SCLK pin when the EXT/ pin is INT and wiring connections when desired, as, for instance, in held high. In this mode, several methods can be used to read isolated multiconverter applications. the data. The external serial clock is gated by CS. When CS and are both low, the data can be read after each conversion or RD An example of the concatenation of two devices is shown in during the following conversion. The external clock can be Figure 38. Simultaneous sampling is possible by using a either a continuous or a discontinuous clock. A discontinuous common CNVST signal. It should be noted that the RDC/SDIN clock can be either normally high or normally low when input is latched on the edge of SCLK opposite to the one used to inactive. Figure 39 and Figure 40 show the detailed timing shift out the data on SDOUT. Therefore, the MSB of the diagrams of these methods. upstream converter just follows the LSB of the downstream converter on the next SCLK cycle. While the AD7643 is performing a bit decision, it is important BUSY that voltage transients be avoided on digital input/output pins OUT or degradation of the conversion result could occur. This is particularly important during the second half of the conversion BUSY BUSY phase because the AD7643 provides error correction circuitry AD7643 AD7643 #2 #1 that can correct for an improper bit decision made during (UPSTREAM) (DOWNSTREAM) DATA the first half of the conversion phase. For this reason, it is RDC/SDIN SDOUT RDC/SDIN SDOUT OUT recommended that when an external clock is being provided, CNVST CNVST a discontinuous clock is toggled only when BUSY is low or, CS CS more importantly, that it does not transition during the latter SCLK SCLK half of BUSY high. External Discontinuous Clock Data Read After Conversion SCLK IN CS IN Figure 39 shows the detailed timing diagrams of this method. CNVST IN After a conversion is complete, indicated by BUSY returning Figure 38. Two AD7643 Devices in a Daisy-Chain Configuration low, the conversion result can be read while both CS and RD are External Clock Data Read During Previous Conversion low. Data is shifted out MSB first with 18 clock pulses and is valid on the rising and falling edges of the clock. Figure 40 shows the detailed timing diagrams of this method. During a conversion, while CS and RD are both low, the result Among the advantages of this method is the fact that conversion of the previous conversion can be read. The data is shifted out, performance is not degraded because there are no voltage MSB first, with 18 clock pulses and is valid on both the rising transients on the digital interface during the conversion process. and falling edge of the clock. The 18 bits have to be read before Another advantage is the ability to read the data at any speed up the current conversion is complete; otherwise, RDERROR is to 80 MHz, which accommodates both the slow digital host pulsed high and can be used to interrupt the host interface to interface and the fast serial reading. prevent incomplete data reading. There is no daisy-chain feature in this mode, and the RDC/SDIN input should always It is also possible to begin to read data after conversion and be tied either high or low. continue to read the last bits after a new conversion is initiated. In this reading mode, it is recommended to pause digital To reduce performance degradation due to digital activity, a fast activity just prior to initiating a conversion (SCLK should be discontinuous clock of at least 67 MHz is recommended to held high or low). Once the conversion has begun, the reading ensure that all the bits are read during the first half of the SAR can continue. Also, in this mode, the use of a slower clock speed conversion phase, t , because the ADC can correct for errors 7 can be used to read the data because the total reading time is the introduced by digital activity during this time. acquisition time, t + half of the conversion time, t (t + ½ × t , see 8 7 8 7 the External Clock Data Read During Previous Conversion section). Rev. 0 | Page 24 of 28 06024-038 AD7643 RD = 0 EXT/INT = 1 INVSCLK = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 16 17 18 19 20 t 31 t 32 X D17 D16 D15 D1 X17 X16 SDOUT D0 t 16 t 34 SDIN X17 X16 X15 X1 X0 Y17 Y16 t 33 Figure 39. Slave Serial Data Timing for Reading (Read After Convert) t 31 EXT/INT = 1 INVSCLK = 0 RD = 0 CS t 3 CNVST t 35 BUSY t t 36 37 SCLK 16 2 3 4 17 18 1 t 32 SDOUT X D17 D16 D15 D2 D1 D0 t 16 Figure 40. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 28 06024-039 06024-040 AD7643 SPI Interface (ADSP-219x) MICROPROCESSOR INTERFACING Figure 41 shows an interface diagram between the AD7643 and The AD7643 is ideally suited for traditional dc measurement an SPI-equipped DSP, the ADSP-219x. To accommodate the applications supporting a microprocessor, and ac signal processing slower speed of the DSP, the AD7643 acts as a slave device and applications interfacing to a digital signal processor. The data must be read after conversion. This mode also allows the AD7643 is designed to interface with a parallel 8-bit or 16-bit daisy-chain feature. The convert command can be initiated in wide interface or with a general-purpose serial port or I/O ports response to an internal timer interrupt. The 18-bit output data on a microcontroller. A variety of external buffers can be used are read with three SPI byte access. The reading process can be with the AD7643 to prevent digital noise from coupling into the initiated in response to the end-of-conversion signal (BUSY ADC. The SPI Interface (ADSP-219x) section illustrates the use going low) using an interrupt line of the DSP. The serial of the AD7643 with the ADSP-219x SPI-equipped DSP. peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. DVDD 1 AD7643 ADSP-219x MODE0 MODE1 BUSY PFx EXT/INT CS SPIxSEL (PFx) SDOUT MISOx RD SCLK SCKx INVSCLK CNVST PFx OR TFSx 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 41. Interfacing the AD7643 to ADSP-219x Rev. 0 | Page 26 of 28 06024-041 AD7643 APPLICATION HINTS LAYOUT The DVDD supply of the AD7643 can be either a separate supply or come from the analog supply, AVDD, or from the While the AD7643 has very good immunity to noise on the digital interface supply, OVDD. When the system digital supply power supplies, exercise care with the grounding layout. To is noisy, or fast switching digital signals are present, and no facilitate the use of ground planes that can be easily separated, separate supply is available, it is recommended to connect the design the printed circuit board that houses the AD7643 so that DVDD digital supply to the analog supply AVDD through an the analog and digital sections are separated and confined to RC filter, and to connect the system supply to the interface certain areas of the board. Digital and analog ground planes digital supply OVDD and the remaining digital circuitry. Refer should be joined in only one place, preferably underneath the to Figure 23 for an example of this configuration. When DVDD AD7643, or as close as possible to the AD7643. If the AD7643 is is powered from the system supply, it is useful to insert a bead in a system where multiple devices require analog-to-digital to further reduce high frequency spikes. ground connections, the connections should still be made at one point only, a star ground point, established as close as The AD7643 has four different ground pins: REFGND, AGND, possible to the AD7643. DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should have a low impedance To prevent coupling noise onto the die, avoid radiating noise, return to the reference. AGND is the ground to which most and reduce feedthrough: internal ADC analog signals are referenced; it must be connected • Do not run digital lines under the device. with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the • Run the analog ground plane under the AD7643. configuration. OGND is connected to the digital system ground. • Shield fast switching signals, like CNVST or clocks, with The layout of the decoupling of the reference voltage is digital ground to avoid radiating noise to other sections of important. To minimize parasitic inductances, place the the board, and never run them near analog signal paths. decoupling capacitor close to the ADC and connect it with short, thick traces. • Avoid crossover of digital and analog signals. EVALUATING THE AD7643 PERFORMANCE • Run traces on different but close layers of the board, at right A recommended layout for the AD7643 is outlined in the angles to each other, to reduce the effect of feedthrough documentation of the EVAL-AD7643-CB evaluation board for through the board. the AD7643. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and The power supply lines to the AD7643 should use as large a software for controlling the board from a PC via the EVAL- trace as possible to provide low impedance paths and reduce the CONTROL BRD3. effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7643, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 27 of 28 PAD AD7643 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO AGND. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP 0.85 REQUIRED TO MEET THE 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 0.75 9.00 1.60 0.60 BSC SQ MAX 0.45 37 48 1 36 PIN 1 7.00 TOP VIEW BSC SQ 1.45 (PINS DOWN) 0.20 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 MAX PLANE 0.27 VIEW A COPLANARITY 0.50 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 43. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7643BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7643BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7643BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7643BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7643CB Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06024–0–4/06(0) TTTT Rev. 0 | Page 28 of 28